drivers/gpu/drm/i915/i915_pci.c

   1 /*
   2  * Copyright © 2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include <drm/drm_color_mgmt.h>
  26 #include <drm/drm_drv.h>
  27 #include <drm/i915_pciids.h>
  28
  29 #include "gt/intel_gt_regs.h"
  30 #include "gt/intel_sa_media.h"
  31
  32 #include "i915_driver.h"
  33 #include "i915_drv.h"
  34 #include "i915_pci.h"
  35 #include "i915_reg.h"
  36 #include "intel_pci_config.h"
  37
  38 #define PLATFORM(x) .platform = (x)
  39 #define GEN(x) \
  40         .__runtime.graphics.ver = (x), \
  41         .media.ver = (x), \
  42         .display.ver = (x)
  43
  44 #define I845_PIPE_OFFSETS \
  45         .display.pipe_offsets = { \
  46                 [TRANSCODER_A] = PIPE_A_OFFSET, \
  47         }, \
  48         .display.trans_offsets = { \
  49                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
  50         }
  51
  52 #define I9XX_PIPE_OFFSETS \
  53         .display.pipe_offsets = { \
  54                 [TRANSCODER_A] = PIPE_A_OFFSET, \
  55                 [TRANSCODER_B] = PIPE_B_OFFSET, \
  56         }, \
  57         .display.trans_offsets = { \
  58                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
  59                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
  60         }
  61
  62 #define IVB_PIPE_OFFSETS \
  63         .display.pipe_offsets = { \
  64                 [TRANSCODER_A] = PIPE_A_OFFSET, \
  65                 [TRANSCODER_B] = PIPE_B_OFFSET, \
  66                 [TRANSCODER_C] = PIPE_C_OFFSET, \
  67         }, \
  68         .display.trans_offsets = { \
  69                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
  70                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
  71                 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
  72         }
  73
  74 #define HSW_PIPE_OFFSETS \
  75         .display.pipe_offsets = { \
  76                 [TRANSCODER_A] = PIPE_A_OFFSET, \
  77                 [TRANSCODER_B] = PIPE_B_OFFSET, \
  78                 [TRANSCODER_C] = PIPE_C_OFFSET, \
  79                 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
  80         }, \
  81         .display.trans_offsets = { \
  82                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
  83                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
  84                 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
  85                 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
  86         }
  87
  88 #define CHV_PIPE_OFFSETS \
  89         .display.pipe_offsets = { \
  90                 [TRANSCODER_A] = PIPE_A_OFFSET, \
  91                 [TRANSCODER_B] = PIPE_B_OFFSET, \
  92                 [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
  93         }, \
  94         .display.trans_offsets = { \
  95                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
  96                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
  97                 [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
  98         }
  99
 100 #define I845_CURSOR_OFFSETS \
 101         .display.cursor_offsets = { \
 102                 [PIPE_A] = CURSOR_A_OFFSET, \
 103         }
 104
 105 #define I9XX_CURSOR_OFFSETS \
 106         .display.cursor_offsets = { \
 107                 [PIPE_A] = CURSOR_A_OFFSET, \
 108                 [PIPE_B] = CURSOR_B_OFFSET, \
 109         }
 110
 111 #define CHV_CURSOR_OFFSETS \
 112         .display.cursor_offsets = { \
 113                 [PIPE_A] = CURSOR_A_OFFSET, \
 114                 [PIPE_B] = CURSOR_B_OFFSET, \
 115                 [PIPE_C] = CHV_CURSOR_C_OFFSET, \
 116         }
 117
 118 #define IVB_CURSOR_OFFSETS \
 119         .display.cursor_offsets = { \
 120                 [PIPE_A] = CURSOR_A_OFFSET, \
 121                 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
 122                 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
 123         }
 124
 125 #define TGL_CURSOR_OFFSETS \
 126         .display.cursor_offsets = { \
 127                 [PIPE_A] = CURSOR_A_OFFSET, \
 128                 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
 129                 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
 130                 [PIPE_D] = TGL_CURSOR_D_OFFSET, \
 131         }
 132
 133 #define I9XX_COLORS \
 134         .display.color = { .gamma_lut_size = 256 }
 135 #define I965_COLORS \
 136         .display.color = { .gamma_lut_size = 129, \
 137                    .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
 138         }
 139 #define ILK_COLORS \
 140         .display.color = { .gamma_lut_size = 1024 }
 141 #define IVB_COLORS \
 142         .display.color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 }
 143 #define CHV_COLORS \
 144         .display.color = { \
 145                 .degamma_lut_size = 65, .gamma_lut_size = 257, \
 146                 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
 147                 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
 148         }
 149 #define GLK_COLORS \
 150         .display.color = { \
 151                 .degamma_lut_size = 33, .gamma_lut_size = 1024, \
 152                 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
 153                                      DRM_COLOR_LUT_EQUAL_CHANNELS, \
 154         }
 155 #define ICL_COLORS \
 156         .display.color = { \
 157                 .degamma_lut_size = 33, .gamma_lut_size = 262145, \
 158                 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
 159                                      DRM_COLOR_LUT_EQUAL_CHANNELS, \
 160                 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
 161         }
 162
 163 /* Keep in gen based order, and chronological order within a gen */
 164
 165 #define GEN_DEFAULT_PAGE_SIZES \
 166         .__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K
 167
 168 #define GEN_DEFAULT_REGIONS \
 169         .__runtime.memory_regions = REGION_SMEM | REGION_STOLEN_SMEM
 170
 171 #define I830_FEATURES \
 172         GEN(2), \
 173         .is_mobile = 1, \
 174         .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
 175         .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
 176         .display.has_overlay = 1, \
 177         .display.cursor_needs_physical = 1, \
 178         .display.overlay_needs_physical = 1, \
 179         .display.has_gmch = 1, \
 180         .gpu_reset_clobbers_display = true, \
 181         .has_3d_pipeline = 1, \
 182         .hws_needs_physical = 1, \
 183         .unfenced_needs_alignment = 1, \
 184         .__runtime.platform_engine_mask = BIT(RCS0), \
 185         .has_snoop = true, \
 186         .has_coherent_ggtt = false, \
 187         .dma_mask_size = 32, \
 188         I9XX_PIPE_OFFSETS, \
 189         I9XX_CURSOR_OFFSETS, \
 190         I9XX_COLORS, \
 191         GEN_DEFAULT_PAGE_SIZES, \
 192         GEN_DEFAULT_REGIONS
 193
 194 #define I845_FEATURES \
 195         GEN(2), \
 196         .__runtime.pipe_mask = BIT(PIPE_A), \
 197         .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A), \
 198         .display.has_overlay = 1, \
 199         .display.overlay_needs_physical = 1, \
 200         .display.has_gmch = 1, \
 201         .has_3d_pipeline = 1, \
 202         .gpu_reset_clobbers_display = true, \
 203         .hws_needs_physical = 1, \
 204         .unfenced_needs_alignment = 1, \
 205         .__runtime.platform_engine_mask = BIT(RCS0), \
 206         .has_snoop = true, \
 207         .has_coherent_ggtt = false, \
 208         .dma_mask_size = 32, \
 209         I845_PIPE_OFFSETS, \
 210         I845_CURSOR_OFFSETS, \
 211         I9XX_COLORS, \
 212         GEN_DEFAULT_PAGE_SIZES, \
 213         GEN_DEFAULT_REGIONS
 214
 215 static const struct intel_device_info i830_info = {
 216         I830_FEATURES,
 217         PLATFORM(INTEL_I830),
 218 };
 219
 220 static const struct intel_device_info i845g_info = {
 221         I845_FEATURES,
 222         PLATFORM(INTEL_I845G),
 223 };
 224
 225 static const struct intel_device_info i85x_info = {
 226         I830_FEATURES,
 227         PLATFORM(INTEL_I85X),
 228         .__runtime.fbc_mask = BIT(INTEL_FBC_A),
 229 };
 230
 231 static const struct intel_device_info i865g_info = {
 232         I845_FEATURES,
 233         PLATFORM(INTEL_I865G),
 234         .__runtime.fbc_mask = BIT(INTEL_FBC_A),
 235 };
 236
 237 #define GEN3_FEATURES \
 238         GEN(3), \
 239         .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
 240         .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
 241         .display.has_gmch = 1, \
 242         .gpu_reset_clobbers_display = true, \
 243         .__runtime.platform_engine_mask = BIT(RCS0), \
 244         .has_3d_pipeline = 1, \
 245         .has_snoop = true, \
 246         .has_coherent_ggtt = true, \
 247         .dma_mask_size = 32, \
 248         I9XX_PIPE_OFFSETS, \
 249         I9XX_CURSOR_OFFSETS, \
 250         I9XX_COLORS, \
 251         GEN_DEFAULT_PAGE_SIZES, \
 252         GEN_DEFAULT_REGIONS
 253
 254 static const struct intel_device_info i915g_info = {
 255         GEN3_FEATURES,
 256         PLATFORM(INTEL_I915G),
 257         .has_coherent_ggtt = false,
 258         .display.cursor_needs_physical = 1,
 259         .display.has_overlay = 1,
 260         .display.overlay_needs_physical = 1,
 261         .hws_needs_physical = 1,
 262         .unfenced_needs_alignment = 1,
 263 };
 264
 265 static const struct intel_device_info i915gm_info = {
 266         GEN3_FEATURES,
 267         PLATFORM(INTEL_I915GM),
 268         .is_mobile = 1,
 269         .display.cursor_needs_physical = 1,
 270         .display.has_overlay = 1,
 271         .display.overlay_needs_physical = 1,
 272         .display.supports_tv = 1,
 273         .__runtime.fbc_mask = BIT(INTEL_FBC_A),
 274         .hws_needs_physical = 1,
 275         .unfenced_needs_alignment = 1,
 276 };
 277
 278 static const struct intel_device_info i945g_info = {
 279         GEN3_FEATURES,
 280         PLATFORM(INTEL_I945G),
 281         .display.has_hotplug = 1,
 282         .display.cursor_needs_physical = 1,
 283         .display.has_overlay = 1,
 284         .display.overlay_needs_physical = 1,
 285         .hws_needs_physical = 1,
 286         .unfenced_needs_alignment = 1,
 287 };
 288
 289 static const struct intel_device_info i945gm_info = {
 290         GEN3_FEATURES,
 291         PLATFORM(INTEL_I945GM),
 292         .is_mobile = 1,
 293         .display.has_hotplug = 1,
 294         .display.cursor_needs_physical = 1,
 295         .display.has_overlay = 1,
 296         .display.overlay_needs_physical = 1,
 297         .display.supports_tv = 1,
 298         .__runtime.fbc_mask = BIT(INTEL_FBC_A),
 299         .hws_needs_physical = 1,
 300         .unfenced_needs_alignment = 1,
 301 };
 302
 303 static const struct intel_device_info g33_info = {
 304         GEN3_FEATURES,
 305         PLATFORM(INTEL_G33),
 306         .display.has_hotplug = 1,
 307         .display.has_overlay = 1,
 308         .dma_mask_size = 36,
 309 };
 310
 311 static const struct intel_device_info pnv_g_info = {
 312         GEN3_FEATURES,
 313         PLATFORM(INTEL_PINEVIEW),
 314         .display.has_hotplug = 1,
 315         .display.has_overlay = 1,
 316         .dma_mask_size = 36,
 317 };
 318
 319 static const struct intel_device_info pnv_m_info = {
 320         GEN3_FEATURES,
 321         PLATFORM(INTEL_PINEVIEW),
 322         .is_mobile = 1,
 323         .display.has_hotplug = 1,
 324         .display.has_overlay = 1,
 325         .dma_mask_size = 36,
 326 };
 327
 328 #define GEN4_FEATURES \
 329         GEN(4), \
 330         .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
 331         .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
 332         .display.has_hotplug = 1, \
 333         .display.has_gmch = 1, \
 334         .gpu_reset_clobbers_display = true, \
 335         .__runtime.platform_engine_mask = BIT(RCS0), \
 336         .has_3d_pipeline = 1, \
 337         .has_snoop = true, \
 338         .has_coherent_ggtt = true, \
 339         .dma_mask_size = 36, \
 340         I9XX_PIPE_OFFSETS, \
 341         I9XX_CURSOR_OFFSETS, \
 342         I965_COLORS, \
 343         GEN_DEFAULT_PAGE_SIZES, \
 344         GEN_DEFAULT_REGIONS
 345
 346 static const struct intel_device_info i965g_info = {
 347         GEN4_FEATURES,
 348         PLATFORM(INTEL_I965G),
 349         .display.has_overlay = 1,
 350         .hws_needs_physical = 1,
 351         .has_snoop = false,
 352 };
 353
 354 static const struct intel_device_info i965gm_info = {
 355         GEN4_FEATURES,
 356         PLATFORM(INTEL_I965GM),
 357         .is_mobile = 1,
 358         .__runtime.fbc_mask = BIT(INTEL_FBC_A),
 359         .display.has_overlay = 1,
 360         .display.supports_tv = 1,
 361         .hws_needs_physical = 1,
 362         .has_snoop = false,
 363 };
 364
 365 static const struct intel_device_info g45_info = {
 366         GEN4_FEATURES,
 367         PLATFORM(INTEL_G45),
 368         .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0),
 369         .gpu_reset_clobbers_display = false,
 370 };
 371
 372 static const struct intel_device_info gm45_info = {
 373         GEN4_FEATURES,
 374         PLATFORM(INTEL_GM45),
 375         .is_mobile = 1,
 376         .__runtime.fbc_mask = BIT(INTEL_FBC_A),
 377         .display.supports_tv = 1,
 378         .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0),
 379         .gpu_reset_clobbers_display = false,
 380 };
 381
 382 #define GEN5_FEATURES \
 383         GEN(5), \
 384         .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
 385         .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
 386         .display.has_hotplug = 1, \
 387         .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0), \
 388         .has_3d_pipeline = 1, \
 389         .has_snoop = true, \
 390         .has_coherent_ggtt = true, \
 391         /* ilk does support rc6, but we do not implement [power] contexts */ \
 392         .has_rc6 = 0, \
 393         .dma_mask_size = 36, \
 394         I9XX_PIPE_OFFSETS, \
 395         I9XX_CURSOR_OFFSETS, \
 396         ILK_COLORS, \
 397         GEN_DEFAULT_PAGE_SIZES, \
 398         GEN_DEFAULT_REGIONS
 399
 400 static const struct intel_device_info ilk_d_info = {
 401         GEN5_FEATURES,
 402         PLATFORM(INTEL_IRONLAKE),
 403 };
 404
 405 static const struct intel_device_info ilk_m_info = {
 406         GEN5_FEATURES,
 407         PLATFORM(INTEL_IRONLAKE),
 408         .is_mobile = 1,
 409         .has_rps = true,
 410         .__runtime.fbc_mask = BIT(INTEL_FBC_A),
 411 };
 412
 413 #define GEN6_FEATURES \
 414         GEN(6), \
 415         .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
 416         .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
 417         .display.has_hotplug = 1, \
 418         .__runtime.fbc_mask = BIT(INTEL_FBC_A), \
 419         .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
 420         .has_3d_pipeline = 1, \
 421         .has_coherent_ggtt = true, \
 422         .has_llc = 1, \
 423         .has_rc6 = 1, \
 424         .has_rc6p = 1, \
 425         .has_rps = true, \
 426         .dma_mask_size = 40, \
 427         .__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, \
 428         .__runtime.ppgtt_size = 31, \
 429         I9XX_PIPE_OFFSETS, \
 430         I9XX_CURSOR_OFFSETS, \
 431         ILK_COLORS, \
 432         GEN_DEFAULT_PAGE_SIZES, \
 433         GEN_DEFAULT_REGIONS
 434
 435 #define SNB_D_PLATFORM \
 436         GEN6_FEATURES, \
 437         PLATFORM(INTEL_SANDYBRIDGE)
 438
 439 static const struct intel_device_info snb_d_gt1_info = {
 440         SNB_D_PLATFORM,
 441         .gt = 1,
 442 };
 443
 444 static const struct intel_device_info snb_d_gt2_info = {
 445         SNB_D_PLATFORM,
 446         .gt = 2,
 447 };
 448
 449 #define SNB_M_PLATFORM \
 450         GEN6_FEATURES, \
 451         PLATFORM(INTEL_SANDYBRIDGE), \
 452         .is_mobile = 1
 453
 454
 455 static const struct intel_device_info snb_m_gt1_info = {
 456         SNB_M_PLATFORM,
 457         .gt = 1,
 458 };
 459
 460 static const struct intel_device_info snb_m_gt2_info = {
 461         SNB_M_PLATFORM,
 462         .gt = 2,
 463 };
 464
 465 #define GEN7_FEATURES  \
 466         GEN(7), \
 467         .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
 468         .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \
 469         .display.has_hotplug = 1, \
 470         .__runtime.fbc_mask = BIT(INTEL_FBC_A), \
 471         .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
 472         .has_3d_pipeline = 1, \
 473         .has_coherent_ggtt = true, \
 474         .has_llc = 1, \
 475         .has_rc6 = 1, \
 476         .has_rc6p = 1, \
 477         .has_reset_engine = true, \
 478         .has_rps = true, \
 479         .dma_mask_size = 40, \
 480         .__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, \
 481         .__runtime.ppgtt_size = 31, \
 482         IVB_PIPE_OFFSETS, \
 483         IVB_CURSOR_OFFSETS, \
 484         IVB_COLORS, \
 485         GEN_DEFAULT_PAGE_SIZES, \
 486         GEN_DEFAULT_REGIONS
 487
 488 #define IVB_D_PLATFORM \
 489         GEN7_FEATURES, \
 490         PLATFORM(INTEL_IVYBRIDGE), \
 491         .has_l3_dpf = 1
 492
 493 static const struct intel_device_info ivb_d_gt1_info = {
 494         IVB_D_PLATFORM,
 495         .gt = 1,
 496 };
 497
 498 static const struct intel_device_info ivb_d_gt2_info = {
 499         IVB_D_PLATFORM,
 500         .gt = 2,
 501 };
 502
 503 #define IVB_M_PLATFORM \
 504         GEN7_FEATURES, \
 505         PLATFORM(INTEL_IVYBRIDGE), \
 506         .is_mobile = 1, \
 507         .has_l3_dpf = 1
 508
 509 static const struct intel_device_info ivb_m_gt1_info = {
 510         IVB_M_PLATFORM,
 511         .gt = 1,
 512 };
 513
 514 static const struct intel_device_info ivb_m_gt2_info = {
 515         IVB_M_PLATFORM,
 516         .gt = 2,
 517 };
 518
 519 static const struct intel_device_info ivb_q_info = {
 520         GEN7_FEATURES,
 521         PLATFORM(INTEL_IVYBRIDGE),
 522         .gt = 2,
 523         .__runtime.pipe_mask = 0, /* legal, last one wins */
 524         .__runtime.cpu_transcoder_mask = 0,
 525         .has_l3_dpf = 1,
 526 };
 527
 528 static const struct intel_device_info vlv_info = {
 529         PLATFORM(INTEL_VALLEYVIEW),
 530         GEN(7),
 531         .is_lp = 1,
 532         .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
 533         .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
 534         .has_runtime_pm = 1,
 535         .has_rc6 = 1,
 536         .has_reset_engine = true,
 537         .has_rps = true,
 538         .display.has_gmch = 1,
 539         .display.has_hotplug = 1,
 540         .dma_mask_size = 40,
 541         .__runtime.ppgtt_type = INTEL_PPGTT_ALIASING,
 542         .__runtime.ppgtt_size = 31,
 543         .has_snoop = true,
 544         .has_coherent_ggtt = false,
 545         .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
 546         .display.mmio_offset = VLV_DISPLAY_BASE,
 547         I9XX_PIPE_OFFSETS,
 548         I9XX_CURSOR_OFFSETS,
 549         I965_COLORS,
 550         GEN_DEFAULT_PAGE_SIZES,
 551         GEN_DEFAULT_REGIONS,
 552 };
 553
 554 #define G75_FEATURES  \
 555         GEN7_FEATURES, \
 556         .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
 557         .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
 558                 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \
 559         .display.has_ddi = 1, \
 560         .display.has_fpga_dbg = 1, \
 561         .display.has_dp_mst = 1, \
 562         .has_rc6p = 0 /* RC6p removed-by HSW */, \
 563         HSW_PIPE_OFFSETS, \
 564         .has_runtime_pm = 1
 565
 566 #define HSW_PLATFORM \
 567         G75_FEATURES, \
 568         PLATFORM(INTEL_HASWELL), \
 569         .has_l3_dpf = 1
 570
 571 static const struct intel_device_info hsw_gt1_info = {
 572         HSW_PLATFORM,
 573         .gt = 1,
 574 };
 575
 576 static const struct intel_device_info hsw_gt2_info = {
 577         HSW_PLATFORM,
 578         .gt = 2,
 579 };
 580
 581 static const struct intel_device_info hsw_gt3_info = {
 582         HSW_PLATFORM,
 583         .gt = 3,
 584 };
 585
 586 #define GEN8_FEATURES \
 587         G75_FEATURES, \
 588         GEN(8), \
 589         .has_logical_ring_contexts = 1, \
 590         .dma_mask_size = 39, \
 591         .__runtime.ppgtt_type = INTEL_PPGTT_FULL, \
 592         .__runtime.ppgtt_size = 48, \
 593         .has_64bit_reloc = 1
 594
 595 #define BDW_PLATFORM \
 596         GEN8_FEATURES, \
 597         PLATFORM(INTEL_BROADWELL)
 598
 599 static const struct intel_device_info bdw_gt1_info = {
 600         BDW_PLATFORM,
 601         .gt = 1,
 602 };
 603
 604 static const struct intel_device_info bdw_gt2_info = {
 605         BDW_PLATFORM,
 606         .gt = 2,
 607 };
 608
 609 static const struct intel_device_info bdw_rsvd_info = {
 610         BDW_PLATFORM,
 611         .gt = 3,
 612         /* According to the device ID those devices are GT3, they were
 613          * previously treated as not GT3, keep it like that.
 614          */
 615 };
 616
 617 static const struct intel_device_info bdw_gt3_info = {
 618         BDW_PLATFORM,
 619         .gt = 3,
 620         .__runtime.platform_engine_mask =
 621                 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
 622 };
 623
 624 static const struct intel_device_info chv_info = {
 625         PLATFORM(INTEL_CHERRYVIEW),
 626         GEN(8),
 627         .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
 628         .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
 629         .display.has_hotplug = 1,
 630         .is_lp = 1,
 631         .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
 632         .has_64bit_reloc = 1,
 633         .has_runtime_pm = 1,
 634         .has_rc6 = 1,
 635         .has_rps = true,
 636         .has_logical_ring_contexts = 1,
 637         .display.has_gmch = 1,
 638         .dma_mask_size = 39,
 639         .__runtime.ppgtt_type = INTEL_PPGTT_FULL,
 640         .__runtime.ppgtt_size = 32,
 641         .has_reset_engine = 1,
 642         .has_snoop = true,
 643         .has_coherent_ggtt = false,
 644         .display.mmio_offset = VLV_DISPLAY_BASE,
 645         CHV_PIPE_OFFSETS,
 646         CHV_CURSOR_OFFSETS,
 647         CHV_COLORS,
 648         GEN_DEFAULT_PAGE_SIZES,
 649         GEN_DEFAULT_REGIONS,
 650 };
 651
 652 #define GEN9_DEFAULT_PAGE_SIZES \
 653         .__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K | \
 654                 I915_GTT_PAGE_SIZE_64K
 655
 656 #define GEN9_FEATURES \
 657         GEN8_FEATURES, \
 658         GEN(9), \
 659         GEN9_DEFAULT_PAGE_SIZES, \
 660         .__runtime.has_dmc = 1, \
 661         .has_gt_uc = 1, \
 662         .__runtime.has_hdcp = 1, \
 663         .display.has_ipc = 1, \
 664         .display.has_psr = 1, \
 665         .display.has_psr_hw_tracking = 1, \
 666         .display.dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
 667         .display.dbuf.slice_mask = BIT(DBUF_S1)
 668
 669 #define SKL_PLATFORM \
 670         GEN9_FEATURES, \
 671         PLATFORM(INTEL_SKYLAKE)
 672
 673 static const struct intel_device_info skl_gt1_info = {
 674         SKL_PLATFORM,
 675         .gt = 1,
 676 };
 677
 678 static const struct intel_device_info skl_gt2_info = {
 679         SKL_PLATFORM,
 680         .gt = 2,
 681 };
 682
 683 #define SKL_GT3_PLUS_PLATFORM \
 684         SKL_PLATFORM, \
 685         .__runtime.platform_engine_mask = \
 686                 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)
 687
 688
 689 static const struct intel_device_info skl_gt3_info = {
 690         SKL_GT3_PLUS_PLATFORM,
 691         .gt = 3,
 692 };
 693
 694 static const struct intel_device_info skl_gt4_info = {
 695         SKL_GT3_PLUS_PLATFORM,
 696         .gt = 4,
 697 };
 698
 699 #define GEN9_LP_FEATURES \
 700         GEN(9), \
 701         .is_lp = 1, \
 702         .display.dbuf.slice_mask = BIT(DBUF_S1), \
 703         .display.has_hotplug = 1, \
 704         .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
 705         .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
 706         .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
 707                 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
 708                 BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \
 709         .has_3d_pipeline = 1, \
 710         .has_64bit_reloc = 1, \
 711         .display.has_ddi = 1, \
 712         .display.has_fpga_dbg = 1, \
 713         .__runtime.fbc_mask = BIT(INTEL_FBC_A), \
 714         .__runtime.has_hdcp = 1, \
 715         .display.has_psr = 1, \
 716         .display.has_psr_hw_tracking = 1, \
 717         .has_runtime_pm = 1, \
 718         .__runtime.has_dmc = 1, \
 719         .has_rc6 = 1, \
 720         .has_rps = true, \
 721         .display.has_dp_mst = 1, \
 722         .has_logical_ring_contexts = 1, \
 723         .has_gt_uc = 1, \
 724         .dma_mask_size = 39, \
 725         .__runtime.ppgtt_type = INTEL_PPGTT_FULL, \
 726         .__runtime.ppgtt_size = 48, \
 727         .has_reset_engine = 1, \
 728         .has_snoop = true, \
 729         .has_coherent_ggtt = false, \
 730         .display.has_ipc = 1, \
 731         HSW_PIPE_OFFSETS, \
 732         IVB_CURSOR_OFFSETS, \
 733         IVB_COLORS, \
 734         GEN9_DEFAULT_PAGE_SIZES, \
 735         GEN_DEFAULT_REGIONS
 736
 737 static const struct intel_device_info bxt_info = {
 738         GEN9_LP_FEATURES,
 739         PLATFORM(INTEL_BROXTON),
 740         .display.dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */
 741 };
 742
 743 static const struct intel_device_info glk_info = {
 744         GEN9_LP_FEATURES,
 745         PLATFORM(INTEL_GEMINILAKE),
 746         .display.ver = 10,
 747         .display.dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */
 748         GLK_COLORS,
 749 };
 750
 751 #define KBL_PLATFORM \
 752         GEN9_FEATURES, \
 753         PLATFORM(INTEL_KABYLAKE)
 754
 755 static const struct intel_device_info kbl_gt1_info = {
 756         KBL_PLATFORM,
 757         .gt = 1,
 758 };
 759
 760 static const struct intel_device_info kbl_gt2_info = {
 761         KBL_PLATFORM,
 762         .gt = 2,
 763 };
 764
 765 static const struct intel_device_info kbl_gt3_info = {
 766         KBL_PLATFORM,
 767         .gt = 3,
 768         .__runtime.platform_engine_mask =
 769                 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
 770 };
 771
 772 #define CFL_PLATFORM \
 773         GEN9_FEATURES, \
 774         PLATFORM(INTEL_COFFEELAKE)
 775
 776 static const struct intel_device_info cfl_gt1_info = {
 777         CFL_PLATFORM,
 778         .gt = 1,
 779 };
 780
 781 static const struct intel_device_info cfl_gt2_info = {
 782         CFL_PLATFORM,
 783         .gt = 2,
 784 };
 785
 786 static const struct intel_device_info cfl_gt3_info = {
 787         CFL_PLATFORM,
 788         .gt = 3,
 789         .__runtime.platform_engine_mask =
 790                 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
 791 };
 792
 793 #define CML_PLATFORM \
 794         GEN9_FEATURES, \
 795         PLATFORM(INTEL_COMETLAKE)
 796
 797 static const struct intel_device_info cml_gt1_info = {
 798         CML_PLATFORM,
 799         .gt = 1,
 800 };
 801
 802 static const struct intel_device_info cml_gt2_info = {
 803         CML_PLATFORM,
 804         .gt = 2,
 805 };
 806
 807 #define GEN11_DEFAULT_PAGE_SIZES \
 808         .__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K | \
 809                 I915_GTT_PAGE_SIZE_64K |                \
 810                 I915_GTT_PAGE_SIZE_2M
 811
 812 #define GEN11_FEATURES \
 813         GEN9_FEATURES, \
 814         GEN11_DEFAULT_PAGE_SIZES, \
 815         .display.abox_mask = BIT(0), \
 816         .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
 817                 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
 818                 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
 819         .display.pipe_offsets = { \
 820                 [TRANSCODER_A] = PIPE_A_OFFSET, \
 821                 [TRANSCODER_B] = PIPE_B_OFFSET, \
 822                 [TRANSCODER_C] = PIPE_C_OFFSET, \
 823                 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
 824                 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
 825                 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
 826         }, \
 827         .display.trans_offsets = { \
 828                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
 829                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
 830                 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
 831                 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
 832                 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
 833                 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
 834         }, \
 835         GEN(11), \
 836         ICL_COLORS, \
 837         .display.dbuf.size = 2048, \
 838         .display.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
 839         .__runtime.has_dsc = 1, \
 840         .has_coherent_ggtt = false, \
 841         .has_logical_ring_elsq = 1
 842
 843 static const struct intel_device_info icl_info = {
 844         GEN11_FEATURES,
 845         PLATFORM(INTEL_ICELAKE),
 846         .__runtime.platform_engine_mask =
 847                 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
 848 };
 849
 850 static const struct intel_device_info ehl_info = {
 851         GEN11_FEATURES,
 852         PLATFORM(INTEL_ELKHARTLAKE),
 853         .__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
 854         .__runtime.ppgtt_size = 36,
 855 };
 856
 857 static const struct intel_device_info jsl_info = {
 858         GEN11_FEATURES,
 859         PLATFORM(INTEL_JASPERLAKE),
 860         .__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
 861         .__runtime.ppgtt_size = 36,
 862 };
 863
 864 #define GEN12_FEATURES \
 865         GEN11_FEATURES, \
 866         GEN(12), \
 867         .display.abox_mask = GENMASK(2, 1), \
 868         .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
 869         .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
 870                 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
 871                 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
 872         .display.pipe_offsets = { \
 873                 [TRANSCODER_A] = PIPE_A_OFFSET, \
 874                 [TRANSCODER_B] = PIPE_B_OFFSET, \
 875                 [TRANSCODER_C] = PIPE_C_OFFSET, \
 876                 [TRANSCODER_D] = PIPE_D_OFFSET, \
 877                 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
 878                 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
 879         }, \
 880         .display.trans_offsets = { \
 881                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
 882                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
 883                 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
 884                 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \
 885                 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
 886                 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
 887         }, \
 888         TGL_CURSOR_OFFSETS, \
 889         .has_global_mocs = 1, \
 890         .has_pxp = 1, \
 891         .display.has_dsb = 0 /* FIXME: LUT load is broken with DSB */
 892
 893 static const struct intel_device_info tgl_info = {
 894         GEN12_FEATURES,
 895         PLATFORM(INTEL_TIGERLAKE),
 896         .display.has_modular_fia = 1,
 897         .__runtime.platform_engine_mask =
 898                 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
 899 };
 900
 901 static const struct intel_device_info rkl_info = {
 902         GEN12_FEATURES,
 903         PLATFORM(INTEL_ROCKETLAKE),
 904         .display.abox_mask = BIT(0),
 905         .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
 906         .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
 907                 BIT(TRANSCODER_C),
 908         .display.has_hti = 1,
 909         .display.has_psr_hw_tracking = 0,
 910         .__runtime.platform_engine_mask =
 911                 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
 912 };
 913
 914 #define DGFX_FEATURES \
 915         .__runtime.memory_regions = REGION_SMEM | REGION_LMEM | REGION_STOLEN_LMEM, \
 916         .has_llc = 0, \
 917         .has_pxp = 0, \
 918         .has_snoop = 1, \
 919         .is_dgfx = 1, \
 920         .has_heci_gscfi = 1
 921
 922 static const struct intel_device_info dg1_info = {
 923         GEN12_FEATURES,
 924         DGFX_FEATURES,
 925         .__runtime.graphics.rel = 10,
 926         PLATFORM(INTEL_DG1),
 927         .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
 928         .require_force_probe = 1,
 929         .__runtime.platform_engine_mask =
 930                 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |
 931                 BIT(VCS0) | BIT(VCS2),
 932         /* Wa_16011227922 */
 933         .__runtime.ppgtt_size = 47,
 934 };
 935
 936 static const struct intel_device_info adl_s_info = {
 937         GEN12_FEATURES,
 938         PLATFORM(INTEL_ALDERLAKE_S),
 939         .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
 940         .display.has_hti = 1,
 941         .display.has_psr_hw_tracking = 0,
 942         .__runtime.platform_engine_mask =
 943                 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
 944         .dma_mask_size = 39,
 945 };
 946
 947 #define XE_LPD_FEATURES \
 948         .display.abox_mask = GENMASK(1, 0),                                     \
 949         .display.color = {                                                      \
 950                 .degamma_lut_size = 128, .gamma_lut_size = 1024,                \
 951                 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING |             \
 952                                      DRM_COLOR_LUT_EQUAL_CHANNELS,              \
 953         },                                                                      \
 954         .display.dbuf.size = 4096,                                              \
 955         .display.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \
 956                 BIT(DBUF_S4),                                                   \
 957         .display.has_ddi = 1,                                                   \
 958         .__runtime.has_dmc = 1,                                                 \
 959         .display.has_dp_mst = 1,                                                \
 960         .display.has_dsb = 1,                                                   \
 961         .__runtime.has_dsc = 1,                                                 \
 962         .__runtime.fbc_mask = BIT(INTEL_FBC_A),                                 \
 963         .display.has_fpga_dbg = 1,                                              \
 964         .__runtime.has_hdcp = 1,                                                \
 965         .display.has_hotplug = 1,                                               \
 966         .display.has_ipc = 1,                                                   \
 967         .display.has_psr = 1,                                                   \
 968         .display.ver = 13,                                                      \
 969         .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),   \
 970         .display.pipe_offsets = {                                               \
 971                 [TRANSCODER_A] = PIPE_A_OFFSET,                                 \
 972                 [TRANSCODER_B] = PIPE_B_OFFSET,                                 \
 973                 [TRANSCODER_C] = PIPE_C_OFFSET,                                 \
 974                 [TRANSCODER_D] = PIPE_D_OFFSET,                                 \
 975                 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET,                          \
 976                 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET,                          \
 977         },                                                                      \
 978         .display.trans_offsets = {                                              \
 979                 [TRANSCODER_A] = TRANSCODER_A_OFFSET,                           \
 980                 [TRANSCODER_B] = TRANSCODER_B_OFFSET,                           \
 981                 [TRANSCODER_C] = TRANSCODER_C_OFFSET,                           \
 982                 [TRANSCODER_D] = TRANSCODER_D_OFFSET,                           \
 983                 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET,                    \
 984                 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET,                    \
 985         },                                                                      \
 986         TGL_CURSOR_OFFSETS
 987
 988 static const struct intel_device_info adl_p_info = {
 989         GEN12_FEATURES,
 990         XE_LPD_FEATURES,
 991         PLATFORM(INTEL_ALDERLAKE_P),
 992         .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
 993                                BIT(TRANSCODER_C) | BIT(TRANSCODER_D) |
 994                                BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
 995         .display.has_cdclk_crawl = 1,
 996         .display.has_modular_fia = 1,
 997         .display.has_psr_hw_tracking = 0,
 998         .__runtime.platform_engine_mask =
 999                 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
1000         .__runtime.ppgtt_size = 48,
1001         .dma_mask_size = 39,
1002 };
1003
1004 #undef GEN
1005
1006 #define XE_HP_PAGE_SIZES \
1007         .__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K | \
1008                 I915_GTT_PAGE_SIZE_64K |                \
1009                 I915_GTT_PAGE_SIZE_2M
1010
1011 #define XE_HP_FEATURES \
1012         .__runtime.graphics.ver = 12, \
1013         .__runtime.graphics.rel = 50, \
1014         XE_HP_PAGE_SIZES, \
1015         .dma_mask_size = 46, \
1016         .has_3d_pipeline = 1, \
1017         .has_64bit_reloc = 1, \
1018         .has_flat_ccs = 1, \
1019         .has_global_mocs = 1, \
1020         .has_gt_uc = 1, \
1021         .has_llc = 1, \
1022         .has_logical_ring_contexts = 1, \
1023         .has_logical_ring_elsq = 1, \
1024         .has_mslice_steering = 1, \
1025         .has_rc6 = 1, \
1026         .has_reset_engine = 1, \
1027         .has_rps = 1, \
1028         .has_runtime_pm = 1, \
1029         .__runtime.ppgtt_size = 48, \
1030         .__runtime.ppgtt_type = INTEL_PPGTT_FULL
1031
1032 #define XE_HPM_FEATURES \
1033         .media.ver = 12, \
1034         .media.rel = 50
1035
1036 __maybe_unused
1037 static const struct intel_device_info xehpsdv_info = {
1038         XE_HP_FEATURES,
1039         XE_HPM_FEATURES,
1040         DGFX_FEATURES,
1041         PLATFORM(INTEL_XEHPSDV),
1042         .display = { },
1043         .has_64k_pages = 1,
1044         .needs_compact_pt = 1,
1045         .has_media_ratio_mode = 1,
1046         .__runtime.platform_engine_mask =
1047                 BIT(RCS0) | BIT(BCS0) |
1048                 BIT(VECS0) | BIT(VECS1) | BIT(VECS2) | BIT(VECS3) |
1049                 BIT(VCS0) | BIT(VCS1) | BIT(VCS2) | BIT(VCS3) |
1050                 BIT(VCS4) | BIT(VCS5) | BIT(VCS6) | BIT(VCS7) |
1051                 BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3),
1052         .require_force_probe = 1,
1053 };
1054
1055 #define DG2_FEATURES \
1056         XE_HP_FEATURES, \
1057         XE_HPM_FEATURES, \
1058         DGFX_FEATURES, \
1059         .__runtime.graphics.rel = 55, \
1060         .media.rel = 55, \
1061         PLATFORM(INTEL_DG2), \
1062         .has_4tile = 1, \
1063         .has_64k_pages = 1, \
1064         .has_guc_deprivilege = 1, \
1065         .has_heci_pxp = 1, \
1066         .needs_compact_pt = 1, \
1067         .has_media_ratio_mode = 1, \
1068         .__runtime.platform_engine_mask = \
1069                 BIT(RCS0) | BIT(BCS0) | \
1070                 BIT(VECS0) | BIT(VECS1) | \
1071                 BIT(VCS0) | BIT(VCS2) | \
1072                 BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3)
1073
1074 static const struct intel_device_info dg2_info = {
1075         DG2_FEATURES,
1076         XE_LPD_FEATURES,
1077         .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
1078                                BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
1079         .require_force_probe = 1,
1080 };
1081
1082 static const struct intel_device_info ats_m_info = {
1083         DG2_FEATURES,
1084         .display = { 0 },
1085         .require_force_probe = 1,
1086         .tuning_thread_rr_after_dep = 1,
1087 };
1088
1089 #define XE_HPC_FEATURES \
1090         XE_HP_FEATURES, \
1091         .dma_mask_size = 52, \
1092         .has_3d_pipeline = 0, \
1093         .has_guc_deprivilege = 1, \
1094         .has_l3_ccs_read = 1, \
1095         .has_mslice_steering = 0, \
1096         .has_one_eu_per_fuse_bit = 1
1097
1098 __maybe_unused
1099 static const struct intel_device_info pvc_info = {
1100         XE_HPC_FEATURES,
1101         XE_HPM_FEATURES,
1102         DGFX_FEATURES,
1103         .__runtime.graphics.rel = 60,
1104         .media.rel = 60,
1105         PLATFORM(INTEL_PONTEVECCHIO),
1106         .display = { 0 },
1107         .has_flat_ccs = 0,
1108         .__runtime.platform_engine_mask =
1109                 BIT(BCS0) |
1110                 BIT(VCS0) |
1111                 BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3),
1112         .require_force_probe = 1,
1113 };
1114
1115 #define XE_LPDP_FEATURES        \
1116         XE_LPD_FEATURES,        \
1117         .display.ver = 14,      \
1118         .display.has_cdclk_crawl = 1, \
1119         .__runtime.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B)
1120
1121 static const struct intel_gt_definition xelpmp_extra_gt[] = {
1122         {
1123                 .type = GT_MEDIA,
1124                 .name = "Standalone Media GT",
1125                 .gsi_offset = MTL_MEDIA_GSI_BASE,
1126                 .engine_mask = BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
1127         },
1128         {}
1129 };
1130
1131 __maybe_unused
1132 static const struct intel_device_info mtl_info = {
1133         XE_HP_FEATURES,
1134         XE_LPDP_FEATURES,
1135         /*
1136          * Real graphics IP version will be obtained from hardware GMD_ID
1137          * register.  Value provided here is just for sanity checking.
1138          */
1139         .__runtime.graphics.ver = 12,
1140         .__runtime.graphics.rel = 70,
1141         .media.ver = 13,
1142         PLATFORM(INTEL_METEORLAKE),
1143         .display.has_modular_fia = 1,
1144         .extra_gt_list = xelpmp_extra_gt,
1145         .has_flat_ccs = 0,
1146         .has_snoop = 1,
1147         .__runtime.memory_regions = REGION_SMEM | REGION_STOLEN_LMEM,
1148         .__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(CCS0),
1149         .require_force_probe = 1,
1150 };
1151
1152 #undef PLATFORM
1153
1154 /*
1155  * Make sure any device matches here are from most specific to most
1156  * general.  For example, since the Quanta match is based on the subsystem
1157  * and subvendor IDs, we need it to come before the more general IVB
1158  * PCI ID matches, otherwise we'll use the wrong info struct above.
1159  */
1160 static const struct pci_device_id pciidlist[] = {
1161         INTEL_I830_IDS(&i830_info),
1162         INTEL_I845G_IDS(&i845g_info),
1163         INTEL_I85X_IDS(&i85x_info),
1164         INTEL_I865G_IDS(&i865g_info),
1165         INTEL_I915G_IDS(&i915g_info),
1166         INTEL_I915GM_IDS(&i915gm_info),
1167         INTEL_I945G_IDS(&i945g_info),
1168         INTEL_I945GM_IDS(&i945gm_info),
1169         INTEL_I965G_IDS(&i965g_info),
1170         INTEL_G33_IDS(&g33_info),
1171         INTEL_I965GM_IDS(&i965gm_info),
1172         INTEL_GM45_IDS(&gm45_info),
1173         INTEL_G45_IDS(&g45_info),
1174         INTEL_PINEVIEW_G_IDS(&pnv_g_info),
1175         INTEL_PINEVIEW_M_IDS(&pnv_m_info),
1176         INTEL_IRONLAKE_D_IDS(&ilk_d_info),
1177         INTEL_IRONLAKE_M_IDS(&ilk_m_info),
1178         INTEL_SNB_D_GT1_IDS(&snb_d_gt1_info),
1179         INTEL_SNB_D_GT2_IDS(&snb_d_gt2_info),
1180         INTEL_SNB_M_GT1_IDS(&snb_m_gt1_info),
1181         INTEL_SNB_M_GT2_IDS(&snb_m_gt2_info),
1182         INTEL_IVB_Q_IDS(&ivb_q_info), /* must be first IVB */
1183         INTEL_IVB_M_GT1_IDS(&ivb_m_gt1_info),
1184         INTEL_IVB_M_GT2_IDS(&ivb_m_gt2_info),
1185         INTEL_IVB_D_GT1_IDS(&ivb_d_gt1_info),
1186         INTEL_IVB_D_GT2_IDS(&ivb_d_gt2_info),
1187         INTEL_HSW_GT1_IDS(&hsw_gt1_info),
1188         INTEL_HSW_GT2_IDS(&hsw_gt2_info),
1189         INTEL_HSW_GT3_IDS(&hsw_gt3_info),
1190         INTEL_VLV_IDS(&vlv_info),
1191         INTEL_BDW_GT1_IDS(&bdw_gt1_info),
1192         INTEL_BDW_GT2_IDS(&bdw_gt2_info),
1193         INTEL_BDW_GT3_IDS(&bdw_gt3_info),
1194         INTEL_BDW_RSVD_IDS(&bdw_rsvd_info),
1195         INTEL_CHV_IDS(&chv_info),
1196         INTEL_SKL_GT1_IDS(&skl_gt1_info),
1197         INTEL_SKL_GT2_IDS(&skl_gt2_info),
1198         INTEL_SKL_GT3_IDS(&skl_gt3_info),
1199         INTEL_SKL_GT4_IDS(&skl_gt4_info),
1200         INTEL_BXT_IDS(&bxt_info),
1201         INTEL_GLK_IDS(&glk_info),
1202         INTEL_KBL_GT1_IDS(&kbl_gt1_info),
1203         INTEL_KBL_GT2_IDS(&kbl_gt2_info),
1204         INTEL_KBL_GT3_IDS(&kbl_gt3_info),
1205         INTEL_KBL_GT4_IDS(&kbl_gt3_info),
1206         INTEL_AML_KBL_GT2_IDS(&kbl_gt2_info),
1207         INTEL_CFL_S_GT1_IDS(&cfl_gt1_info),
1208         INTEL_CFL_S_GT2_IDS(&cfl_gt2_info),
1209         INTEL_CFL_H_GT1_IDS(&cfl_gt1_info),
1210         INTEL_CFL_H_GT2_IDS(&cfl_gt2_info),
1211         INTEL_CFL_U_GT2_IDS(&cfl_gt2_info),
1212         INTEL_CFL_U_GT3_IDS(&cfl_gt3_info),
1213         INTEL_WHL_U_GT1_IDS(&cfl_gt1_info),
1214         INTEL_WHL_U_GT2_IDS(&cfl_gt2_info),
1215         INTEL_AML_CFL_GT2_IDS(&cfl_gt2_info),
1216         INTEL_WHL_U_GT3_IDS(&cfl_gt3_info),
1217         INTEL_CML_GT1_IDS(&cml_gt1_info),
1218         INTEL_CML_GT2_IDS(&cml_gt2_info),
1219         INTEL_CML_U_GT1_IDS(&cml_gt1_info),
1220         INTEL_CML_U_GT2_IDS(&cml_gt2_info),
1221         INTEL_ICL_11_IDS(&icl_info),
1222         INTEL_EHL_IDS(&ehl_info),
1223         INTEL_JSL_IDS(&jsl_info),
1224         INTEL_TGL_12_IDS(&tgl_info),
1225         INTEL_RKL_IDS(&rkl_info),
1226         INTEL_ADLS_IDS(&adl_s_info),
1227         INTEL_ADLP_IDS(&adl_p_info),
1228         INTEL_ADLN_IDS(&adl_p_info),
1229         INTEL_DG1_IDS(&dg1_info),
1230         INTEL_RPLS_IDS(&adl_s_info),
1231         INTEL_RPLP_IDS(&adl_p_info),
1232         INTEL_DG2_IDS(&dg2_info),
1233         INTEL_ATS_M_IDS(&ats_m_info),
1234         INTEL_MTL_IDS(&mtl_info),
1235         {0, 0, 0}
1236 };
1237 MODULE_DEVICE_TABLE(pci, pciidlist);
1238
1239 static void i915_pci_remove(struct pci_dev *pdev)
1240 {
1241         struct drm_i915_private *i915;
1242
1243         i915 = pci_get_drvdata(pdev);
1244         if (!i915) /* driver load aborted, nothing to cleanup */
1245                 return;
1246
1247         i915_driver_remove(i915);
1248         pci_set_drvdata(pdev, NULL);
1249 }
1250
1251 /* is device_id present in comma separated list of ids */
1252 static bool force_probe(u16 device_id, const char *devices)
1253 {
1254         char *s, *p, *tok;
1255         bool ret;
1256
1257         if (!devices || !*devices)
1258                 return false;
1259
1260         /* match everything */
1261         if (strcmp(devices, "*") == 0)
1262                 return true;
1263
1264         s = kstrdup(devices, GFP_KERNEL);
1265         if (!s)
1266                 return false;
1267
1268         for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) {
1269                 u16 val;
1270
1271                 if (kstrtou16(tok, 16, &val) == 0 && val == device_id) {
1272                         ret = true;
1273                         break;
1274                 }
1275         }
1276
1277         kfree(s);
1278
1279         return ret;
1280 }
1281
1282 bool i915_pci_resource_valid(struct pci_dev *pdev, int bar)
1283 {
1284         if (!pci_resource_flags(pdev, bar))
1285                 return false;
1286
1287         if (pci_resource_flags(pdev, bar) & IORESOURCE_UNSET)
1288                 return false;
1289
1290         if (!pci_resource_len(pdev, bar))
1291                 return false;
1292
1293         return true;
1294 }
1295
1296 static bool intel_mmio_bar_valid(struct pci_dev *pdev, struct intel_device_info *intel_info)
1297 {
1298         int gttmmaddr_bar = intel_info->__runtime.graphics.ver == 2 ? GEN2_GTTMMADR_BAR : GTTMMADR_BAR;
1299
1300         return i915_pci_resource_valid(pdev, gttmmaddr_bar);
1301 }
1302
1303 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1304 {
1305         struct intel_device_info *intel_info =
1306                 (struct intel_device_info *) ent->driver_data;
1307         int err;
1308
1309         if (intel_info->require_force_probe &&
1310             !force_probe(pdev->device, i915_modparams.force_probe)) {
1311                 dev_info(&pdev->dev,
1312                          "Your graphics device %04x is not properly supported by the driver in this\n"
1313                          "kernel version. To force driver probe anyway, use i915.force_probe=%04x\n"
1314                          "module parameter or CONFIG_DRM_I915_FORCE_PROBE=%04x configuration option,\n"
1315                          "or (recommended) check for kernel updates.\n",
1316                          pdev->device, pdev->device, pdev->device);
1317                 return -ENODEV;
1318         }
1319
1320         /* Only bind to function 0 of the device. Early generations
1321          * used function 1 as a placeholder for multi-head. This causes
1322          * us confusion instead, especially on the systems where both
1323          * functions have the same PCI-ID!
1324          */
1325         if (PCI_FUNC(pdev->devfn))
1326                 return -ENODEV;
1327
1328         if (!intel_mmio_bar_valid(pdev, intel_info))
1329                 return -ENXIO;
1330
1331         /* Detect if we need to wait for other drivers early on */
1332         if (intel_modeset_probe_defer(pdev))
1333                 return -EPROBE_DEFER;
1334
1335         err = i915_driver_probe(pdev, ent);
1336         if (err)
1337                 return err;
1338
1339         if (i915_inject_probe_failure(pci_get_drvdata(pdev))) {
1340                 i915_pci_remove(pdev);
1341                 return -ENODEV;
1342         }
1343
1344         err = i915_live_selftests(pdev);
1345         if (err) {
1346                 i915_pci_remove(pdev);
1347                 return err > 0 ? -ENOTTY : err;
1348         }
1349
1350         err = i915_perf_selftests(pdev);
1351         if (err) {
1352                 i915_pci_remove(pdev);
1353                 return err > 0 ? -ENOTTY : err;
1354         }
1355
1356         return 0;
1357 }
1358
1359 static void i915_pci_shutdown(struct pci_dev *pdev)
1360 {
1361         struct drm_i915_private *i915 = pci_get_drvdata(pdev);
1362
1363         i915_driver_shutdown(i915);
1364 }
1365
1366 static struct pci_driver i915_pci_driver = {
1367         .name = DRIVER_NAME,
1368         .id_table = pciidlist,
1369         .probe = i915_pci_probe,
1370         .remove = i915_pci_remove,
1371         .shutdown = i915_pci_shutdown,
1372         .driver.pm = &i915_pm_ops,
1373 };
1374
1375 int i915_pci_register_driver(void)
1376 {
1377         return pci_register_driver(&i915_pci_driver);
1378 }
1379
1380 void i915_pci_unregister_driver(void)
1381 {
1382         pci_unregister_driver(&i915_pci_driver);
1383 }