4 static inline void do_cpuid(unsigned int *eax, unsigned int *ebx,
5 unsigned int *ecx, unsigned int *edx)
8 : "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx)
9 : "0" (*eax), "2" (*ecx)
13 #include "arch-x86-common.h"
15 #define FIO_ARCH (arch_x86_64)
17 #ifndef __NR_ioprio_set
18 #define __NR_ioprio_set 251
19 #define __NR_ioprio_get 252
22 #ifndef __NR_fadvise64
23 #define __NR_fadvise64 221
26 #ifndef __NR_sys_splice
27 #define __NR_sys_splice 275
28 #define __NR_sys_tee 276
29 #define __NR_sys_vmsplice 278
33 #define __NR_shmget 29
35 #define __NR_shmctl 31
39 #define FIO_HUGE_PAGE 2097152
41 #define nop __asm__ __volatile__("rep;nop": : :"memory")
42 #define read_barrier() __asm__ __volatile__("lfence":::"memory")
43 #define write_barrier() __asm__ __volatile__("sfence":::"memory")
45 static inline unsigned long arch_ffz(unsigned long bitmask)
47 __asm__("bsf %1,%0" :"=r" (bitmask) :"r" (~bitmask));
51 static inline unsigned long long get_cpu_clock(void)
55 __asm__ __volatile__("rdtsc" : "=a" (lo), "=d" (hi));
56 return ((unsigned long long) hi << 32ULL) | lo;
60 #define ARCH_HAVE_SSE4_2
61 #define ARCH_HAVE_CPU_CLOCK
63 #define RDRAND_LONG ".byte 0x48,0x0f,0xc7,0xf0"
64 #define RDSEED_LONG ".byte 0x48,0x0f,0xc7,0xf8"
65 #define RDRAND_RETRY 100
67 static inline int arch_rand_long(unsigned long *val)
71 asm volatile("1: " RDRAND_LONG "\n\t"
76 : "=r" (ok), "=a" (*val)
77 : "0" (RDRAND_RETRY));
82 static inline int arch_rand_seed(unsigned long *seed)
86 asm volatile(RDSEED_LONG "\n\t"
88 : "=qm" (ok), "=a" (*seed));