1 #ifndef FIO_ARCH_X86_COMMON
2 #define FIO_ARCH_X86_COMMON
6 #ifndef __NR_sys_io_uring_setup
7 #define __NR_sys_io_uring_setup 425
9 #ifndef __NR_sys_io_uring_enter
10 #define __NR_sys_io_uring_enter 426
12 #ifndef __NR_sys_io_uring_register
13 #define __NR_sys_io_uring_register 427
16 static inline void cpuid(unsigned int op,
17 unsigned int *eax, unsigned int *ebx,
18 unsigned int *ecx, unsigned int *edx)
22 do_cpuid(eax, ebx, ecx, edx);
25 #define ARCH_HAVE_INIT
26 #define ARCH_HAVE_IOURING
28 extern bool tsc_reliable;
29 extern int arch_random;
31 static inline void arch_init_intel(void)
33 unsigned int eax, ebx, ecx = 0, edx;
39 do_cpuid(&eax, &ebx, &ecx, &edx);
40 if (!(edx & (1U << 4)))
44 * Check for constant rate and synced (across cores) TSC
47 do_cpuid(&eax, &ebx, &ecx, &edx);
48 tsc_reliable = (edx & (1U << 8)) != 0;
54 do_cpuid(&eax, &ebx, &ecx, &edx);
55 arch_random = (ecx & (1U << 30)) != 0;
58 static inline void arch_init_amd(void)
60 unsigned int eax, ebx, ecx, edx;
62 cpuid(0x80000000, &eax, &ebx, &ecx, &edx);
66 cpuid(0x80000007, &eax, &ebx, &ecx, &edx);
67 tsc_reliable = (edx & (1U << 8)) != 0;
70 static inline void arch_init(char *envp[])
75 arch_random = tsc_reliable = 0;
77 cpuid(0, &level, (unsigned int *) &str[0],
78 (unsigned int *) &str[8],
79 (unsigned int *) &str[4]);
82 if (!strcmp(str, "GenuineIntel"))
84 else if (!strcmp(str, "AuthenticAMD") || !strcmp(str, "HygonGenuine"))