| 1 | #ifndef FIO_ARCH_X86_COMMON |
| 2 | #define FIO_ARCH_X86_COMMON |
| 3 | |
| 4 | static inline void do_cpuid(unsigned int *eax, unsigned int *ebx, |
| 5 | unsigned int *ecx, unsigned int *edx) |
| 6 | { |
| 7 | asm volatile("cpuid" |
| 8 | : "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx) |
| 9 | : "0" (*eax), "2" (*ecx) |
| 10 | : "memory"); |
| 11 | } |
| 12 | |
| 13 | #define ARCH_HAVE_INIT |
| 14 | extern int tsc_reliable; |
| 15 | static inline int arch_init(char *envp[]) |
| 16 | { |
| 17 | unsigned int eax, ebx, ecx = 0, edx; |
| 18 | |
| 19 | /* |
| 20 | * Check for TSC |
| 21 | */ |
| 22 | eax = 1; |
| 23 | do_cpuid(&eax, &ebx, &ecx, &edx); |
| 24 | if (!(edx & (1U << 4))) |
| 25 | return 0; |
| 26 | |
| 27 | /* |
| 28 | * Check for constant rate and synced (across cores) TSC |
| 29 | */ |
| 30 | eax = 0x80000007; |
| 31 | do_cpuid(&eax, &ebx, &ecx, &edx); |
| 32 | tsc_reliable = edx & (1U << 8); |
| 33 | return 0; |
| 34 | } |
| 35 | |
| 36 | #endif |