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ASoC: pxa: pxa-ssp: add DT bindings
[linux-2.6-block.git] / sound / soc / pxa / pxa-ssp.c
CommitLineData
1b340bd7
MB		 1/*
2 * pxa-ssp.c -- ALSA Soc Audio Layer
3 *
4 * Copyright 2005,2008 Wolfson Microelectronics PLC.
5 * Author: Liam Girdwood
6 * Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * TODO:
14 * o Test network mode for > 16bit sample size
15 */
16
17#include <linux/init.h>
18#include <linux/module.h>
5a0e3ad6 19#include <linux/slab.h>
1b340bd7
MB		 20#include <linux/platform_device.h>
21#include <linux/clk.h>
22#include <linux/io.h>
8348c259 23#include <linux/pxa2xx_ssp.h>
2023c90c 24#include <linux/of.h>
1b340bd7 25
0664678a
PZ		 26#include <asm/irq.h>
27
1b340bd7
MB		 28#include <sound/core.h>
29#include <sound/pcm.h>
30#include <sound/initval.h>
31#include <sound/pcm_params.h>
32#include <sound/soc.h>
33#include <sound/pxa2xx-lib.h>
34
35#include <mach/hardware.h>
7ebc8d56 36#include <mach/dma.h>
1b340bd7 37
dd99a452 38#include "../../arm/pxa2xx-pcm.h"
1b340bd7
MB		 39#include "pxa-ssp.h"
40
41/*
42 * SSP audio private data
43 */
44struct ssp_priv {
f9efc9df 45 struct ssp_device *ssp;
1b340bd7
MB		 46 unsigned int sysclk;
47 int dai_fmt;
48#ifdef CONFIG_PM
f9efc9df
EM		 49 uint32_t cr0;
50 uint32_t cr1;
51 uint32_t to;
52 uint32_t psp;
1b340bd7
MB		 53#endif
54};
55
1b340bd7
MB		 56static void dump_registers(struct ssp_device *ssp)
57{
58 dev_dbg(&ssp->pdev->dev, "SSCR0 0x%08x SSCR1 0x%08x SSTO 0x%08x\n",
baffe169
HZ		 59 pxa_ssp_read_reg(ssp, SSCR0), pxa_ssp_read_reg(ssp, SSCR1),
60 pxa_ssp_read_reg(ssp, SSTO));
1b340bd7
MB		 61
62 dev_dbg(&ssp->pdev->dev, "SSPSP 0x%08x SSSR 0x%08x SSACD 0x%08x\n",
baffe169
HZ		 63 pxa_ssp_read_reg(ssp, SSPSP), pxa_ssp_read_reg(ssp, SSSR),
64 pxa_ssp_read_reg(ssp, SSACD));
1b340bd7
MB		 65}
66
baffe169 67static void pxa_ssp_enable(struct ssp_device *ssp)
f9efc9df
EM		 68{
69 uint32_t sscr0;
70
71 sscr0 = __raw_readl(ssp->mmio_base + SSCR0) | SSCR0_SSE;
72 __raw_writel(sscr0, ssp->mmio_base + SSCR0);
73}
74
baffe169 75static void pxa_ssp_disable(struct ssp_device *ssp)
f9efc9df
EM		 76{
77 uint32_t sscr0;
78
79 sscr0 = __raw_readl(ssp->mmio_base + SSCR0) & ~SSCR0_SSE;
80 __raw_writel(sscr0, ssp->mmio_base + SSCR0);
81}
82
2d7e71fa
EM		 83struct pxa2xx_pcm_dma_data {
84 struct pxa2xx_pcm_dma_params params;
85 char name[20];
1b340bd7
MB		 86};
87
d93ca1ae 88static void pxa_ssp_set_dma_params(struct ssp_device *ssp, int width4,
89 int out, struct pxa2xx_pcm_dma_params *dma_data)
2d7e71fa
EM		 90{
91 struct pxa2xx_pcm_dma_data *dma;
92
d93ca1ae 93 dma = container_of(dma_data, struct pxa2xx_pcm_dma_data, params);
2d7e71fa
EM		 94
95 snprintf(dma->name, 20, "SSP%d PCM %s %s", ssp->port_id,
8eb9feab 96 width4 ? "32-bit" : "16-bit", out ? "out" : "in");
2d7e71fa
EM		 97
98 dma->params.name = dma->name;
99 dma->params.drcmr = &DRCMR(out ? ssp->drcmr_tx : ssp->drcmr_rx);
100 dma->params.dcmd = (out ? (DCMD_INCSRCADDR | DCMD_FLOWTRG) :
101 (DCMD_INCTRGADDR | DCMD_FLOWSRC)) |
8eb9feab 102 (width4 ? DCMD_WIDTH4 : DCMD_WIDTH2) | DCMD_BURST16;
2d7e71fa 103 dma->params.dev_addr = ssp->phys_base + SSDR;
2d7e71fa
EM		 104}
105
dee89c4d 106static int pxa_ssp_startup(struct snd_pcm_substream *substream,
f0fba2ad 107 struct snd_soc_dai *cpu_dai)
1b340bd7 108{
f0fba2ad 109 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
f9efc9df 110 struct ssp_device *ssp = priv->ssp;
d93ca1ae 111 struct pxa2xx_pcm_dma_data *dma;
1b340bd7
MB		 112 int ret = 0;
113
114 if (!cpu_dai->active) {
f9efc9df 115 clk_enable(ssp->clk);
baffe169 116 pxa_ssp_disable(ssp);
1b340bd7 117 }
2d7e71fa 118
d93ca1ae 119 dma = kzalloc(sizeof(struct pxa2xx_pcm_dma_data), GFP_KERNEL);
120 if (!dma)
121 return -ENOMEM;
122 snd_soc_dai_set_dma_data(cpu_dai, substream, &dma->params);
5f712b2b 123
1b340bd7
MB		 124 return ret;
125}
126
dee89c4d 127static void pxa_ssp_shutdown(struct snd_pcm_substream *substream,
f0fba2ad 128 struct snd_soc_dai *cpu_dai)
1b340bd7 129{
f0fba2ad 130 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
f9efc9df 131 struct ssp_device *ssp = priv->ssp;
1b340bd7
MB		 132
133 if (!cpu_dai->active) {
baffe169 134 pxa_ssp_disable(ssp);
f9efc9df 135 clk_disable(ssp->clk);
1b340bd7 136 }
2d7e71fa 137
5f712b2b
DM		 138 kfree(snd_soc_dai_get_dma_data(cpu_dai, substream));
139 snd_soc_dai_set_dma_data(cpu_dai, substream, NULL);
1b340bd7
MB		 140}
141
142#ifdef CONFIG_PM
143
dc7d7b83 144static int pxa_ssp_suspend(struct snd_soc_dai *cpu_dai)
1b340bd7 145{
f0fba2ad 146 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
f9efc9df 147 struct ssp_device *ssp = priv->ssp;
1b340bd7
MB		 148
149 if (!cpu_dai->active)
988addf8 150 clk_enable(ssp->clk);
1b340bd7 151
f9efc9df
EM		 152 priv->cr0 = __raw_readl(ssp->mmio_base + SSCR0);
153 priv->cr1 = __raw_readl(ssp->mmio_base + SSCR1);
154 priv->to = __raw_readl(ssp->mmio_base + SSTO);
155 priv->psp = __raw_readl(ssp->mmio_base + SSPSP);
156
baffe169 157 pxa_ssp_disable(ssp);
f9efc9df 158 clk_disable(ssp->clk);
1b340bd7
MB		 159 return 0;
160}
161
dc7d7b83 162static int pxa_ssp_resume(struct snd_soc_dai *cpu_dai)
1b340bd7 163{
f0fba2ad 164 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
f9efc9df
EM		 165 struct ssp_device *ssp = priv->ssp;
166 uint32_t sssr = SSSR_ROR | SSSR_TUR | SSSR_BCE;
1b340bd7 167
f9efc9df
EM		 168 clk_enable(ssp->clk);
169
170 __raw_writel(sssr, ssp->mmio_base + SSSR);
f9efc9df
EM		 171 __raw_writel(priv->cr0 & ~SSCR0_SSE, ssp->mmio_base + SSCR0);
172 __raw_writel(priv->cr1, ssp->mmio_base + SSCR1);
173 __raw_writel(priv->to, ssp->mmio_base + SSTO);
174 __raw_writel(priv->psp, ssp->mmio_base + SSPSP);
026384d6
DM		 175
176 if (cpu_dai->active)
baffe169 177 pxa_ssp_enable(ssp);
026384d6 178 else
988addf8 179 clk_disable(ssp->clk);
1b340bd7
MB		 180
181 return 0;
182}
183
184#else
185#define pxa_ssp_suspend NULL
186#define pxa_ssp_resume NULL
187#endif
188
189/**
190 * ssp_set_clkdiv - set SSP clock divider
191 * @div: serial clock rate divider
192 */
baffe169 193static void pxa_ssp_set_scr(struct ssp_device *ssp, u32 div)
1b340bd7 194{
baffe169 195 u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
1a297286 196
972a55b6 197 if (ssp->type == PXA25x_SSP) {
1a297286
PZ		 198 sscr0 &= ~0x0000ff00;
199 sscr0 |= ((div - 2)/2) << 8; /* 2..512 */
200 } else {
201 sscr0 &= ~0x000fff00;
202 sscr0 |= (div - 1) << 8; /* 1..4096 */
203 }
baffe169 204 pxa_ssp_write_reg(ssp, SSCR0, sscr0);
1a297286
PZ		 205}
206
207/**
baffe169 208 * pxa_ssp_get_clkdiv - get SSP clock divider
1a297286 209 */
baffe169 210static u32 pxa_ssp_get_scr(struct ssp_device *ssp)
1a297286 211{
baffe169 212 u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
1a297286 213 u32 div;
1b340bd7 214
972a55b6 215 if (ssp->type == PXA25x_SSP)
1a297286
PZ		 216 div = ((sscr0 >> 8) & 0xff) * 2 + 2;
217 else
218 div = ((sscr0 >> 8) & 0xfff) + 1;
219 return div;
1b340bd7
MB		 220}
221
222/*
223 * Set the SSP ports SYSCLK.
224 */
225static int pxa_ssp_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
226 int clk_id, unsigned int freq, int dir)
227{
f0fba2ad 228 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
f9efc9df 229 struct ssp_device *ssp = priv->ssp;
1b340bd7
MB		 230 int val;
231
baffe169 232 u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0) &
20a41eac 233 ~(SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ACS);
1b340bd7
MB		 234
235 dev_dbg(&ssp->pdev->dev,
449bd54d 236 "pxa_ssp_set_dai_sysclk id: %d, clk_id %d, freq %u\n",
1b340bd7
MB		 237 cpu_dai->id, clk_id, freq);
238
239 switch (clk_id) {
240 case PXA_SSP_CLK_NET_PLL:
241 sscr0 |= SSCR0_MOD;
242 break;
243 case PXA_SSP_CLK_PLL:
244 /* Internal PLL is fixed */
972a55b6 245 if (ssp->type == PXA25x_SSP)
1b340bd7
MB		 246 priv->sysclk = 1843200;
247 else
248 priv->sysclk = 13000000;
249 break;
250 case PXA_SSP_CLK_EXT:
251 priv->sysclk = freq;
252 sscr0 |= SSCR0_ECS;
253 break;
254 case PXA_SSP_CLK_NET:
255 priv->sysclk = freq;
256 sscr0 |= SSCR0_NCS | SSCR0_MOD;
257 break;
258 case PXA_SSP_CLK_AUDIO:
259 priv->sysclk = 0;
baffe169 260 pxa_ssp_set_scr(ssp, 1);
20a41eac 261 sscr0 |= SSCR0_ACS;
1b340bd7
MB		 262 break;
263 default:
264 return -ENODEV;
265 }
266
267 /* The SSP clock must be disabled when changing SSP clock mode
268 * on PXA2xx. On PXA3xx it must be enabled when doing so. */
972a55b6 269 if (ssp->type != PXA3xx_SSP)
f9efc9df 270 clk_disable(ssp->clk);
baffe169
HZ		 271 val = pxa_ssp_read_reg(ssp, SSCR0) | sscr0;
272 pxa_ssp_write_reg(ssp, SSCR0, val);
972a55b6 273 if (ssp->type != PXA3xx_SSP)
f9efc9df 274 clk_enable(ssp->clk);
1b340bd7
MB		 275
276 return 0;
277}
278
279/*
280 * Set the SSP clock dividers.
281 */
282static int pxa_ssp_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
283 int div_id, int div)
284{
f0fba2ad 285 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
f9efc9df 286 struct ssp_device *ssp = priv->ssp;
1b340bd7
MB		 287 int val;
288
289 switch (div_id) {
290 case PXA_SSP_AUDIO_DIV_ACDS:
baffe169
HZ		 291 val = (pxa_ssp_read_reg(ssp, SSACD) & ~0x7) | SSACD_ACDS(div);
292 pxa_ssp_write_reg(ssp, SSACD, val);
1b340bd7
MB		 293 break;
294 case PXA_SSP_AUDIO_DIV_SCDB:
baffe169 295 val = pxa_ssp_read_reg(ssp, SSACD);
1b340bd7 296 val &= ~SSACD_SCDB;
972a55b6 297 if (ssp->type == PXA3xx_SSP)
1b340bd7 298 val &= ~SSACD_SCDX8;
1b340bd7
MB		 299 switch (div) {
300 case PXA_SSP_CLK_SCDB_1:
301 val |= SSACD_SCDB;
302 break;
303 case PXA_SSP_CLK_SCDB_4:
304 break;
1b340bd7 305 case PXA_SSP_CLK_SCDB_8:
972a55b6 306 if (ssp->type == PXA3xx_SSP)
1b340bd7
MB		 307 val |= SSACD_SCDX8;
308 else
309 return -EINVAL;
310 break;
1b340bd7
MB		 311 default:
312 return -EINVAL;
313 }
baffe169 314 pxa_ssp_write_reg(ssp, SSACD, val);
1b340bd7
MB		 315 break;
316 case PXA_SSP_DIV_SCR:
baffe169 317 pxa_ssp_set_scr(ssp, div);
1b340bd7
MB		 318 break;
319 default:
320 return -ENODEV;
321 }
322
323 return 0;
324}
325
326/*
327 * Configure the PLL frequency pxa27x and (afaik - pxa320 only)
328 */
85488037
MB		 329static int pxa_ssp_set_dai_pll(struct snd_soc_dai *cpu_dai, int pll_id,
330 int source, unsigned int freq_in, unsigned int freq_out)
1b340bd7 331{
f0fba2ad 332 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
f9efc9df 333 struct ssp_device *ssp = priv->ssp;
baffe169 334 u32 ssacd = pxa_ssp_read_reg(ssp, SSACD) & ~0x70;
1b340bd7 335
972a55b6 336 if (ssp->type == PXA3xx_SSP)
baffe169 337 pxa_ssp_write_reg(ssp, SSACDD, 0);
1b340bd7
MB		 338
339 switch (freq_out) {
340 case 5622000:
341 break;
342 case 11345000:
343 ssacd |= (0x1 << 4);
344 break;
345 case 12235000:
346 ssacd |= (0x2 << 4);
347 break;
348 case 14857000:
349 ssacd |= (0x3 << 4);
350 break;
351 case 32842000:
352 ssacd |= (0x4 << 4);
353 break;
354 case 48000000:
355 ssacd |= (0x5 << 4);
356 break;
357 case 0:
358 /* Disable */
359 break;
360
361 default:
1b340bd7
MB		 362 /* PXA3xx has a clock ditherer which can be used to generate
363 * a wider range of frequencies - calculate a value for it.
364 */
972a55b6 365 if (ssp->type == PXA3xx_SSP) {
1b340bd7
MB		 366 u32 val;
367 u64 tmp = 19968;
368 tmp *= 1000000;
369 do_div(tmp, freq_out);
370 val = tmp;
371
a419aef8 372 val = (val << 16) | 64;
baffe169 373 pxa_ssp_write_reg(ssp, SSACDD, val);
1b340bd7
MB		 374
375 ssacd |= (0x6 << 4);
376
377 dev_dbg(&ssp->pdev->dev,
449bd54d 378 "Using SSACDD %x to supply %uHz\n",
1b340bd7
MB		 379 val, freq_out);
380 break;
381 }
1b340bd7
MB		 382
383 return -EINVAL;
384 }
385
baffe169 386 pxa_ssp_write_reg(ssp, SSACD, ssacd);
1b340bd7
MB		 387
388 return 0;
389}
390
391/*
392 * Set the active slots in TDM/Network mode
393 */
394static int pxa_ssp_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai,
a5479e38 395 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
1b340bd7 396{
f0fba2ad 397 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
f9efc9df 398 struct ssp_device *ssp = priv->ssp;
1b340bd7
MB		 399 u32 sscr0;
400
baffe169 401 sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
a5479e38 402 sscr0 &= ~(SSCR0_MOD | SSCR0_SlotsPerFrm(8) | SSCR0_EDSS | SSCR0_DSS);
1b340bd7 403
a5479e38
DR		 404 /* set slot width */
405 if (slot_width > 16)
406 sscr0 |= SSCR0_EDSS | SSCR0_DataSize(slot_width - 16);
407 else
408 sscr0 |= SSCR0_DataSize(slot_width);
409
410 if (slots > 1) {
411 /* enable network mode */
412 sscr0 |= SSCR0_MOD;
413
414 /* set number of active slots */
415 sscr0 |= SSCR0_SlotsPerFrm(slots);
416
417 /* set active slot mask */
baffe169
HZ		 418 pxa_ssp_write_reg(ssp, SSTSA, tx_mask);
419 pxa_ssp_write_reg(ssp, SSRSA, rx_mask);
a5479e38 420 }
baffe169 421 pxa_ssp_write_reg(ssp, SSCR0, sscr0);
1b340bd7 422
1b340bd7
MB		 423 return 0;
424}
425
426/*
427 * Tristate the SSP DAI lines
428 */
429static int pxa_ssp_set_dai_tristate(struct snd_soc_dai *cpu_dai,
430 int tristate)
431{
f0fba2ad 432 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
f9efc9df 433 struct ssp_device *ssp = priv->ssp;
1b340bd7
MB		 434 u32 sscr1;
435
baffe169 436 sscr1 = pxa_ssp_read_reg(ssp, SSCR1);
1b340bd7
MB		 437 if (tristate)
438 sscr1 &= ~SSCR1_TTE;
439 else
440 sscr1 |= SSCR1_TTE;
baffe169 441 pxa_ssp_write_reg(ssp, SSCR1, sscr1);
1b340bd7
MB		 442
443 return 0;
444}
445
446/*
447 * Set up the SSP DAI format.
448 * The SSP Port must be inactive before calling this function as the
449 * physical interface format is changed.
450 */
451static int pxa_ssp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
452 unsigned int fmt)
453{
f0fba2ad 454 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
f9efc9df 455 struct ssp_device *ssp = priv->ssp;
f5d1e5ed 456 u32 sscr0, sscr1, sspsp, scfr;
1b340bd7 457
cbf1146d
DM		 458 /* check if we need to change anything at all */
459 if (priv->dai_fmt == fmt)
460 return 0;
461
462 /* we can only change the settings if the port is not in use */
baffe169 463 if (pxa_ssp_read_reg(ssp, SSCR0) & SSCR0_SSE) {
cbf1146d
DM		 464 dev_err(&ssp->pdev->dev,
465 "can't change hardware dai format: stream is in use");
466 return -EINVAL;
467 }
468
1b340bd7 469 /* reset port settings */
baffe169 470 sscr0 = pxa_ssp_read_reg(ssp, SSCR0) &
f5d1e5ed 471 ~(SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ACS);
1b340bd7
MB		 472 sscr1 = SSCR1_RxTresh(8) | SSCR1_TxTresh(7);
473 sspsp = 0;
474
475 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
476 case SND_SOC_DAIFMT_CBM_CFM:
f5d1e5ed 477 sscr1 |= SSCR1_SCLKDIR | SSCR1_SFRMDIR | SSCR1_SCFR;
1b340bd7
MB		 478 break;
479 case SND_SOC_DAIFMT_CBM_CFS:
f5d1e5ed 480 sscr1 |= SSCR1_SCLKDIR | SSCR1_SCFR;
1b340bd7
MB		 481 break;
482 case SND_SOC_DAIFMT_CBS_CFS:
483 break;
484 default:
485 return -EINVAL;
486 }
487
fa44c077
DR		 488 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
489 case SND_SOC_DAIFMT_NB_NF:
490 sspsp |= SSPSP_SFRMP;
491 break;
492 case SND_SOC_DAIFMT_NB_IF:
493 break;
494 case SND_SOC_DAIFMT_IB_IF:
495 sspsp |= SSPSP_SCMODE(2);
496 break;
497 case SND_SOC_DAIFMT_IB_NF:
498 sspsp |= SSPSP_SCMODE(2) | SSPSP_SFRMP;
499 break;
500 default:
501 return -EINVAL;
502 }
1b340bd7
MB		 503
504 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
505 case SND_SOC_DAIFMT_I2S:
72d74664 506 sscr0 |= SSCR0_PSP;
1b340bd7 507 sscr1 |= SSCR1_RWOT | SSCR1_TRAIL;
0ce36c5f 508 /* See hw_params() */
1b340bd7
MB		 509 break;
510
511 case SND_SOC_DAIFMT_DSP_A:
512 sspsp |= SSPSP_FSRT;
513 case SND_SOC_DAIFMT_DSP_B:
514 sscr0 |= SSCR0_MOD | SSCR0_PSP;
515 sscr1 |= SSCR1_TRAIL | SSCR1_RWOT;
1b340bd7
MB		 516 break;
517
518 default:
519 return -EINVAL;
520 }
521
baffe169
HZ		 522 pxa_ssp_write_reg(ssp, SSCR0, sscr0);
523 pxa_ssp_write_reg(ssp, SSCR1, sscr1);
524 pxa_ssp_write_reg(ssp, SSPSP, sspsp);
1b340bd7 525
f5d1e5ed
HZ		 526 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
527 case SND_SOC_DAIFMT_CBM_CFM:
528 case SND_SOC_DAIFMT_CBM_CFS:
529 scfr = pxa_ssp_read_reg(ssp, SSCR1) | SSCR1_SCFR;
530 pxa_ssp_write_reg(ssp, SSCR1, scfr);
531
532 while (pxa_ssp_read_reg(ssp, SSSR) & SSSR_BSY)
533 cpu_relax();
534 break;
535 }
536
1b340bd7
MB		 537 dump_registers(ssp);
538
539 /* Since we are configuring the timings for the format by hand
540 * we have to defer some things until hw_params() where we
541 * know parameters like the sample size.
542 */
543 priv->dai_fmt = fmt;
544
545 return 0;
546}
547
548/*
549 * Set the SSP audio DMA parameters and sample size.
550 * Can be called multiple times by oss emulation.
551 */
552static int pxa_ssp_hw_params(struct snd_pcm_substream *substream,
dee89c4d 553 struct snd_pcm_hw_params *params,
f0fba2ad 554 struct snd_soc_dai *cpu_dai)
1b340bd7 555{
f0fba2ad 556 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
f9efc9df 557 struct ssp_device *ssp = priv->ssp;
2d7e71fa 558 int chn = params_channels(params);
1b340bd7
MB		 559 u32 sscr0;
560 u32 sspsp;
561 int width = snd_pcm_format_physical_width(params_format(params));
baffe169 562 int ttsa = pxa_ssp_read_reg(ssp, SSTSA) & 0xf;
5f712b2b
DM		 563 struct pxa2xx_pcm_dma_params *dma_data;
564
f0fba2ad 565 dma_data = snd_soc_dai_get_dma_data(cpu_dai, substream);
1b340bd7 566
92429069
PZ		 567 /* Network mode with one active slot (ttsa == 1) can be used
568 * to force 16-bit frame width on the wire (for S16_LE), even
569 * with two channels. Use 16-bit DMA transfers for this case.
570 */
d93ca1ae 571 pxa_ssp_set_dma_params(ssp,
572 ((chn == 2) && (ttsa != 1)) || (width == 32),
573 substream->stream == SNDRV_PCM_STREAM_PLAYBACK, dma_data);
5f712b2b 574
1b340bd7 575 /* we can only change the settings if the port is not in use */
baffe169 576 if (pxa_ssp_read_reg(ssp, SSCR0) & SSCR0_SSE)
1b340bd7
MB		 577 return 0;
578
579 /* clear selected SSP bits */
baffe169 580 sscr0 = pxa_ssp_read_reg(ssp, SSCR0) & ~(SSCR0_DSS | SSCR0_EDSS);
1b340bd7
MB		 581
582 /* bit size */
1b340bd7
MB		 583 switch (params_format(params)) {
584 case SNDRV_PCM_FORMAT_S16_LE:
972a55b6 585 if (ssp->type == PXA3xx_SSP)
1b340bd7 586 sscr0 |= SSCR0_FPCKE;
1b340bd7 587 sscr0 |= SSCR0_DataSize(16);
1b340bd7
MB		 588 break;
589 case SNDRV_PCM_FORMAT_S24_LE:
590 sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(8));
1b340bd7
MB		 591 break;
592 case SNDRV_PCM_FORMAT_S32_LE:
593 sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(16));
1b340bd7
MB		 594 break;
595 }
baffe169 596 pxa_ssp_write_reg(ssp, SSCR0, sscr0);
1b340bd7
MB		 597
598 switch (priv->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
599 case SND_SOC_DAIFMT_I2S:
baffe169 600 sspsp = pxa_ssp_read_reg(ssp, SSPSP);
72d74664 601
baffe169 602 if ((pxa_ssp_get_scr(ssp) == 4) && (width == 16)) {
72d74664
DM		 603 /* This is a special case where the bitclk is 64fs
604 * and we're not dealing with 2*32 bits of audio
605 * samples.
606 *
607 * The SSP values used for that are all found out by
608 * trying and failing a lot; some of the registers
609 * needed for that mode are only available on PXA3xx.
610 */
972a55b6 611 if (ssp->type != PXA3xx_SSP)
72d74664
DM		 612 return -EINVAL;
613
614 sspsp |= SSPSP_SFRMWDTH(width * 2);
615 sspsp |= SSPSP_SFRMDLY(width * 4);
616 sspsp |= SSPSP_EDMYSTOP(3);
617 sspsp |= SSPSP_DMYSTOP(3);
618 sspsp |= SSPSP_DMYSTRT(1);
0ce36c5f
MB		 619 } else {
620 /* The frame width is the width the LRCLK is
621 * asserted for; the delay is expressed in
622 * half cycle units. We need the extra cycle
623 * because the data starts clocking out one BCLK
624 * after LRCLK changes polarity.
625 */
626 sspsp |= SSPSP_SFRMWDTH(width + 1);
627 sspsp |= SSPSP_SFRMDLY((width + 1) * 2);
628 sspsp |= SSPSP_DMYSTRT(1);
629 }
72d74664 630
baffe169 631 pxa_ssp_write_reg(ssp, SSPSP, sspsp);
1b340bd7
MB		 632 break;
633 default:
634 break;
635 }
636
72d74664 637 /* When we use a network mode, we always require TDM slots
1b340bd7
MB		 638 * - complain loudly and fail if they've not been set up yet.
639 */
92429069 640 if ((sscr0 & SSCR0_MOD) && !ttsa) {
1b340bd7
MB		 641 dev_err(&ssp->pdev->dev, "No TDM timeslot configured\n");
642 return -EINVAL;
643 }
644
645 dump_registers(ssp);
646
647 return 0;
648}
649
273b72c8
DM		 650static void pxa_ssp_set_running_bit(struct snd_pcm_substream *substream,
651 struct ssp_device *ssp, int value)
652{
653 uint32_t sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
654 uint32_t sscr1 = pxa_ssp_read_reg(ssp, SSCR1);
655 uint32_t sspsp = pxa_ssp_read_reg(ssp, SSPSP);
656 uint32_t sssr = pxa_ssp_read_reg(ssp, SSSR);
657
658 if (value && (sscr0 & SSCR0_SSE))
659 pxa_ssp_write_reg(ssp, SSCR0, sscr0 & ~SSCR0_SSE);
660
661 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
662 if (value)
663 sscr1 |= SSCR1_TSRE;
664 else
665 sscr1 &= ~SSCR1_TSRE;
666 } else {
667 if (value)
668 sscr1 |= SSCR1_RSRE;
669 else
670 sscr1 &= ~SSCR1_RSRE;
671 }
672
673 pxa_ssp_write_reg(ssp, SSCR1, sscr1);
674
675 if (value) {
676 pxa_ssp_write_reg(ssp, SSSR, sssr);
677 pxa_ssp_write_reg(ssp, SSPSP, sspsp);
678 pxa_ssp_write_reg(ssp, SSCR0, sscr0 | SSCR0_SSE);
679 }
680}
681
dee89c4d 682static int pxa_ssp_trigger(struct snd_pcm_substream *substream, int cmd,
f0fba2ad 683 struct snd_soc_dai *cpu_dai)
1b340bd7 684{
1b340bd7 685 int ret = 0;
f0fba2ad 686 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
f9efc9df 687 struct ssp_device *ssp = priv->ssp;
1b340bd7
MB		 688 int val;
689
690 switch (cmd) {
691 case SNDRV_PCM_TRIGGER_RESUME:
baffe169 692 pxa_ssp_enable(ssp);
1b340bd7
MB		 693 break;
694 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
273b72c8 695 pxa_ssp_set_running_bit(substream, ssp, 1);
baffe169
HZ		 696 val = pxa_ssp_read_reg(ssp, SSSR);
697 pxa_ssp_write_reg(ssp, SSSR, val);
1b340bd7
MB		 698 break;
699 case SNDRV_PCM_TRIGGER_START:
273b72c8 700 pxa_ssp_set_running_bit(substream, ssp, 1);
1b340bd7
MB		 701 break;
702 case SNDRV_PCM_TRIGGER_STOP:
273b72c8 703 pxa_ssp_set_running_bit(substream, ssp, 0);
1b340bd7
MB		 704 break;
705 case SNDRV_PCM_TRIGGER_SUSPEND:
baffe169 706 pxa_ssp_disable(ssp);
1b340bd7
MB		 707 break;
708 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
273b72c8 709 pxa_ssp_set_running_bit(substream, ssp, 0);
1b340bd7
MB		 710 break;
711
712 default:
713 ret = -EINVAL;
714 }
715
716 dump_registers(ssp);
717
718 return ret;
719}
720
f0fba2ad 721static int pxa_ssp_probe(struct snd_soc_dai *dai)
1b340bd7 722{
2023c90c 723 struct device *dev = dai->dev;
1b340bd7
MB		 724 struct ssp_priv *priv;
725 int ret;
726
727 priv = kzalloc(sizeof(struct ssp_priv), GFP_KERNEL);
728 if (!priv)
729 return -ENOMEM;
730
2023c90c
DM		 731 if (dev->of_node) {
732 struct device_node *ssp_handle;
733
734 ssp_handle = of_parse_phandle(dev->of_node, "port", 0);
735 if (!ssp_handle) {
736 dev_err(dev, "unable to get 'port' phandle\n");
737 return -ENODEV;
738 }
739
740 priv->ssp = pxa_ssp_request_of(ssp_handle, "SoC audio");
741 if (priv->ssp == NULL) {
742 ret = -ENODEV;
743 goto err_priv;
744 }
745 } else {
746 priv->ssp = pxa_ssp_request(dai->id + 1, "SoC audio");
747 if (priv->ssp == NULL) {
748 ret = -ENODEV;
749 goto err_priv;
750 }
1b340bd7
MB		 751 }
752
a5735b7e 753 priv->dai_fmt = (unsigned int) -1;
f0fba2ad 754 snd_soc_dai_set_drvdata(dai, priv);
1b340bd7
MB		 755
756 return 0;
757
758err_priv:
759 kfree(priv);
760 return ret;
761}
762
f0fba2ad 763static int pxa_ssp_remove(struct snd_soc_dai *dai)
1b340bd7 764{
f0fba2ad
LG		 765 struct ssp_priv *priv = snd_soc_dai_get_drvdata(dai);
766
baffe169 767 pxa_ssp_free(priv->ssp);
014a2755 768 kfree(priv);
f0fba2ad 769 return 0;
1b340bd7
MB		 770}
771
772#define PXA_SSP_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
773 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \
8d8bf58b
QZ		 774 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
775 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | \
1b340bd7
MB		 776 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
777
778#define PXA_SSP_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
779 SNDRV_PCM_FMTBIT_S24_LE | \
780 SNDRV_PCM_FMTBIT_S32_LE)
781
85e7652d 782static const struct snd_soc_dai_ops pxa_ssp_dai_ops = {
6335d055
EM		 783 .startup = pxa_ssp_startup,
784 .shutdown = pxa_ssp_shutdown,
785 .trigger = pxa_ssp_trigger,
786 .hw_params = pxa_ssp_hw_params,
787 .set_sysclk = pxa_ssp_set_dai_sysclk,
788 .set_clkdiv = pxa_ssp_set_dai_clkdiv,
789 .set_pll = pxa_ssp_set_dai_pll,
790 .set_fmt = pxa_ssp_set_dai_fmt,
791 .set_tdm_slot = pxa_ssp_set_dai_tdm_slot,
792 .set_tristate = pxa_ssp_set_dai_tristate,
793};
794
f0fba2ad 795static struct snd_soc_dai_driver pxa_ssp_dai = {
1b340bd7
MB		 796 .probe = pxa_ssp_probe,
797 .remove = pxa_ssp_remove,
798 .suspend = pxa_ssp_suspend,
799 .resume = pxa_ssp_resume,
800 .playback = {
801 .channels_min = 1,
f34762b6 802 .channels_max = 8,
1b340bd7
MB		 803 .rates = PXA_SSP_RATES,
804 .formats = PXA_SSP_FORMATS,
805 },
806 .capture = {
807 .channels_min = 1,
f34762b6 808 .channels_max = 8,
1b340bd7
MB		 809 .rates = PXA_SSP_RATES,
810 .formats = PXA_SSP_FORMATS,
811 },
6335d055 812 .ops = &pxa_ssp_dai_ops,
f0fba2ad
LG		 813};
814
e580f1ce
KM		 815static const struct snd_soc_component_driver pxa_ssp_component = {
816 .name = "pxa-ssp",
817};
818
2023c90c
DM		 819#ifdef CONFIG_OF
820static const struct of_device_id pxa_ssp_of_ids[] = {
821 { .compatible = "mrvl,pxa-ssp-dai" },
822};
823#endif
824
570f6fe1 825static int asoc_ssp_probe(struct platform_device *pdev)
f0fba2ad 826{
e580f1ce
KM		 827 return snd_soc_register_component(&pdev->dev, &pxa_ssp_component,
828 &pxa_ssp_dai, 1);
f0fba2ad
LG		 829}
830
570f6fe1 831static int asoc_ssp_remove(struct platform_device *pdev)
f0fba2ad 832{
e580f1ce 833 snd_soc_unregister_component(&pdev->dev);
f0fba2ad
LG		 834 return 0;
835}
836
837static struct platform_driver asoc_ssp_driver = {
838 .driver = {
2023c90c
DM		 839 .name = "pxa-ssp-dai",
840 .owner = THIS_MODULE,
841 .of_match_table = of_match_ptr(pxa_ssp_of_ids),
1b340bd7 842 },
f0fba2ad
LG		 843
844 .probe = asoc_ssp_probe,
570f6fe1 845 .remove = asoc_ssp_remove,
1b340bd7 846};
1b340bd7 847
2f702a19 848module_platform_driver(asoc_ssp_driver);
3f4b783c 849
1b340bd7
MB		 850/* Module information */
851MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
852MODULE_DESCRIPTION("PXA SSP/PCM SoC Interface");
853MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)