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Merge branch 'for-rmk/samsung6' of git://git.fluff.org/bjdooks/linux into devel-stable
[linux-2.6-block.git] / sound / soc / pxa / pxa-ssp.c
CommitLineData
1b340bd7
MB		 1/*
2 * pxa-ssp.c -- ALSA Soc Audio Layer
3 *
4 * Copyright 2005,2008 Wolfson Microelectronics PLC.
5 * Author: Liam Girdwood
6 * Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * TODO:
14 * o Test network mode for > 16bit sample size
15 */
16
17#include <linux/init.h>
18#include <linux/module.h>
19#include <linux/platform_device.h>
20#include <linux/clk.h>
21#include <linux/io.h>
22
0664678a
PZ		 23#include <asm/irq.h>
24
1b340bd7
MB		 25#include <sound/core.h>
26#include <sound/pcm.h>
27#include <sound/initval.h>
28#include <sound/pcm_params.h>
29#include <sound/soc.h>
30#include <sound/pxa2xx-lib.h>
31
32#include <mach/hardware.h>
7ebc8d56 33#include <mach/dma.h>
1b340bd7
MB		 34#include <mach/regs-ssp.h>
35#include <mach/audio.h>
36#include <mach/ssp.h>
37
38#include "pxa2xx-pcm.h"
39#include "pxa-ssp.h"
40
41/*
42 * SSP audio private data
43 */
44struct ssp_priv {
f9efc9df 45 struct ssp_device *ssp;
1b340bd7
MB		 46 unsigned int sysclk;
47 int dai_fmt;
48#ifdef CONFIG_PM
f9efc9df
EM		 49 uint32_t cr0;
50 uint32_t cr1;
51 uint32_t to;
52 uint32_t psp;
1b340bd7
MB		 53#endif
54};
55
1b340bd7
MB		 56static void dump_registers(struct ssp_device *ssp)
57{
58 dev_dbg(&ssp->pdev->dev, "SSCR0 0x%08x SSCR1 0x%08x SSTO 0x%08x\n",
59 ssp_read_reg(ssp, SSCR0), ssp_read_reg(ssp, SSCR1),
60 ssp_read_reg(ssp, SSTO));
61
62 dev_dbg(&ssp->pdev->dev, "SSPSP 0x%08x SSSR 0x%08x SSACD 0x%08x\n",
63 ssp_read_reg(ssp, SSPSP), ssp_read_reg(ssp, SSSR),
64 ssp_read_reg(ssp, SSACD));
65}
66
f9efc9df
EM		 67static void ssp_enable(struct ssp_device *ssp)
68{
69 uint32_t sscr0;
70
71 sscr0 = __raw_readl(ssp->mmio_base + SSCR0) | SSCR0_SSE;
72 __raw_writel(sscr0, ssp->mmio_base + SSCR0);
73}
74
75static void ssp_disable(struct ssp_device *ssp)
76{
77 uint32_t sscr0;
78
79 sscr0 = __raw_readl(ssp->mmio_base + SSCR0) & ~SSCR0_SSE;
80 __raw_writel(sscr0, ssp->mmio_base + SSCR0);
81}
82
2d7e71fa
EM		 83struct pxa2xx_pcm_dma_data {
84 struct pxa2xx_pcm_dma_params params;
85 char name[20];
1b340bd7
MB		 86};
87
2d7e71fa 88static struct pxa2xx_pcm_dma_params *
8eb9feab 89ssp_get_dma_params(struct ssp_device *ssp, int width4, int out)
2d7e71fa
EM		 90{
91 struct pxa2xx_pcm_dma_data *dma;
92
93 dma = kzalloc(sizeof(struct pxa2xx_pcm_dma_data), GFP_KERNEL);
94 if (dma == NULL)
95 return NULL;
96
97 snprintf(dma->name, 20, "SSP%d PCM %s %s", ssp->port_id,
8eb9feab 98 width4 ? "32-bit" : "16-bit", out ? "out" : "in");
2d7e71fa
EM		 99
100 dma->params.name = dma->name;
101 dma->params.drcmr = &DRCMR(out ? ssp->drcmr_tx : ssp->drcmr_rx);
102 dma->params.dcmd = (out ? (DCMD_INCSRCADDR | DCMD_FLOWTRG) :
103 (DCMD_INCTRGADDR | DCMD_FLOWSRC)) |
8eb9feab 104 (width4 ? DCMD_WIDTH4 : DCMD_WIDTH2) | DCMD_BURST16;
2d7e71fa
EM		 105 dma->params.dev_addr = ssp->phys_base + SSDR;
106
107 return &dma->params;
108}
109
dee89c4d
MB		 110static int pxa_ssp_startup(struct snd_pcm_substream *substream,
111 struct snd_soc_dai *dai)
1b340bd7
MB		 112{
113 struct snd_soc_pcm_runtime *rtd = substream->private_data;
114 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
115 struct ssp_priv *priv = cpu_dai->private_data;
f9efc9df 116 struct ssp_device *ssp = priv->ssp;
1b340bd7
MB		 117 int ret = 0;
118
119 if (!cpu_dai->active) {
f9efc9df
EM		 120 clk_enable(ssp->clk);
121 ssp_disable(ssp);
1b340bd7 122 }
2d7e71fa
EM		 123
124 if (cpu_dai->dma_data) {
125 kfree(cpu_dai->dma_data);
126 cpu_dai->dma_data = NULL;
127 }
1b340bd7
MB		 128 return ret;
129}
130
dee89c4d
MB		 131static void pxa_ssp_shutdown(struct snd_pcm_substream *substream,
132 struct snd_soc_dai *dai)
1b340bd7
MB		 133{
134 struct snd_soc_pcm_runtime *rtd = substream->private_data;
135 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
136 struct ssp_priv *priv = cpu_dai->private_data;
f9efc9df 137 struct ssp_device *ssp = priv->ssp;
1b340bd7
MB		 138
139 if (!cpu_dai->active) {
f9efc9df
EM		 140 ssp_disable(ssp);
141 clk_disable(ssp->clk);
1b340bd7 142 }
2d7e71fa
EM		 143
144 if (cpu_dai->dma_data) {
145 kfree(cpu_dai->dma_data);
146 cpu_dai->dma_data = NULL;
147 }
1b340bd7
MB		 148}
149
150#ifdef CONFIG_PM
151
dc7d7b83 152static int pxa_ssp_suspend(struct snd_soc_dai *cpu_dai)
1b340bd7
MB		 153{
154 struct ssp_priv *priv = cpu_dai->private_data;
f9efc9df 155 struct ssp_device *ssp = priv->ssp;
1b340bd7
MB		 156
157 if (!cpu_dai->active)
158 return 0;
159
f9efc9df
EM		 160 priv->cr0 = __raw_readl(ssp->mmio_base + SSCR0);
161 priv->cr1 = __raw_readl(ssp->mmio_base + SSCR1);
162 priv->to = __raw_readl(ssp->mmio_base + SSTO);
163 priv->psp = __raw_readl(ssp->mmio_base + SSPSP);
164
165 ssp_disable(ssp);
166 clk_disable(ssp->clk);
1b340bd7
MB		 167 return 0;
168}
169
dc7d7b83 170static int pxa_ssp_resume(struct snd_soc_dai *cpu_dai)
1b340bd7
MB		 171{
172 struct ssp_priv *priv = cpu_dai->private_data;
f9efc9df
EM		 173 struct ssp_device *ssp = priv->ssp;
174 uint32_t sssr = SSSR_ROR | SSSR_TUR | SSSR_BCE;
1b340bd7
MB		 175
176 if (!cpu_dai->active)
177 return 0;
178
f9efc9df
EM		 179 clk_enable(ssp->clk);
180
181 __raw_writel(sssr, ssp->mmio_base + SSSR);
1b340bd7 182
f9efc9df
EM		 183 __raw_writel(priv->cr0 & ~SSCR0_SSE, ssp->mmio_base + SSCR0);
184 __raw_writel(priv->cr1, ssp->mmio_base + SSCR1);
185 __raw_writel(priv->to, ssp->mmio_base + SSTO);
186 __raw_writel(priv->psp, ssp->mmio_base + SSPSP);
187 __raw_writel(priv->cr0 | SSCR0_SSE, ssp->mmio_base + SSCR0);
1b340bd7
MB		 188 return 0;
189}
190
191#else
192#define pxa_ssp_suspend NULL
193#define pxa_ssp_resume NULL
194#endif
195
196/**
197 * ssp_set_clkdiv - set SSP clock divider
198 * @div: serial clock rate divider
199 */
1a297286 200static void ssp_set_scr(struct ssp_device *ssp, u32 div)
1b340bd7 201{
1a297286
PZ		 202 u32 sscr0 = ssp_read_reg(ssp, SSCR0);
203
204 if (cpu_is_pxa25x() && ssp->type == PXA25x_SSP) {
205 sscr0 &= ~0x0000ff00;
206 sscr0 |= ((div - 2)/2) << 8; /* 2..512 */
207 } else {
208 sscr0 &= ~0x000fff00;
209 sscr0 |= (div - 1) << 8; /* 1..4096 */
210 }
211 ssp_write_reg(ssp, SSCR0, sscr0);
212}
213
214/**
215 * ssp_get_clkdiv - get SSP clock divider
216 */
217static u32 ssp_get_scr(struct ssp_device *ssp)
218{
219 u32 sscr0 = ssp_read_reg(ssp, SSCR0);
220 u32 div;
1b340bd7 221
1a297286
PZ		 222 if (cpu_is_pxa25x() && ssp->type == PXA25x_SSP)
223 div = ((sscr0 >> 8) & 0xff) * 2 + 2;
224 else
225 div = ((sscr0 >> 8) & 0xfff) + 1;
226 return div;
1b340bd7
MB		 227}
228
229/*
230 * Set the SSP ports SYSCLK.
231 */
232static int pxa_ssp_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
233 int clk_id, unsigned int freq, int dir)
234{
235 struct ssp_priv *priv = cpu_dai->private_data;
f9efc9df 236 struct ssp_device *ssp = priv->ssp;
1b340bd7
MB		 237 int val;
238
239 u32 sscr0 = ssp_read_reg(ssp, SSCR0) &
20a41eac 240 ~(SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ACS);
1b340bd7
MB		 241
242 dev_dbg(&ssp->pdev->dev,
449bd54d 243 "pxa_ssp_set_dai_sysclk id: %d, clk_id %d, freq %u\n",
1b340bd7
MB		 244 cpu_dai->id, clk_id, freq);
245
246 switch (clk_id) {
247 case PXA_SSP_CLK_NET_PLL:
248 sscr0 |= SSCR0_MOD;
249 break;
250 case PXA_SSP_CLK_PLL:
251 /* Internal PLL is fixed */
252 if (cpu_is_pxa25x())
253 priv->sysclk = 1843200;
254 else
255 priv->sysclk = 13000000;
256 break;
257 case PXA_SSP_CLK_EXT:
258 priv->sysclk = freq;
259 sscr0 |= SSCR0_ECS;
260 break;
261 case PXA_SSP_CLK_NET:
262 priv->sysclk = freq;
263 sscr0 |= SSCR0_NCS | SSCR0_MOD;
264 break;
265 case PXA_SSP_CLK_AUDIO:
266 priv->sysclk = 0;
1a297286 267 ssp_set_scr(ssp, 1);
20a41eac 268 sscr0 |= SSCR0_ACS;
1b340bd7
MB		 269 break;
270 default:
271 return -ENODEV;
272 }
273
274 /* The SSP clock must be disabled when changing SSP clock mode
275 * on PXA2xx. On PXA3xx it must be enabled when doing so. */
276 if (!cpu_is_pxa3xx())
f9efc9df 277 clk_disable(ssp->clk);
1b340bd7
MB		 278 val = ssp_read_reg(ssp, SSCR0) | sscr0;
279 ssp_write_reg(ssp, SSCR0, val);
280 if (!cpu_is_pxa3xx())
f9efc9df 281 clk_enable(ssp->clk);
1b340bd7
MB		 282
283 return 0;
284}
285
286/*
287 * Set the SSP clock dividers.
288 */
289static int pxa_ssp_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
290 int div_id, int div)
291{
292 struct ssp_priv *priv = cpu_dai->private_data;
f9efc9df 293 struct ssp_device *ssp = priv->ssp;
1b340bd7
MB		 294 int val;
295
296 switch (div_id) {
297 case PXA_SSP_AUDIO_DIV_ACDS:
298 val = (ssp_read_reg(ssp, SSACD) & ~0x7) | SSACD_ACDS(div);
299 ssp_write_reg(ssp, SSACD, val);
300 break;
301 case PXA_SSP_AUDIO_DIV_SCDB:
302 val = ssp_read_reg(ssp, SSACD);
303 val &= ~SSACD_SCDB;
304#if defined(CONFIG_PXA3xx)
305 if (cpu_is_pxa3xx())
306 val &= ~SSACD_SCDX8;
307#endif
308 switch (div) {
309 case PXA_SSP_CLK_SCDB_1:
310 val |= SSACD_SCDB;
311 break;
312 case PXA_SSP_CLK_SCDB_4:
313 break;
314#if defined(CONFIG_PXA3xx)
315 case PXA_SSP_CLK_SCDB_8:
316 if (cpu_is_pxa3xx())
317 val |= SSACD_SCDX8;
318 else
319 return -EINVAL;
320 break;
321#endif
322 default:
323 return -EINVAL;
324 }
325 ssp_write_reg(ssp, SSACD, val);
326 break;
327 case PXA_SSP_DIV_SCR:
1a297286 328 ssp_set_scr(ssp, div);
1b340bd7
MB		 329 break;
330 default:
331 return -ENODEV;
332 }
333
334 return 0;
335}
336
337/*
338 * Configure the PLL frequency pxa27x and (afaik - pxa320 only)
339 */
85488037
MB		 340static int pxa_ssp_set_dai_pll(struct snd_soc_dai *cpu_dai, int pll_id,
341 int source, unsigned int freq_in, unsigned int freq_out)
1b340bd7
MB		 342{
343 struct ssp_priv *priv = cpu_dai->private_data;
f9efc9df 344 struct ssp_device *ssp = priv->ssp;
1b340bd7
MB		 345 u32 ssacd = ssp_read_reg(ssp, SSACD) & ~0x70;
346
347#if defined(CONFIG_PXA3xx)
348 if (cpu_is_pxa3xx())
349 ssp_write_reg(ssp, SSACDD, 0);
350#endif
351
352 switch (freq_out) {
353 case 5622000:
354 break;
355 case 11345000:
356 ssacd |= (0x1 << 4);
357 break;
358 case 12235000:
359 ssacd |= (0x2 << 4);
360 break;
361 case 14857000:
362 ssacd |= (0x3 << 4);
363 break;
364 case 32842000:
365 ssacd |= (0x4 << 4);
366 break;
367 case 48000000:
368 ssacd |= (0x5 << 4);
369 break;
370 case 0:
371 /* Disable */
372 break;
373
374 default:
375#ifdef CONFIG_PXA3xx
376 /* PXA3xx has a clock ditherer which can be used to generate
377 * a wider range of frequencies - calculate a value for it.
378 */
379 if (cpu_is_pxa3xx()) {
380 u32 val;
381 u64 tmp = 19968;
382 tmp *= 1000000;
383 do_div(tmp, freq_out);
384 val = tmp;
385
a419aef8 386 val = (val << 16) | 64;
1b340bd7
MB		 387 ssp_write_reg(ssp, SSACDD, val);
388
389 ssacd |= (0x6 << 4);
390
391 dev_dbg(&ssp->pdev->dev,
449bd54d 392 "Using SSACDD %x to supply %uHz\n",
1b340bd7
MB		 393 val, freq_out);
394 break;
395 }
396#endif
397
398 return -EINVAL;
399 }
400
401 ssp_write_reg(ssp, SSACD, ssacd);
402
403 return 0;
404}
405
406/*
407 * Set the active slots in TDM/Network mode
408 */
409static int pxa_ssp_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai,
a5479e38 410 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
1b340bd7
MB		 411{
412 struct ssp_priv *priv = cpu_dai->private_data;
f9efc9df 413 struct ssp_device *ssp = priv->ssp;
1b340bd7
MB		 414 u32 sscr0;
415
a5479e38
DR		 416 sscr0 = ssp_read_reg(ssp, SSCR0);
417 sscr0 &= ~(SSCR0_MOD | SSCR0_SlotsPerFrm(8) | SSCR0_EDSS | SSCR0_DSS);
1b340bd7 418
a5479e38
DR		 419 /* set slot width */
420 if (slot_width > 16)
421 sscr0 |= SSCR0_EDSS | SSCR0_DataSize(slot_width - 16);
422 else
423 sscr0 |= SSCR0_DataSize(slot_width);
424
425 if (slots > 1) {
426 /* enable network mode */
427 sscr0 |= SSCR0_MOD;
428
429 /* set number of active slots */
430 sscr0 |= SSCR0_SlotsPerFrm(slots);
431
432 /* set active slot mask */
433 ssp_write_reg(ssp, SSTSA, tx_mask);
434 ssp_write_reg(ssp, SSRSA, rx_mask);
435 }
1b340bd7
MB		 436 ssp_write_reg(ssp, SSCR0, sscr0);
437
1b340bd7
MB		 438 return 0;
439}
440
441/*
442 * Tristate the SSP DAI lines
443 */
444static int pxa_ssp_set_dai_tristate(struct snd_soc_dai *cpu_dai,
445 int tristate)
446{
447 struct ssp_priv *priv = cpu_dai->private_data;
f9efc9df 448 struct ssp_device *ssp = priv->ssp;
1b340bd7
MB		 449 u32 sscr1;
450
451 sscr1 = ssp_read_reg(ssp, SSCR1);
452 if (tristate)
453 sscr1 &= ~SSCR1_TTE;
454 else
455 sscr1 |= SSCR1_TTE;
456 ssp_write_reg(ssp, SSCR1, sscr1);
457
458 return 0;
459}
460
461/*
462 * Set up the SSP DAI format.
463 * The SSP Port must be inactive before calling this function as the
464 * physical interface format is changed.
465 */
466static int pxa_ssp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
467 unsigned int fmt)
468{
469 struct ssp_priv *priv = cpu_dai->private_data;
f9efc9df 470 struct ssp_device *ssp = priv->ssp;
1b340bd7
MB		 471 u32 sscr0;
472 u32 sscr1;
473 u32 sspsp;
474
cbf1146d
DM		 475 /* check if we need to change anything at all */
476 if (priv->dai_fmt == fmt)
477 return 0;
478
479 /* we can only change the settings if the port is not in use */
480 if (ssp_read_reg(ssp, SSCR0) & SSCR0_SSE) {
481 dev_err(&ssp->pdev->dev,
482 "can't change hardware dai format: stream is in use");
483 return -EINVAL;
484 }
485
1b340bd7
MB		 486 /* reset port settings */
487 sscr0 = ssp_read_reg(ssp, SSCR0) &
20a41eac 488 (SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ACS);
1b340bd7
MB		 489 sscr1 = SSCR1_RxTresh(8) | SSCR1_TxTresh(7);
490 sspsp = 0;
491
492 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
493 case SND_SOC_DAIFMT_CBM_CFM:
494 sscr1 |= SSCR1_SCLKDIR | SSCR1_SFRMDIR;
495 break;
496 case SND_SOC_DAIFMT_CBM_CFS:
497 sscr1 |= SSCR1_SCLKDIR;
498 break;
499 case SND_SOC_DAIFMT_CBS_CFS:
500 break;
501 default:
502 return -EINVAL;
503 }
504
fa44c077
DR		 505 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
506 case SND_SOC_DAIFMT_NB_NF:
507 sspsp |= SSPSP_SFRMP;
508 break;
509 case SND_SOC_DAIFMT_NB_IF:
510 break;
511 case SND_SOC_DAIFMT_IB_IF:
512 sspsp |= SSPSP_SCMODE(2);
513 break;
514 case SND_SOC_DAIFMT_IB_NF:
515 sspsp |= SSPSP_SCMODE(2) | SSPSP_SFRMP;
516 break;
517 default:
518 return -EINVAL;
519 }
1b340bd7
MB		 520
521 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
522 case SND_SOC_DAIFMT_I2S:
72d74664 523 sscr0 |= SSCR0_PSP;
1b340bd7 524 sscr1 |= SSCR1_RWOT | SSCR1_TRAIL;
0ce36c5f 525 /* See hw_params() */
1b340bd7
MB		 526 break;
527
528 case SND_SOC_DAIFMT_DSP_A:
529 sspsp |= SSPSP_FSRT;
530 case SND_SOC_DAIFMT_DSP_B:
531 sscr0 |= SSCR0_MOD | SSCR0_PSP;
532 sscr1 |= SSCR1_TRAIL | SSCR1_RWOT;
1b340bd7
MB		 533 break;
534
535 default:
536 return -EINVAL;
537 }
538
539 ssp_write_reg(ssp, SSCR0, sscr0);
540 ssp_write_reg(ssp, SSCR1, sscr1);
541 ssp_write_reg(ssp, SSPSP, sspsp);
542
543 dump_registers(ssp);
544
545 /* Since we are configuring the timings for the format by hand
546 * we have to defer some things until hw_params() where we
547 * know parameters like the sample size.
548 */
549 priv->dai_fmt = fmt;
550
551 return 0;
552}
553
554/*
555 * Set the SSP audio DMA parameters and sample size.
556 * Can be called multiple times by oss emulation.
557 */
558static int pxa_ssp_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 559 struct snd_pcm_hw_params *params,
560 struct snd_soc_dai *dai)
1b340bd7
MB		 561{
562 struct snd_soc_pcm_runtime *rtd = substream->private_data;
563 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
564 struct ssp_priv *priv = cpu_dai->private_data;
f9efc9df 565 struct ssp_device *ssp = priv->ssp;
2d7e71fa 566 int chn = params_channels(params);
1b340bd7
MB		 567 u32 sscr0;
568 u32 sspsp;
569 int width = snd_pcm_format_physical_width(params_format(params));
92429069 570 int ttsa = ssp_read_reg(ssp, SSTSA) & 0xf;
1b340bd7 571
2d7e71fa
EM		 572 /* generate correct DMA params */
573 if (cpu_dai->dma_data)
574 kfree(cpu_dai->dma_data);
575
92429069
PZ		 576 /* Network mode with one active slot (ttsa == 1) can be used
577 * to force 16-bit frame width on the wire (for S16_LE), even
578 * with two channels. Use 16-bit DMA transfers for this case.
579 */
2d7e71fa
EM		 580 cpu_dai->dma_data = ssp_get_dma_params(ssp,
581 ((chn == 2) && (ttsa != 1)) || (width == 32),
582 substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
1b340bd7
MB		 583
584 /* we can only change the settings if the port is not in use */
585 if (ssp_read_reg(ssp, SSCR0) & SSCR0_SSE)
586 return 0;
587
588 /* clear selected SSP bits */
589 sscr0 = ssp_read_reg(ssp, SSCR0) & ~(SSCR0_DSS | SSCR0_EDSS);
590 ssp_write_reg(ssp, SSCR0, sscr0);
591
592 /* bit size */
593 sscr0 = ssp_read_reg(ssp, SSCR0);
594 switch (params_format(params)) {
595 case SNDRV_PCM_FORMAT_S16_LE:
596#ifdef CONFIG_PXA3xx
597 if (cpu_is_pxa3xx())
598 sscr0 |= SSCR0_FPCKE;
599#endif
600 sscr0 |= SSCR0_DataSize(16);
1b340bd7
MB		 601 break;
602 case SNDRV_PCM_FORMAT_S24_LE:
603 sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(8));
1b340bd7
MB		 604 break;
605 case SNDRV_PCM_FORMAT_S32_LE:
606 sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(16));
1b340bd7
MB		 607 break;
608 }
609 ssp_write_reg(ssp, SSCR0, sscr0);
610
611 switch (priv->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
612 case SND_SOC_DAIFMT_I2S:
72d74664
DM		 613 sspsp = ssp_read_reg(ssp, SSPSP);
614
1a297286 615 if ((ssp_get_scr(ssp) == 4) && (width == 16)) {
72d74664
DM		 616 /* This is a special case where the bitclk is 64fs
617 * and we're not dealing with 2*32 bits of audio
618 * samples.
619 *
620 * The SSP values used for that are all found out by
621 * trying and failing a lot; some of the registers
622 * needed for that mode are only available on PXA3xx.
623 */
624
625#ifdef CONFIG_PXA3xx
626 if (!cpu_is_pxa3xx())
627 return -EINVAL;
628
629 sspsp |= SSPSP_SFRMWDTH(width * 2);
630 sspsp |= SSPSP_SFRMDLY(width * 4);
631 sspsp |= SSPSP_EDMYSTOP(3);
632 sspsp |= SSPSP_DMYSTOP(3);
633 sspsp |= SSPSP_DMYSTRT(1);
634#else
635 return -EINVAL;
636#endif
0ce36c5f
MB		 637 } else {
638 /* The frame width is the width the LRCLK is
639 * asserted for; the delay is expressed in
640 * half cycle units. We need the extra cycle
641 * because the data starts clocking out one BCLK
642 * after LRCLK changes polarity.
643 */
644 sspsp |= SSPSP_SFRMWDTH(width + 1);
645 sspsp |= SSPSP_SFRMDLY((width + 1) * 2);
646 sspsp |= SSPSP_DMYSTRT(1);
647 }
72d74664 648
1b340bd7
MB		 649 ssp_write_reg(ssp, SSPSP, sspsp);
650 break;
651 default:
652 break;
653 }
654
72d74664 655 /* When we use a network mode, we always require TDM slots
1b340bd7
MB		 656 * - complain loudly and fail if they've not been set up yet.
657 */
92429069 658 if ((sscr0 & SSCR0_MOD) && !ttsa) {
1b340bd7
MB		 659 dev_err(&ssp->pdev->dev, "No TDM timeslot configured\n");
660 return -EINVAL;
661 }
662
663 dump_registers(ssp);
664
665 return 0;
666}
667
dee89c4d
MB		 668static int pxa_ssp_trigger(struct snd_pcm_substream *substream, int cmd,
669 struct snd_soc_dai *dai)
1b340bd7
MB		 670{
671 struct snd_soc_pcm_runtime *rtd = substream->private_data;
672 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
673 int ret = 0;
674 struct ssp_priv *priv = cpu_dai->private_data;
f9efc9df 675 struct ssp_device *ssp = priv->ssp;
1b340bd7
MB		 676 int val;
677
678 switch (cmd) {
679 case SNDRV_PCM_TRIGGER_RESUME:
f9efc9df 680 ssp_enable(ssp);
1b340bd7
MB		 681 break;
682 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
683 val = ssp_read_reg(ssp, SSCR1);
684 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
685 val |= SSCR1_TSRE;
686 else
687 val |= SSCR1_RSRE;
688 ssp_write_reg(ssp, SSCR1, val);
689 val = ssp_read_reg(ssp, SSSR);
690 ssp_write_reg(ssp, SSSR, val);
691 break;
692 case SNDRV_PCM_TRIGGER_START:
693 val = ssp_read_reg(ssp, SSCR1);
694 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
695 val |= SSCR1_TSRE;
696 else
697 val |= SSCR1_RSRE;
698 ssp_write_reg(ssp, SSCR1, val);
f9efc9df 699 ssp_enable(ssp);
1b340bd7
MB		 700 break;
701 case SNDRV_PCM_TRIGGER_STOP:
702 val = ssp_read_reg(ssp, SSCR1);
703 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
704 val &= ~SSCR1_TSRE;
705 else
706 val &= ~SSCR1_RSRE;
707 ssp_write_reg(ssp, SSCR1, val);
708 break;
709 case SNDRV_PCM_TRIGGER_SUSPEND:
f9efc9df 710 ssp_disable(ssp);
1b340bd7
MB		 711 break;
712 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
713 val = ssp_read_reg(ssp, SSCR1);
714 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
715 val &= ~SSCR1_TSRE;
716 else
717 val &= ~SSCR1_RSRE;
718 ssp_write_reg(ssp, SSCR1, val);
719 break;
720
721 default:
722 ret = -EINVAL;
723 }
724
725 dump_registers(ssp);
726
727 return ret;
728}
729
730static int pxa_ssp_probe(struct platform_device *pdev,
731 struct snd_soc_dai *dai)
732{
733 struct ssp_priv *priv;
734 int ret;
735
736 priv = kzalloc(sizeof(struct ssp_priv), GFP_KERNEL);
737 if (!priv)
738 return -ENOMEM;
739
f9efc9df
EM		 740 priv->ssp = ssp_request(dai->id + 1, "SoC audio");
741 if (priv->ssp == NULL) {
1b340bd7
MB		 742 ret = -ENODEV;
743 goto err_priv;
744 }
745
a5735b7e 746 priv->dai_fmt = (unsigned int) -1;
1b340bd7
MB		 747 dai->private_data = priv;
748
749 return 0;
750
751err_priv:
752 kfree(priv);
753 return ret;
754}
755
756static void pxa_ssp_remove(struct platform_device *pdev,
757 struct snd_soc_dai *dai)
758{
759 struct ssp_priv *priv = dai->private_data;
f9efc9df 760 ssp_free(priv->ssp);
1b340bd7
MB		 761}
762
763#define PXA_SSP_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
764 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \
765 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | \
766 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
767
768#define PXA_SSP_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
769 SNDRV_PCM_FMTBIT_S24_LE | \
770 SNDRV_PCM_FMTBIT_S32_LE)
771
6335d055
EM		 772static struct snd_soc_dai_ops pxa_ssp_dai_ops = {
773 .startup = pxa_ssp_startup,
774 .shutdown = pxa_ssp_shutdown,
775 .trigger = pxa_ssp_trigger,
776 .hw_params = pxa_ssp_hw_params,
777 .set_sysclk = pxa_ssp_set_dai_sysclk,
778 .set_clkdiv = pxa_ssp_set_dai_clkdiv,
779 .set_pll = pxa_ssp_set_dai_pll,
780 .set_fmt = pxa_ssp_set_dai_fmt,
781 .set_tdm_slot = pxa_ssp_set_dai_tdm_slot,
782 .set_tristate = pxa_ssp_set_dai_tristate,
783};
784
1b340bd7
MB		 785struct snd_soc_dai pxa_ssp_dai[] = {
786 {
787 .name = "pxa2xx-ssp1",
788 .id = 0,
1b340bd7
MB		 789 .probe = pxa_ssp_probe,
790 .remove = pxa_ssp_remove,
791 .suspend = pxa_ssp_suspend,
792 .resume = pxa_ssp_resume,
793 .playback = {
794 .channels_min = 1,
f34762b6 795 .channels_max = 8,
1b340bd7
MB		 796 .rates = PXA_SSP_RATES,
797 .formats = PXA_SSP_FORMATS,
798 },
799 .capture = {
800 .channels_min = 1,
f34762b6 801 .channels_max = 8,
1b340bd7
MB		 802 .rates = PXA_SSP_RATES,
803 .formats = PXA_SSP_FORMATS,
804 },
6335d055 805 .ops = &pxa_ssp_dai_ops,
1b340bd7
MB		 806 },
807 { .name = "pxa2xx-ssp2",
808 .id = 1,
1b340bd7
MB		 809 .probe = pxa_ssp_probe,
810 .remove = pxa_ssp_remove,
811 .suspend = pxa_ssp_suspend,
812 .resume = pxa_ssp_resume,
813 .playback = {
814 .channels_min = 1,
f34762b6 815 .channels_max = 8,
1b340bd7
MB		 816 .rates = PXA_SSP_RATES,
817 .formats = PXA_SSP_FORMATS,
818 },
819 .capture = {
820 .channels_min = 1,
f34762b6 821 .channels_max = 8,
1b340bd7
MB		 822 .rates = PXA_SSP_RATES,
823 .formats = PXA_SSP_FORMATS,
824 },
6335d055 825 .ops = &pxa_ssp_dai_ops,
1b340bd7
MB		 826 },
827 {
828 .name = "pxa2xx-ssp3",
829 .id = 2,
1b340bd7
MB		 830 .probe = pxa_ssp_probe,
831 .remove = pxa_ssp_remove,
832 .suspend = pxa_ssp_suspend,
833 .resume = pxa_ssp_resume,
834 .playback = {
835 .channels_min = 1,
f34762b6 836 .channels_max = 8,
1b340bd7
MB		 837 .rates = PXA_SSP_RATES,
838 .formats = PXA_SSP_FORMATS,
839 },
840 .capture = {
841 .channels_min = 1,
f34762b6 842 .channels_max = 8,
1b340bd7
MB		 843 .rates = PXA_SSP_RATES,
844 .formats = PXA_SSP_FORMATS,
845 },
6335d055 846 .ops = &pxa_ssp_dai_ops,
1b340bd7
MB		 847 },
848 {
849 .name = "pxa2xx-ssp4",
850 .id = 3,
1b340bd7
MB		 851 .probe = pxa_ssp_probe,
852 .remove = pxa_ssp_remove,
853 .suspend = pxa_ssp_suspend,
854 .resume = pxa_ssp_resume,
855 .playback = {
856 .channels_min = 1,
f34762b6 857 .channels_max = 8,
1b340bd7
MB		 858 .rates = PXA_SSP_RATES,
859 .formats = PXA_SSP_FORMATS,
860 },
861 .capture = {
862 .channels_min = 1,
f34762b6 863 .channels_max = 8,
1b340bd7
MB		 864 .rates = PXA_SSP_RATES,
865 .formats = PXA_SSP_FORMATS,
866 },
6335d055 867 .ops = &pxa_ssp_dai_ops,
1b340bd7
MB		 868 },
869};
870EXPORT_SYMBOL_GPL(pxa_ssp_dai);
871
c9b3a40f 872static int __init pxa_ssp_init(void)
3f4b783c
MB		 873{
874 return snd_soc_register_dais(pxa_ssp_dai, ARRAY_SIZE(pxa_ssp_dai));
875}
876module_init(pxa_ssp_init);
877
878static void __exit pxa_ssp_exit(void)
879{
880 snd_soc_unregister_dais(pxa_ssp_dai, ARRAY_SIZE(pxa_ssp_dai));
881}
882module_exit(pxa_ssp_exit);
883
1b340bd7
MB		 884/* Module information */
885MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
886MODULE_DESCRIPTION("PXA SSP/PCM SoC Interface");
887MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)