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1b340bd7 MB |
1 | /* |
2 | * pxa-ssp.c -- ALSA Soc Audio Layer | |
3 | * | |
4 | * Copyright 2005,2008 Wolfson Microelectronics PLC. | |
5 | * Author: Liam Girdwood | |
6 | * Mark Brown <broonie@opensource.wolfsonmicro.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | * | |
13 | * TODO: | |
14 | * o Test network mode for > 16bit sample size | |
15 | */ | |
16 | ||
17 | #include <linux/init.h> | |
18 | #include <linux/module.h> | |
5a0e3ad6 | 19 | #include <linux/slab.h> |
1b340bd7 MB |
20 | #include <linux/platform_device.h> |
21 | #include <linux/clk.h> | |
22 | #include <linux/io.h> | |
8348c259 | 23 | #include <linux/pxa2xx_ssp.h> |
1b340bd7 | 24 | |
0664678a PZ |
25 | #include <asm/irq.h> |
26 | ||
1b340bd7 MB |
27 | #include <sound/core.h> |
28 | #include <sound/pcm.h> | |
29 | #include <sound/initval.h> | |
30 | #include <sound/pcm_params.h> | |
31 | #include <sound/soc.h> | |
32 | #include <sound/pxa2xx-lib.h> | |
33 | ||
34 | #include <mach/hardware.h> | |
7ebc8d56 | 35 | #include <mach/dma.h> |
1b340bd7 | 36 | |
dd99a452 | 37 | #include "../../arm/pxa2xx-pcm.h" |
1b340bd7 MB |
38 | #include "pxa-ssp.h" |
39 | ||
40 | /* | |
41 | * SSP audio private data | |
42 | */ | |
43 | struct ssp_priv { | |
f9efc9df | 44 | struct ssp_device *ssp; |
1b340bd7 MB |
45 | unsigned int sysclk; |
46 | int dai_fmt; | |
47 | #ifdef CONFIG_PM | |
f9efc9df EM |
48 | uint32_t cr0; |
49 | uint32_t cr1; | |
50 | uint32_t to; | |
51 | uint32_t psp; | |
1b340bd7 MB |
52 | #endif |
53 | }; | |
54 | ||
1b340bd7 MB |
55 | static void dump_registers(struct ssp_device *ssp) |
56 | { | |
57 | dev_dbg(&ssp->pdev->dev, "SSCR0 0x%08x SSCR1 0x%08x SSTO 0x%08x\n", | |
baffe169 HZ |
58 | pxa_ssp_read_reg(ssp, SSCR0), pxa_ssp_read_reg(ssp, SSCR1), |
59 | pxa_ssp_read_reg(ssp, SSTO)); | |
1b340bd7 MB |
60 | |
61 | dev_dbg(&ssp->pdev->dev, "SSPSP 0x%08x SSSR 0x%08x SSACD 0x%08x\n", | |
baffe169 HZ |
62 | pxa_ssp_read_reg(ssp, SSPSP), pxa_ssp_read_reg(ssp, SSSR), |
63 | pxa_ssp_read_reg(ssp, SSACD)); | |
1b340bd7 MB |
64 | } |
65 | ||
baffe169 | 66 | static void pxa_ssp_enable(struct ssp_device *ssp) |
f9efc9df EM |
67 | { |
68 | uint32_t sscr0; | |
69 | ||
70 | sscr0 = __raw_readl(ssp->mmio_base + SSCR0) | SSCR0_SSE; | |
71 | __raw_writel(sscr0, ssp->mmio_base + SSCR0); | |
72 | } | |
73 | ||
baffe169 | 74 | static void pxa_ssp_disable(struct ssp_device *ssp) |
f9efc9df EM |
75 | { |
76 | uint32_t sscr0; | |
77 | ||
78 | sscr0 = __raw_readl(ssp->mmio_base + SSCR0) & ~SSCR0_SSE; | |
79 | __raw_writel(sscr0, ssp->mmio_base + SSCR0); | |
80 | } | |
81 | ||
2d7e71fa EM |
82 | struct pxa2xx_pcm_dma_data { |
83 | struct pxa2xx_pcm_dma_params params; | |
84 | char name[20]; | |
1b340bd7 MB |
85 | }; |
86 | ||
d93ca1ae | 87 | static void pxa_ssp_set_dma_params(struct ssp_device *ssp, int width4, |
88 | int out, struct pxa2xx_pcm_dma_params *dma_data) | |
2d7e71fa EM |
89 | { |
90 | struct pxa2xx_pcm_dma_data *dma; | |
91 | ||
d93ca1ae | 92 | dma = container_of(dma_data, struct pxa2xx_pcm_dma_data, params); |
2d7e71fa EM |
93 | |
94 | snprintf(dma->name, 20, "SSP%d PCM %s %s", ssp->port_id, | |
8eb9feab | 95 | width4 ? "32-bit" : "16-bit", out ? "out" : "in"); |
2d7e71fa EM |
96 | |
97 | dma->params.name = dma->name; | |
98 | dma->params.drcmr = &DRCMR(out ? ssp->drcmr_tx : ssp->drcmr_rx); | |
99 | dma->params.dcmd = (out ? (DCMD_INCSRCADDR | DCMD_FLOWTRG) : | |
100 | (DCMD_INCTRGADDR | DCMD_FLOWSRC)) | | |
8eb9feab | 101 | (width4 ? DCMD_WIDTH4 : DCMD_WIDTH2) | DCMD_BURST16; |
2d7e71fa | 102 | dma->params.dev_addr = ssp->phys_base + SSDR; |
2d7e71fa EM |
103 | } |
104 | ||
dee89c4d | 105 | static int pxa_ssp_startup(struct snd_pcm_substream *substream, |
f0fba2ad | 106 | struct snd_soc_dai *cpu_dai) |
1b340bd7 | 107 | { |
f0fba2ad | 108 | struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai); |
f9efc9df | 109 | struct ssp_device *ssp = priv->ssp; |
d93ca1ae | 110 | struct pxa2xx_pcm_dma_data *dma; |
1b340bd7 MB |
111 | int ret = 0; |
112 | ||
113 | if (!cpu_dai->active) { | |
f9efc9df | 114 | clk_enable(ssp->clk); |
baffe169 | 115 | pxa_ssp_disable(ssp); |
1b340bd7 | 116 | } |
2d7e71fa | 117 | |
d93ca1ae | 118 | dma = kzalloc(sizeof(struct pxa2xx_pcm_dma_data), GFP_KERNEL); |
119 | if (!dma) | |
120 | return -ENOMEM; | |
121 | snd_soc_dai_set_dma_data(cpu_dai, substream, &dma->params); | |
5f712b2b | 122 | |
1b340bd7 MB |
123 | return ret; |
124 | } | |
125 | ||
dee89c4d | 126 | static void pxa_ssp_shutdown(struct snd_pcm_substream *substream, |
f0fba2ad | 127 | struct snd_soc_dai *cpu_dai) |
1b340bd7 | 128 | { |
f0fba2ad | 129 | struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai); |
f9efc9df | 130 | struct ssp_device *ssp = priv->ssp; |
1b340bd7 MB |
131 | |
132 | if (!cpu_dai->active) { | |
baffe169 | 133 | pxa_ssp_disable(ssp); |
f9efc9df | 134 | clk_disable(ssp->clk); |
1b340bd7 | 135 | } |
2d7e71fa | 136 | |
5f712b2b DM |
137 | kfree(snd_soc_dai_get_dma_data(cpu_dai, substream)); |
138 | snd_soc_dai_set_dma_data(cpu_dai, substream, NULL); | |
1b340bd7 MB |
139 | } |
140 | ||
141 | #ifdef CONFIG_PM | |
142 | ||
dc7d7b83 | 143 | static int pxa_ssp_suspend(struct snd_soc_dai *cpu_dai) |
1b340bd7 | 144 | { |
f0fba2ad | 145 | struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai); |
f9efc9df | 146 | struct ssp_device *ssp = priv->ssp; |
1b340bd7 MB |
147 | |
148 | if (!cpu_dai->active) | |
988addf8 | 149 | clk_enable(ssp->clk); |
1b340bd7 | 150 | |
f9efc9df EM |
151 | priv->cr0 = __raw_readl(ssp->mmio_base + SSCR0); |
152 | priv->cr1 = __raw_readl(ssp->mmio_base + SSCR1); | |
153 | priv->to = __raw_readl(ssp->mmio_base + SSTO); | |
154 | priv->psp = __raw_readl(ssp->mmio_base + SSPSP); | |
155 | ||
baffe169 | 156 | pxa_ssp_disable(ssp); |
f9efc9df | 157 | clk_disable(ssp->clk); |
1b340bd7 MB |
158 | return 0; |
159 | } | |
160 | ||
dc7d7b83 | 161 | static int pxa_ssp_resume(struct snd_soc_dai *cpu_dai) |
1b340bd7 | 162 | { |
f0fba2ad | 163 | struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai); |
f9efc9df EM |
164 | struct ssp_device *ssp = priv->ssp; |
165 | uint32_t sssr = SSSR_ROR | SSSR_TUR | SSSR_BCE; | |
1b340bd7 | 166 | |
f9efc9df EM |
167 | clk_enable(ssp->clk); |
168 | ||
169 | __raw_writel(sssr, ssp->mmio_base + SSSR); | |
f9efc9df EM |
170 | __raw_writel(priv->cr0 & ~SSCR0_SSE, ssp->mmio_base + SSCR0); |
171 | __raw_writel(priv->cr1, ssp->mmio_base + SSCR1); | |
172 | __raw_writel(priv->to, ssp->mmio_base + SSTO); | |
173 | __raw_writel(priv->psp, ssp->mmio_base + SSPSP); | |
026384d6 DM |
174 | |
175 | if (cpu_dai->active) | |
baffe169 | 176 | pxa_ssp_enable(ssp); |
026384d6 | 177 | else |
988addf8 | 178 | clk_disable(ssp->clk); |
1b340bd7 MB |
179 | |
180 | return 0; | |
181 | } | |
182 | ||
183 | #else | |
184 | #define pxa_ssp_suspend NULL | |
185 | #define pxa_ssp_resume NULL | |
186 | #endif | |
187 | ||
188 | /** | |
189 | * ssp_set_clkdiv - set SSP clock divider | |
190 | * @div: serial clock rate divider | |
191 | */ | |
baffe169 | 192 | static void pxa_ssp_set_scr(struct ssp_device *ssp, u32 div) |
1b340bd7 | 193 | { |
baffe169 | 194 | u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0); |
1a297286 | 195 | |
972a55b6 | 196 | if (ssp->type == PXA25x_SSP) { |
1a297286 PZ |
197 | sscr0 &= ~0x0000ff00; |
198 | sscr0 |= ((div - 2)/2) << 8; /* 2..512 */ | |
199 | } else { | |
200 | sscr0 &= ~0x000fff00; | |
201 | sscr0 |= (div - 1) << 8; /* 1..4096 */ | |
202 | } | |
baffe169 | 203 | pxa_ssp_write_reg(ssp, SSCR0, sscr0); |
1a297286 PZ |
204 | } |
205 | ||
206 | /** | |
baffe169 | 207 | * pxa_ssp_get_clkdiv - get SSP clock divider |
1a297286 | 208 | */ |
baffe169 | 209 | static u32 pxa_ssp_get_scr(struct ssp_device *ssp) |
1a297286 | 210 | { |
baffe169 | 211 | u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0); |
1a297286 | 212 | u32 div; |
1b340bd7 | 213 | |
972a55b6 | 214 | if (ssp->type == PXA25x_SSP) |
1a297286 PZ |
215 | div = ((sscr0 >> 8) & 0xff) * 2 + 2; |
216 | else | |
217 | div = ((sscr0 >> 8) & 0xfff) + 1; | |
218 | return div; | |
1b340bd7 MB |
219 | } |
220 | ||
221 | /* | |
222 | * Set the SSP ports SYSCLK. | |
223 | */ | |
224 | static int pxa_ssp_set_dai_sysclk(struct snd_soc_dai *cpu_dai, | |
225 | int clk_id, unsigned int freq, int dir) | |
226 | { | |
f0fba2ad | 227 | struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai); |
f9efc9df | 228 | struct ssp_device *ssp = priv->ssp; |
1b340bd7 MB |
229 | int val; |
230 | ||
baffe169 | 231 | u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0) & |
20a41eac | 232 | ~(SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ACS); |
1b340bd7 MB |
233 | |
234 | dev_dbg(&ssp->pdev->dev, | |
449bd54d | 235 | "pxa_ssp_set_dai_sysclk id: %d, clk_id %d, freq %u\n", |
1b340bd7 MB |
236 | cpu_dai->id, clk_id, freq); |
237 | ||
238 | switch (clk_id) { | |
239 | case PXA_SSP_CLK_NET_PLL: | |
240 | sscr0 |= SSCR0_MOD; | |
241 | break; | |
242 | case PXA_SSP_CLK_PLL: | |
243 | /* Internal PLL is fixed */ | |
972a55b6 | 244 | if (ssp->type == PXA25x_SSP) |
1b340bd7 MB |
245 | priv->sysclk = 1843200; |
246 | else | |
247 | priv->sysclk = 13000000; | |
248 | break; | |
249 | case PXA_SSP_CLK_EXT: | |
250 | priv->sysclk = freq; | |
251 | sscr0 |= SSCR0_ECS; | |
252 | break; | |
253 | case PXA_SSP_CLK_NET: | |
254 | priv->sysclk = freq; | |
255 | sscr0 |= SSCR0_NCS | SSCR0_MOD; | |
256 | break; | |
257 | case PXA_SSP_CLK_AUDIO: | |
258 | priv->sysclk = 0; | |
baffe169 | 259 | pxa_ssp_set_scr(ssp, 1); |
20a41eac | 260 | sscr0 |= SSCR0_ACS; |
1b340bd7 MB |
261 | break; |
262 | default: | |
263 | return -ENODEV; | |
264 | } | |
265 | ||
266 | /* The SSP clock must be disabled when changing SSP clock mode | |
267 | * on PXA2xx. On PXA3xx it must be enabled when doing so. */ | |
972a55b6 | 268 | if (ssp->type != PXA3xx_SSP) |
f9efc9df | 269 | clk_disable(ssp->clk); |
baffe169 HZ |
270 | val = pxa_ssp_read_reg(ssp, SSCR0) | sscr0; |
271 | pxa_ssp_write_reg(ssp, SSCR0, val); | |
972a55b6 | 272 | if (ssp->type != PXA3xx_SSP) |
f9efc9df | 273 | clk_enable(ssp->clk); |
1b340bd7 MB |
274 | |
275 | return 0; | |
276 | } | |
277 | ||
278 | /* | |
279 | * Set the SSP clock dividers. | |
280 | */ | |
281 | static int pxa_ssp_set_dai_clkdiv(struct snd_soc_dai *cpu_dai, | |
282 | int div_id, int div) | |
283 | { | |
f0fba2ad | 284 | struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai); |
f9efc9df | 285 | struct ssp_device *ssp = priv->ssp; |
1b340bd7 MB |
286 | int val; |
287 | ||
288 | switch (div_id) { | |
289 | case PXA_SSP_AUDIO_DIV_ACDS: | |
baffe169 HZ |
290 | val = (pxa_ssp_read_reg(ssp, SSACD) & ~0x7) | SSACD_ACDS(div); |
291 | pxa_ssp_write_reg(ssp, SSACD, val); | |
1b340bd7 MB |
292 | break; |
293 | case PXA_SSP_AUDIO_DIV_SCDB: | |
baffe169 | 294 | val = pxa_ssp_read_reg(ssp, SSACD); |
1b340bd7 | 295 | val &= ~SSACD_SCDB; |
972a55b6 | 296 | if (ssp->type == PXA3xx_SSP) |
1b340bd7 | 297 | val &= ~SSACD_SCDX8; |
1b340bd7 MB |
298 | switch (div) { |
299 | case PXA_SSP_CLK_SCDB_1: | |
300 | val |= SSACD_SCDB; | |
301 | break; | |
302 | case PXA_SSP_CLK_SCDB_4: | |
303 | break; | |
1b340bd7 | 304 | case PXA_SSP_CLK_SCDB_8: |
972a55b6 | 305 | if (ssp->type == PXA3xx_SSP) |
1b340bd7 MB |
306 | val |= SSACD_SCDX8; |
307 | else | |
308 | return -EINVAL; | |
309 | break; | |
1b340bd7 MB |
310 | default: |
311 | return -EINVAL; | |
312 | } | |
baffe169 | 313 | pxa_ssp_write_reg(ssp, SSACD, val); |
1b340bd7 MB |
314 | break; |
315 | case PXA_SSP_DIV_SCR: | |
baffe169 | 316 | pxa_ssp_set_scr(ssp, div); |
1b340bd7 MB |
317 | break; |
318 | default: | |
319 | return -ENODEV; | |
320 | } | |
321 | ||
322 | return 0; | |
323 | } | |
324 | ||
325 | /* | |
326 | * Configure the PLL frequency pxa27x and (afaik - pxa320 only) | |
327 | */ | |
85488037 MB |
328 | static int pxa_ssp_set_dai_pll(struct snd_soc_dai *cpu_dai, int pll_id, |
329 | int source, unsigned int freq_in, unsigned int freq_out) | |
1b340bd7 | 330 | { |
f0fba2ad | 331 | struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai); |
f9efc9df | 332 | struct ssp_device *ssp = priv->ssp; |
baffe169 | 333 | u32 ssacd = pxa_ssp_read_reg(ssp, SSACD) & ~0x70; |
1b340bd7 | 334 | |
972a55b6 | 335 | if (ssp->type == PXA3xx_SSP) |
baffe169 | 336 | pxa_ssp_write_reg(ssp, SSACDD, 0); |
1b340bd7 MB |
337 | |
338 | switch (freq_out) { | |
339 | case 5622000: | |
340 | break; | |
341 | case 11345000: | |
342 | ssacd |= (0x1 << 4); | |
343 | break; | |
344 | case 12235000: | |
345 | ssacd |= (0x2 << 4); | |
346 | break; | |
347 | case 14857000: | |
348 | ssacd |= (0x3 << 4); | |
349 | break; | |
350 | case 32842000: | |
351 | ssacd |= (0x4 << 4); | |
352 | break; | |
353 | case 48000000: | |
354 | ssacd |= (0x5 << 4); | |
355 | break; | |
356 | case 0: | |
357 | /* Disable */ | |
358 | break; | |
359 | ||
360 | default: | |
1b340bd7 MB |
361 | /* PXA3xx has a clock ditherer which can be used to generate |
362 | * a wider range of frequencies - calculate a value for it. | |
363 | */ | |
972a55b6 | 364 | if (ssp->type == PXA3xx_SSP) { |
1b340bd7 MB |
365 | u32 val; |
366 | u64 tmp = 19968; | |
367 | tmp *= 1000000; | |
368 | do_div(tmp, freq_out); | |
369 | val = tmp; | |
370 | ||
a419aef8 | 371 | val = (val << 16) | 64; |
baffe169 | 372 | pxa_ssp_write_reg(ssp, SSACDD, val); |
1b340bd7 MB |
373 | |
374 | ssacd |= (0x6 << 4); | |
375 | ||
376 | dev_dbg(&ssp->pdev->dev, | |
449bd54d | 377 | "Using SSACDD %x to supply %uHz\n", |
1b340bd7 MB |
378 | val, freq_out); |
379 | break; | |
380 | } | |
1b340bd7 MB |
381 | |
382 | return -EINVAL; | |
383 | } | |
384 | ||
baffe169 | 385 | pxa_ssp_write_reg(ssp, SSACD, ssacd); |
1b340bd7 MB |
386 | |
387 | return 0; | |
388 | } | |
389 | ||
390 | /* | |
391 | * Set the active slots in TDM/Network mode | |
392 | */ | |
393 | static int pxa_ssp_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, | |
a5479e38 | 394 | unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width) |
1b340bd7 | 395 | { |
f0fba2ad | 396 | struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai); |
f9efc9df | 397 | struct ssp_device *ssp = priv->ssp; |
1b340bd7 MB |
398 | u32 sscr0; |
399 | ||
baffe169 | 400 | sscr0 = pxa_ssp_read_reg(ssp, SSCR0); |
a5479e38 | 401 | sscr0 &= ~(SSCR0_MOD | SSCR0_SlotsPerFrm(8) | SSCR0_EDSS | SSCR0_DSS); |
1b340bd7 | 402 | |
a5479e38 DR |
403 | /* set slot width */ |
404 | if (slot_width > 16) | |
405 | sscr0 |= SSCR0_EDSS | SSCR0_DataSize(slot_width - 16); | |
406 | else | |
407 | sscr0 |= SSCR0_DataSize(slot_width); | |
408 | ||
409 | if (slots > 1) { | |
410 | /* enable network mode */ | |
411 | sscr0 |= SSCR0_MOD; | |
412 | ||
413 | /* set number of active slots */ | |
414 | sscr0 |= SSCR0_SlotsPerFrm(slots); | |
415 | ||
416 | /* set active slot mask */ | |
baffe169 HZ |
417 | pxa_ssp_write_reg(ssp, SSTSA, tx_mask); |
418 | pxa_ssp_write_reg(ssp, SSRSA, rx_mask); | |
a5479e38 | 419 | } |
baffe169 | 420 | pxa_ssp_write_reg(ssp, SSCR0, sscr0); |
1b340bd7 | 421 | |
1b340bd7 MB |
422 | return 0; |
423 | } | |
424 | ||
425 | /* | |
426 | * Tristate the SSP DAI lines | |
427 | */ | |
428 | static int pxa_ssp_set_dai_tristate(struct snd_soc_dai *cpu_dai, | |
429 | int tristate) | |
430 | { | |
f0fba2ad | 431 | struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai); |
f9efc9df | 432 | struct ssp_device *ssp = priv->ssp; |
1b340bd7 MB |
433 | u32 sscr1; |
434 | ||
baffe169 | 435 | sscr1 = pxa_ssp_read_reg(ssp, SSCR1); |
1b340bd7 MB |
436 | if (tristate) |
437 | sscr1 &= ~SSCR1_TTE; | |
438 | else | |
439 | sscr1 |= SSCR1_TTE; | |
baffe169 | 440 | pxa_ssp_write_reg(ssp, SSCR1, sscr1); |
1b340bd7 MB |
441 | |
442 | return 0; | |
443 | } | |
444 | ||
445 | /* | |
446 | * Set up the SSP DAI format. | |
447 | * The SSP Port must be inactive before calling this function as the | |
448 | * physical interface format is changed. | |
449 | */ | |
450 | static int pxa_ssp_set_dai_fmt(struct snd_soc_dai *cpu_dai, | |
451 | unsigned int fmt) | |
452 | { | |
f0fba2ad | 453 | struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai); |
f9efc9df | 454 | struct ssp_device *ssp = priv->ssp; |
f5d1e5ed | 455 | u32 sscr0, sscr1, sspsp, scfr; |
1b340bd7 | 456 | |
cbf1146d DM |
457 | /* check if we need to change anything at all */ |
458 | if (priv->dai_fmt == fmt) | |
459 | return 0; | |
460 | ||
461 | /* we can only change the settings if the port is not in use */ | |
baffe169 | 462 | if (pxa_ssp_read_reg(ssp, SSCR0) & SSCR0_SSE) { |
cbf1146d DM |
463 | dev_err(&ssp->pdev->dev, |
464 | "can't change hardware dai format: stream is in use"); | |
465 | return -EINVAL; | |
466 | } | |
467 | ||
1b340bd7 | 468 | /* reset port settings */ |
baffe169 | 469 | sscr0 = pxa_ssp_read_reg(ssp, SSCR0) & |
f5d1e5ed | 470 | ~(SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ACS); |
1b340bd7 MB |
471 | sscr1 = SSCR1_RxTresh(8) | SSCR1_TxTresh(7); |
472 | sspsp = 0; | |
473 | ||
474 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
475 | case SND_SOC_DAIFMT_CBM_CFM: | |
f5d1e5ed | 476 | sscr1 |= SSCR1_SCLKDIR | SSCR1_SFRMDIR | SSCR1_SCFR; |
1b340bd7 MB |
477 | break; |
478 | case SND_SOC_DAIFMT_CBM_CFS: | |
f5d1e5ed | 479 | sscr1 |= SSCR1_SCLKDIR | SSCR1_SCFR; |
1b340bd7 MB |
480 | break; |
481 | case SND_SOC_DAIFMT_CBS_CFS: | |
482 | break; | |
483 | default: | |
484 | return -EINVAL; | |
485 | } | |
486 | ||
fa44c077 DR |
487 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
488 | case SND_SOC_DAIFMT_NB_NF: | |
489 | sspsp |= SSPSP_SFRMP; | |
490 | break; | |
491 | case SND_SOC_DAIFMT_NB_IF: | |
492 | break; | |
493 | case SND_SOC_DAIFMT_IB_IF: | |
494 | sspsp |= SSPSP_SCMODE(2); | |
495 | break; | |
496 | case SND_SOC_DAIFMT_IB_NF: | |
497 | sspsp |= SSPSP_SCMODE(2) | SSPSP_SFRMP; | |
498 | break; | |
499 | default: | |
500 | return -EINVAL; | |
501 | } | |
1b340bd7 MB |
502 | |
503 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
504 | case SND_SOC_DAIFMT_I2S: | |
72d74664 | 505 | sscr0 |= SSCR0_PSP; |
1b340bd7 | 506 | sscr1 |= SSCR1_RWOT | SSCR1_TRAIL; |
0ce36c5f | 507 | /* See hw_params() */ |
1b340bd7 MB |
508 | break; |
509 | ||
510 | case SND_SOC_DAIFMT_DSP_A: | |
511 | sspsp |= SSPSP_FSRT; | |
512 | case SND_SOC_DAIFMT_DSP_B: | |
513 | sscr0 |= SSCR0_MOD | SSCR0_PSP; | |
514 | sscr1 |= SSCR1_TRAIL | SSCR1_RWOT; | |
1b340bd7 MB |
515 | break; |
516 | ||
517 | default: | |
518 | return -EINVAL; | |
519 | } | |
520 | ||
baffe169 HZ |
521 | pxa_ssp_write_reg(ssp, SSCR0, sscr0); |
522 | pxa_ssp_write_reg(ssp, SSCR1, sscr1); | |
523 | pxa_ssp_write_reg(ssp, SSPSP, sspsp); | |
1b340bd7 | 524 | |
f5d1e5ed HZ |
525 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
526 | case SND_SOC_DAIFMT_CBM_CFM: | |
527 | case SND_SOC_DAIFMT_CBM_CFS: | |
528 | scfr = pxa_ssp_read_reg(ssp, SSCR1) | SSCR1_SCFR; | |
529 | pxa_ssp_write_reg(ssp, SSCR1, scfr); | |
530 | ||
531 | while (pxa_ssp_read_reg(ssp, SSSR) & SSSR_BSY) | |
532 | cpu_relax(); | |
533 | break; | |
534 | } | |
535 | ||
1b340bd7 MB |
536 | dump_registers(ssp); |
537 | ||
538 | /* Since we are configuring the timings for the format by hand | |
539 | * we have to defer some things until hw_params() where we | |
540 | * know parameters like the sample size. | |
541 | */ | |
542 | priv->dai_fmt = fmt; | |
543 | ||
544 | return 0; | |
545 | } | |
546 | ||
547 | /* | |
548 | * Set the SSP audio DMA parameters and sample size. | |
549 | * Can be called multiple times by oss emulation. | |
550 | */ | |
551 | static int pxa_ssp_hw_params(struct snd_pcm_substream *substream, | |
dee89c4d | 552 | struct snd_pcm_hw_params *params, |
f0fba2ad | 553 | struct snd_soc_dai *cpu_dai) |
1b340bd7 | 554 | { |
f0fba2ad | 555 | struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai); |
f9efc9df | 556 | struct ssp_device *ssp = priv->ssp; |
2d7e71fa | 557 | int chn = params_channels(params); |
1b340bd7 MB |
558 | u32 sscr0; |
559 | u32 sspsp; | |
560 | int width = snd_pcm_format_physical_width(params_format(params)); | |
baffe169 | 561 | int ttsa = pxa_ssp_read_reg(ssp, SSTSA) & 0xf; |
5f712b2b DM |
562 | struct pxa2xx_pcm_dma_params *dma_data; |
563 | ||
f0fba2ad | 564 | dma_data = snd_soc_dai_get_dma_data(cpu_dai, substream); |
1b340bd7 | 565 | |
92429069 PZ |
566 | /* Network mode with one active slot (ttsa == 1) can be used |
567 | * to force 16-bit frame width on the wire (for S16_LE), even | |
568 | * with two channels. Use 16-bit DMA transfers for this case. | |
569 | */ | |
d93ca1ae | 570 | pxa_ssp_set_dma_params(ssp, |
571 | ((chn == 2) && (ttsa != 1)) || (width == 32), | |
572 | substream->stream == SNDRV_PCM_STREAM_PLAYBACK, dma_data); | |
5f712b2b | 573 | |
1b340bd7 | 574 | /* we can only change the settings if the port is not in use */ |
baffe169 | 575 | if (pxa_ssp_read_reg(ssp, SSCR0) & SSCR0_SSE) |
1b340bd7 MB |
576 | return 0; |
577 | ||
578 | /* clear selected SSP bits */ | |
baffe169 | 579 | sscr0 = pxa_ssp_read_reg(ssp, SSCR0) & ~(SSCR0_DSS | SSCR0_EDSS); |
1b340bd7 MB |
580 | |
581 | /* bit size */ | |
1b340bd7 MB |
582 | switch (params_format(params)) { |
583 | case SNDRV_PCM_FORMAT_S16_LE: | |
972a55b6 | 584 | if (ssp->type == PXA3xx_SSP) |
1b340bd7 | 585 | sscr0 |= SSCR0_FPCKE; |
1b340bd7 | 586 | sscr0 |= SSCR0_DataSize(16); |
1b340bd7 MB |
587 | break; |
588 | case SNDRV_PCM_FORMAT_S24_LE: | |
589 | sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(8)); | |
1b340bd7 MB |
590 | break; |
591 | case SNDRV_PCM_FORMAT_S32_LE: | |
592 | sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(16)); | |
1b340bd7 MB |
593 | break; |
594 | } | |
baffe169 | 595 | pxa_ssp_write_reg(ssp, SSCR0, sscr0); |
1b340bd7 MB |
596 | |
597 | switch (priv->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
598 | case SND_SOC_DAIFMT_I2S: | |
baffe169 | 599 | sspsp = pxa_ssp_read_reg(ssp, SSPSP); |
72d74664 | 600 | |
baffe169 | 601 | if ((pxa_ssp_get_scr(ssp) == 4) && (width == 16)) { |
72d74664 DM |
602 | /* This is a special case where the bitclk is 64fs |
603 | * and we're not dealing with 2*32 bits of audio | |
604 | * samples. | |
605 | * | |
606 | * The SSP values used for that are all found out by | |
607 | * trying and failing a lot; some of the registers | |
608 | * needed for that mode are only available on PXA3xx. | |
609 | */ | |
972a55b6 | 610 | if (ssp->type != PXA3xx_SSP) |
72d74664 DM |
611 | return -EINVAL; |
612 | ||
613 | sspsp |= SSPSP_SFRMWDTH(width * 2); | |
614 | sspsp |= SSPSP_SFRMDLY(width * 4); | |
615 | sspsp |= SSPSP_EDMYSTOP(3); | |
616 | sspsp |= SSPSP_DMYSTOP(3); | |
617 | sspsp |= SSPSP_DMYSTRT(1); | |
0ce36c5f MB |
618 | } else { |
619 | /* The frame width is the width the LRCLK is | |
620 | * asserted for; the delay is expressed in | |
621 | * half cycle units. We need the extra cycle | |
622 | * because the data starts clocking out one BCLK | |
623 | * after LRCLK changes polarity. | |
624 | */ | |
625 | sspsp |= SSPSP_SFRMWDTH(width + 1); | |
626 | sspsp |= SSPSP_SFRMDLY((width + 1) * 2); | |
627 | sspsp |= SSPSP_DMYSTRT(1); | |
628 | } | |
72d74664 | 629 | |
baffe169 | 630 | pxa_ssp_write_reg(ssp, SSPSP, sspsp); |
1b340bd7 MB |
631 | break; |
632 | default: | |
633 | break; | |
634 | } | |
635 | ||
72d74664 | 636 | /* When we use a network mode, we always require TDM slots |
1b340bd7 MB |
637 | * - complain loudly and fail if they've not been set up yet. |
638 | */ | |
92429069 | 639 | if ((sscr0 & SSCR0_MOD) && !ttsa) { |
1b340bd7 MB |
640 | dev_err(&ssp->pdev->dev, "No TDM timeslot configured\n"); |
641 | return -EINVAL; | |
642 | } | |
643 | ||
644 | dump_registers(ssp); | |
645 | ||
646 | return 0; | |
647 | } | |
648 | ||
273b72c8 DM |
649 | static void pxa_ssp_set_running_bit(struct snd_pcm_substream *substream, |
650 | struct ssp_device *ssp, int value) | |
651 | { | |
652 | uint32_t sscr0 = pxa_ssp_read_reg(ssp, SSCR0); | |
653 | uint32_t sscr1 = pxa_ssp_read_reg(ssp, SSCR1); | |
654 | uint32_t sspsp = pxa_ssp_read_reg(ssp, SSPSP); | |
655 | uint32_t sssr = pxa_ssp_read_reg(ssp, SSSR); | |
656 | ||
657 | if (value && (sscr0 & SSCR0_SSE)) | |
658 | pxa_ssp_write_reg(ssp, SSCR0, sscr0 & ~SSCR0_SSE); | |
659 | ||
660 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
661 | if (value) | |
662 | sscr1 |= SSCR1_TSRE; | |
663 | else | |
664 | sscr1 &= ~SSCR1_TSRE; | |
665 | } else { | |
666 | if (value) | |
667 | sscr1 |= SSCR1_RSRE; | |
668 | else | |
669 | sscr1 &= ~SSCR1_RSRE; | |
670 | } | |
671 | ||
672 | pxa_ssp_write_reg(ssp, SSCR1, sscr1); | |
673 | ||
674 | if (value) { | |
675 | pxa_ssp_write_reg(ssp, SSSR, sssr); | |
676 | pxa_ssp_write_reg(ssp, SSPSP, sspsp); | |
677 | pxa_ssp_write_reg(ssp, SSCR0, sscr0 | SSCR0_SSE); | |
678 | } | |
679 | } | |
680 | ||
dee89c4d | 681 | static int pxa_ssp_trigger(struct snd_pcm_substream *substream, int cmd, |
f0fba2ad | 682 | struct snd_soc_dai *cpu_dai) |
1b340bd7 | 683 | { |
1b340bd7 | 684 | int ret = 0; |
f0fba2ad | 685 | struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai); |
f9efc9df | 686 | struct ssp_device *ssp = priv->ssp; |
1b340bd7 MB |
687 | int val; |
688 | ||
689 | switch (cmd) { | |
690 | case SNDRV_PCM_TRIGGER_RESUME: | |
baffe169 | 691 | pxa_ssp_enable(ssp); |
1b340bd7 MB |
692 | break; |
693 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
273b72c8 | 694 | pxa_ssp_set_running_bit(substream, ssp, 1); |
baffe169 HZ |
695 | val = pxa_ssp_read_reg(ssp, SSSR); |
696 | pxa_ssp_write_reg(ssp, SSSR, val); | |
1b340bd7 MB |
697 | break; |
698 | case SNDRV_PCM_TRIGGER_START: | |
273b72c8 | 699 | pxa_ssp_set_running_bit(substream, ssp, 1); |
1b340bd7 MB |
700 | break; |
701 | case SNDRV_PCM_TRIGGER_STOP: | |
273b72c8 | 702 | pxa_ssp_set_running_bit(substream, ssp, 0); |
1b340bd7 MB |
703 | break; |
704 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
baffe169 | 705 | pxa_ssp_disable(ssp); |
1b340bd7 MB |
706 | break; |
707 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
273b72c8 | 708 | pxa_ssp_set_running_bit(substream, ssp, 0); |
1b340bd7 MB |
709 | break; |
710 | ||
711 | default: | |
712 | ret = -EINVAL; | |
713 | } | |
714 | ||
715 | dump_registers(ssp); | |
716 | ||
717 | return ret; | |
718 | } | |
719 | ||
f0fba2ad | 720 | static int pxa_ssp_probe(struct snd_soc_dai *dai) |
1b340bd7 MB |
721 | { |
722 | struct ssp_priv *priv; | |
723 | int ret; | |
724 | ||
725 | priv = kzalloc(sizeof(struct ssp_priv), GFP_KERNEL); | |
726 | if (!priv) | |
727 | return -ENOMEM; | |
728 | ||
baffe169 | 729 | priv->ssp = pxa_ssp_request(dai->id + 1, "SoC audio"); |
f9efc9df | 730 | if (priv->ssp == NULL) { |
1b340bd7 MB |
731 | ret = -ENODEV; |
732 | goto err_priv; | |
733 | } | |
734 | ||
a5735b7e | 735 | priv->dai_fmt = (unsigned int) -1; |
f0fba2ad | 736 | snd_soc_dai_set_drvdata(dai, priv); |
1b340bd7 MB |
737 | |
738 | return 0; | |
739 | ||
740 | err_priv: | |
741 | kfree(priv); | |
742 | return ret; | |
743 | } | |
744 | ||
f0fba2ad | 745 | static int pxa_ssp_remove(struct snd_soc_dai *dai) |
1b340bd7 | 746 | { |
f0fba2ad LG |
747 | struct ssp_priv *priv = snd_soc_dai_get_drvdata(dai); |
748 | ||
baffe169 | 749 | pxa_ssp_free(priv->ssp); |
014a2755 | 750 | kfree(priv); |
f0fba2ad | 751 | return 0; |
1b340bd7 MB |
752 | } |
753 | ||
754 | #define PXA_SSP_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\ | |
755 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \ | |
8d8bf58b QZ |
756 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \ |
757 | SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | \ | |
1b340bd7 MB |
758 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000) |
759 | ||
760 | #define PXA_SSP_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ | |
761 | SNDRV_PCM_FMTBIT_S24_LE | \ | |
762 | SNDRV_PCM_FMTBIT_S32_LE) | |
763 | ||
85e7652d | 764 | static const struct snd_soc_dai_ops pxa_ssp_dai_ops = { |
6335d055 EM |
765 | .startup = pxa_ssp_startup, |
766 | .shutdown = pxa_ssp_shutdown, | |
767 | .trigger = pxa_ssp_trigger, | |
768 | .hw_params = pxa_ssp_hw_params, | |
769 | .set_sysclk = pxa_ssp_set_dai_sysclk, | |
770 | .set_clkdiv = pxa_ssp_set_dai_clkdiv, | |
771 | .set_pll = pxa_ssp_set_dai_pll, | |
772 | .set_fmt = pxa_ssp_set_dai_fmt, | |
773 | .set_tdm_slot = pxa_ssp_set_dai_tdm_slot, | |
774 | .set_tristate = pxa_ssp_set_dai_tristate, | |
775 | }; | |
776 | ||
f0fba2ad | 777 | static struct snd_soc_dai_driver pxa_ssp_dai = { |
1b340bd7 MB |
778 | .probe = pxa_ssp_probe, |
779 | .remove = pxa_ssp_remove, | |
780 | .suspend = pxa_ssp_suspend, | |
781 | .resume = pxa_ssp_resume, | |
782 | .playback = { | |
783 | .channels_min = 1, | |
f34762b6 | 784 | .channels_max = 8, |
1b340bd7 MB |
785 | .rates = PXA_SSP_RATES, |
786 | .formats = PXA_SSP_FORMATS, | |
787 | }, | |
788 | .capture = { | |
789 | .channels_min = 1, | |
f34762b6 | 790 | .channels_max = 8, |
1b340bd7 MB |
791 | .rates = PXA_SSP_RATES, |
792 | .formats = PXA_SSP_FORMATS, | |
793 | }, | |
6335d055 | 794 | .ops = &pxa_ssp_dai_ops, |
f0fba2ad LG |
795 | }; |
796 | ||
797 | static __devinit int asoc_ssp_probe(struct platform_device *pdev) | |
798 | { | |
799 | return snd_soc_register_dai(&pdev->dev, &pxa_ssp_dai); | |
800 | } | |
801 | ||
802 | static int __devexit asoc_ssp_remove(struct platform_device *pdev) | |
803 | { | |
804 | snd_soc_unregister_dai(&pdev->dev); | |
805 | return 0; | |
806 | } | |
807 | ||
808 | static struct platform_driver asoc_ssp_driver = { | |
809 | .driver = { | |
810 | .name = "pxa-ssp-dai", | |
811 | .owner = THIS_MODULE, | |
1b340bd7 | 812 | }, |
f0fba2ad LG |
813 | |
814 | .probe = asoc_ssp_probe, | |
815 | .remove = __devexit_p(asoc_ssp_remove), | |
1b340bd7 | 816 | }; |
1b340bd7 | 817 | |
2f702a19 | 818 | module_platform_driver(asoc_ssp_driver); |
3f4b783c | 819 | |
1b340bd7 MB |
820 | /* Module information */ |
821 | MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); | |
822 | MODULE_DESCRIPTION("PXA SSP/PCM SoC Interface"); | |
823 | MODULE_LICENSE("GPL"); |