Commit | Line | Data |
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da607e19 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
31ef9134 CL |
2 | /* |
3 | * Audio and Music Data Transmission Protocol (IEC 61883-6) streams | |
4 | * with Common Isochronous Packet (IEC 61883-1) headers | |
5 | * | |
6 | * Copyright (c) Clemens Ladisch <clemens@ladisch.de> | |
31ef9134 CL |
7 | */ |
8 | ||
9 | #include <linux/device.h> | |
10 | #include <linux/err.h> | |
11 | #include <linux/firewire.h> | |
acfedcbe | 12 | #include <linux/firewire-constants.h> |
31ef9134 CL |
13 | #include <linux/module.h> |
14 | #include <linux/slab.h> | |
15 | #include <sound/pcm.h> | |
7b2d99fa | 16 | #include <sound/pcm_params.h> |
d67c46b9 | 17 | #include "amdtp-stream.h" |
31ef9134 CL |
18 | |
19 | #define TICKS_PER_CYCLE 3072 | |
20 | #define CYCLES_PER_SECOND 8000 | |
21 | #define TICKS_PER_SECOND (TICKS_PER_CYCLE * CYCLES_PER_SECOND) | |
22 | ||
3e106f4f | 23 | #define OHCI_SECOND_MODULUS 8 |
10aa8e4a | 24 | |
0c95c1d6 TS |
25 | /* Always support Linux tracing subsystem. */ |
26 | #define CREATE_TRACE_POINTS | |
27 | #include "amdtp-stream-trace.h" | |
28 | ||
ca5b5050 | 29 | #define TRANSFER_DELAY_TICKS 0x2e00 /* 479.17 microseconds */ |
31ef9134 | 30 | |
b445db44 TS |
31 | /* isochronous header parameters */ |
32 | #define ISO_DATA_LENGTH_SHIFT 16 | |
3b196c39 | 33 | #define TAG_NO_CIP_HEADER 0 |
31ef9134 CL |
34 | #define TAG_CIP 1 |
35 | ||
67d92ee7 TS |
36 | // Common Isochronous Packet (CIP) header parameters. Use two quadlets CIP header when supported. |
37 | #define CIP_HEADER_QUADLETS 2 | |
9a2820c1 TS |
38 | #define CIP_EOH_SHIFT 31 |
39 | #define CIP_EOH (1u << CIP_EOH_SHIFT) | |
b445db44 | 40 | #define CIP_EOH_MASK 0x80000000 |
9a2820c1 TS |
41 | #define CIP_SID_SHIFT 24 |
42 | #define CIP_SID_MASK 0x3f000000 | |
43 | #define CIP_DBS_MASK 0x00ff0000 | |
44 | #define CIP_DBS_SHIFT 16 | |
9863874f TS |
45 | #define CIP_SPH_MASK 0x00000400 |
46 | #define CIP_SPH_SHIFT 10 | |
9a2820c1 TS |
47 | #define CIP_DBC_MASK 0x000000ff |
48 | #define CIP_FMT_SHIFT 24 | |
b445db44 | 49 | #define CIP_FMT_MASK 0x3f000000 |
9a2820c1 TS |
50 | #define CIP_FDF_MASK 0x00ff0000 |
51 | #define CIP_FDF_SHIFT 16 | |
fb25dcc8 | 52 | #define CIP_FDF_NO_DATA 0xff |
b445db44 TS |
53 | #define CIP_SYT_MASK 0x0000ffff |
54 | #define CIP_SYT_NO_INFO 0xffff | |
f9e5ecdf | 55 | #define CIP_SYT_CYCLE_MODULUS 16 |
fb25dcc8 | 56 | #define CIP_NO_DATA ((CIP_FDF_NO_DATA << CIP_FDF_SHIFT) | CIP_SYT_NO_INFO) |
b445db44 | 57 | |
67d92ee7 TS |
58 | #define CIP_HEADER_SIZE (sizeof(__be32) * CIP_HEADER_QUADLETS) |
59 | ||
51c29fd2 | 60 | /* Audio and Music transfer protocol specific parameters */ |
414ba022 | 61 | #define CIP_FMT_AM 0x10 |
2b3fc456 | 62 | #define AMDTP_FDF_NO_DATA 0xff |
31ef9134 | 63 | |
f11453c7 | 64 | // For iso header and tstamp. |
67d92ee7 TS |
65 | #define IR_CTX_HEADER_DEFAULT_QUADLETS 2 |
66 | // Add nothing. | |
67 | #define IR_CTX_HEADER_SIZE_NO_CIP (sizeof(__be32) * IR_CTX_HEADER_DEFAULT_QUADLETS) | |
68 | // Add two quadlets CIP header. | |
69 | #define IR_CTX_HEADER_SIZE_CIP (IR_CTX_HEADER_SIZE_NO_CIP + CIP_HEADER_SIZE) | |
cc4f8e91 | 70 | #define HEADER_TSTAMP_MASK 0x0000ffff |
4b7da117 | 71 | |
67d92ee7 | 72 | #define IT_PKT_HEADER_SIZE_CIP CIP_HEADER_SIZE |
b18f0cfa TS |
73 | #define IT_PKT_HEADER_SIZE_NO_CIP 0 // Nothing. |
74 | ||
6a3ce97d TS |
75 | // The initial firmware of OXFW970 can postpone transmission of packet during finishing |
76 | // asynchronous transaction. This module accepts 5 cycles to skip as maximum to avoid buffer | |
77 | // overrun. Actual device can skip more, then this module stops the packet streaming. | |
78 | #define IR_JUMBO_PAYLOAD_MAX_SKIP_CYCLES 5 | |
79 | ||
31ef9134 | 80 | /** |
be4a2894 TS |
81 | * amdtp_stream_init - initialize an AMDTP stream structure |
82 | * @s: the AMDTP stream to initialize | |
31ef9134 | 83 | * @unit: the target of the stream |
3ff7e8f0 | 84 | * @dir: the direction of stream |
ffe66bbe | 85 | * @flags: the details of the streaming protocol consist of cip_flags enumeration-constants. |
5955815e | 86 | * @fmt: the value of fmt field in CIP header |
9a738ad1 | 87 | * @process_ctx_payloads: callback handler to process payloads of isoc context |
df075fee | 88 | * @protocol_size: the size to allocate newly for protocol |
31ef9134 | 89 | */ |
be4a2894 | 90 | int amdtp_stream_init(struct amdtp_stream *s, struct fw_unit *unit, |
ffe66bbe | 91 | enum amdtp_stream_direction dir, unsigned int flags, |
df075fee | 92 | unsigned int fmt, |
9a738ad1 | 93 | amdtp_stream_process_ctx_payloads_t process_ctx_payloads, |
df075fee | 94 | unsigned int protocol_size) |
31ef9134 | 95 | { |
9a738ad1 | 96 | if (process_ctx_payloads == NULL) |
df075fee TS |
97 | return -EINVAL; |
98 | ||
99 | s->protocol = kzalloc(protocol_size, GFP_KERNEL); | |
100 | if (!s->protocol) | |
101 | return -ENOMEM; | |
102 | ||
c6f224dc | 103 | s->unit = unit; |
3ff7e8f0 | 104 | s->direction = dir; |
31ef9134 CL |
105 | s->flags = flags; |
106 | s->context = ERR_PTR(-1); | |
107 | mutex_init(&s->mutex); | |
ec00f5e4 | 108 | s->packet_index = 0; |
31ef9134 | 109 | |
bdaedca7 | 110 | init_waitqueue_head(&s->ready_wait); |
7b3b0d85 | 111 | |
5955815e | 112 | s->fmt = fmt; |
9a738ad1 | 113 | s->process_ctx_payloads = process_ctx_payloads; |
414ba022 | 114 | |
31ef9134 CL |
115 | return 0; |
116 | } | |
be4a2894 | 117 | EXPORT_SYMBOL(amdtp_stream_init); |
31ef9134 CL |
118 | |
119 | /** | |
be4a2894 TS |
120 | * amdtp_stream_destroy - free stream resources |
121 | * @s: the AMDTP stream to destroy | |
31ef9134 | 122 | */ |
be4a2894 | 123 | void amdtp_stream_destroy(struct amdtp_stream *s) |
31ef9134 | 124 | { |
44c376b9 TS |
125 | /* Not initialized. */ |
126 | if (s->protocol == NULL) | |
127 | return; | |
128 | ||
be4a2894 | 129 | WARN_ON(amdtp_stream_running(s)); |
df075fee | 130 | kfree(s->protocol); |
31ef9134 | 131 | mutex_destroy(&s->mutex); |
31ef9134 | 132 | } |
be4a2894 | 133 | EXPORT_SYMBOL(amdtp_stream_destroy); |
31ef9134 | 134 | |
c5280e99 | 135 | const unsigned int amdtp_syt_intervals[CIP_SFC_COUNT] = { |
a7304e3b CL |
136 | [CIP_SFC_32000] = 8, |
137 | [CIP_SFC_44100] = 8, | |
138 | [CIP_SFC_48000] = 8, | |
139 | [CIP_SFC_88200] = 16, | |
140 | [CIP_SFC_96000] = 16, | |
141 | [CIP_SFC_176400] = 32, | |
142 | [CIP_SFC_192000] = 32, | |
143 | }; | |
144 | EXPORT_SYMBOL(amdtp_syt_intervals); | |
145 | ||
f9503a68 | 146 | const unsigned int amdtp_rate_table[CIP_SFC_COUNT] = { |
1017abed TS |
147 | [CIP_SFC_32000] = 32000, |
148 | [CIP_SFC_44100] = 44100, | |
149 | [CIP_SFC_48000] = 48000, | |
150 | [CIP_SFC_88200] = 88200, | |
151 | [CIP_SFC_96000] = 96000, | |
152 | [CIP_SFC_176400] = 176400, | |
153 | [CIP_SFC_192000] = 192000, | |
154 | }; | |
155 | EXPORT_SYMBOL(amdtp_rate_table); | |
156 | ||
59502295 TS |
157 | static int apply_constraint_to_size(struct snd_pcm_hw_params *params, |
158 | struct snd_pcm_hw_rule *rule) | |
159 | { | |
160 | struct snd_interval *s = hw_param_interval(params, rule->var); | |
161 | const struct snd_interval *r = | |
162 | hw_param_interval_c(params, SNDRV_PCM_HW_PARAM_RATE); | |
826b5de9 TS |
163 | struct snd_interval t = {0}; |
164 | unsigned int step = 0; | |
59502295 TS |
165 | int i; |
166 | ||
167 | for (i = 0; i < CIP_SFC_COUNT; ++i) { | |
826b5de9 TS |
168 | if (snd_interval_test(r, amdtp_rate_table[i])) |
169 | step = max(step, amdtp_syt_intervals[i]); | |
59502295 TS |
170 | } |
171 | ||
826b5de9 TS |
172 | t.min = roundup(s->min, step); |
173 | t.max = rounddown(s->max, step); | |
174 | t.integer = 1; | |
59502295 TS |
175 | |
176 | return snd_interval_refine(s, &t); | |
177 | } | |
178 | ||
7b2d99fa TS |
179 | /** |
180 | * amdtp_stream_add_pcm_hw_constraints - add hw constraints for PCM substream | |
181 | * @s: the AMDTP stream, which must be initialized. | |
182 | * @runtime: the PCM substream runtime | |
183 | */ | |
184 | int amdtp_stream_add_pcm_hw_constraints(struct amdtp_stream *s, | |
185 | struct snd_pcm_runtime *runtime) | |
186 | { | |
55799c5a | 187 | struct snd_pcm_hardware *hw = &runtime->hw; |
99921ec6 TS |
188 | unsigned int ctx_header_size; |
189 | unsigned int maximum_usec_per_period; | |
7b2d99fa TS |
190 | int err; |
191 | ||
d360870a | 192 | hw->info = SNDRV_PCM_INFO_BLOCK_TRANSFER | |
55799c5a TS |
193 | SNDRV_PCM_INFO_INTERLEAVED | |
194 | SNDRV_PCM_INFO_JOINT_DUPLEX | | |
195 | SNDRV_PCM_INFO_MMAP | | |
d360870a TS |
196 | SNDRV_PCM_INFO_MMAP_VALID | |
197 | SNDRV_PCM_INFO_NO_PERIOD_WAKEUP; | |
55799c5a | 198 | |
55799c5a TS |
199 | hw->periods_min = 2; |
200 | hw->periods_max = UINT_MAX; | |
201 | ||
202 | /* bytes for a frame */ | |
203 | hw->period_bytes_min = 4 * hw->channels_max; | |
204 | ||
205 | /* Just to prevent from allocating much pages. */ | |
206 | hw->period_bytes_max = hw->period_bytes_min * 2048; | |
207 | hw->buffer_bytes_max = hw->period_bytes_max * hw->periods_min; | |
208 | ||
99921ec6 TS |
209 | // Linux driver for 1394 OHCI controller voluntarily flushes isoc |
210 | // context when total size of accumulated context header reaches | |
2b3d2987 | 211 | // PAGE_SIZE. This kicks work for the isoc context and brings |
99921ec6 TS |
212 | // callback in the middle of scheduled interrupts. |
213 | // Although AMDTP streams in the same domain use the same events per | |
214 | // IRQ, use the largest size of context header between IT/IR contexts. | |
215 | // Here, use the value of context header in IR context is for both | |
216 | // contexts. | |
217 | if (!(s->flags & CIP_NO_HEADER)) | |
218 | ctx_header_size = IR_CTX_HEADER_SIZE_CIP; | |
219 | else | |
220 | ctx_header_size = IR_CTX_HEADER_SIZE_NO_CIP; | |
221 | maximum_usec_per_period = USEC_PER_SEC * PAGE_SIZE / | |
222 | CYCLES_PER_SECOND / ctx_header_size; | |
223 | ||
f706df4f TS |
224 | // In IEC 61883-6, one isoc packet can transfer events up to the value |
225 | // of syt interval. This comes from the interval of isoc cycle. As 1394 | |
226 | // OHCI controller can generate hardware IRQ per isoc packet, the | |
227 | // interval is 125 usec. | |
228 | // However, there are two ways of transmission in IEC 61883-6; blocking | |
229 | // and non-blocking modes. In blocking mode, the sequence of isoc packet | |
230 | // includes 'empty' or 'NODATA' packets which include no event. In | |
231 | // non-blocking mode, the number of events per packet is variable up to | |
232 | // the syt interval. | |
233 | // Due to the above protocol design, the minimum PCM frames per | |
234 | // interrupt should be double of the value of syt interval, thus it is | |
235 | // 250 usec. | |
7b2d99fa TS |
236 | err = snd_pcm_hw_constraint_minmax(runtime, |
237 | SNDRV_PCM_HW_PARAM_PERIOD_TIME, | |
f706df4f | 238 | 250, maximum_usec_per_period); |
7b2d99fa TS |
239 | if (err < 0) |
240 | goto end; | |
241 | ||
242 | /* Non-Blocking stream has no more constraints */ | |
243 | if (!(s->flags & CIP_BLOCKING)) | |
244 | goto end; | |
245 | ||
246 | /* | |
247 | * One AMDTP packet can include some frames. In blocking mode, the | |
248 | * number equals to SYT_INTERVAL. So the number is 8, 16 or 32, | |
249 | * depending on its sampling rate. For accurate period interrupt, it's | |
ce991981 | 250 | * preferrable to align period/buffer sizes to current SYT_INTERVAL. |
7b2d99fa | 251 | */ |
59502295 TS |
252 | err = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, |
253 | apply_constraint_to_size, NULL, | |
826b5de9 | 254 | SNDRV_PCM_HW_PARAM_PERIOD_SIZE, |
59502295 TS |
255 | SNDRV_PCM_HW_PARAM_RATE, -1); |
256 | if (err < 0) | |
257 | goto end; | |
59502295 TS |
258 | err = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, |
259 | apply_constraint_to_size, NULL, | |
826b5de9 | 260 | SNDRV_PCM_HW_PARAM_BUFFER_SIZE, |
59502295 TS |
261 | SNDRV_PCM_HW_PARAM_RATE, -1); |
262 | if (err < 0) | |
263 | goto end; | |
7b2d99fa TS |
264 | end: |
265 | return err; | |
266 | } | |
267 | EXPORT_SYMBOL(amdtp_stream_add_pcm_hw_constraints); | |
268 | ||
31ef9134 | 269 | /** |
be4a2894 TS |
270 | * amdtp_stream_set_parameters - set stream parameters |
271 | * @s: the AMDTP stream to configure | |
31ef9134 | 272 | * @rate: the sample rate |
df075fee | 273 | * @data_block_quadlets: the size of a data block in quadlet unit |
a36183f6 TS |
274 | * @pcm_frame_multiplier: the multiplier to compute the number of PCM frames by the number of AMDTP |
275 | * events. | |
31ef9134 | 276 | * |
a7304e3b | 277 | * The parameters must be set before the stream is started, and must not be |
31ef9134 CL |
278 | * changed while the stream is running. |
279 | */ | |
df075fee | 280 | int amdtp_stream_set_parameters(struct amdtp_stream *s, unsigned int rate, |
a36183f6 | 281 | unsigned int data_block_quadlets, unsigned int pcm_frame_multiplier) |
31ef9134 | 282 | { |
df075fee | 283 | unsigned int sfc; |
31ef9134 | 284 | |
547e631c | 285 | for (sfc = 0; sfc < ARRAY_SIZE(amdtp_rate_table); ++sfc) { |
1017abed | 286 | if (amdtp_rate_table[sfc] == rate) |
547e631c TS |
287 | break; |
288 | } | |
289 | if (sfc == ARRAY_SIZE(amdtp_rate_table)) | |
290 | return -EINVAL; | |
e84d15f6 | 291 | |
e84d15f6 | 292 | s->sfc = sfc; |
df075fee | 293 | s->data_block_quadlets = data_block_quadlets; |
a7304e3b | 294 | s->syt_interval = amdtp_syt_intervals[sfc]; |
e84d15f6 | 295 | |
d3d10a4a | 296 | // default buffering in the device. |
13d11f14 TS |
297 | s->transfer_delay = TRANSFER_DELAY_TICKS - TICKS_PER_CYCLE; |
298 | ||
299 | // additional buffering needed to adjust for no-data packets. | |
300 | if (s->flags & CIP_BLOCKING) | |
301 | s->transfer_delay += TICKS_PER_SECOND * s->syt_interval / rate; | |
77d2a8a4 | 302 | |
a36183f6 TS |
303 | s->pcm_frame_multiplier = pcm_frame_multiplier; |
304 | ||
547e631c | 305 | return 0; |
31ef9134 | 306 | } |
be4a2894 | 307 | EXPORT_SYMBOL(amdtp_stream_set_parameters); |
31ef9134 | 308 | |
c75f3678 TS |
309 | // The CIP header is processed in context header apart from context payload. |
310 | static int amdtp_stream_get_max_ctx_payload_size(struct amdtp_stream *s) | |
311 | { | |
312 | unsigned int multiplier; | |
313 | ||
314 | if (s->flags & CIP_JUMBO_PAYLOAD) | |
315 | multiplier = IR_JUMBO_PAYLOAD_MAX_SKIP_CYCLES; | |
316 | else | |
317 | multiplier = 1; | |
318 | ||
319 | return s->syt_interval * s->data_block_quadlets * sizeof(__be32) * multiplier; | |
320 | } | |
321 | ||
31ef9134 | 322 | /** |
be4a2894 TS |
323 | * amdtp_stream_get_max_payload - get the stream's packet size |
324 | * @s: the AMDTP stream | |
31ef9134 CL |
325 | * |
326 | * This function must not be called before the stream has been configured | |
be4a2894 | 327 | * with amdtp_stream_set_parameters(). |
31ef9134 | 328 | */ |
be4a2894 | 329 | unsigned int amdtp_stream_get_max_payload(struct amdtp_stream *s) |
31ef9134 | 330 | { |
c75f3678 | 331 | unsigned int cip_header_size; |
a2064710 | 332 | |
3b196c39 | 333 | if (!(s->flags & CIP_NO_HEADER)) |
67d92ee7 | 334 | cip_header_size = CIP_HEADER_SIZE; |
c75f3678 TS |
335 | else |
336 | cip_header_size = 0; | |
a2064710 | 337 | |
c75f3678 | 338 | return cip_header_size + amdtp_stream_get_max_ctx_payload_size(s); |
31ef9134 | 339 | } |
be4a2894 | 340 | EXPORT_SYMBOL(amdtp_stream_get_max_payload); |
31ef9134 | 341 | |
76fb8789 | 342 | /** |
be4a2894 TS |
343 | * amdtp_stream_pcm_prepare - prepare PCM device for running |
344 | * @s: the AMDTP stream | |
76fb8789 CL |
345 | * |
346 | * This function should be called from the PCM device's .prepare callback. | |
347 | */ | |
be4a2894 | 348 | void amdtp_stream_pcm_prepare(struct amdtp_stream *s) |
76fb8789 | 349 | { |
76fb8789 CL |
350 | s->pcm_buffer_pointer = 0; |
351 | s->pcm_period_pointer = 0; | |
352 | } | |
be4a2894 | 353 | EXPORT_SYMBOL(amdtp_stream_pcm_prepare); |
76fb8789 | 354 | |
af13842c TS |
355 | #define prev_packet_desc(s, desc) \ |
356 | list_prev_entry_circular(desc, &s->packet_descs_list, link) | |
357 | ||
c9f3ac2a | 358 | static void pool_blocking_data_blocks(struct amdtp_stream *s, struct seq_desc *descs, |
119c446a | 359 | unsigned int size, unsigned int pos, unsigned int count) |
31ef9134 | 360 | { |
c9f3ac2a TS |
361 | const unsigned int syt_interval = s->syt_interval; |
362 | int i; | |
31ef9134 | 363 | |
c9f3ac2a | 364 | for (i = 0; i < count; ++i) { |
119c446a | 365 | struct seq_desc *desc = descs + pos; |
c9f3ac2a TS |
366 | |
367 | if (desc->syt_offset != CIP_SYT_NO_INFO) | |
368 | desc->data_blocks = syt_interval; | |
875be091 | 369 | else |
c9f3ac2a TS |
370 | desc->data_blocks = 0; |
371 | ||
119c446a | 372 | pos = (pos + 1) % size; |
c9f3ac2a TS |
373 | } |
374 | } | |
375 | ||
376 | static void pool_ideal_nonblocking_data_blocks(struct amdtp_stream *s, struct seq_desc *descs, | |
119c446a | 377 | unsigned int size, unsigned int pos, |
c9f3ac2a TS |
378 | unsigned int count) |
379 | { | |
380 | const enum cip_sfc sfc = s->sfc; | |
381 | unsigned int state = s->ctx_data.rx.data_block_state; | |
382 | int i; | |
383 | ||
384 | for (i = 0; i < count; ++i) { | |
119c446a | 385 | struct seq_desc *desc = descs + pos; |
c9f3ac2a | 386 | |
274fc355 | 387 | if (!cip_sfc_is_base_44100(sfc)) { |
d3d10a4a | 388 | // Sample_rate / 8000 is an integer, and precomputed. |
c9f3ac2a | 389 | desc->data_blocks = state; |
875be091 | 390 | } else { |
c9f3ac2a | 391 | unsigned int phase = state; |
31ef9134 CL |
392 | |
393 | /* | |
394 | * This calculates the number of data blocks per packet so that | |
395 | * 1) the overall rate is correct and exactly synchronized to | |
396 | * the bus clock, and | |
397 | * 2) packets with a rounded-up number of blocks occur as early | |
398 | * as possible in the sequence (to prevent underruns of the | |
399 | * device's buffer). | |
400 | */ | |
274fc355 | 401 | if (sfc == CIP_SFC_44100) |
875be091 | 402 | /* 6 6 5 6 5 6 5 ... */ |
c9f3ac2a | 403 | desc->data_blocks = 5 + ((phase & 1) ^ (phase == 0 || phase >= 40)); |
875be091 TS |
404 | else |
405 | /* 12 11 11 11 11 ... or 23 22 22 22 22 ... */ | |
c9f3ac2a | 406 | desc->data_blocks = 11 * (sfc >> 1) + (phase == 0); |
274fc355 | 407 | if (++phase >= (80 >> (sfc >> 1))) |
875be091 | 408 | phase = 0; |
c9f3ac2a | 409 | state = phase; |
875be091 | 410 | } |
c9f3ac2a | 411 | |
119c446a | 412 | pos = (pos + 1) % size; |
31ef9134 CL |
413 | } |
414 | ||
c9f3ac2a | 415 | s->ctx_data.rx.data_block_state = state; |
31ef9134 CL |
416 | } |
417 | ||
816d8482 TS |
418 | static unsigned int calculate_syt_offset(unsigned int *last_syt_offset, |
419 | unsigned int *syt_offset_state, enum cip_sfc sfc) | |
31ef9134 | 420 | { |
816d8482 | 421 | unsigned int syt_offset; |
31ef9134 | 422 | |
816d8482 TS |
423 | if (*last_syt_offset < TICKS_PER_CYCLE) { |
424 | if (!cip_sfc_is_base_44100(sfc)) | |
425 | syt_offset = *last_syt_offset + *syt_offset_state; | |
31ef9134 CL |
426 | else { |
427 | /* | |
428 | * The time, in ticks, of the n'th SYT_INTERVAL sample is: | |
429 | * n * SYT_INTERVAL * 24576000 / sample_rate | |
430 | * Modulo TICKS_PER_CYCLE, the difference between successive | |
431 | * elements is about 1386.23. Rounding the results of this | |
432 | * formula to the SYT precision results in a sequence of | |
433 | * differences that begins with: | |
434 | * 1386 1386 1387 1386 1386 1386 1387 1386 1386 1386 1387 ... | |
435 | * This code generates _exactly_ the same sequence. | |
436 | */ | |
816d8482 TS |
437 | unsigned int phase = *syt_offset_state; |
438 | unsigned int index = phase % 13; | |
439 | ||
440 | syt_offset = *last_syt_offset; | |
31ef9134 CL |
441 | syt_offset += 1386 + ((index && !(index & 3)) || |
442 | phase == 146); | |
443 | if (++phase >= 147) | |
444 | phase = 0; | |
816d8482 | 445 | *syt_offset_state = phase; |
31ef9134 CL |
446 | } |
447 | } else | |
816d8482 TS |
448 | syt_offset = *last_syt_offset - TICKS_PER_CYCLE; |
449 | *last_syt_offset = syt_offset; | |
31ef9134 | 450 | |
83cfb5c5 TS |
451 | if (syt_offset >= TICKS_PER_CYCLE) |
452 | syt_offset = CIP_SYT_NO_INFO; | |
31ef9134 | 453 | |
83cfb5c5 | 454 | return syt_offset; |
31ef9134 CL |
455 | } |
456 | ||
c79b7158 | 457 | static void pool_ideal_syt_offsets(struct amdtp_stream *s, struct seq_desc *descs, |
119c446a | 458 | unsigned int size, unsigned int pos, unsigned int count) |
c79b7158 TS |
459 | { |
460 | const enum cip_sfc sfc = s->sfc; | |
461 | unsigned int last = s->ctx_data.rx.last_syt_offset; | |
462 | unsigned int state = s->ctx_data.rx.syt_offset_state; | |
463 | int i; | |
464 | ||
465 | for (i = 0; i < count; ++i) { | |
119c446a | 466 | struct seq_desc *desc = descs + pos; |
c79b7158 TS |
467 | |
468 | desc->syt_offset = calculate_syt_offset(&last, &state, sfc); | |
469 | ||
119c446a | 470 | pos = (pos + 1) % size; |
c79b7158 TS |
471 | } |
472 | ||
473 | s->ctx_data.rx.last_syt_offset = last; | |
474 | s->ctx_data.rx.syt_offset_state = state; | |
475 | } | |
476 | ||
f9e5ecdf TS |
477 | static unsigned int compute_syt_offset(unsigned int syt, unsigned int cycle, |
478 | unsigned int transfer_delay) | |
479 | { | |
480 | unsigned int cycle_lo = (cycle % CYCLES_PER_SECOND) & 0x0f; | |
481 | unsigned int syt_cycle_lo = (syt & 0xf000) >> 12; | |
482 | unsigned int syt_offset; | |
483 | ||
484 | // Round up. | |
485 | if (syt_cycle_lo < cycle_lo) | |
486 | syt_cycle_lo += CIP_SYT_CYCLE_MODULUS; | |
487 | syt_cycle_lo -= cycle_lo; | |
488 | ||
489 | // Subtract transfer delay so that the synchronization offset is not so large | |
490 | // at transmission. | |
491 | syt_offset = syt_cycle_lo * TICKS_PER_CYCLE + (syt & 0x0fff); | |
492 | if (syt_offset < transfer_delay) | |
493 | syt_offset += CIP_SYT_CYCLE_MODULUS * TICKS_PER_CYCLE; | |
494 | ||
495 | return syt_offset - transfer_delay; | |
496 | } | |
497 | ||
39c2649c TS |
498 | // Both of the producer and consumer of the queue runs in the same clock of IEEE 1394 bus. |
499 | // Additionally, the sequence of tx packets is severely checked against any discontinuity | |
500 | // before filling entries in the queue. The calculation is safe even if it looks fragile by | |
501 | // overrun. | |
502 | static unsigned int calculate_cached_cycle_count(struct amdtp_stream *s, unsigned int head) | |
503 | { | |
504 | const unsigned int cache_size = s->ctx_data.tx.cache.size; | |
cccddec4 | 505 | unsigned int cycles = s->ctx_data.tx.cache.pos; |
39c2649c TS |
506 | |
507 | if (cycles < head) | |
508 | cycles += cache_size; | |
509 | cycles -= head; | |
510 | ||
511 | return cycles; | |
512 | } | |
513 | ||
cec371ff | 514 | static void cache_seq(struct amdtp_stream *s, const struct pkt_desc *src, unsigned int desc_count) |
f9e5ecdf TS |
515 | { |
516 | const unsigned int transfer_delay = s->transfer_delay; | |
517 | const unsigned int cache_size = s->ctx_data.tx.cache.size; | |
518 | struct seq_desc *cache = s->ctx_data.tx.cache.descs; | |
cccddec4 | 519 | unsigned int cache_pos = s->ctx_data.tx.cache.pos; |
f9e5ecdf TS |
520 | bool aware_syt = !(s->flags & CIP_UNAWARE_SYT); |
521 | int i; | |
522 | ||
523 | for (i = 0; i < desc_count; ++i) { | |
cccddec4 | 524 | struct seq_desc *dst = cache + cache_pos; |
f9e5ecdf TS |
525 | |
526 | if (aware_syt && src->syt != CIP_SYT_NO_INFO) | |
527 | dst->syt_offset = compute_syt_offset(src->syt, src->cycle, transfer_delay); | |
528 | else | |
529 | dst->syt_offset = CIP_SYT_NO_INFO; | |
530 | dst->data_blocks = src->data_blocks; | |
531 | ||
cccddec4 | 532 | cache_pos = (cache_pos + 1) % cache_size; |
cec371ff | 533 | src = amdtp_stream_next_packet_desc(s, src); |
f9e5ecdf TS |
534 | } |
535 | ||
cccddec4 | 536 | s->ctx_data.tx.cache.pos = cache_pos; |
f9e5ecdf TS |
537 | } |
538 | ||
119c446a TS |
539 | static void pool_ideal_seq_descs(struct amdtp_stream *s, struct seq_desc *descs, unsigned int size, |
540 | unsigned int pos, unsigned int count) | |
6f24bb8a | 541 | { |
119c446a | 542 | pool_ideal_syt_offsets(s, descs, size, pos, count); |
c79b7158 | 543 | |
c9f3ac2a | 544 | if (s->flags & CIP_BLOCKING) |
119c446a | 545 | pool_blocking_data_blocks(s, descs, size, pos, count); |
c9f3ac2a | 546 | else |
119c446a | 547 | pool_ideal_nonblocking_data_blocks(s, descs, size, pos, count); |
6f24bb8a TS |
548 | } |
549 | ||
119c446a TS |
550 | static void pool_replayed_seq(struct amdtp_stream *s, struct seq_desc *descs, unsigned int size, |
551 | unsigned int pos, unsigned int count) | |
39c2649c TS |
552 | { |
553 | struct amdtp_stream *target = s->ctx_data.rx.replay_target; | |
554 | const struct seq_desc *cache = target->ctx_data.tx.cache.descs; | |
555 | const unsigned int cache_size = target->ctx_data.tx.cache.size; | |
c38d8cff | 556 | unsigned int cache_pos = s->ctx_data.rx.cache_pos; |
39c2649c TS |
557 | int i; |
558 | ||
559 | for (i = 0; i < count; ++i) { | |
c38d8cff TS |
560 | descs[pos] = cache[cache_pos]; |
561 | cache_pos = (cache_pos + 1) % cache_size; | |
119c446a | 562 | pos = (pos + 1) % size; |
39c2649c TS |
563 | } |
564 | ||
c38d8cff | 565 | s->ctx_data.rx.cache_pos = cache_pos; |
39c2649c TS |
566 | } |
567 | ||
f2bdee85 TS |
568 | static void pool_seq_descs(struct amdtp_stream *s, struct seq_desc *descs, unsigned int size, |
569 | unsigned int pos, unsigned int count) | |
39c2649c TS |
570 | { |
571 | struct amdtp_domain *d = s->domain; | |
119c446a TS |
572 | void (*pool_seq_descs)(struct amdtp_stream *s, struct seq_desc *descs, unsigned int size, |
573 | unsigned int pos, unsigned int count); | |
39c2649c | 574 | |
2f21a177 | 575 | if (!d->replay.enable || !s->ctx_data.rx.replay_target) { |
119c446a | 576 | pool_seq_descs = pool_ideal_seq_descs; |
2f21a177 TS |
577 | } else { |
578 | if (!d->replay.on_the_fly) { | |
119c446a | 579 | pool_seq_descs = pool_replayed_seq; |
2f21a177 TS |
580 | } else { |
581 | struct amdtp_stream *tx = s->ctx_data.rx.replay_target; | |
582 | const unsigned int cache_size = tx->ctx_data.tx.cache.size; | |
c38d8cff TS |
583 | const unsigned int cache_pos = s->ctx_data.rx.cache_pos; |
584 | unsigned int cached_cycles = calculate_cached_cycle_count(tx, cache_pos); | |
2f21a177 TS |
585 | |
586 | if (cached_cycles > count && cached_cycles > cache_size / 2) | |
119c446a | 587 | pool_seq_descs = pool_replayed_seq; |
2f21a177 | 588 | else |
119c446a | 589 | pool_seq_descs = pool_ideal_seq_descs; |
2f21a177 TS |
590 | } |
591 | } | |
119c446a TS |
592 | |
593 | pool_seq_descs(s, descs, size, pos, count); | |
39c2649c TS |
594 | } |
595 | ||
4b7da117 TS |
596 | static void update_pcm_pointers(struct amdtp_stream *s, |
597 | struct snd_pcm_substream *pcm, | |
598 | unsigned int frames) | |
65845f29 TS |
599 | { |
600 | unsigned int ptr; | |
601 | ||
4b7da117 TS |
602 | ptr = s->pcm_buffer_pointer + frames; |
603 | if (ptr >= pcm->runtime->buffer_size) | |
604 | ptr -= pcm->runtime->buffer_size; | |
6aa7de05 | 605 | WRITE_ONCE(s->pcm_buffer_pointer, ptr); |
4b7da117 TS |
606 | |
607 | s->pcm_period_pointer += frames; | |
608 | if (s->pcm_period_pointer >= pcm->runtime->period_size) { | |
609 | s->pcm_period_pointer -= pcm->runtime->period_size; | |
d360870a TS |
610 | |
611 | // The program in user process should periodically check the status of intermediate | |
612 | // buffer associated to PCM substream to process PCM frames in the buffer, instead | |
613 | // of receiving notification of period elapsed by poll wait. | |
7ba5ca32 | 614 | if (!pcm->runtime->no_period_wakeup) { |
3b86ec63 | 615 | if (in_softirq()) { |
7ba5ca32 TS |
616 | // In software IRQ context for 1394 OHCI. |
617 | snd_pcm_period_elapsed(pcm); | |
618 | } else { | |
619 | // In process context of ALSA PCM application under acquired lock of | |
620 | // PCM substream. | |
621 | snd_pcm_period_elapsed_under_stream_lock(pcm); | |
622 | } | |
623 | } | |
4b7da117 TS |
624 | } |
625 | } | |
626 | ||
e229853d TS |
627 | static int queue_packet(struct amdtp_stream *s, struct fw_iso_packet *params, |
628 | bool sched_irq) | |
4b7da117 | 629 | { |
6007bf54 | 630 | int err; |
df9160b9 | 631 | |
e229853d | 632 | params->interrupt = sched_irq; |
6007bf54 TS |
633 | params->tag = s->tag; |
634 | params->sy = 0; | |
df9160b9 | 635 | |
6007bf54 | 636 | err = fw_iso_context_queue(s->context, params, &s->buffer.iso_buffer, |
4b7da117 TS |
637 | s->buffer.packets[s->packet_index].offset); |
638 | if (err < 0) { | |
639 | dev_err(&s->unit->device, "queueing error: %d\n", err); | |
640 | goto end; | |
641 | } | |
642 | ||
a0e02331 | 643 | if (++s->packet_index >= s->queue_size) |
4b7da117 TS |
644 | s->packet_index = 0; |
645 | end: | |
646 | return err; | |
647 | } | |
648 | ||
649 | static inline int queue_out_packet(struct amdtp_stream *s, | |
e229853d | 650 | struct fw_iso_packet *params, bool sched_irq) |
4b7da117 | 651 | { |
b18f0cfa TS |
652 | params->skip = |
653 | !!(params->header_length == 0 && params->payload_length == 0); | |
e229853d | 654 | return queue_packet(s, params, sched_irq); |
4b7da117 TS |
655 | } |
656 | ||
6007bf54 | 657 | static inline int queue_in_packet(struct amdtp_stream *s, |
60dd4929 | 658 | struct fw_iso_packet *params) |
2b3fc456 | 659 | { |
6007bf54 TS |
660 | // Queue one packet for IR context. |
661 | params->header_length = s->ctx_data.tx.ctx_header_size; | |
662 | params->payload_length = s->ctx_data.tx.max_ctx_payload_length; | |
663 | params->skip = false; | |
60dd4929 | 664 | return queue_packet(s, params, false); |
2b3fc456 TS |
665 | } |
666 | ||
252219c7 | 667 | static void generate_cip_header(struct amdtp_stream *s, __be32 cip_header[2], |
860d798c | 668 | unsigned int data_block_counter, unsigned int syt) |
252219c7 TS |
669 | { |
670 | cip_header[0] = cpu_to_be32(READ_ONCE(s->source_node_id_field) | | |
671 | (s->data_block_quadlets << CIP_DBS_SHIFT) | | |
672 | ((s->sph << CIP_SPH_SHIFT) & CIP_SPH_MASK) | | |
860d798c | 673 | data_block_counter); |
252219c7 TS |
674 | cip_header[1] = cpu_to_be32(CIP_EOH | |
675 | ((s->fmt << CIP_FMT_SHIFT) & CIP_FMT_MASK) | | |
676 | ((s->ctx_data.rx.fdf << CIP_FDF_SHIFT) & CIP_FDF_MASK) | | |
677 | (syt & CIP_SYT_MASK)); | |
678 | } | |
679 | ||
6bc1a269 | 680 | static void build_it_pkt_header(struct amdtp_stream *s, unsigned int cycle, |
233dbbc7 | 681 | struct fw_iso_packet *params, unsigned int header_length, |
860d798c TS |
682 | unsigned int data_blocks, |
683 | unsigned int data_block_counter, | |
fef4e61b | 684 | unsigned int syt, unsigned int index, u32 curr_cycle_time) |
31ef9134 | 685 | { |
0ebf3ceb | 686 | unsigned int payload_length; |
16be4589 | 687 | __be32 *cip_header; |
20e44577 | 688 | |
0ebf3ceb TS |
689 | payload_length = data_blocks * sizeof(__be32) * s->data_block_quadlets; |
690 | params->payload_length = payload_length; | |
691 | ||
233dbbc7 | 692 | if (header_length > 0) { |
6bc1a269 | 693 | cip_header = (__be32 *)params->header; |
860d798c | 694 | generate_cip_header(s, cip_header, data_block_counter, syt); |
233dbbc7 | 695 | params->header_length = header_length; |
b18f0cfa TS |
696 | } else { |
697 | cip_header = NULL; | |
698 | } | |
31ef9134 | 699 | |
233dbbc7 | 700 | trace_amdtp_packet(s, cycle, cip_header, payload_length + header_length, data_blocks, |
fef4e61b | 701 | data_block_counter, s->packet_index, index, curr_cycle_time); |
3b196c39 TS |
702 | } |
703 | ||
e335425b TS |
704 | static int check_cip_header(struct amdtp_stream *s, const __be32 *buf, |
705 | unsigned int payload_length, | |
a35463d1 TS |
706 | unsigned int *data_blocks, |
707 | unsigned int *data_block_counter, unsigned int *syt) | |
2b3fc456 TS |
708 | { |
709 | u32 cip_header[2]; | |
e335425b TS |
710 | unsigned int sph; |
711 | unsigned int fmt; | |
712 | unsigned int fdf; | |
a35463d1 | 713 | unsigned int dbc; |
c8bdf49b | 714 | bool lost; |
2b3fc456 | 715 | |
e335425b TS |
716 | cip_header[0] = be32_to_cpu(buf[0]); |
717 | cip_header[1] = be32_to_cpu(buf[1]); | |
2b3fc456 TS |
718 | |
719 | /* | |
720 | * This module supports 'Two-quadlet CIP header with SYT field'. | |
77d2a8a4 | 721 | * For convenience, also check FMT field is AM824 or not. |
2b3fc456 | 722 | */ |
2128f78f TS |
723 | if ((((cip_header[0] & CIP_EOH_MASK) == CIP_EOH) || |
724 | ((cip_header[1] & CIP_EOH_MASK) != CIP_EOH)) && | |
725 | (!(s->flags & CIP_HEADER_WITHOUT_EOH))) { | |
2b3fc456 TS |
726 | dev_info_ratelimited(&s->unit->device, |
727 | "Invalid CIP header for AMDTP: %08X:%08X\n", | |
728 | cip_header[0], cip_header[1]); | |
e335425b | 729 | return -EAGAIN; |
2b3fc456 TS |
730 | } |
731 | ||
414ba022 | 732 | /* Check valid protocol or not. */ |
9863874f | 733 | sph = (cip_header[0] & CIP_SPH_MASK) >> CIP_SPH_SHIFT; |
414ba022 | 734 | fmt = (cip_header[1] & CIP_FMT_MASK) >> CIP_FMT_SHIFT; |
9863874f | 735 | if (sph != s->sph || fmt != s->fmt) { |
2a7e1713 TS |
736 | dev_info_ratelimited(&s->unit->device, |
737 | "Detect unexpected protocol: %08x %08x\n", | |
738 | cip_header[0], cip_header[1]); | |
e335425b | 739 | return -EAGAIN; |
414ba022 TS |
740 | } |
741 | ||
2b3fc456 | 742 | /* Calculate data blocks */ |
414ba022 | 743 | fdf = (cip_header[1] & CIP_FDF_MASK) >> CIP_FDF_SHIFT; |
4fd18787 | 744 | if (payload_length == 0 || (fmt == CIP_FMT_AM && fdf == AMDTP_FDF_NO_DATA)) { |
e335425b | 745 | *data_blocks = 0; |
2b3fc456 | 746 | } else { |
e335425b TS |
747 | unsigned int data_block_quadlets = |
748 | (cip_header[0] & CIP_DBS_MASK) >> CIP_DBS_SHIFT; | |
2b3fc456 TS |
749 | /* avoid division by zero */ |
750 | if (data_block_quadlets == 0) { | |
12e0f438 | 751 | dev_err(&s->unit->device, |
2b3fc456 TS |
752 | "Detect invalid value in dbs field: %08X\n", |
753 | cip_header[0]); | |
a9007054 | 754 | return -EPROTO; |
2b3fc456 | 755 | } |
69702239 TS |
756 | if (s->flags & CIP_WRONG_DBS) |
757 | data_block_quadlets = s->data_block_quadlets; | |
2b3fc456 | 758 | |
4fd18787 | 759 | *data_blocks = payload_length / sizeof(__be32) / data_block_quadlets; |
2b3fc456 TS |
760 | } |
761 | ||
762 | /* Check data block counter continuity */ | |
a35463d1 | 763 | dbc = cip_header[0] & CIP_DBC_MASK; |
e335425b | 764 | if (*data_blocks == 0 && (s->flags & CIP_EMPTY_HAS_WRONG_DBC) && |
a35463d1 TS |
765 | *data_block_counter != UINT_MAX) |
766 | dbc = *data_block_counter; | |
9d59124c | 767 | |
a35463d1 TS |
768 | if ((dbc == 0x00 && (s->flags & CIP_SKIP_DBC_ZERO_CHECK)) || |
769 | *data_block_counter == UINT_MAX) { | |
b84b1a27 TS |
770 | lost = false; |
771 | } else if (!(s->flags & CIP_DBC_IS_END_EVENT)) { | |
a35463d1 | 772 | lost = dbc != *data_block_counter; |
d9cd0065 | 773 | } else { |
e335425b TS |
774 | unsigned int dbc_interval; |
775 | ||
776 | if (*data_blocks > 0 && s->ctx_data.tx.dbc_interval > 0) | |
d3d10a4a | 777 | dbc_interval = s->ctx_data.tx.dbc_interval; |
d9cd0065 | 778 | else |
e335425b | 779 | dbc_interval = *data_blocks; |
d9cd0065 | 780 | |
a35463d1 | 781 | lost = dbc != ((*data_block_counter + dbc_interval) & 0xff); |
d9cd0065 | 782 | } |
c8bdf49b TS |
783 | |
784 | if (lost) { | |
12e0f438 TS |
785 | dev_err(&s->unit->device, |
786 | "Detect discontinuity of CIP: %02X %02X\n", | |
a35463d1 | 787 | *data_block_counter, dbc); |
6fc6b9ce | 788 | return -EIO; |
2b3fc456 TS |
789 | } |
790 | ||
753e7179 TS |
791 | *data_block_counter = dbc; |
792 | ||
8070d265 TS |
793 | if (!(s->flags & CIP_UNAWARE_SYT)) |
794 | *syt = cip_header[1] & CIP_SYT_MASK; | |
2b3fc456 | 795 | |
e335425b TS |
796 | return 0; |
797 | } | |
798 | ||
98e3e43b TS |
799 | static int parse_ir_ctx_header(struct amdtp_stream *s, unsigned int cycle, |
800 | const __be32 *ctx_header, | |
a35463d1 TS |
801 | unsigned int *data_blocks, |
802 | unsigned int *data_block_counter, | |
fef4e61b TS |
803 | unsigned int *syt, unsigned int packet_index, unsigned int index, |
804 | u32 curr_cycle_time) | |
e335425b | 805 | { |
ebd2a647 | 806 | unsigned int payload_length; |
f11453c7 | 807 | const __be32 *cip_header; |
395f41e2 | 808 | unsigned int cip_header_size; |
e335425b | 809 | |
ebd2a647 | 810 | payload_length = be32_to_cpu(ctx_header[0]) >> ISO_DATA_LENGTH_SHIFT; |
395f41e2 TS |
811 | |
812 | if (!(s->flags & CIP_NO_HEADER)) | |
67d92ee7 | 813 | cip_header_size = CIP_HEADER_SIZE; |
395f41e2 TS |
814 | else |
815 | cip_header_size = 0; | |
816 | ||
ebd2a647 | 817 | if (payload_length > cip_header_size + s->ctx_data.tx.max_ctx_payload_length) { |
e335425b TS |
818 | dev_err(&s->unit->device, |
819 | "Detect jumbo payload: %04x %04x\n", | |
ebd2a647 | 820 | payload_length, cip_header_size + s->ctx_data.tx.max_ctx_payload_length); |
e335425b TS |
821 | return -EIO; |
822 | } | |
823 | ||
395f41e2 | 824 | if (cip_header_size > 0) { |
ebd2a647 | 825 | if (payload_length >= cip_header_size) { |
344f0f82 TS |
826 | int err; |
827 | ||
67d92ee7 | 828 | cip_header = ctx_header + IR_CTX_HEADER_DEFAULT_QUADLETS; |
4fd18787 TS |
829 | err = check_cip_header(s, cip_header, payload_length - cip_header_size, |
830 | data_blocks, data_block_counter, syt); | |
c09010ee TS |
831 | if (err < 0) |
832 | return err; | |
833 | } else { | |
834 | // Handle the cycle so that empty packet arrives. | |
835 | cip_header = NULL; | |
836 | *data_blocks = 0; | |
837 | *syt = 0; | |
838 | } | |
947b437e TS |
839 | } else { |
840 | cip_header = NULL; | |
ebd2a647 | 841 | *data_blocks = payload_length / sizeof(__be32) / s->data_block_quadlets; |
98e3e43b | 842 | *syt = 0; |
7fbf9096 | 843 | |
a35463d1 TS |
844 | if (*data_block_counter == UINT_MAX) |
845 | *data_block_counter = 0; | |
e335425b TS |
846 | } |
847 | ||
ebd2a647 | 848 | trace_amdtp_packet(s, cycle, cip_header, payload_length, *data_blocks, |
fef4e61b | 849 | *data_block_counter, packet_index, index, curr_cycle_time); |
e335425b | 850 | |
344f0f82 | 851 | return 0; |
2b3fc456 TS |
852 | } |
853 | ||
26cd1e58 TS |
854 | // In CYCLE_TIMER register of IEEE 1394, 7 bits are used to represent second. On |
855 | // the other hand, in DMA descriptors of 1394 OHCI, 3 bits are used to represent | |
856 | // it. Thus, via Linux firewire subsystem, we can get the 3 bits for second. | |
af13842c TS |
857 | static inline u32 compute_ohci_iso_ctx_cycle_count(u32 tstamp) |
858 | { | |
859 | return (((tstamp >> 13) & 0x07) * CYCLES_PER_SECOND) + (tstamp & 0x1fff); | |
860 | } | |
861 | ||
3e106f4f | 862 | static inline u32 compute_ohci_cycle_count(__be32 ctx_header_tstamp) |
73fc7f08 | 863 | { |
26cd1e58 | 864 | u32 tstamp = be32_to_cpu(ctx_header_tstamp) & HEADER_TSTAMP_MASK; |
af13842c | 865 | return compute_ohci_iso_ctx_cycle_count(tstamp); |
73fc7f08 TS |
866 | } |
867 | ||
3e106f4f | 868 | static inline u32 increment_ohci_cycle_count(u32 cycle, unsigned int addend) |
73fc7f08 TS |
869 | { |
870 | cycle += addend; | |
3e106f4f TS |
871 | if (cycle >= OHCI_SECOND_MODULUS * CYCLES_PER_SECOND) |
872 | cycle -= OHCI_SECOND_MODULUS * CYCLES_PER_SECOND; | |
73fc7f08 TS |
873 | return cycle; |
874 | } | |
875 | ||
af13842c TS |
876 | static inline u32 decrement_ohci_cycle_count(u32 minuend, u32 subtrahend) |
877 | { | |
878 | if (minuend < subtrahend) | |
879 | minuend += OHCI_SECOND_MODULUS * CYCLES_PER_SECOND; | |
880 | ||
881 | return minuend - subtrahend; | |
882 | } | |
883 | ||
705794c5 TS |
884 | static int compare_ohci_cycle_count(u32 lval, u32 rval) |
885 | { | |
886 | if (lval == rval) | |
887 | return 0; | |
888 | else if (lval < rval && rval - lval < OHCI_SECOND_MODULUS * CYCLES_PER_SECOND / 2) | |
889 | return -1; | |
890 | else | |
891 | return 1; | |
892 | } | |
893 | ||
26cd1e58 | 894 | // Align to actual cycle count for the packet which is going to be scheduled. |
a0e02331 TS |
895 | // This module queued the same number of isochronous cycle as the size of queue |
896 | // to kip isochronous cycle, therefore it's OK to just increment the cycle by | |
897 | // the size of queue for scheduled cycle. | |
3e106f4f TS |
898 | static inline u32 compute_ohci_it_cycle(const __be32 ctx_header_tstamp, |
899 | unsigned int queue_size) | |
26cd1e58 | 900 | { |
3e106f4f TS |
901 | u32 cycle = compute_ohci_cycle_count(ctx_header_tstamp); |
902 | return increment_ohci_cycle_count(cycle, queue_size); | |
26cd1e58 TS |
903 | } |
904 | ||
cec371ff | 905 | static int generate_tx_packet_descs(struct amdtp_stream *s, struct pkt_desc *desc, |
cccddec4 TS |
906 | const __be32 *ctx_header, unsigned int packet_count, |
907 | unsigned int *desc_count) | |
753e7179 | 908 | { |
705794c5 | 909 | unsigned int next_cycle = s->next_cycle; |
753e7179 | 910 | unsigned int dbc = s->data_block_counter; |
814b4312 TS |
911 | unsigned int packet_index = s->packet_index; |
912 | unsigned int queue_size = s->queue_size; | |
d8dc8720 | 913 | u32 curr_cycle_time = 0; |
753e7179 TS |
914 | int i; |
915 | int err; | |
916 | ||
fef4e61b TS |
917 | if (trace_amdtp_packet_enabled()) |
918 | (void)fw_card_read_cycle_time(fw_parent_device(s->unit)->card, &curr_cycle_time); | |
919 | ||
73246fc4 | 920 | *desc_count = 0; |
cccddec4 | 921 | for (i = 0; i < packet_count; ++i) { |
753e7179 | 922 | unsigned int cycle; |
705794c5 | 923 | bool lost; |
753e7179 TS |
924 | unsigned int data_blocks; |
925 | unsigned int syt; | |
926 | ||
3e106f4f | 927 | cycle = compute_ohci_cycle_count(ctx_header[1]); |
705794c5 TS |
928 | lost = (next_cycle != cycle); |
929 | if (lost) { | |
930 | if (s->flags & CIP_NO_HEADER) { | |
931 | // Fireface skips transmission just for an isoc cycle corresponding | |
932 | // to empty packet. | |
73246fc4 TS |
933 | unsigned int prev_cycle = next_cycle; |
934 | ||
705794c5 TS |
935 | next_cycle = increment_ohci_cycle_count(next_cycle, 1); |
936 | lost = (next_cycle != cycle); | |
73246fc4 TS |
937 | if (!lost) { |
938 | // Prepare a description for the skipped cycle for | |
939 | // sequence replay. | |
940 | desc->cycle = prev_cycle; | |
941 | desc->syt = 0; | |
942 | desc->data_blocks = 0; | |
943 | desc->data_block_counter = dbc; | |
944 | desc->ctx_payload = NULL; | |
cec371ff | 945 | desc = amdtp_stream_next_packet_desc(s, desc); |
73246fc4 TS |
946 | ++(*desc_count); |
947 | } | |
705794c5 TS |
948 | } else if (s->flags & CIP_JUMBO_PAYLOAD) { |
949 | // OXFW970 skips transmission for several isoc cycles during | |
73246fc4 TS |
950 | // asynchronous transaction. The sequence replay is impossible due |
951 | // to the reason. | |
705794c5 TS |
952 | unsigned int safe_cycle = increment_ohci_cycle_count(next_cycle, |
953 | IR_JUMBO_PAYLOAD_MAX_SKIP_CYCLES); | |
954 | lost = (compare_ohci_cycle_count(safe_cycle, cycle) > 0); | |
955 | } | |
956 | if (lost) { | |
957 | dev_err(&s->unit->device, "Detect discontinuity of cycle: %d %d\n", | |
958 | next_cycle, cycle); | |
959 | return -EIO; | |
960 | } | |
961 | } | |
753e7179 | 962 | |
ebd2a647 | 963 | err = parse_ir_ctx_header(s, cycle, ctx_header, &data_blocks, &dbc, &syt, |
fef4e61b | 964 | packet_index, i, curr_cycle_time); |
753e7179 TS |
965 | if (err < 0) |
966 | return err; | |
967 | ||
968 | desc->cycle = cycle; | |
969 | desc->syt = syt; | |
970 | desc->data_blocks = data_blocks; | |
971 | desc->data_block_counter = dbc; | |
814b4312 | 972 | desc->ctx_payload = s->buffer.packets[packet_index].buffer; |
753e7179 TS |
973 | |
974 | if (!(s->flags & CIP_DBC_IS_END_EVENT)) | |
975 | dbc = (dbc + desc->data_blocks) & 0xff; | |
976 | ||
705794c5 | 977 | next_cycle = increment_ohci_cycle_count(next_cycle, 1); |
cec371ff | 978 | desc = amdtp_stream_next_packet_desc(s, desc); |
73246fc4 | 979 | ++(*desc_count); |
705794c5 | 980 | ctx_header += s->ctx_data.tx.ctx_header_size / sizeof(*ctx_header); |
814b4312 | 981 | packet_index = (packet_index + 1) % queue_size; |
753e7179 TS |
982 | } |
983 | ||
705794c5 | 984 | s->next_cycle = next_cycle; |
753e7179 TS |
985 | s->data_block_counter = dbc; |
986 | ||
987 | return 0; | |
988 | } | |
989 | ||
83cfb5c5 TS |
990 | static unsigned int compute_syt(unsigned int syt_offset, unsigned int cycle, |
991 | unsigned int transfer_delay) | |
992 | { | |
993 | unsigned int syt; | |
994 | ||
995 | syt_offset += transfer_delay; | |
996 | syt = ((cycle + syt_offset / TICKS_PER_CYCLE) << 12) | | |
997 | (syt_offset % TICKS_PER_CYCLE); | |
998 | return syt & CIP_SYT_MASK; | |
999 | } | |
1000 | ||
cec371ff | 1001 | static void generate_rx_packet_descs(struct amdtp_stream *s, struct pkt_desc *desc, |
f2bdee85 | 1002 | const __be32 *ctx_header, unsigned int packet_count) |
f4f6ae7b | 1003 | { |
f2bdee85 TS |
1004 | struct seq_desc *seq_descs = s->ctx_data.rx.seq.descs; |
1005 | unsigned int seq_size = s->ctx_data.rx.seq.size; | |
1006 | unsigned int seq_pos = s->ctx_data.rx.seq.pos; | |
f4f6ae7b | 1007 | unsigned int dbc = s->data_block_counter; |
8070d265 | 1008 | bool aware_syt = !(s->flags & CIP_UNAWARE_SYT); |
f4f6ae7b TS |
1009 | int i; |
1010 | ||
f2bdee85 TS |
1011 | pool_seq_descs(s, seq_descs, seq_size, seq_pos, packet_count); |
1012 | ||
1013 | for (i = 0; i < packet_count; ++i) { | |
a0e02331 | 1014 | unsigned int index = (s->packet_index + i) % s->queue_size; |
f2bdee85 | 1015 | const struct seq_desc *seq = seq_descs + seq_pos; |
f4f6ae7b | 1016 | |
3e106f4f | 1017 | desc->cycle = compute_ohci_it_cycle(*ctx_header, s->queue_size); |
69efd5c4 | 1018 | |
13d11f14 TS |
1019 | if (aware_syt && seq->syt_offset != CIP_SYT_NO_INFO) |
1020 | desc->syt = compute_syt(seq->syt_offset, desc->cycle, s->transfer_delay); | |
1021 | else | |
8070d265 | 1022 | desc->syt = CIP_SYT_NO_INFO; |
8070d265 | 1023 | |
69efd5c4 | 1024 | desc->data_blocks = seq->data_blocks; |
f4f6ae7b TS |
1025 | |
1026 | if (s->flags & CIP_DBC_IS_END_EVENT) | |
1027 | dbc = (dbc + desc->data_blocks) & 0xff; | |
1028 | ||
1029 | desc->data_block_counter = dbc; | |
1030 | ||
1031 | if (!(s->flags & CIP_DBC_IS_END_EVENT)) | |
1032 | dbc = (dbc + desc->data_blocks) & 0xff; | |
1033 | ||
1034 | desc->ctx_payload = s->buffer.packets[index].buffer; | |
1035 | ||
f2bdee85 | 1036 | seq_pos = (seq_pos + 1) % seq_size; |
cec371ff | 1037 | desc = amdtp_stream_next_packet_desc(s, desc); |
69efd5c4 | 1038 | |
f4f6ae7b TS |
1039 | ++ctx_header; |
1040 | } | |
1041 | ||
1042 | s->data_block_counter = dbc; | |
f2bdee85 | 1043 | s->ctx_data.rx.seq.pos = seq_pos; |
f4f6ae7b TS |
1044 | } |
1045 | ||
fce9b013 TS |
1046 | static inline void cancel_stream(struct amdtp_stream *s) |
1047 | { | |
1048 | s->packet_index = -1; | |
3b86ec63 | 1049 | if (in_softirq()) |
fce9b013 TS |
1050 | amdtp_stream_pcm_abort(s); |
1051 | WRITE_ONCE(s->pcm_buffer_pointer, SNDRV_PCM_POS_XRUN); | |
1052 | } | |
1053 | ||
af13842c TS |
1054 | static snd_pcm_sframes_t compute_pcm_extra_delay(struct amdtp_stream *s, |
1055 | const struct pkt_desc *desc, unsigned int count) | |
1056 | { | |
1057 | unsigned int data_block_count = 0; | |
1058 | u32 latest_cycle; | |
1059 | u32 cycle_time; | |
1060 | u32 curr_cycle; | |
1061 | u32 cycle_gap; | |
1062 | int i, err; | |
1063 | ||
1064 | if (count == 0) | |
1065 | goto end; | |
1066 | ||
1067 | // Forward to the latest record. | |
1068 | for (i = 0; i < count - 1; ++i) | |
1069 | desc = amdtp_stream_next_packet_desc(s, desc); | |
1070 | latest_cycle = desc->cycle; | |
1071 | ||
1072 | err = fw_card_read_cycle_time(fw_parent_device(s->unit)->card, &cycle_time); | |
1073 | if (err < 0) | |
1074 | goto end; | |
1075 | ||
1076 | // Compute cycle count with lower 3 bits of second field and cycle field like timestamp | |
1077 | // format of 1394 OHCI isochronous context. | |
1078 | curr_cycle = compute_ohci_iso_ctx_cycle_count((cycle_time >> 12) & 0x0000ffff); | |
1079 | ||
1080 | if (s->direction == AMDTP_IN_STREAM) { | |
1081 | // NOTE: The AMDTP packet descriptor should be for the past isochronous cycle since | |
1082 | // it corresponds to arrived isochronous packet. | |
1083 | if (compare_ohci_cycle_count(latest_cycle, curr_cycle) > 0) | |
1084 | goto end; | |
1085 | cycle_gap = decrement_ohci_cycle_count(curr_cycle, latest_cycle); | |
1086 | ||
1087 | // NOTE: estimate delay by recent history of arrived AMDTP packets. The estimated | |
1088 | // value expectedly corresponds to a few packets (0-2) since the packet arrived at | |
1089 | // the most recent isochronous cycle has been already processed. | |
1090 | for (i = 0; i < cycle_gap; ++i) { | |
1091 | desc = amdtp_stream_next_packet_desc(s, desc); | |
1092 | data_block_count += desc->data_blocks; | |
1093 | } | |
1094 | } else { | |
1095 | // NOTE: The AMDTP packet descriptor should be for the future isochronous cycle | |
1096 | // since it was already scheduled. | |
1097 | if (compare_ohci_cycle_count(latest_cycle, curr_cycle) < 0) | |
1098 | goto end; | |
1099 | cycle_gap = decrement_ohci_cycle_count(latest_cycle, curr_cycle); | |
1100 | ||
1101 | // NOTE: use history of scheduled packets. | |
1102 | for (i = 0; i < cycle_gap; ++i) { | |
1103 | data_block_count += desc->data_blocks; | |
1104 | desc = prev_packet_desc(s, desc); | |
1105 | } | |
1106 | } | |
1107 | end: | |
1108 | return data_block_count * s->pcm_frame_multiplier; | |
1109 | } | |
1110 | ||
0f5cfcb2 | 1111 | static void process_ctx_payloads(struct amdtp_stream *s, |
a36183f6 | 1112 | const struct pkt_desc *desc, |
0cac60c7 | 1113 | unsigned int count) |
31ef9134 | 1114 | { |
9a738ad1 | 1115 | struct snd_pcm_substream *pcm; |
a36183f6 | 1116 | int i; |
5e2ece0f | 1117 | |
9a738ad1 | 1118 | pcm = READ_ONCE(s->pcm); |
7fc693e4 | 1119 | s->process_ctx_payloads(s, desc, count, pcm); |
a36183f6 TS |
1120 | |
1121 | if (pcm) { | |
1122 | unsigned int data_block_count = 0; | |
1123 | ||
af13842c TS |
1124 | pcm->runtime->delay = compute_pcm_extra_delay(s, desc, count); |
1125 | ||
a36183f6 TS |
1126 | for (i = 0; i < count; ++i) { |
1127 | data_block_count += desc->data_blocks; | |
1128 | desc = amdtp_stream_next_packet_desc(s, desc); | |
1129 | } | |
1130 | ||
1131 | update_pcm_pointers(s, pcm, data_block_count * s->pcm_frame_multiplier); | |
1132 | } | |
0f5cfcb2 TS |
1133 | } |
1134 | ||
9b1fcd9b TS |
1135 | static void process_rx_packets(struct fw_iso_context *context, u32 tstamp, size_t header_length, |
1136 | void *header, void *private_data) | |
0f5cfcb2 TS |
1137 | { |
1138 | struct amdtp_stream *s = private_data; | |
69efd5c4 | 1139 | const struct amdtp_domain *d = s->domain; |
0f5cfcb2 | 1140 | const __be32 *ctx_header = header; |
9b1fcd9b | 1141 | const unsigned int events_per_period = d->events_per_period; |
60dd4929 | 1142 | unsigned int event_count = s->ctx_data.rx.event_count; |
f0117128 | 1143 | struct pkt_desc *desc = s->packet_descs_cursor; |
233dbbc7 | 1144 | unsigned int pkt_header_length; |
a0e02331 | 1145 | unsigned int packets; |
fef4e61b | 1146 | u32 curr_cycle_time; |
d360870a | 1147 | bool need_hw_irq; |
0f5cfcb2 TS |
1148 | int i; |
1149 | ||
1150 | if (s->packet_index < 0) | |
1151 | return; | |
1152 | ||
a0e02331 TS |
1153 | // Calculate the number of packets in buffer and check XRUN. |
1154 | packets = header_length / sizeof(*ctx_header); | |
1155 | ||
cec371ff | 1156 | generate_rx_packet_descs(s, desc, ctx_header, packets); |
0f5cfcb2 | 1157 | |
cec371ff | 1158 | process_ctx_payloads(s, desc, packets); |
5e2ece0f | 1159 | |
233dbbc7 TS |
1160 | if (!(s->flags & CIP_NO_HEADER)) |
1161 | pkt_header_length = IT_PKT_HEADER_SIZE_CIP; | |
1162 | else | |
1163 | pkt_header_length = 0; | |
1164 | ||
d360870a TS |
1165 | if (s == d->irq_target) { |
1166 | // At NO_PERIOD_WAKEUP mode, the packets for all IT/IR contexts are processed by | |
1167 | // the tasks of user process operating ALSA PCM character device by calling ioctl(2) | |
1168 | // with some requests, instead of scheduled hardware IRQ of an IT context. | |
1169 | struct snd_pcm_substream *pcm = READ_ONCE(s->pcm); | |
1170 | need_hw_irq = !pcm || !pcm->runtime->no_period_wakeup; | |
1171 | } else { | |
1172 | need_hw_irq = false; | |
1173 | } | |
1174 | ||
fef4e61b TS |
1175 | if (trace_amdtp_packet_enabled()) |
1176 | (void)fw_card_read_cycle_time(fw_parent_device(s->unit)->card, &curr_cycle_time); | |
1177 | ||
5e2ece0f | 1178 | for (i = 0; i < packets; ++i) { |
6bc1a269 TS |
1179 | struct { |
1180 | struct fw_iso_packet params; | |
67d92ee7 | 1181 | __be32 header[CIP_HEADER_QUADLETS]; |
6bc1a269 | 1182 | } template = { {0}, {0} }; |
e229853d | 1183 | bool sched_irq = false; |
31ef9134 | 1184 | |
233dbbc7 | 1185 | build_it_pkt_header(s, desc->cycle, &template.params, pkt_header_length, |
f4f6ae7b | 1186 | desc->data_blocks, desc->data_block_counter, |
fef4e61b | 1187 | desc->syt, i, curr_cycle_time); |
6bc1a269 | 1188 | |
2472cfb3 | 1189 | if (s == s->domain->irq_target) { |
60dd4929 TS |
1190 | event_count += desc->data_blocks; |
1191 | if (event_count >= events_per_period) { | |
1192 | event_count -= events_per_period; | |
d360870a | 1193 | sched_irq = need_hw_irq; |
60dd4929 | 1194 | } |
e229853d TS |
1195 | } |
1196 | ||
1197 | if (queue_out_packet(s, &template.params, sched_irq) < 0) { | |
fce9b013 | 1198 | cancel_stream(s); |
a4103bd7 TS |
1199 | return; |
1200 | } | |
cec371ff TS |
1201 | |
1202 | desc = amdtp_stream_next_packet_desc(s, desc); | |
ccccad86 | 1203 | } |
a4103bd7 | 1204 | |
60dd4929 | 1205 | s->ctx_data.rx.event_count = event_count; |
f0117128 | 1206 | s->packet_descs_cursor = desc; |
31ef9134 CL |
1207 | } |
1208 | ||
9b1fcd9b TS |
1209 | static void skip_rx_packets(struct fw_iso_context *context, u32 tstamp, size_t header_length, |
1210 | void *header, void *private_data) | |
1211 | { | |
1212 | struct amdtp_stream *s = private_data; | |
1213 | struct amdtp_domain *d = s->domain; | |
1214 | const __be32 *ctx_header = header; | |
1215 | unsigned int packets; | |
1216 | unsigned int cycle; | |
1217 | int i; | |
1218 | ||
1219 | if (s->packet_index < 0) | |
1220 | return; | |
1221 | ||
1222 | packets = header_length / sizeof(*ctx_header); | |
1223 | ||
1224 | cycle = compute_ohci_it_cycle(ctx_header[packets - 1], s->queue_size); | |
1225 | s->next_cycle = increment_ohci_cycle_count(cycle, 1); | |
1226 | ||
1227 | for (i = 0; i < packets; ++i) { | |
1228 | struct fw_iso_packet params = { | |
1229 | .header_length = 0, | |
1230 | .payload_length = 0, | |
1231 | }; | |
1232 | bool sched_irq = (s == d->irq_target && i == packets - 1); | |
1233 | ||
1234 | if (queue_out_packet(s, ¶ms, sched_irq) < 0) { | |
1235 | cancel_stream(s); | |
1236 | return; | |
1237 | } | |
1238 | } | |
1239 | } | |
1240 | ||
1241 | static void irq_target_callback(struct fw_iso_context *context, u32 tstamp, size_t header_length, | |
1242 | void *header, void *private_data); | |
1243 | ||
1244 | static void process_rx_packets_intermediately(struct fw_iso_context *context, u32 tstamp, | |
1245 | size_t header_length, void *header, void *private_data) | |
1246 | { | |
1247 | struct amdtp_stream *s = private_data; | |
1248 | struct amdtp_domain *d = s->domain; | |
1249 | __be32 *ctx_header = header; | |
1250 | const unsigned int queue_size = s->queue_size; | |
1251 | unsigned int packets; | |
1252 | unsigned int offset; | |
1253 | ||
1254 | if (s->packet_index < 0) | |
1255 | return; | |
1256 | ||
1257 | packets = header_length / sizeof(*ctx_header); | |
1258 | ||
1259 | offset = 0; | |
1260 | while (offset < packets) { | |
1261 | unsigned int cycle = compute_ohci_it_cycle(ctx_header[offset], queue_size); | |
1262 | ||
1263 | if (compare_ohci_cycle_count(cycle, d->processing_cycle.rx_start) >= 0) | |
1264 | break; | |
1265 | ||
1266 | ++offset; | |
1267 | } | |
1268 | ||
1269 | if (offset > 0) { | |
1270 | unsigned int length = sizeof(*ctx_header) * offset; | |
1271 | ||
1272 | skip_rx_packets(context, tstamp, length, ctx_header, private_data); | |
1273 | if (amdtp_streaming_error(s)) | |
1274 | return; | |
1275 | ||
1276 | ctx_header += offset; | |
1277 | header_length -= length; | |
1278 | } | |
1279 | ||
1280 | if (offset < packets) { | |
bdaedca7 TS |
1281 | s->ready_processing = true; |
1282 | wake_up(&s->ready_wait); | |
1283 | ||
c38d8cff TS |
1284 | if (d->replay.enable) |
1285 | s->ctx_data.rx.cache_pos = 0; | |
1286 | ||
9b1fcd9b TS |
1287 | process_rx_packets(context, tstamp, header_length, ctx_header, private_data); |
1288 | if (amdtp_streaming_error(s)) | |
1289 | return; | |
1290 | ||
1291 | if (s == d->irq_target) | |
1292 | s->context->callback.sc = irq_target_callback; | |
1293 | else | |
1294 | s->context->callback.sc = process_rx_packets; | |
1295 | } | |
1296 | } | |
1297 | ||
da3623ab TS |
1298 | static void process_tx_packets(struct fw_iso_context *context, u32 tstamp, size_t header_length, |
1299 | void *header, void *private_data) | |
2b3fc456 TS |
1300 | { |
1301 | struct amdtp_stream *s = private_data; | |
cc4f8e91 | 1302 | __be32 *ctx_header = header; |
f0117128 | 1303 | struct pkt_desc *desc = s->packet_descs_cursor; |
cccddec4 | 1304 | unsigned int packet_count; |
73246fc4 | 1305 | unsigned int desc_count; |
753e7179 TS |
1306 | int i; |
1307 | int err; | |
2b3fc456 | 1308 | |
a4103bd7 TS |
1309 | if (s->packet_index < 0) |
1310 | return; | |
1311 | ||
a0e02331 | 1312 | // Calculate the number of packets in buffer and check XRUN. |
cccddec4 | 1313 | packet_count = header_length / s->ctx_data.tx.ctx_header_size; |
f90e2ded | 1314 | |
73246fc4 | 1315 | desc_count = 0; |
cec371ff | 1316 | err = generate_tx_packet_descs(s, desc, ctx_header, packet_count, &desc_count); |
753e7179 TS |
1317 | if (err < 0) { |
1318 | if (err != -EAGAIN) { | |
1319 | cancel_stream(s); | |
1320 | return; | |
1321 | } | |
5e2ece0f | 1322 | } else { |
f9e5ecdf TS |
1323 | struct amdtp_domain *d = s->domain; |
1324 | ||
cec371ff | 1325 | process_ctx_payloads(s, desc, desc_count); |
f9e5ecdf TS |
1326 | |
1327 | if (d->replay.enable) | |
cec371ff | 1328 | cache_seq(s, desc, desc_count); |
f0117128 TS |
1329 | |
1330 | for (i = 0; i < desc_count; ++i) | |
1331 | desc = amdtp_stream_next_packet_desc(s, desc); | |
1332 | s->packet_descs_cursor = desc; | |
5e2ece0f TS |
1333 | } |
1334 | ||
cccddec4 | 1335 | for (i = 0; i < packet_count; ++i) { |
5e2ece0f | 1336 | struct fw_iso_packet params = {0}; |
2b3fc456 | 1337 | |
60dd4929 | 1338 | if (queue_in_packet(s, ¶ms) < 0) { |
753e7179 TS |
1339 | cancel_stream(s); |
1340 | return; | |
1341 | } | |
7b3b0d85 | 1342 | } |
60dd4929 TS |
1343 | } |
1344 | ||
da3623ab TS |
1345 | static void drop_tx_packets(struct fw_iso_context *context, u32 tstamp, size_t header_length, |
1346 | void *header, void *private_data) | |
1347 | { | |
1348 | struct amdtp_stream *s = private_data; | |
1349 | const __be32 *ctx_header = header; | |
1350 | unsigned int packets; | |
1351 | unsigned int cycle; | |
1352 | int i; | |
1353 | ||
1354 | if (s->packet_index < 0) | |
1355 | return; | |
1356 | ||
1357 | packets = header_length / s->ctx_data.tx.ctx_header_size; | |
1358 | ||
1359 | ctx_header += (packets - 1) * s->ctx_data.tx.ctx_header_size / sizeof(*ctx_header); | |
1360 | cycle = compute_ohci_cycle_count(ctx_header[1]); | |
1361 | s->next_cycle = increment_ohci_cycle_count(cycle, 1); | |
1362 | ||
1363 | for (i = 0; i < packets; ++i) { | |
1364 | struct fw_iso_packet params = {0}; | |
1365 | ||
1366 | if (queue_in_packet(s, ¶ms) < 0) { | |
1367 | cancel_stream(s); | |
1368 | return; | |
1369 | } | |
1370 | } | |
1371 | } | |
1372 | ||
1373 | static void process_tx_packets_intermediately(struct fw_iso_context *context, u32 tstamp, | |
1374 | size_t header_length, void *header, void *private_data) | |
1375 | { | |
1376 | struct amdtp_stream *s = private_data; | |
1377 | struct amdtp_domain *d = s->domain; | |
1378 | __be32 *ctx_header; | |
1379 | unsigned int packets; | |
1380 | unsigned int offset; | |
1381 | ||
1382 | if (s->packet_index < 0) | |
1383 | return; | |
1384 | ||
1385 | packets = header_length / s->ctx_data.tx.ctx_header_size; | |
1386 | ||
1387 | offset = 0; | |
1388 | ctx_header = header; | |
1389 | while (offset < packets) { | |
1390 | unsigned int cycle = compute_ohci_cycle_count(ctx_header[1]); | |
1391 | ||
1392 | if (compare_ohci_cycle_count(cycle, d->processing_cycle.tx_start) >= 0) | |
1393 | break; | |
1394 | ||
1395 | ctx_header += s->ctx_data.tx.ctx_header_size / sizeof(__be32); | |
1396 | ++offset; | |
1397 | } | |
1398 | ||
1399 | ctx_header = header; | |
1400 | ||
1401 | if (offset > 0) { | |
1402 | size_t length = s->ctx_data.tx.ctx_header_size * offset; | |
1403 | ||
1404 | drop_tx_packets(context, tstamp, length, ctx_header, s); | |
1405 | if (amdtp_streaming_error(s)) | |
1406 | return; | |
1407 | ||
1408 | ctx_header += length / sizeof(*ctx_header); | |
1409 | header_length -= length; | |
1410 | } | |
1411 | ||
1412 | if (offset < packets) { | |
bdaedca7 TS |
1413 | s->ready_processing = true; |
1414 | wake_up(&s->ready_wait); | |
1415 | ||
da3623ab TS |
1416 | process_tx_packets(context, tstamp, header_length, ctx_header, s); |
1417 | if (amdtp_streaming_error(s)) | |
1418 | return; | |
1419 | ||
1420 | context->callback.sc = process_tx_packets; | |
1421 | } | |
1422 | } | |
1423 | ||
fb25dcc8 TS |
1424 | static void drop_tx_packets_initially(struct fw_iso_context *context, u32 tstamp, |
1425 | size_t header_length, void *header, void *private_data) | |
1426 | { | |
1427 | struct amdtp_stream *s = private_data; | |
1428 | struct amdtp_domain *d = s->domain; | |
1429 | __be32 *ctx_header; | |
1430 | unsigned int count; | |
1431 | unsigned int events; | |
1432 | int i; | |
1433 | ||
1434 | if (s->packet_index < 0) | |
1435 | return; | |
1436 | ||
1437 | count = header_length / s->ctx_data.tx.ctx_header_size; | |
1438 | ||
1439 | // Attempt to detect any event in the batch of packets. | |
1440 | events = 0; | |
1441 | ctx_header = header; | |
1442 | for (i = 0; i < count; ++i) { | |
1443 | unsigned int payload_quads = | |
1444 | (be32_to_cpu(*ctx_header) >> ISO_DATA_LENGTH_SHIFT) / sizeof(__be32); | |
1445 | unsigned int data_blocks; | |
1446 | ||
1447 | if (s->flags & CIP_NO_HEADER) { | |
1448 | data_blocks = payload_quads / s->data_block_quadlets; | |
1449 | } else { | |
1450 | __be32 *cip_headers = ctx_header + IR_CTX_HEADER_DEFAULT_QUADLETS; | |
1451 | ||
1452 | if (payload_quads < CIP_HEADER_QUADLETS) { | |
1453 | data_blocks = 0; | |
1454 | } else { | |
1455 | payload_quads -= CIP_HEADER_QUADLETS; | |
1456 | ||
1457 | if (s->flags & CIP_UNAWARE_SYT) { | |
1458 | data_blocks = payload_quads / s->data_block_quadlets; | |
1459 | } else { | |
1460 | u32 cip1 = be32_to_cpu(cip_headers[1]); | |
1461 | ||
1462 | // NODATA packet can includes any data blocks but they are | |
1463 | // not available as event. | |
1464 | if ((cip1 & CIP_NO_DATA) == CIP_NO_DATA) | |
1465 | data_blocks = 0; | |
1466 | else | |
1467 | data_blocks = payload_quads / s->data_block_quadlets; | |
1468 | } | |
1469 | } | |
1470 | } | |
1471 | ||
1472 | events += data_blocks; | |
1473 | ||
1474 | ctx_header += s->ctx_data.tx.ctx_header_size / sizeof(__be32); | |
1475 | } | |
1476 | ||
1477 | drop_tx_packets(context, tstamp, header_length, header, s); | |
1478 | ||
1479 | if (events > 0) | |
1480 | s->ctx_data.tx.event_starts = true; | |
1481 | ||
1482 | // Decide the cycle count to begin processing content of packet in IR contexts. | |
1483 | { | |
1484 | unsigned int stream_count = 0; | |
1485 | unsigned int event_starts_count = 0; | |
1486 | unsigned int cycle = UINT_MAX; | |
1487 | ||
1488 | list_for_each_entry(s, &d->streams, list) { | |
1489 | if (s->direction == AMDTP_IN_STREAM) { | |
1490 | ++stream_count; | |
1491 | if (s->ctx_data.tx.event_starts) | |
1492 | ++event_starts_count; | |
1493 | } | |
1494 | } | |
1495 | ||
1496 | if (stream_count == event_starts_count) { | |
1497 | unsigned int next_cycle; | |
1498 | ||
1499 | list_for_each_entry(s, &d->streams, list) { | |
1500 | if (s->direction != AMDTP_IN_STREAM) | |
1501 | continue; | |
1502 | ||
1503 | next_cycle = increment_ohci_cycle_count(s->next_cycle, | |
1504 | d->processing_cycle.tx_init_skip); | |
1505 | if (cycle == UINT_MAX || | |
1506 | compare_ohci_cycle_count(next_cycle, cycle) > 0) | |
1507 | cycle = next_cycle; | |
1508 | ||
1509 | s->context->callback.sc = process_tx_packets_intermediately; | |
1510 | } | |
1511 | ||
1512 | d->processing_cycle.tx_start = cycle; | |
1513 | } | |
1514 | } | |
1515 | } | |
1516 | ||
9b1fcd9b | 1517 | static void process_ctxs_in_domain(struct amdtp_domain *d) |
60dd4929 | 1518 | { |
60dd4929 TS |
1519 | struct amdtp_stream *s; |
1520 | ||
60dd4929 | 1521 | list_for_each_entry(s, &d->streams, list) { |
9b1fcd9b | 1522 | if (s != d->irq_target && amdtp_stream_running(s)) |
60dd4929 | 1523 | fw_iso_context_flush_completions(s->context); |
9b1fcd9b TS |
1524 | |
1525 | if (amdtp_streaming_error(s)) | |
1526 | goto error; | |
60dd4929 TS |
1527 | } |
1528 | ||
1529 | return; | |
1530 | error: | |
9b1fcd9b TS |
1531 | if (amdtp_stream_running(d->irq_target)) |
1532 | cancel_stream(d->irq_target); | |
60dd4929 TS |
1533 | |
1534 | list_for_each_entry(s, &d->streams, list) { | |
1535 | if (amdtp_stream_running(s)) | |
1536 | cancel_stream(s); | |
1537 | } | |
2b3fc456 TS |
1538 | } |
1539 | ||
9b1fcd9b TS |
1540 | static void irq_target_callback(struct fw_iso_context *context, u32 tstamp, size_t header_length, |
1541 | void *header, void *private_data) | |
1542 | { | |
1543 | struct amdtp_stream *s = private_data; | |
1544 | struct amdtp_domain *d = s->domain; | |
9b1fcd9b TS |
1545 | |
1546 | process_rx_packets(context, tstamp, header_length, header, private_data); | |
1547 | process_ctxs_in_domain(d); | |
1548 | } | |
1549 | ||
1550 | static void irq_target_callback_intermediately(struct fw_iso_context *context, u32 tstamp, | |
1551 | size_t header_length, void *header, void *private_data) | |
1552 | { | |
1553 | struct amdtp_stream *s = private_data; | |
1554 | struct amdtp_domain *d = s->domain; | |
9b1fcd9b TS |
1555 | |
1556 | process_rx_packets_intermediately(context, tstamp, header_length, header, private_data); | |
1557 | process_ctxs_in_domain(d); | |
1558 | } | |
1559 | ||
1560 | static void irq_target_callback_skip(struct fw_iso_context *context, u32 tstamp, | |
1561 | size_t header_length, void *header, void *private_data) | |
1562 | { | |
1563 | struct amdtp_stream *s = private_data; | |
1564 | struct amdtp_domain *d = s->domain; | |
39c2649c | 1565 | bool ready_to_start; |
9b1fcd9b TS |
1566 | |
1567 | skip_rx_packets(context, tstamp, header_length, header, private_data); | |
1568 | process_ctxs_in_domain(d); | |
1569 | ||
2f21a177 | 1570 | if (d->replay.enable && !d->replay.on_the_fly) { |
39c2649c TS |
1571 | unsigned int rx_count = 0; |
1572 | unsigned int rx_ready_count = 0; | |
1573 | struct amdtp_stream *rx; | |
1574 | ||
1575 | list_for_each_entry(rx, &d->streams, list) { | |
1576 | struct amdtp_stream *tx; | |
1577 | unsigned int cached_cycles; | |
1578 | ||
1579 | if (rx->direction != AMDTP_OUT_STREAM) | |
1580 | continue; | |
1581 | ++rx_count; | |
1582 | ||
1583 | tx = rx->ctx_data.rx.replay_target; | |
1584 | cached_cycles = calculate_cached_cycle_count(tx, 0); | |
1585 | if (cached_cycles > tx->ctx_data.tx.cache.size / 2) | |
1586 | ++rx_ready_count; | |
1587 | } | |
1588 | ||
1589 | ready_to_start = (rx_count == rx_ready_count); | |
1590 | } else { | |
1591 | ready_to_start = true; | |
1592 | } | |
1593 | ||
9b1fcd9b TS |
1594 | // Decide the cycle count to begin processing content of packet in IT contexts. All of IT |
1595 | // contexts are expected to start and get callback when reaching here. | |
39c2649c TS |
1596 | if (ready_to_start) { |
1597 | unsigned int cycle = s->next_cycle; | |
1598 | list_for_each_entry(s, &d->streams, list) { | |
1599 | if (s->direction != AMDTP_OUT_STREAM) | |
1600 | continue; | |
9b1fcd9b | 1601 | |
39c2649c TS |
1602 | if (compare_ohci_cycle_count(s->next_cycle, cycle) > 0) |
1603 | cycle = s->next_cycle; | |
9b1fcd9b | 1604 | |
39c2649c TS |
1605 | if (s == d->irq_target) |
1606 | s->context->callback.sc = irq_target_callback_intermediately; | |
1607 | else | |
1608 | s->context->callback.sc = process_rx_packets_intermediately; | |
1609 | } | |
9b1fcd9b | 1610 | |
39c2649c TS |
1611 | d->processing_cycle.rx_start = cycle; |
1612 | } | |
9b1fcd9b TS |
1613 | } |
1614 | ||
b7c7699b TS |
1615 | // This is executed one time. For in-stream, first packet has come. For out-stream, prepared to |
1616 | // transmit first packet. | |
7b3b0d85 | 1617 | static void amdtp_stream_first_callback(struct fw_iso_context *context, |
73fc7f08 | 1618 | u32 tstamp, size_t header_length, |
7b3b0d85 TS |
1619 | void *header, void *private_data) |
1620 | { | |
1621 | struct amdtp_stream *s = private_data; | |
da3623ab | 1622 | struct amdtp_domain *d = s->domain; |
7b3b0d85 | 1623 | |
a04513f8 | 1624 | if (s->direction == AMDTP_IN_STREAM) { |
fb25dcc8 | 1625 | context->callback.sc = drop_tx_packets_initially; |
a04513f8 | 1626 | } else { |
da3623ab | 1627 | if (s == d->irq_target) |
9b1fcd9b | 1628 | context->callback.sc = irq_target_callback_skip; |
2472cfb3 | 1629 | else |
9b1fcd9b | 1630 | context->callback.sc = skip_rx_packets; |
a04513f8 TS |
1631 | } |
1632 | ||
73fc7f08 | 1633 | context->callback.sc(context, tstamp, header_length, header, s); |
7b3b0d85 TS |
1634 | } |
1635 | ||
31ef9134 | 1636 | /** |
be4a2894 TS |
1637 | * amdtp_stream_start - start transferring packets |
1638 | * @s: the AMDTP stream to start | |
31ef9134 CL |
1639 | * @channel: the isochronous channel on the bus |
1640 | * @speed: firewire speed code | |
af86b0b1 TS |
1641 | * @queue_size: The number of packets in the queue. |
1642 | * @idle_irq_interval: the interval to queue packet during initial state. | |
31ef9134 CL |
1643 | * |
1644 | * The stream cannot be started until it has been configured with | |
be4a2894 TS |
1645 | * amdtp_stream_set_parameters() and it must be started before any PCM or MIDI |
1646 | * device can be started. | |
31ef9134 | 1647 | */ |
a0e02331 | 1648 | static int amdtp_stream_start(struct amdtp_stream *s, int channel, int speed, |
bd165079 | 1649 | unsigned int queue_size, unsigned int idle_irq_interval) |
31ef9134 | 1650 | { |
2472cfb3 | 1651 | bool is_irq_target = (s == s->domain->irq_target); |
d3d10a4a | 1652 | unsigned int ctx_header_size; |
f11453c7 | 1653 | unsigned int max_ctx_payload_size; |
2b3fc456 | 1654 | enum dma_data_direction dir; |
cec371ff TS |
1655 | struct pkt_desc *descs; |
1656 | int i, type, tag, err; | |
31ef9134 CL |
1657 | |
1658 | mutex_lock(&s->mutex); | |
1659 | ||
be4a2894 | 1660 | if (WARN_ON(amdtp_stream_running(s) || |
4b7da117 | 1661 | (s->data_block_quadlets < 1))) { |
31ef9134 CL |
1662 | err = -EBADFD; |
1663 | goto err_unlock; | |
1664 | } | |
1665 | ||
d3d10a4a | 1666 | if (s->direction == AMDTP_IN_STREAM) { |
60dd4929 TS |
1667 | // NOTE: IT context should be used for constant IRQ. |
1668 | if (is_irq_target) { | |
1669 | err = -EINVAL; | |
1670 | goto err_unlock; | |
1671 | } | |
1672 | ||
b6bc8123 | 1673 | s->data_block_counter = UINT_MAX; |
d3d10a4a | 1674 | } else { |
b6bc8123 | 1675 | s->data_block_counter = 0; |
d3d10a4a | 1676 | } |
31ef9134 | 1677 | |
1be4f21d | 1678 | // initialize packet buffer. |
2b3fc456 TS |
1679 | if (s->direction == AMDTP_IN_STREAM) { |
1680 | dir = DMA_FROM_DEVICE; | |
1681 | type = FW_ISO_CONTEXT_RECEIVE; | |
c75f3678 | 1682 | if (!(s->flags & CIP_NO_HEADER)) |
f11453c7 | 1683 | ctx_header_size = IR_CTX_HEADER_SIZE_CIP; |
c75f3678 | 1684 | else |
f11453c7 | 1685 | ctx_header_size = IR_CTX_HEADER_SIZE_NO_CIP; |
2b3fc456 TS |
1686 | } else { |
1687 | dir = DMA_TO_DEVICE; | |
1688 | type = FW_ISO_CONTEXT_TRANSMIT; | |
df9160b9 | 1689 | ctx_header_size = 0; // No effect for IT context. |
b18f0cfa | 1690 | } |
c75f3678 | 1691 | max_ctx_payload_size = amdtp_stream_get_max_ctx_payload_size(s); |
f11453c7 | 1692 | |
c75f3678 | 1693 | err = iso_packets_buffer_init(&s->buffer, s->unit, queue_size, max_ctx_payload_size, dir); |
31ef9134 CL |
1694 | if (err < 0) |
1695 | goto err_unlock; | |
af86b0b1 | 1696 | s->queue_size = queue_size; |
60dd4929 | 1697 | |
31ef9134 | 1698 | s->context = fw_iso_context_create(fw_parent_device(s->unit)->card, |
d3d10a4a | 1699 | type, channel, speed, ctx_header_size, |
2472cfb3 | 1700 | amdtp_stream_first_callback, s); |
31ef9134 CL |
1701 | if (IS_ERR(s->context)) { |
1702 | err = PTR_ERR(s->context); | |
1703 | if (err == -EBUSY) | |
1704 | dev_err(&s->unit->device, | |
be4a2894 | 1705 | "no free stream on this controller\n"); |
31ef9134 CL |
1706 | goto err_buffer; |
1707 | } | |
1708 | ||
be4a2894 | 1709 | amdtp_stream_update(s); |
31ef9134 | 1710 | |
d3d10a4a | 1711 | if (s->direction == AMDTP_IN_STREAM) { |
f11453c7 | 1712 | s->ctx_data.tx.max_ctx_payload_length = max_ctx_payload_size; |
d3d10a4a | 1713 | s->ctx_data.tx.ctx_header_size = ctx_header_size; |
fb25dcc8 | 1714 | s->ctx_data.tx.event_starts = false; |
f9e5ecdf TS |
1715 | |
1716 | if (s->domain->replay.enable) { | |
1717 | // struct fw_iso_context.drop_overflow_headers is false therefore it's | |
1718 | // possible to cache much unexpectedly. | |
1719 | s->ctx_data.tx.cache.size = max_t(unsigned int, s->syt_interval * 2, | |
1720 | queue_size * 3 / 2); | |
cccddec4 | 1721 | s->ctx_data.tx.cache.pos = 0; |
f9e5ecdf TS |
1722 | s->ctx_data.tx.cache.descs = kcalloc(s->ctx_data.tx.cache.size, |
1723 | sizeof(*s->ctx_data.tx.cache.descs), GFP_KERNEL); | |
8b6e2193 DC |
1724 | if (!s->ctx_data.tx.cache.descs) { |
1725 | err = -ENOMEM; | |
f9e5ecdf | 1726 | goto err_context; |
8b6e2193 | 1727 | } |
f9e5ecdf | 1728 | } |
bd165079 | 1729 | } else { |
6f24bb8a TS |
1730 | static const struct { |
1731 | unsigned int data_block; | |
1732 | unsigned int syt_offset; | |
1733 | } *entry, initial_state[] = { | |
1734 | [CIP_SFC_32000] = { 4, 3072 }, | |
1735 | [CIP_SFC_48000] = { 6, 1024 }, | |
1736 | [CIP_SFC_96000] = { 12, 1024 }, | |
1737 | [CIP_SFC_192000] = { 24, 1024 }, | |
1738 | [CIP_SFC_44100] = { 0, 67 }, | |
1739 | [CIP_SFC_88200] = { 0, 67 }, | |
1740 | [CIP_SFC_176400] = { 0, 67 }, | |
1741 | }; | |
1742 | ||
1743 | s->ctx_data.rx.seq.descs = kcalloc(queue_size, sizeof(*s->ctx_data.rx.seq.descs), GFP_KERNEL); | |
8b6e2193 DC |
1744 | if (!s->ctx_data.rx.seq.descs) { |
1745 | err = -ENOMEM; | |
6f24bb8a | 1746 | goto err_context; |
8b6e2193 | 1747 | } |
6f24bb8a | 1748 | s->ctx_data.rx.seq.size = queue_size; |
119c446a | 1749 | s->ctx_data.rx.seq.pos = 0; |
6f24bb8a TS |
1750 | |
1751 | entry = &initial_state[s->sfc]; | |
1752 | s->ctx_data.rx.data_block_state = entry->data_block; | |
1753 | s->ctx_data.rx.syt_offset_state = entry->syt_offset; | |
1754 | s->ctx_data.rx.last_syt_offset = TICKS_PER_CYCLE; | |
1755 | ||
bd165079 | 1756 | s->ctx_data.rx.event_count = 0; |
d3d10a4a | 1757 | } |
52759c09 | 1758 | |
3b196c39 TS |
1759 | if (s->flags & CIP_NO_HEADER) |
1760 | s->tag = TAG_NO_CIP_HEADER; | |
1761 | else | |
1762 | s->tag = TAG_CIP; | |
1763 | ||
af13842c TS |
1764 | // NOTE: When operating without hardIRQ/softIRQ, applications tends to call ioctl request |
1765 | // for runtime of PCM substream in the interval equivalent to the size of PCM buffer. It | |
1766 | // could take a round over queue of AMDTP packet descriptors and small loss of history. For | |
1767 | // safe, keep more 8 elements for the queue, equivalent to 1 ms. | |
1768 | descs = kcalloc(s->queue_size + 8, sizeof(*descs), GFP_KERNEL); | |
cec371ff | 1769 | if (!descs) { |
04130cf8 TS |
1770 | err = -ENOMEM; |
1771 | goto err_context; | |
1772 | } | |
f0117128 | 1773 | s->packet_descs = descs; |
cec371ff TS |
1774 | |
1775 | INIT_LIST_HEAD(&s->packet_descs_list); | |
1776 | for (i = 0; i < s->queue_size; ++i) { | |
1777 | INIT_LIST_HEAD(&descs->link); | |
1778 | list_add_tail(&descs->link, &s->packet_descs_list); | |
1779 | ++descs; | |
1780 | } | |
f0117128 | 1781 | s->packet_descs_cursor = list_first_entry(&s->packet_descs_list, struct pkt_desc, link); |
04130cf8 | 1782 | |
ec00f5e4 | 1783 | s->packet_index = 0; |
4b7da117 | 1784 | do { |
6007bf54 | 1785 | struct fw_iso_packet params; |
e229853d | 1786 | |
b18f0cfa | 1787 | if (s->direction == AMDTP_IN_STREAM) { |
60dd4929 | 1788 | err = queue_in_packet(s, ¶ms); |
b18f0cfa | 1789 | } else { |
60dd4929 TS |
1790 | bool sched_irq = false; |
1791 | ||
b18f0cfa TS |
1792 | params.header_length = 0; |
1793 | params.payload_length = 0; | |
60dd4929 TS |
1794 | |
1795 | if (is_irq_target) { | |
1796 | sched_irq = !((s->packet_index + 1) % | |
1797 | idle_irq_interval); | |
1798 | } | |
1799 | ||
e229853d | 1800 | err = queue_out_packet(s, ¶ms, sched_irq); |
b18f0cfa | 1801 | } |
4b7da117 | 1802 | if (err < 0) |
04130cf8 | 1803 | goto err_pkt_descs; |
4b7da117 | 1804 | } while (s->packet_index > 0); |
31ef9134 | 1805 | |
2b3fc456 | 1806 | /* NOTE: TAG1 matches CIP. This just affects in stream. */ |
7ab56645 | 1807 | tag = FW_ISO_CONTEXT_MATCH_TAG1; |
3b196c39 | 1808 | if ((s->flags & CIP_EMPTY_WITH_TAG0) || (s->flags & CIP_NO_HEADER)) |
7ab56645 TS |
1809 | tag |= FW_ISO_CONTEXT_MATCH_TAG0; |
1810 | ||
bdaedca7 | 1811 | s->ready_processing = false; |
bd165079 | 1812 | err = fw_iso_context_start(s->context, -1, 0, tag); |
31ef9134 | 1813 | if (err < 0) |
04130cf8 | 1814 | goto err_pkt_descs; |
31ef9134 CL |
1815 | |
1816 | mutex_unlock(&s->mutex); | |
1817 | ||
1818 | return 0; | |
04130cf8 | 1819 | err_pkt_descs: |
f0117128 TS |
1820 | kfree(s->packet_descs); |
1821 | s->packet_descs = NULL; | |
31ef9134 | 1822 | err_context: |
f9e5ecdf | 1823 | if (s->direction == AMDTP_OUT_STREAM) { |
6f24bb8a | 1824 | kfree(s->ctx_data.rx.seq.descs); |
f9e5ecdf TS |
1825 | } else { |
1826 | if (s->domain->replay.enable) | |
1827 | kfree(s->ctx_data.tx.cache.descs); | |
1828 | } | |
31ef9134 CL |
1829 | fw_iso_context_destroy(s->context); |
1830 | s->context = ERR_PTR(-1); | |
1831 | err_buffer: | |
1832 | iso_packets_buffer_destroy(&s->buffer, s->unit); | |
1833 | err_unlock: | |
1834 | mutex_unlock(&s->mutex); | |
1835 | ||
1836 | return err; | |
1837 | } | |
31ef9134 | 1838 | |
e9148ddd | 1839 | /** |
f890f9a0 TS |
1840 | * amdtp_domain_stream_pcm_pointer - get the PCM buffer position |
1841 | * @d: the AMDTP domain. | |
be4a2894 | 1842 | * @s: the AMDTP stream that transports the PCM data |
e9148ddd CL |
1843 | * |
1844 | * Returns the current buffer position, in frames. | |
1845 | */ | |
f890f9a0 TS |
1846 | unsigned long amdtp_domain_stream_pcm_pointer(struct amdtp_domain *d, |
1847 | struct amdtp_stream *s) | |
e9148ddd | 1848 | { |
f890f9a0 TS |
1849 | struct amdtp_stream *irq_target = d->irq_target; |
1850 | ||
7ba5ca32 | 1851 | // Process isochronous packets queued till recent isochronous cycle to handle PCM frames. |
f890f9a0 | 1852 | if (irq_target && amdtp_stream_running(irq_target)) { |
7ba5ca32 TS |
1853 | // In software IRQ context, the call causes dead-lock to disable the tasklet |
1854 | // synchronously. | |
3b86ec63 | 1855 | if (!in_softirq()) |
f890f9a0 | 1856 | fw_iso_context_flush_completions(irq_target->context); |
f890f9a0 | 1857 | } |
e9148ddd | 1858 | |
6aa7de05 | 1859 | return READ_ONCE(s->pcm_buffer_pointer); |
e9148ddd | 1860 | } |
f890f9a0 | 1861 | EXPORT_SYMBOL_GPL(amdtp_domain_stream_pcm_pointer); |
e9148ddd | 1862 | |
875becf8 | 1863 | /** |
e6dcc92f TS |
1864 | * amdtp_domain_stream_pcm_ack - acknowledge queued PCM frames |
1865 | * @d: the AMDTP domain. | |
875becf8 TS |
1866 | * @s: the AMDTP stream that transfers the PCM frames |
1867 | * | |
1868 | * Returns zero always. | |
1869 | */ | |
e6dcc92f | 1870 | int amdtp_domain_stream_pcm_ack(struct amdtp_domain *d, struct amdtp_stream *s) |
875becf8 | 1871 | { |
e6dcc92f TS |
1872 | struct amdtp_stream *irq_target = d->irq_target; |
1873 | ||
1874 | // Process isochronous packets for recent isochronous cycle to handle | |
1875 | // queued PCM frames. | |
987b705b | 1876 | if (irq_target && amdtp_stream_running(irq_target)) |
e6dcc92f | 1877 | fw_iso_context_flush_completions(irq_target->context); |
875becf8 TS |
1878 | |
1879 | return 0; | |
1880 | } | |
e6dcc92f | 1881 | EXPORT_SYMBOL_GPL(amdtp_domain_stream_pcm_ack); |
875becf8 | 1882 | |
31ef9134 | 1883 | /** |
be4a2894 TS |
1884 | * amdtp_stream_update - update the stream after a bus reset |
1885 | * @s: the AMDTP stream | |
31ef9134 | 1886 | */ |
be4a2894 | 1887 | void amdtp_stream_update(struct amdtp_stream *s) |
31ef9134 | 1888 | { |
9a2820c1 | 1889 | /* Precomputing. */ |
6aa7de05 MR |
1890 | WRITE_ONCE(s->source_node_id_field, |
1891 | (fw_parent_device(s->unit)->card->node_id << CIP_SID_SHIFT) & CIP_SID_MASK); | |
31ef9134 | 1892 | } |
be4a2894 | 1893 | EXPORT_SYMBOL(amdtp_stream_update); |
31ef9134 CL |
1894 | |
1895 | /** | |
be4a2894 TS |
1896 | * amdtp_stream_stop - stop sending packets |
1897 | * @s: the AMDTP stream to stop | |
31ef9134 CL |
1898 | * |
1899 | * All PCM and MIDI devices of the stream must be stopped before the stream | |
1900 | * itself can be stopped. | |
1901 | */ | |
74f94e41 | 1902 | static void amdtp_stream_stop(struct amdtp_stream *s) |
31ef9134 CL |
1903 | { |
1904 | mutex_lock(&s->mutex); | |
1905 | ||
be4a2894 | 1906 | if (!amdtp_stream_running(s)) { |
31ef9134 CL |
1907 | mutex_unlock(&s->mutex); |
1908 | return; | |
1909 | } | |
1910 | ||
1911 | fw_iso_context_stop(s->context); | |
1912 | fw_iso_context_destroy(s->context); | |
1913 | s->context = ERR_PTR(-1); | |
1914 | iso_packets_buffer_destroy(&s->buffer, s->unit); | |
f0117128 TS |
1915 | kfree(s->packet_descs); |
1916 | s->packet_descs = NULL; | |
31ef9134 | 1917 | |
f9e5ecdf | 1918 | if (s->direction == AMDTP_OUT_STREAM) { |
6f24bb8a | 1919 | kfree(s->ctx_data.rx.seq.descs); |
f9e5ecdf TS |
1920 | } else { |
1921 | if (s->domain->replay.enable) | |
1922 | kfree(s->ctx_data.tx.cache.descs); | |
1923 | } | |
7b3b0d85 | 1924 | |
31ef9134 CL |
1925 | mutex_unlock(&s->mutex); |
1926 | } | |
31ef9134 CL |
1927 | |
1928 | /** | |
be4a2894 | 1929 | * amdtp_stream_pcm_abort - abort the running PCM device |
31ef9134 CL |
1930 | * @s: the AMDTP stream about to be stopped |
1931 | * | |
1932 | * If the isochronous stream needs to be stopped asynchronously, call this | |
1933 | * function first to stop the PCM device. | |
1934 | */ | |
be4a2894 | 1935 | void amdtp_stream_pcm_abort(struct amdtp_stream *s) |
31ef9134 CL |
1936 | { |
1937 | struct snd_pcm_substream *pcm; | |
1938 | ||
6aa7de05 | 1939 | pcm = READ_ONCE(s->pcm); |
1fb8510c TI |
1940 | if (pcm) |
1941 | snd_pcm_stop_xrun(pcm); | |
31ef9134 | 1942 | } |
be4a2894 | 1943 | EXPORT_SYMBOL(amdtp_stream_pcm_abort); |
3ec3d7a3 TS |
1944 | |
1945 | /** | |
1946 | * amdtp_domain_init - initialize an AMDTP domain structure | |
1947 | * @d: the AMDTP domain to initialize. | |
1948 | */ | |
1949 | int amdtp_domain_init(struct amdtp_domain *d) | |
1950 | { | |
1951 | INIT_LIST_HEAD(&d->streams); | |
1952 | ||
d68c3123 TS |
1953 | d->events_per_period = 0; |
1954 | ||
3ec3d7a3 TS |
1955 | return 0; |
1956 | } | |
1957 | EXPORT_SYMBOL_GPL(amdtp_domain_init); | |
1958 | ||
1959 | /** | |
1960 | * amdtp_domain_destroy - destroy an AMDTP domain structure | |
1961 | * @d: the AMDTP domain to destroy. | |
1962 | */ | |
1963 | void amdtp_domain_destroy(struct amdtp_domain *d) | |
1964 | { | |
8d0d5c3f TS |
1965 | // At present nothing to do. |
1966 | return; | |
3ec3d7a3 TS |
1967 | } |
1968 | EXPORT_SYMBOL_GPL(amdtp_domain_destroy); | |
6261f90b | 1969 | |
157a53ee TS |
1970 | /** |
1971 | * amdtp_domain_add_stream - register isoc context into the domain. | |
1972 | * @d: the AMDTP domain. | |
1973 | * @s: the AMDTP stream. | |
1974 | * @channel: the isochronous channel on the bus. | |
1975 | * @speed: firewire speed code. | |
1976 | */ | |
1977 | int amdtp_domain_add_stream(struct amdtp_domain *d, struct amdtp_stream *s, | |
1978 | int channel, int speed) | |
1979 | { | |
1980 | struct amdtp_stream *tmp; | |
1981 | ||
1982 | list_for_each_entry(tmp, &d->streams, list) { | |
1983 | if (s == tmp) | |
1984 | return -EBUSY; | |
1985 | } | |
1986 | ||
1987 | list_add(&s->list, &d->streams); | |
1988 | ||
1989 | s->channel = channel; | |
1990 | s->speed = speed; | |
2472cfb3 | 1991 | s->domain = d; |
157a53ee TS |
1992 | |
1993 | return 0; | |
1994 | } | |
1995 | EXPORT_SYMBOL_GPL(amdtp_domain_add_stream); | |
1996 | ||
39c2649c TS |
1997 | // Make the reference from rx stream to tx stream for sequence replay. When the number of tx streams |
1998 | // is less than the number of rx streams, the first tx stream is selected. | |
1999 | static int make_association(struct amdtp_domain *d) | |
2000 | { | |
2001 | unsigned int dst_index = 0; | |
2002 | struct amdtp_stream *rx; | |
2003 | ||
2004 | // Make association to replay target. | |
2005 | list_for_each_entry(rx, &d->streams, list) { | |
2006 | if (rx->direction == AMDTP_OUT_STREAM) { | |
2007 | unsigned int src_index = 0; | |
2008 | struct amdtp_stream *tx = NULL; | |
2009 | struct amdtp_stream *s; | |
2010 | ||
2011 | list_for_each_entry(s, &d->streams, list) { | |
2012 | if (s->direction == AMDTP_IN_STREAM) { | |
2013 | if (dst_index == src_index) { | |
2014 | tx = s; | |
2015 | break; | |
2016 | } | |
2017 | ||
2018 | ++src_index; | |
2019 | } | |
2020 | } | |
2021 | if (!tx) { | |
2022 | // Select the first entry. | |
2023 | list_for_each_entry(s, &d->streams, list) { | |
2024 | if (s->direction == AMDTP_IN_STREAM) { | |
2025 | tx = s; | |
2026 | break; | |
2027 | } | |
2028 | } | |
2029 | // No target is available to replay sequence. | |
2030 | if (!tx) | |
2031 | return -EINVAL; | |
2032 | } | |
2033 | ||
2034 | rx->ctx_data.rx.replay_target = tx; | |
39c2649c TS |
2035 | |
2036 | ++dst_index; | |
2037 | } | |
2038 | } | |
2039 | ||
2040 | return 0; | |
2041 | } | |
2042 | ||
9b4702b0 TS |
2043 | /** |
2044 | * amdtp_domain_start - start sending packets for isoc context in the domain. | |
2045 | * @d: the AMDTP domain. | |
26541cb1 TS |
2046 | * @tx_init_skip_cycles: the number of cycles to skip processing packets at initial stage of IR |
2047 | * contexts. | |
f9e5ecdf TS |
2048 | * @replay_seq: whether to replay the sequence of packet in IR context for the sequence of packet in |
2049 | * IT context. | |
2f21a177 TS |
2050 | * @replay_on_the_fly: transfer rx packets according to nominal frequency, then begin to replay |
2051 | * according to arrival of events in tx packets. | |
9b4702b0 | 2052 | */ |
2f21a177 TS |
2053 | int amdtp_domain_start(struct amdtp_domain *d, unsigned int tx_init_skip_cycles, bool replay_seq, |
2054 | bool replay_on_the_fly) | |
9b4702b0 | 2055 | { |
af86b0b1 TS |
2056 | unsigned int events_per_buffer = d->events_per_buffer; |
2057 | unsigned int events_per_period = d->events_per_period; | |
af86b0b1 | 2058 | unsigned int queue_size; |
9b4702b0 | 2059 | struct amdtp_stream *s; |
0cbbeaf3 | 2060 | bool found = false; |
acfedcbe | 2061 | int err; |
9b4702b0 | 2062 | |
39c2649c TS |
2063 | if (replay_seq) { |
2064 | err = make_association(d); | |
2065 | if (err < 0) | |
2066 | return err; | |
2067 | } | |
f9e5ecdf | 2068 | d->replay.enable = replay_seq; |
2f21a177 | 2069 | d->replay.on_the_fly = replay_on_the_fly; |
f9e5ecdf | 2070 | |
60dd4929 | 2071 | // Select an IT context as IRQ target. |
9b4702b0 | 2072 | list_for_each_entry(s, &d->streams, list) { |
0cbbeaf3 CJ |
2073 | if (s->direction == AMDTP_OUT_STREAM) { |
2074 | found = true; | |
9b4702b0 | 2075 | break; |
0cbbeaf3 | 2076 | } |
9b4702b0 | 2077 | } |
0cbbeaf3 | 2078 | if (!found) |
60dd4929 TS |
2079 | return -ENXIO; |
2080 | d->irq_target = s; | |
9b4702b0 | 2081 | |
26541cb1 TS |
2082 | d->processing_cycle.tx_init_skip = tx_init_skip_cycles; |
2083 | ||
af86b0b1 TS |
2084 | // This is a case that AMDTP streams in domain run just for MIDI |
2085 | // substream. Use the number of events equivalent to 10 msec as | |
2086 | // interval of hardware IRQ. | |
2087 | if (events_per_period == 0) | |
2088 | events_per_period = amdtp_rate_table[d->irq_target->sfc] / 100; | |
2089 | if (events_per_buffer == 0) | |
2090 | events_per_buffer = events_per_period * 3; | |
2091 | ||
2092 | queue_size = DIV_ROUND_UP(CYCLES_PER_SECOND * events_per_buffer, | |
2093 | amdtp_rate_table[d->irq_target->sfc]); | |
2094 | ||
60dd4929 | 2095 | list_for_each_entry(s, &d->streams, list) { |
bd165079 | 2096 | unsigned int idle_irq_interval = 0; |
acfedcbe | 2097 | |
bd165079 TS |
2098 | if (s->direction == AMDTP_OUT_STREAM && s == d->irq_target) { |
2099 | idle_irq_interval = DIV_ROUND_UP(CYCLES_PER_SECOND * events_per_period, | |
2100 | amdtp_rate_table[d->irq_target->sfc]); | |
60dd4929 | 2101 | } |
9b4702b0 | 2102 | |
bd165079 TS |
2103 | // Starts immediately but actually DMA context starts several hundred cycles later. |
2104 | err = amdtp_stream_start(s, s->channel, s->speed, queue_size, idle_irq_interval); | |
2105 | if (err < 0) | |
2106 | goto error; | |
2107 | } | |
60dd4929 TS |
2108 | |
2109 | return 0; | |
2110 | error: | |
2111 | list_for_each_entry(s, &d->streams, list) | |
2112 | amdtp_stream_stop(s); | |
9b4702b0 TS |
2113 | return err; |
2114 | } | |
2115 | EXPORT_SYMBOL_GPL(amdtp_domain_start); | |
2116 | ||
6261f90b TS |
2117 | /** |
2118 | * amdtp_domain_stop - stop sending packets for isoc context in the same domain. | |
2119 | * @d: the AMDTP domain to which the isoc contexts belong. | |
2120 | */ | |
2121 | void amdtp_domain_stop(struct amdtp_domain *d) | |
2122 | { | |
2123 | struct amdtp_stream *s, *next; | |
2124 | ||
60dd4929 TS |
2125 | if (d->irq_target) |
2126 | amdtp_stream_stop(d->irq_target); | |
2127 | ||
6261f90b TS |
2128 | list_for_each_entry_safe(s, next, &d->streams, list) { |
2129 | list_del(&s->list); | |
2130 | ||
60dd4929 TS |
2131 | if (s != d->irq_target) |
2132 | amdtp_stream_stop(s); | |
6261f90b | 2133 | } |
d68c3123 TS |
2134 | |
2135 | d->events_per_period = 0; | |
60dd4929 | 2136 | d->irq_target = NULL; |
6261f90b TS |
2137 | } |
2138 | EXPORT_SYMBOL_GPL(amdtp_domain_stop); |