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fa80feae JA |
1 | #ifndef FIO_ARCH_X86_COMMON |
2 | #define FIO_ARCH_X86_COMMON | |
3 | ||
7189c969 JA |
4 | #include <string.h> |
5 | ||
63ed8254 JA |
6 | #ifndef __NR_sys_io_uring_setup |
7 | #define __NR_sys_io_uring_setup 425 | |
8 | #endif | |
9 | #ifndef __NR_sys_io_uring_enter | |
10 | #define __NR_sys_io_uring_enter 426 | |
11 | #endif | |
12 | #ifndef __NR_sys_io_uring_register | |
13 | #define __NR_sys_io_uring_register 427 | |
14 | #endif | |
15 | ||
7189c969 JA |
16 | static inline void cpuid(unsigned int op, |
17 | unsigned int *eax, unsigned int *ebx, | |
18 | unsigned int *ecx, unsigned int *edx) | |
19 | { | |
20 | *eax = op; | |
21 | *ecx = 0; | |
22 | do_cpuid(eax, ebx, ecx, edx); | |
23 | } | |
24 | ||
fa80feae | 25 | #define ARCH_HAVE_INIT |
63ed8254 | 26 | #define ARCH_HAVE_IOURING |
7189c969 | 27 | |
24575392 | 28 | extern bool tsc_reliable; |
16dc0710 | 29 | extern int arch_random; |
7189c969 | 30 | |
ce892609 | 31 | static inline void arch_init_intel(void) |
fa80feae | 32 | { |
267339ff | 33 | unsigned int eax, ebx, ecx = 0, edx; |
fa80feae JA |
34 | |
35 | /* | |
36 | * Check for TSC | |
37 | */ | |
38 | eax = 1; | |
39 | do_cpuid(&eax, &ebx, &ecx, &edx); | |
40 | if (!(edx & (1U << 4))) | |
16dc0710 | 41 | return; |
fa80feae JA |
42 | |
43 | /* | |
44 | * Check for constant rate and synced (across cores) TSC | |
45 | */ | |
46 | eax = 0x80000007; | |
47 | do_cpuid(&eax, &ebx, &ecx, &edx); | |
16dc0710 JA |
48 | tsc_reliable = (edx & (1U << 8)) != 0; |
49 | ||
50 | /* | |
51 | * Check for FDRAND | |
52 | */ | |
53 | eax = 0x1; | |
54 | do_cpuid(&eax, &ebx, &ecx, &edx); | |
55 | arch_random = (ecx & (1U << 30)) != 0; | |
7189c969 JA |
56 | } |
57 | ||
ce892609 | 58 | static inline void arch_init_amd(void) |
7189c969 JA |
59 | { |
60 | unsigned int eax, ebx, ecx, edx; | |
61 | ||
62 | cpuid(0x80000000, &eax, &ebx, &ecx, &edx); | |
63 | if (eax < 0x80000007) | |
16dc0710 | 64 | return; |
7189c969 JA |
65 | |
66 | cpuid(0x80000007, &eax, &ebx, &ecx, &edx); | |
16dc0710 | 67 | tsc_reliable = (edx & (1U << 8)) != 0; |
7189c969 JA |
68 | } |
69 | ||
16dc0710 | 70 | static inline void arch_init(char *envp[]) |
7189c969 JA |
71 | { |
72 | unsigned int level; | |
81fa6e06 | 73 | char str[13]; |
7189c969 | 74 | |
16dc0710 JA |
75 | arch_random = tsc_reliable = 0; |
76 | ||
7189c969 JA |
77 | cpuid(0, &level, (unsigned int *) &str[0], |
78 | (unsigned int *) &str[8], | |
79 | (unsigned int *) &str[4]); | |
80 | ||
81fa6e06 | 81 | str[12] = '\0'; |
7189c969 | 82 | if (!strcmp(str, "GenuineIntel")) |
ce892609 | 83 | arch_init_intel(); |
c3e028ca | 84 | else if (!strcmp(str, "AuthenticAMD") || !strcmp(str, "HygonGenuine")) |
ce892609 | 85 | arch_init_amd(); |
fa80feae JA |
86 | } |
87 | ||
88 | #endif |