Commit | Line | Data |
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ebac4655 JA |
1 | #ifndef ARCH_IA64_H |
2 | #define ARCH_IA64_H | |
3 | ||
cca84643 | 4 | #define FIO_ARCH (arch_ia64) |
ebac4655 | 5 | |
db6defc7 JA |
6 | #define nop asm volatile ("hint @pause" ::: "memory"); |
7 | #define read_barrier() asm volatile ("mf" ::: "memory") | |
783500ad | 8 | #define write_barrier() asm volatile ("mf" ::: "memory") |
ebac4655 | 9 | |
8f7e39dd JA |
10 | #define ia64_popcnt(x) \ |
11 | ({ \ | |
12 | unsigned long ia64_intri_res; \ | |
13 | asm ("popcnt %0=%1" : "=r" (ia64_intri_res) : "r" (x)); \ | |
14 | ia64_intri_res; \ | |
15 | }) | |
16 | ||
17 | static inline unsigned long arch_ffz(unsigned long bitmask) | |
18 | { | |
19 | return ia64_popcnt(bitmask & (~bitmask - 1)); | |
20 | } | |
ab480047 | 21 | |
d93904c4 | 22 | static inline unsigned long long get_cpu_clock(void) |
ab480047 | 23 | { |
d93904c4 | 24 | unsigned long long ret; |
ab480047 JA |
25 | |
26 | __asm__ __volatile__("mov %0=ar.itc" : "=r" (ret) : : "memory"); | |
27 | return ret; | |
28 | } | |
29 | ||
1b745f55 | 30 | #define ARCH_HAVE_INIT |
24575392 | 31 | extern bool tsc_reliable; |
1b745f55 JA |
32 | static inline int arch_init(char *envp[]) |
33 | { | |
24575392 | 34 | tsc_reliable = true; |
d20b2ca6 | 35 | return 0; |
1b745f55 JA |
36 | } |
37 | ||
8f7e39dd | 38 | #define ARCH_HAVE_FFZ |
ab480047 | 39 | #define ARCH_HAVE_CPU_CLOCK |
8f7e39dd | 40 | |
ebac4655 | 41 | #endif |