Commit | Line | Data |
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ebac4655 JA |
1 | #ifndef ARCH_IA64_H |
2 | #define ARCH_IA64_H | |
3 | ||
cca84643 | 4 | #define FIO_ARCH (arch_ia64) |
ebac4655 JA |
5 | |
6 | #ifndef __NR_ioprio_set | |
7 | #define __NR_ioprio_set 1274 | |
8 | #define __NR_ioprio_get 1275 | |
9 | #endif | |
10 | ||
11 | #ifndef __NR_fadvise64 | |
12 | #define __NR_fadvise64 1234 | |
13 | #endif | |
14 | ||
8756e4d4 JA |
15 | #ifndef __NR_sys_splice |
16 | #define __NR_sys_splice 1297 | |
17 | #define __NR_sys_tee 1301 | |
18 | #define __NR_sys_vmsplice 1302 | |
19 | #endif | |
20 | ||
db6defc7 JA |
21 | #define nop asm volatile ("hint @pause" ::: "memory"); |
22 | #define read_barrier() asm volatile ("mf" ::: "memory") | |
783500ad | 23 | #define write_barrier() asm volatile ("mf" ::: "memory") |
ebac4655 | 24 | |
8f7e39dd JA |
25 | #define ia64_popcnt(x) \ |
26 | ({ \ | |
27 | unsigned long ia64_intri_res; \ | |
28 | asm ("popcnt %0=%1" : "=r" (ia64_intri_res) : "r" (x)); \ | |
29 | ia64_intri_res; \ | |
30 | }) | |
31 | ||
32 | static inline unsigned long arch_ffz(unsigned long bitmask) | |
33 | { | |
34 | return ia64_popcnt(bitmask & (~bitmask - 1)); | |
35 | } | |
ab480047 JA |
36 | |
37 | static inline unsigned long get_cpu_clock(void) | |
38 | { | |
39 | unsigned long ret; | |
40 | ||
41 | __asm__ __volatile__("mov %0=ar.itc" : "=r" (ret) : : "memory"); | |
42 | return ret; | |
43 | } | |
44 | ||
1b745f55 JA |
45 | #define ARCH_HAVE_INIT |
46 | extern int tsc_reliable; | |
47 | static inline int arch_init(char *envp[]) | |
48 | { | |
49 | tsc_reliable = 1; | |
d20b2ca6 | 50 | return 0; |
1b745f55 JA |
51 | } |
52 | ||
8f7e39dd | 53 | #define ARCH_HAVE_FFZ |
ab480047 | 54 | #define ARCH_HAVE_CPU_CLOCK |
8f7e39dd | 55 | |
ebac4655 | 56 | #endif |