Merge branch 'imx-fb-fix' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async...
authorRussell King <rmk@dyn-67.arm.linux.org.uk>
Mon, 16 Mar 2009 22:28:04 +0000 (22:28 +0000)
committerRussell King <rmk+kernel@arm.linux.org.uk>
Mon, 16 Mar 2009 22:28:04 +0000 (22:28 +0000)
Conflicts:

drivers/video/mx3fb.c

1  2 
drivers/video/Kconfig
drivers/video/Makefile
drivers/video/mx3fb.c

index 330204a61ea8b561700dd4d54ef724de7e19e3d7,5c5e3fe090ea9b4452ac0c17b135aba72afbd1ad..41c27a44bd82bf5ec95e937cdea0485f610a58ed
@@@ -2120,31 -2126,17 +2120,31 @@@ config FB_PRE_INIT_F
          the bootloader.
  
  config FB_MX3
-        tristate "MX3 Framebuffer support"
-        depends on FB && MX3_IPU
-        select FB_CFB_FILLRECT
-        select FB_CFB_COPYAREA
-        select FB_CFB_IMAGEBLIT
-        default y
-        help
-          This is a framebuffer device for the i.MX31 LCD Controller. So
-          far only synchronous displays are supported. If you plan to use
-          an LCD display with your i.MX31 system, say Y here.
+       tristate "MX3 Framebuffer support"
+       depends on FB && MX3_IPU
+       select FB_CFB_FILLRECT
+       select FB_CFB_COPYAREA
+       select FB_CFB_IMAGEBLIT
+       default y
+       help
+         This is a framebuffer device for the i.MX31 LCD Controller. So
+         far only synchronous displays are supported. If you plan to use
+         an LCD display with your i.MX31 system, say Y here.
  
 +config FB_BROADSHEET
 +      tristate "E-Ink Broadsheet/Epson S1D13521 controller support"
 +      depends on FB
 +      select FB_SYS_FILLRECT
 +      select FB_SYS_COPYAREA
 +      select FB_SYS_IMAGEBLIT
 +      select FB_SYS_FOPS
 +      select FB_DEFERRED_IO
 +      help
 +        This driver implements support for the E-Ink Broadsheet
 +        controller. The release name for this device was Epson S1D13521
 +        and could also have been called by other names when coupled with
 +        a bridge adapter.
 +
  source "drivers/video/omap/Kconfig"
  
  source "drivers/video/backlight/Kconfig"
Simple merge
index 0c27961e47f24d5a2ad752d7b8f399933d005d5d,3e8463562deee4481f3ce2736e23159985330dbc..fa1a512ce030d501999cacb3121d36909c89926a
@@@ -412,162 -412,162 +412,162 @@@ static int sdc_set_window_pos(struct mx
  
  /**
   * sdc_init_panel() - initialize a synchronous LCD panel.
-  * @mx3fb:             mx3fb context.
-  * @panel:             panel type.
-  * @pixel_clk:         desired pixel clock frequency in Hz.
-  * @width:             width of panel in pixels.
-  * @height:            height of panel in pixels.
-  * @pixel_fmt:         pixel format of buffer as FOURCC ASCII code.
-  * @h_start_width:     number of pixel clocks between the HSYNC signal pulse
-  *                     and the start of valid data.
-  * @h_sync_width:      width of the HSYNC signal in units of pixel clocks.
-  * @h_end_width:       number of pixel clocks between the end of valid data
-  *                     and the HSYNC signal for next line.
-  * @v_start_width:     number of lines between the VSYNC signal pulse and the
-  *                     start of valid data.
-  * @v_sync_width:      width of the VSYNC signal in units of lines
-  * @v_end_width:       number of lines between the end of valid data and the
-  *                     VSYNC signal for next frame.
-  * @sig:               bitfield of signal polarities for LCD interface.
-  * @return:            0 on success or negative error code on failure.
+  * @mx3fb:            mx3fb context.
+  * @panel:            panel type.
+  * @pixel_clk:                desired pixel clock frequency in Hz.
+  * @width:            width of panel in pixels.
+  * @height:           height of panel in pixels.
+  * @pixel_fmt:                pixel format of buffer as FOURCC ASCII code.
+  * @h_start_width:    number of pixel clocks between the HSYNC signal pulse
+  *                    and the start of valid data.
+  * @h_sync_width:     width of the HSYNC signal in units of pixel clocks.
+  * @h_end_width:      number of pixel clocks between the end of valid data
+  *                    and the HSYNC signal for next line.
+  * @v_start_width:    number of lines between the VSYNC signal pulse and the
+  *                    start of valid data.
+  * @v_sync_width:     width of the VSYNC signal in units of lines
+  * @v_end_width:      number of lines between the end of valid data and the
+  *                    VSYNC signal for next frame.
+  * @sig:              bitfield of signal polarities for LCD interface.
+  * @return:           0 on success or negative error code on failure.
   */
  static int sdc_init_panel(struct mx3fb_data *mx3fb, enum ipu_panel panel,
-                          uint32_t pixel_clk,
-                          uint16_t width, uint16_t height,
-                          enum pixel_fmt pixel_fmt,
-                          uint16_t h_start_width, uint16_t h_sync_width,
-                          uint16_t h_end_width, uint16_t v_start_width,
-                          uint16_t v_sync_width, uint16_t v_end_width,
-                          struct ipu_di_signal_cfg sig)
+                         uint32_t pixel_clk,
+                         uint16_t width, uint16_t height,
+                         enum pixel_fmt pixel_fmt,
+                         uint16_t h_start_width, uint16_t h_sync_width,
+                         uint16_t h_end_width, uint16_t v_start_width,
+                         uint16_t v_sync_width, uint16_t v_end_width,
+                         struct ipu_di_signal_cfg sig)
  {
-        unsigned long lock_flags;
-        uint32_t reg;
-        uint32_t old_conf;
-        uint32_t div;
-        struct clk *ipu_clk;
+       unsigned long lock_flags;
+       uint32_t reg;
+       uint32_t old_conf;
+       uint32_t div;
+       struct clk *ipu_clk;
  
-        dev_dbg(mx3fb->dev, "panel size = %d x %d", width, height);
+       dev_dbg(mx3fb->dev, "panel size = %d x %d", width, height);
  
-        if (v_sync_width == 0 || h_sync_width == 0)
-                return -EINVAL;
+       if (v_sync_width == 0 || h_sync_width == 0)
+               return -EINVAL;
  
-        /* Init panel size and blanking periods */
-        reg = ((uint32_t) (h_sync_width - 1) << 26) |
-                ((uint32_t) (width + h_start_width + h_end_width - 1) << 16);
-        mx3fb_write_reg(mx3fb, reg, SDC_HOR_CONF);
+       /* Init panel size and blanking periods */
+       reg = ((uint32_t) (h_sync_width - 1) << 26) |
+               ((uint32_t) (width + h_start_width + h_end_width - 1) << 16);
+       mx3fb_write_reg(mx3fb, reg, SDC_HOR_CONF);
  
  #ifdef DEBUG
-        printk(KERN_CONT " hor_conf %x,", reg);
+       printk(KERN_CONT " hor_conf %x,", reg);
  #endif
  
-        reg = ((uint32_t) (v_sync_width - 1) << 26) | SDC_V_SYNC_WIDTH_L |
-            ((uint32_t) (height + v_start_width + v_end_width - 1) << 16);
-        mx3fb_write_reg(mx3fb, reg, SDC_VER_CONF);
+       reg = ((uint32_t) (v_sync_width - 1) << 26) | SDC_V_SYNC_WIDTH_L |
+           ((uint32_t) (height + v_start_width + v_end_width - 1) << 16);
+       mx3fb_write_reg(mx3fb, reg, SDC_VER_CONF);
  
  #ifdef DEBUG
-        printk(KERN_CONT " ver_conf %x\n", reg);
+       printk(KERN_CONT " ver_conf %x\n", reg);
  #endif
  
-        mx3fb->h_start_width = h_start_width;
-        mx3fb->v_start_width = v_start_width;
-        switch (panel) {
-        case IPU_PANEL_SHARP_TFT:
-                mx3fb_write_reg(mx3fb, 0x00FD0102L, SDC_SHARP_CONF_1);
-                mx3fb_write_reg(mx3fb, 0x00F500F4L, SDC_SHARP_CONF_2);
-                mx3fb_write_reg(mx3fb, SDC_COM_SHARP | SDC_COM_TFT_COLOR, SDC_COM_CONF);
-                break;
-        case IPU_PANEL_TFT:
-                mx3fb_write_reg(mx3fb, SDC_COM_TFT_COLOR, SDC_COM_CONF);
-                break;
-        default:
-                return -EINVAL;
-        }
-        /* Init clocking */
-        /*
-         * Calculate divider: fractional part is 4 bits so simply multiple by
-         * 24 to get fractional part, as long as we stay under ~250MHz and on
-         * i.MX31 it (HSP_CLK) is <= 178MHz. Currently 128.267MHz
-         */
-        dev_dbg(mx3fb->dev, "pixel clk = %d\n", pixel_clk);
-        ipu_clk = clk_get(mx3fb->dev, NULL);
-        div = clk_get_rate(ipu_clk) * 16 / pixel_clk;
-        clk_put(ipu_clk);
-        if (div < 0x40) {       /* Divider less than 4 */
-                dev_dbg(mx3fb->dev,
-                        "InitPanel() - Pixel clock divider less than 4\n");
-                div = 0x40;
-        }
-        spin_lock_irqsave(&mx3fb->lock, lock_flags);
-        /*
-         * DISP3_IF_CLK_DOWN_WR is half the divider value and 2 fraction bits
-         * fewer. Subtract 1 extra from DISP3_IF_CLK_DOWN_WR based on timing
-         * debug. DISP3_IF_CLK_UP_WR is 0
-         */
-        mx3fb_write_reg(mx3fb, (((div / 8) - 1) << 22) | div, DI_DISP3_TIME_CONF);
-        /* DI settings */
-        old_conf = mx3fb_read_reg(mx3fb, DI_DISP_IF_CONF) & 0x78FFFFFF;
-        old_conf |= sig.datamask_en << DI_D3_DATAMSK_SHIFT |
-            sig.clksel_en << DI_D3_CLK_SEL_SHIFT |
-            sig.clkidle_en << DI_D3_CLK_IDLE_SHIFT;
-        mx3fb_write_reg(mx3fb, old_conf, DI_DISP_IF_CONF);
-        old_conf = mx3fb_read_reg(mx3fb, DI_DISP_SIG_POL) & 0xE0FFFFFF;
-        old_conf |= sig.data_pol << DI_D3_DATA_POL_SHIFT |
-            sig.clk_pol << DI_D3_CLK_POL_SHIFT |
-            sig.enable_pol << DI_D3_DRDY_SHARP_POL_SHIFT |
-            sig.Hsync_pol << DI_D3_HSYNC_POL_SHIFT |
-            sig.Vsync_pol << DI_D3_VSYNC_POL_SHIFT;
-        mx3fb_write_reg(mx3fb, old_conf, DI_DISP_SIG_POL);
-        switch (pixel_fmt) {
-        case IPU_PIX_FMT_RGB24:
-                mx3fb_write_reg(mx3fb, di_mappings[0], DI_DISP3_B0_MAP);
-                mx3fb_write_reg(mx3fb, di_mappings[1], DI_DISP3_B1_MAP);
-                mx3fb_write_reg(mx3fb, di_mappings[2], DI_DISP3_B2_MAP);
-                mx3fb_write_reg(mx3fb, mx3fb_read_reg(mx3fb, DI_DISP_ACC_CC) |
-                             ((di_mappings[3] - 1) << 12), DI_DISP_ACC_CC);
-                break;
-        case IPU_PIX_FMT_RGB666:
-                mx3fb_write_reg(mx3fb, di_mappings[4], DI_DISP3_B0_MAP);
-                mx3fb_write_reg(mx3fb, di_mappings[5], DI_DISP3_B1_MAP);
-                mx3fb_write_reg(mx3fb, di_mappings[6], DI_DISP3_B2_MAP);
-                mx3fb_write_reg(mx3fb, mx3fb_read_reg(mx3fb, DI_DISP_ACC_CC) |
-                             ((di_mappings[7] - 1) << 12), DI_DISP_ACC_CC);
-                break;
-        case IPU_PIX_FMT_BGR666:
-                mx3fb_write_reg(mx3fb, di_mappings[8], DI_DISP3_B0_MAP);
-                mx3fb_write_reg(mx3fb, di_mappings[9], DI_DISP3_B1_MAP);
-                mx3fb_write_reg(mx3fb, di_mappings[10], DI_DISP3_B2_MAP);
-                mx3fb_write_reg(mx3fb, mx3fb_read_reg(mx3fb, DI_DISP_ACC_CC) |
-                             ((di_mappings[11] - 1) << 12), DI_DISP_ACC_CC);
-                break;
-        default:
-                mx3fb_write_reg(mx3fb, di_mappings[12], DI_DISP3_B0_MAP);
-                mx3fb_write_reg(mx3fb, di_mappings[13], DI_DISP3_B1_MAP);
-                mx3fb_write_reg(mx3fb, di_mappings[14], DI_DISP3_B2_MAP);
-                mx3fb_write_reg(mx3fb, mx3fb_read_reg(mx3fb, DI_DISP_ACC_CC) |
-                             ((di_mappings[15] - 1) << 12), DI_DISP_ACC_CC);
-                break;
-        }
-        spin_unlock_irqrestore(&mx3fb->lock, lock_flags);
-        dev_dbg(mx3fb->dev, "DI_DISP_IF_CONF = 0x%08X\n",
-                mx3fb_read_reg(mx3fb, DI_DISP_IF_CONF));
-        dev_dbg(mx3fb->dev, "DI_DISP_SIG_POL = 0x%08X\n",
-                mx3fb_read_reg(mx3fb, DI_DISP_SIG_POL));
-        dev_dbg(mx3fb->dev, "DI_DISP3_TIME_CONF = 0x%08X\n",
-                mx3fb_read_reg(mx3fb, DI_DISP3_TIME_CONF));
-        return 0;
+       mx3fb->h_start_width = h_start_width;
+       mx3fb->v_start_width = v_start_width;
+       switch (panel) {
+       case IPU_PANEL_SHARP_TFT:
+               mx3fb_write_reg(mx3fb, 0x00FD0102L, SDC_SHARP_CONF_1);
+               mx3fb_write_reg(mx3fb, 0x00F500F4L, SDC_SHARP_CONF_2);
+               mx3fb_write_reg(mx3fb, SDC_COM_SHARP | SDC_COM_TFT_COLOR, SDC_COM_CONF);
+               break;
+       case IPU_PANEL_TFT:
+               mx3fb_write_reg(mx3fb, SDC_COM_TFT_COLOR, SDC_COM_CONF);
+               break;
+       default:
+               return -EINVAL;
+       }
+       /* Init clocking */
+       /*
+        * Calculate divider: fractional part is 4 bits so simply multiple by
+        * 2^4 to get fractional part, as long as we stay under ~250MHz and on
+        * i.MX31 it (HSP_CLK) is <= 178MHz. Currently 128.267MHz
+        */
+       dev_dbg(mx3fb->dev, "pixel clk = %d\n", pixel_clk);
 -      ipu_clk = clk_get(mx3fb->dev, "ipu_clk");
++      ipu_clk = clk_get(mx3fb->dev, NULL);
+       div = clk_get_rate(ipu_clk) * 16 / pixel_clk;
+       clk_put(ipu_clk);
+       if (div < 0x40) {       /* Divider less than 4 */
+               dev_dbg(mx3fb->dev,
+                       "InitPanel() - Pixel clock divider less than 4\n");
+               div = 0x40;
+       }
+       spin_lock_irqsave(&mx3fb->lock, lock_flags);
+       /*
+        * DISP3_IF_CLK_DOWN_WR is half the divider value and 2 fraction bits
+        * fewer. Subtract 1 extra from DISP3_IF_CLK_DOWN_WR based on timing
+        * debug. DISP3_IF_CLK_UP_WR is 0
+        */
+       mx3fb_write_reg(mx3fb, (((div / 8) - 1) << 22) | div, DI_DISP3_TIME_CONF);
+       /* DI settings */
+       old_conf = mx3fb_read_reg(mx3fb, DI_DISP_IF_CONF) & 0x78FFFFFF;
+       old_conf |= sig.datamask_en << DI_D3_DATAMSK_SHIFT |
+           sig.clksel_en << DI_D3_CLK_SEL_SHIFT |
+           sig.clkidle_en << DI_D3_CLK_IDLE_SHIFT;
+       mx3fb_write_reg(mx3fb, old_conf, DI_DISP_IF_CONF);
+       old_conf = mx3fb_read_reg(mx3fb, DI_DISP_SIG_POL) & 0xE0FFFFFF;
+       old_conf |= sig.data_pol << DI_D3_DATA_POL_SHIFT |
+           sig.clk_pol << DI_D3_CLK_POL_SHIFT |
+           sig.enable_pol << DI_D3_DRDY_SHARP_POL_SHIFT |
+           sig.Hsync_pol << DI_D3_HSYNC_POL_SHIFT |
+           sig.Vsync_pol << DI_D3_VSYNC_POL_SHIFT;
+       mx3fb_write_reg(mx3fb, old_conf, DI_DISP_SIG_POL);
+       switch (pixel_fmt) {
+       case IPU_PIX_FMT_RGB24:
+               mx3fb_write_reg(mx3fb, di_mappings[0], DI_DISP3_B0_MAP);
+               mx3fb_write_reg(mx3fb, di_mappings[1], DI_DISP3_B1_MAP);
+               mx3fb_write_reg(mx3fb, di_mappings[2], DI_DISP3_B2_MAP);
+               mx3fb_write_reg(mx3fb, mx3fb_read_reg(mx3fb, DI_DISP_ACC_CC) |
+                            ((di_mappings[3] - 1) << 12), DI_DISP_ACC_CC);
+               break;
+       case IPU_PIX_FMT_RGB666:
+               mx3fb_write_reg(mx3fb, di_mappings[4], DI_DISP3_B0_MAP);
+               mx3fb_write_reg(mx3fb, di_mappings[5], DI_DISP3_B1_MAP);
+               mx3fb_write_reg(mx3fb, di_mappings[6], DI_DISP3_B2_MAP);
+               mx3fb_write_reg(mx3fb, mx3fb_read_reg(mx3fb, DI_DISP_ACC_CC) |
+                            ((di_mappings[7] - 1) << 12), DI_DISP_ACC_CC);
+               break;
+       case IPU_PIX_FMT_BGR666:
+               mx3fb_write_reg(mx3fb, di_mappings[8], DI_DISP3_B0_MAP);
+               mx3fb_write_reg(mx3fb, di_mappings[9], DI_DISP3_B1_MAP);
+               mx3fb_write_reg(mx3fb, di_mappings[10], DI_DISP3_B2_MAP);
+               mx3fb_write_reg(mx3fb, mx3fb_read_reg(mx3fb, DI_DISP_ACC_CC) |
+                            ((di_mappings[11] - 1) << 12), DI_DISP_ACC_CC);
+               break;
+       default:
+               mx3fb_write_reg(mx3fb, di_mappings[12], DI_DISP3_B0_MAP);
+               mx3fb_write_reg(mx3fb, di_mappings[13], DI_DISP3_B1_MAP);
+               mx3fb_write_reg(mx3fb, di_mappings[14], DI_DISP3_B2_MAP);
+               mx3fb_write_reg(mx3fb, mx3fb_read_reg(mx3fb, DI_DISP_ACC_CC) |
+                            ((di_mappings[15] - 1) << 12), DI_DISP_ACC_CC);
+               break;
+       }
+       spin_unlock_irqrestore(&mx3fb->lock, lock_flags);
+       dev_dbg(mx3fb->dev, "DI_DISP_IF_CONF = 0x%08X\n",
+               mx3fb_read_reg(mx3fb, DI_DISP_IF_CONF));
+       dev_dbg(mx3fb->dev, "DI_DISP_SIG_POL = 0x%08X\n",
+               mx3fb_read_reg(mx3fb, DI_DISP_SIG_POL));
+       dev_dbg(mx3fb->dev, "DI_DISP3_TIME_CONF = 0x%08X\n",
+               mx3fb_read_reg(mx3fb, DI_DISP3_TIME_CONF));
+       return 0;
  }
  
  /**