2 * drivers/net/gianfar.c
4 * Gianfar Ethernet Driver
5 * This driver is designed for the non-CPM ethernet controllers
6 * on the 85xx and 83xx family of integrated processors
7 * Based on 8260_io/fcc_enet.c
10 * Maintainer: Kumar Gala
12 * Copyright (c) 2002-2006 Freescale Semiconductor, Inc.
13 * Copyright (c) 2007 MontaVista Software, Inc.
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
20 * Gianfar: AKA Lambda Draconis, "Dragon"
28 * The driver is initialized through of_device. Configuration information
29 * is therefore conveyed through an OF-style device tree.
31 * The Gianfar Ethernet Controller uses a ring of buffer
32 * descriptors. The beginning is indicated by a register
33 * pointing to the physical address of the start of the ring.
34 * The end is determined by a "wrap" bit being set in the
35 * last descriptor of the ring.
37 * When a packet is received, the RXF bit in the
38 * IEVENT register is set, triggering an interrupt when the
39 * corresponding bit in the IMASK register is also set (if
40 * interrupt coalescing is active, then the interrupt may not
41 * happen immediately, but will wait until either a set number
42 * of frames or amount of time have passed). In NAPI, the
43 * interrupt handler will signal there is work to be done, and
44 * exit. This method will start at the last known empty
45 * descriptor, and process every subsequent descriptor until there
46 * are none left with data (NAPI will stop after a set number of
47 * packets to give time to other tasks, but will eventually
48 * process all the packets). The data arrives inside a
49 * pre-allocated skb, and so after the skb is passed up to the
50 * stack, a new skb must be allocated, and the address field in
51 * the buffer descriptor must be updated to indicate this new
54 * When the kernel requests that a packet be transmitted, the
55 * driver starts where it left off last time, and points the
56 * descriptor at the buffer which was passed in. The driver
57 * then informs the DMA engine that there are packets ready to
58 * be transmitted. Once the controller is finished transmitting
59 * the packet, an interrupt may be triggered (under the same
60 * conditions as for reception, but depending on the TXF bit).
61 * The driver then cleans up the buffer.
64 #include <linux/kernel.h>
65 #include <linux/string.h>
66 #include <linux/errno.h>
67 #include <linux/unistd.h>
68 #include <linux/slab.h>
69 #include <linux/interrupt.h>
70 #include <linux/init.h>
71 #include <linux/delay.h>
72 #include <linux/netdevice.h>
73 #include <linux/etherdevice.h>
74 #include <linux/skbuff.h>
75 #include <linux/if_vlan.h>
76 #include <linux/spinlock.h>
78 #include <linux/of_mdio.h>
79 #include <linux/of_platform.h>
81 #include <linux/tcp.h>
82 #include <linux/udp.h>
87 #include <asm/uaccess.h>
88 #include <linux/module.h>
89 #include <linux/dma-mapping.h>
90 #include <linux/crc32.h>
91 #include <linux/mii.h>
92 #include <linux/phy.h>
93 #include <linux/phy_fixed.h>
97 #include "fsl_pq_mdio.h"
99 #define TX_TIMEOUT (1*HZ)
100 #undef BRIEF_GFAR_ERRORS
101 #undef VERBOSE_GFAR_ERRORS
103 const char gfar_driver_name[] = "Gianfar Ethernet";
104 const char gfar_driver_version[] = "1.3";
106 static int gfar_enet_open(struct net_device *dev);
107 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
108 static void gfar_reset_task(struct work_struct *work);
109 static void gfar_timeout(struct net_device *dev);
110 static int gfar_close(struct net_device *dev);
111 struct sk_buff *gfar_new_skb(struct net_device *dev);
112 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
113 struct sk_buff *skb);
114 static int gfar_set_mac_address(struct net_device *dev);
115 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
116 static irqreturn_t gfar_error(int irq, void *dev_id);
117 static irqreturn_t gfar_transmit(int irq, void *dev_id);
118 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
119 static void adjust_link(struct net_device *dev);
120 static void init_registers(struct net_device *dev);
121 static int init_phy(struct net_device *dev);
122 static int gfar_probe(struct of_device *ofdev,
123 const struct of_device_id *match);
124 static int gfar_remove(struct of_device *ofdev);
125 static void free_skb_resources(struct gfar_private *priv);
126 static void gfar_set_multi(struct net_device *dev);
127 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
128 static void gfar_configure_serdes(struct net_device *dev);
129 static int gfar_poll(struct napi_struct *napi, int budget);
130 #ifdef CONFIG_NET_POLL_CONTROLLER
131 static void gfar_netpoll(struct net_device *dev);
133 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit);
134 static int gfar_clean_tx_ring(struct net_device *dev);
135 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
137 static void gfar_vlan_rx_register(struct net_device *netdev,
138 struct vlan_group *grp);
139 void gfar_halt(struct net_device *dev);
140 static void gfar_halt_nodisable(struct net_device *dev);
141 void gfar_start(struct net_device *dev);
142 static void gfar_clear_exact_match(struct net_device *dev);
143 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
144 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
146 MODULE_AUTHOR("Freescale Semiconductor, Inc");
147 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
148 MODULE_LICENSE("GPL");
150 static const struct net_device_ops gfar_netdev_ops = {
151 .ndo_open = gfar_enet_open,
152 .ndo_start_xmit = gfar_start_xmit,
153 .ndo_stop = gfar_close,
154 .ndo_change_mtu = gfar_change_mtu,
155 .ndo_set_multicast_list = gfar_set_multi,
156 .ndo_tx_timeout = gfar_timeout,
157 .ndo_do_ioctl = gfar_ioctl,
158 .ndo_vlan_rx_register = gfar_vlan_rx_register,
159 .ndo_set_mac_address = eth_mac_addr,
160 .ndo_validate_addr = eth_validate_addr,
161 #ifdef CONFIG_NET_POLL_CONTROLLER
162 .ndo_poll_controller = gfar_netpoll,
166 /* Returns 1 if incoming frames use an FCB */
167 static inline int gfar_uses_fcb(struct gfar_private *priv)
169 return priv->vlgrp || priv->rx_csum_enable;
172 static int gfar_of_init(struct net_device *dev)
176 const void *mac_addr;
179 struct gfar_private *priv = netdev_priv(dev);
180 struct device_node *np = priv->node;
182 const u32 *stash_len;
183 const u32 *stash_idx;
185 if (!np || !of_device_is_available(np))
188 /* get a pointer to the register memory */
189 addr = of_translate_address(np, of_get_address(np, 0, &size, NULL));
190 priv->regs = ioremap(addr, size);
192 if (priv->regs == NULL)
195 priv->interruptTransmit = irq_of_parse_and_map(np, 0);
197 model = of_get_property(np, "model", NULL);
199 /* If we aren't the FEC we have multiple interrupts */
200 if (model && strcasecmp(model, "FEC")) {
201 priv->interruptReceive = irq_of_parse_and_map(np, 1);
203 priv->interruptError = irq_of_parse_and_map(np, 2);
205 if (priv->interruptTransmit < 0 ||
206 priv->interruptReceive < 0 ||
207 priv->interruptError < 0) {
213 stash = of_get_property(np, "bd-stash", NULL);
216 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
217 priv->bd_stash_en = 1;
220 stash_len = of_get_property(np, "rx-stash-len", NULL);
223 priv->rx_stash_size = *stash_len;
225 stash_idx = of_get_property(np, "rx-stash-idx", NULL);
228 priv->rx_stash_index = *stash_idx;
230 if (stash_len || stash_idx)
231 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
233 mac_addr = of_get_mac_address(np);
235 memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN);
237 if (model && !strcasecmp(model, "TSEC"))
239 FSL_GIANFAR_DEV_HAS_GIGABIT |
240 FSL_GIANFAR_DEV_HAS_COALESCE |
241 FSL_GIANFAR_DEV_HAS_RMON |
242 FSL_GIANFAR_DEV_HAS_MULTI_INTR;
243 if (model && !strcasecmp(model, "eTSEC"))
245 FSL_GIANFAR_DEV_HAS_GIGABIT |
246 FSL_GIANFAR_DEV_HAS_COALESCE |
247 FSL_GIANFAR_DEV_HAS_RMON |
248 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
249 FSL_GIANFAR_DEV_HAS_PADDING |
250 FSL_GIANFAR_DEV_HAS_CSUM |
251 FSL_GIANFAR_DEV_HAS_VLAN |
252 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
253 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH;
255 ctype = of_get_property(np, "phy-connection-type", NULL);
257 /* We only care about rgmii-id. The rest are autodetected */
258 if (ctype && !strcmp(ctype, "rgmii-id"))
259 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
261 priv->interface = PHY_INTERFACE_MODE_MII;
263 if (of_get_property(np, "fsl,magic-packet", NULL))
264 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
266 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
267 if (!priv->phy_node) {
270 fixed_link = (u32 *)of_get_property(np, "fixed-link", NULL);
277 /* Find the TBI PHY. If it's not there, we don't support SGMII */
278 priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
287 /* Ioctl MII Interface */
288 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
290 struct gfar_private *priv = netdev_priv(dev);
292 if (!netif_running(dev))
298 return phy_mii_ioctl(priv->phydev, if_mii(rq), cmd);
301 /* Set up the ethernet device structure, private data,
302 * and anything else we need before we start */
303 static int gfar_probe(struct of_device *ofdev,
304 const struct of_device_id *match)
307 struct net_device *dev = NULL;
308 struct gfar_private *priv = NULL;
312 /* Create an ethernet device instance */
313 dev = alloc_etherdev(sizeof (*priv));
318 priv = netdev_priv(dev);
321 priv->node = ofdev->node;
322 SET_NETDEV_DEV(dev, &ofdev->dev);
324 err = gfar_of_init(dev);
329 spin_lock_init(&priv->txlock);
330 spin_lock_init(&priv->rxlock);
331 spin_lock_init(&priv->bflock);
332 INIT_WORK(&priv->reset_task, gfar_reset_task);
334 dev_set_drvdata(&ofdev->dev, priv);
336 /* Stop the DMA engine now, in case it was running before */
337 /* (The firmware could have used it, and left it running). */
340 /* Reset MAC layer */
341 gfar_write(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
343 /* We need to delay at least 3 TX clocks */
346 tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
347 gfar_write(&priv->regs->maccfg1, tempval);
349 /* Initialize MACCFG2. */
350 gfar_write(&priv->regs->maccfg2, MACCFG2_INIT_SETTINGS);
352 /* Initialize ECNTRL */
353 gfar_write(&priv->regs->ecntrl, ECNTRL_INIT_SETTINGS);
355 /* Set the dev->base_addr to the gfar reg region */
356 dev->base_addr = (unsigned long) (priv->regs);
358 SET_NETDEV_DEV(dev, &ofdev->dev);
360 /* Fill in the dev structure */
361 dev->watchdog_timeo = TX_TIMEOUT;
362 netif_napi_add(dev, &priv->napi, gfar_poll, GFAR_DEV_WEIGHT);
365 dev->netdev_ops = &gfar_netdev_ops;
366 dev->ethtool_ops = &gfar_ethtool_ops;
368 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
369 priv->rx_csum_enable = 1;
370 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_HIGHDMA;
372 priv->rx_csum_enable = 0;
376 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN)
377 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
379 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
380 priv->extended_hash = 1;
381 priv->hash_width = 9;
383 priv->hash_regs[0] = &priv->regs->igaddr0;
384 priv->hash_regs[1] = &priv->regs->igaddr1;
385 priv->hash_regs[2] = &priv->regs->igaddr2;
386 priv->hash_regs[3] = &priv->regs->igaddr3;
387 priv->hash_regs[4] = &priv->regs->igaddr4;
388 priv->hash_regs[5] = &priv->regs->igaddr5;
389 priv->hash_regs[6] = &priv->regs->igaddr6;
390 priv->hash_regs[7] = &priv->regs->igaddr7;
391 priv->hash_regs[8] = &priv->regs->gaddr0;
392 priv->hash_regs[9] = &priv->regs->gaddr1;
393 priv->hash_regs[10] = &priv->regs->gaddr2;
394 priv->hash_regs[11] = &priv->regs->gaddr3;
395 priv->hash_regs[12] = &priv->regs->gaddr4;
396 priv->hash_regs[13] = &priv->regs->gaddr5;
397 priv->hash_regs[14] = &priv->regs->gaddr6;
398 priv->hash_regs[15] = &priv->regs->gaddr7;
401 priv->extended_hash = 0;
402 priv->hash_width = 8;
404 priv->hash_regs[0] = &priv->regs->gaddr0;
405 priv->hash_regs[1] = &priv->regs->gaddr1;
406 priv->hash_regs[2] = &priv->regs->gaddr2;
407 priv->hash_regs[3] = &priv->regs->gaddr3;
408 priv->hash_regs[4] = &priv->regs->gaddr4;
409 priv->hash_regs[5] = &priv->regs->gaddr5;
410 priv->hash_regs[6] = &priv->regs->gaddr6;
411 priv->hash_regs[7] = &priv->regs->gaddr7;
414 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
415 priv->padding = DEFAULT_PADDING;
419 if (dev->features & NETIF_F_IP_CSUM)
420 dev->hard_header_len += GMAC_FCB_LEN;
422 priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
423 priv->tx_ring_size = DEFAULT_TX_RING_SIZE;
424 priv->rx_ring_size = DEFAULT_RX_RING_SIZE;
425 priv->num_txbdfree = DEFAULT_TX_RING_SIZE;
427 priv->txcoalescing = DEFAULT_TX_COALESCE;
428 priv->txic = DEFAULT_TXIC;
429 priv->rxcoalescing = DEFAULT_RX_COALESCE;
430 priv->rxic = DEFAULT_RXIC;
432 /* Enable most messages by default */
433 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
435 /* Carrier starts down, phylib will bring it up */
436 netif_carrier_off(dev);
438 err = register_netdev(dev);
441 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
446 device_init_wakeup(&dev->dev,
447 priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
449 /* fill out IRQ number and name fields */
450 len_devname = strlen(dev->name);
451 strncpy(&priv->int_name_tx[0], dev->name, len_devname);
452 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
453 strncpy(&priv->int_name_tx[len_devname],
454 "_tx", sizeof("_tx") + 1);
456 strncpy(&priv->int_name_rx[0], dev->name, len_devname);
457 strncpy(&priv->int_name_rx[len_devname],
458 "_rx", sizeof("_rx") + 1);
460 strncpy(&priv->int_name_er[0], dev->name, len_devname);
461 strncpy(&priv->int_name_er[len_devname],
462 "_er", sizeof("_er") + 1);
464 priv->int_name_tx[len_devname] = '\0';
466 /* Create all the sysfs files */
467 gfar_init_sysfs(dev);
469 /* Print out the device info */
470 printk(KERN_INFO DEVICE_NAME "%pM\n", dev->name, dev->dev_addr);
472 /* Even more device info helps when determining which kernel */
473 /* provided which set of benchmarks. */
474 printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
475 printk(KERN_INFO "%s: %d/%d RX/TX BD ring size\n",
476 dev->name, priv->rx_ring_size, priv->tx_ring_size);
484 of_node_put(priv->phy_node);
486 of_node_put(priv->tbi_node);
491 static int gfar_remove(struct of_device *ofdev)
493 struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
496 of_node_put(priv->phy_node);
498 of_node_put(priv->tbi_node);
500 dev_set_drvdata(&ofdev->dev, NULL);
503 free_netdev(priv->ndev);
509 static int gfar_suspend(struct of_device *ofdev, pm_message_t state)
511 struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
512 struct net_device *dev = priv->ndev;
516 int magic_packet = priv->wol_en &&
517 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
519 netif_device_detach(dev);
521 if (netif_running(dev)) {
522 spin_lock_irqsave(&priv->txlock, flags);
523 spin_lock(&priv->rxlock);
525 gfar_halt_nodisable(dev);
527 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
528 tempval = gfar_read(&priv->regs->maccfg1);
530 tempval &= ~MACCFG1_TX_EN;
533 tempval &= ~MACCFG1_RX_EN;
535 gfar_write(&priv->regs->maccfg1, tempval);
537 spin_unlock(&priv->rxlock);
538 spin_unlock_irqrestore(&priv->txlock, flags);
540 napi_disable(&priv->napi);
543 /* Enable interrupt on Magic Packet */
544 gfar_write(&priv->regs->imask, IMASK_MAG);
546 /* Enable Magic Packet mode */
547 tempval = gfar_read(&priv->regs->maccfg2);
548 tempval |= MACCFG2_MPEN;
549 gfar_write(&priv->regs->maccfg2, tempval);
551 phy_stop(priv->phydev);
558 static int gfar_resume(struct of_device *ofdev)
560 struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
561 struct net_device *dev = priv->ndev;
564 int magic_packet = priv->wol_en &&
565 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
567 if (!netif_running(dev)) {
568 netif_device_attach(dev);
572 if (!magic_packet && priv->phydev)
573 phy_start(priv->phydev);
575 /* Disable Magic Packet mode, in case something
579 spin_lock_irqsave(&priv->txlock, flags);
580 spin_lock(&priv->rxlock);
582 tempval = gfar_read(&priv->regs->maccfg2);
583 tempval &= ~MACCFG2_MPEN;
584 gfar_write(&priv->regs->maccfg2, tempval);
588 spin_unlock(&priv->rxlock);
589 spin_unlock_irqrestore(&priv->txlock, flags);
591 netif_device_attach(dev);
593 napi_enable(&priv->napi);
598 #define gfar_suspend NULL
599 #define gfar_resume NULL
602 /* Reads the controller's registers to determine what interface
603 * connects it to the PHY.
605 static phy_interface_t gfar_get_interface(struct net_device *dev)
607 struct gfar_private *priv = netdev_priv(dev);
608 u32 ecntrl = gfar_read(&priv->regs->ecntrl);
610 if (ecntrl & ECNTRL_SGMII_MODE)
611 return PHY_INTERFACE_MODE_SGMII;
613 if (ecntrl & ECNTRL_TBI_MODE) {
614 if (ecntrl & ECNTRL_REDUCED_MODE)
615 return PHY_INTERFACE_MODE_RTBI;
617 return PHY_INTERFACE_MODE_TBI;
620 if (ecntrl & ECNTRL_REDUCED_MODE) {
621 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
622 return PHY_INTERFACE_MODE_RMII;
624 phy_interface_t interface = priv->interface;
627 * This isn't autodetected right now, so it must
628 * be set by the device tree or platform code.
630 if (interface == PHY_INTERFACE_MODE_RGMII_ID)
631 return PHY_INTERFACE_MODE_RGMII_ID;
633 return PHY_INTERFACE_MODE_RGMII;
637 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
638 return PHY_INTERFACE_MODE_GMII;
640 return PHY_INTERFACE_MODE_MII;
644 /* Initializes driver's PHY state, and attaches to the PHY.
645 * Returns 0 on success.
647 static int init_phy(struct net_device *dev)
649 struct gfar_private *priv = netdev_priv(dev);
650 uint gigabit_support =
651 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
652 SUPPORTED_1000baseT_Full : 0;
653 phy_interface_t interface;
657 priv->oldduplex = -1;
659 interface = gfar_get_interface(dev);
661 if (priv->phy_node) {
662 priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link,
665 dev_err(&dev->dev, "error: Could not attach to PHY\n");
670 if (interface == PHY_INTERFACE_MODE_SGMII)
671 gfar_configure_serdes(dev);
673 /* Remove any features not supported by the controller */
674 priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
675 priv->phydev->advertising = priv->phydev->supported;
681 * Initialize TBI PHY interface for communicating with the
682 * SERDES lynx PHY on the chip. We communicate with this PHY
683 * through the MDIO bus on each controller, treating it as a
684 * "normal" PHY at the address found in the TBIPA register. We assume
685 * that the TBIPA register is valid. Either the MDIO bus code will set
686 * it to a value that doesn't conflict with other PHYs on the bus, or the
687 * value doesn't matter, as there are no other PHYs on the bus.
689 static void gfar_configure_serdes(struct net_device *dev)
691 struct gfar_private *priv = netdev_priv(dev);
692 struct phy_device *tbiphy;
694 if (!priv->tbi_node) {
695 dev_warn(&dev->dev, "error: SGMII mode requires that the "
696 "device tree specify a tbi-handle\n");
700 tbiphy = of_phy_find_device(priv->tbi_node);
702 dev_err(&dev->dev, "error: Could not get TBI device\n");
707 * If the link is already up, we must already be ok, and don't need to
708 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
709 * everything for us? Resetting it takes the link down and requires
710 * several seconds for it to come back.
712 if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
715 /* Single clk mode, mii mode off(for serdes communication) */
716 phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
718 phy_write(tbiphy, MII_ADVERTISE,
719 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
720 ADVERTISE_1000XPSE_ASYM);
722 phy_write(tbiphy, MII_BMCR, BMCR_ANENABLE |
723 BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
726 static void init_registers(struct net_device *dev)
728 struct gfar_private *priv = netdev_priv(dev);
731 gfar_write(&priv->regs->ievent, IEVENT_INIT_CLEAR);
733 /* Initialize IMASK */
734 gfar_write(&priv->regs->imask, IMASK_INIT_CLEAR);
736 /* Init hash registers to zero */
737 gfar_write(&priv->regs->igaddr0, 0);
738 gfar_write(&priv->regs->igaddr1, 0);
739 gfar_write(&priv->regs->igaddr2, 0);
740 gfar_write(&priv->regs->igaddr3, 0);
741 gfar_write(&priv->regs->igaddr4, 0);
742 gfar_write(&priv->regs->igaddr5, 0);
743 gfar_write(&priv->regs->igaddr6, 0);
744 gfar_write(&priv->regs->igaddr7, 0);
746 gfar_write(&priv->regs->gaddr0, 0);
747 gfar_write(&priv->regs->gaddr1, 0);
748 gfar_write(&priv->regs->gaddr2, 0);
749 gfar_write(&priv->regs->gaddr3, 0);
750 gfar_write(&priv->regs->gaddr4, 0);
751 gfar_write(&priv->regs->gaddr5, 0);
752 gfar_write(&priv->regs->gaddr6, 0);
753 gfar_write(&priv->regs->gaddr7, 0);
755 /* Zero out the rmon mib registers if it has them */
756 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
757 memset_io(&(priv->regs->rmon), 0, sizeof (struct rmon_mib));
759 /* Mask off the CAM interrupts */
760 gfar_write(&priv->regs->rmon.cam1, 0xffffffff);
761 gfar_write(&priv->regs->rmon.cam2, 0xffffffff);
764 /* Initialize the max receive buffer length */
765 gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
767 /* Initialize the Minimum Frame Length Register */
768 gfar_write(&priv->regs->minflr, MINFLR_INIT_SETTINGS);
772 /* Halt the receive and transmit queues */
773 static void gfar_halt_nodisable(struct net_device *dev)
775 struct gfar_private *priv = netdev_priv(dev);
776 struct gfar __iomem *regs = priv->regs;
779 /* Mask all interrupts */
780 gfar_write(®s->imask, IMASK_INIT_CLEAR);
782 /* Clear all interrupts */
783 gfar_write(®s->ievent, IEVENT_INIT_CLEAR);
785 /* Stop the DMA, and wait for it to stop */
786 tempval = gfar_read(&priv->regs->dmactrl);
787 if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
788 != (DMACTRL_GRS | DMACTRL_GTS)) {
789 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
790 gfar_write(&priv->regs->dmactrl, tempval);
792 while (!(gfar_read(&priv->regs->ievent) &
793 (IEVENT_GRSC | IEVENT_GTSC)))
798 /* Halt the receive and transmit queues */
799 void gfar_halt(struct net_device *dev)
801 struct gfar_private *priv = netdev_priv(dev);
802 struct gfar __iomem *regs = priv->regs;
805 gfar_halt_nodisable(dev);
807 /* Disable Rx and Tx */
808 tempval = gfar_read(®s->maccfg1);
809 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
810 gfar_write(®s->maccfg1, tempval);
813 void stop_gfar(struct net_device *dev)
815 struct gfar_private *priv = netdev_priv(dev);
816 struct gfar __iomem *regs = priv->regs;
819 phy_stop(priv->phydev);
822 spin_lock_irqsave(&priv->txlock, flags);
823 spin_lock(&priv->rxlock);
827 spin_unlock(&priv->rxlock);
828 spin_unlock_irqrestore(&priv->txlock, flags);
831 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
832 free_irq(priv->interruptError, dev);
833 free_irq(priv->interruptTransmit, dev);
834 free_irq(priv->interruptReceive, dev);
836 free_irq(priv->interruptTransmit, dev);
839 free_skb_resources(priv);
841 dma_free_coherent(&priv->ofdev->dev,
842 sizeof(struct txbd8)*priv->tx_ring_size
843 + sizeof(struct rxbd8)*priv->rx_ring_size,
845 gfar_read(®s->tbase0));
848 /* If there are any tx skbs or rx skbs still around, free them.
849 * Then free tx_skbuff and rx_skbuff */
850 static void free_skb_resources(struct gfar_private *priv)
856 /* Go through all the buffer descriptors and free their data buffers */
857 txbdp = priv->tx_bd_base;
859 for (i = 0; i < priv->tx_ring_size; i++) {
860 if (!priv->tx_skbuff[i])
863 dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr,
864 txbdp->length, DMA_TO_DEVICE);
866 for (j = 0; j < skb_shinfo(priv->tx_skbuff[i])->nr_frags; j++) {
868 dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr,
869 txbdp->length, DMA_TO_DEVICE);
872 dev_kfree_skb_any(priv->tx_skbuff[i]);
873 priv->tx_skbuff[i] = NULL;
876 kfree(priv->tx_skbuff);
878 rxbdp = priv->rx_bd_base;
880 /* rx_skbuff is not guaranteed to be allocated, so only
881 * free it and its contents if it is allocated */
882 if(priv->rx_skbuff != NULL) {
883 for (i = 0; i < priv->rx_ring_size; i++) {
884 if (priv->rx_skbuff[i]) {
885 dma_unmap_single(&priv->ofdev->dev, rxbdp->bufPtr,
886 priv->rx_buffer_size,
889 dev_kfree_skb_any(priv->rx_skbuff[i]);
890 priv->rx_skbuff[i] = NULL;
899 kfree(priv->rx_skbuff);
903 void gfar_start(struct net_device *dev)
905 struct gfar_private *priv = netdev_priv(dev);
906 struct gfar __iomem *regs = priv->regs;
909 /* Enable Rx and Tx in MACCFG1 */
910 tempval = gfar_read(®s->maccfg1);
911 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
912 gfar_write(®s->maccfg1, tempval);
914 /* Initialize DMACTRL to have WWR and WOP */
915 tempval = gfar_read(&priv->regs->dmactrl);
916 tempval |= DMACTRL_INIT_SETTINGS;
917 gfar_write(&priv->regs->dmactrl, tempval);
919 /* Make sure we aren't stopped */
920 tempval = gfar_read(&priv->regs->dmactrl);
921 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
922 gfar_write(&priv->regs->dmactrl, tempval);
924 /* Clear THLT/RHLT, so that the DMA starts polling now */
925 gfar_write(®s->tstat, TSTAT_CLEAR_THALT);
926 gfar_write(®s->rstat, RSTAT_CLEAR_RHALT);
928 /* Unmask the interrupts we look for */
929 gfar_write(®s->imask, IMASK_DEFAULT);
931 dev->trans_start = jiffies;
934 /* Bring the controller up and running */
935 int startup_gfar(struct net_device *dev)
942 struct gfar_private *priv = netdev_priv(dev);
943 struct gfar __iomem *regs = priv->regs;
948 gfar_write(®s->imask, IMASK_INIT_CLEAR);
950 /* Allocate memory for the buffer descriptors */
951 vaddr = (unsigned long) dma_alloc_coherent(&priv->ofdev->dev,
952 sizeof (struct txbd8) * priv->tx_ring_size +
953 sizeof (struct rxbd8) * priv->rx_ring_size,
957 if (netif_msg_ifup(priv))
958 printk(KERN_ERR "%s: Could not allocate buffer descriptors!\n",
963 priv->tx_bd_base = (struct txbd8 *) vaddr;
965 /* enet DMA only understands physical addresses */
966 gfar_write(®s->tbase0, addr);
968 /* Start the rx descriptor ring where the tx ring leaves off */
969 addr = addr + sizeof (struct txbd8) * priv->tx_ring_size;
970 vaddr = vaddr + sizeof (struct txbd8) * priv->tx_ring_size;
971 priv->rx_bd_base = (struct rxbd8 *) vaddr;
972 gfar_write(®s->rbase0, addr);
974 /* Setup the skbuff rings */
976 (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
977 priv->tx_ring_size, GFP_KERNEL);
979 if (NULL == priv->tx_skbuff) {
980 if (netif_msg_ifup(priv))
981 printk(KERN_ERR "%s: Could not allocate tx_skbuff\n",
987 for (i = 0; i < priv->tx_ring_size; i++)
988 priv->tx_skbuff[i] = NULL;
991 (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
992 priv->rx_ring_size, GFP_KERNEL);
994 if (NULL == priv->rx_skbuff) {
995 if (netif_msg_ifup(priv))
996 printk(KERN_ERR "%s: Could not allocate rx_skbuff\n",
1002 for (i = 0; i < priv->rx_ring_size; i++)
1003 priv->rx_skbuff[i] = NULL;
1005 /* Initialize some variables in our dev structure */
1006 priv->num_txbdfree = priv->tx_ring_size;
1007 priv->dirty_tx = priv->cur_tx = priv->tx_bd_base;
1008 priv->cur_rx = priv->rx_bd_base;
1009 priv->skb_curtx = priv->skb_dirtytx = 0;
1010 priv->skb_currx = 0;
1012 /* Initialize Transmit Descriptor Ring */
1013 txbdp = priv->tx_bd_base;
1014 for (i = 0; i < priv->tx_ring_size; i++) {
1020 /* Set the last descriptor in the ring to indicate wrap */
1022 txbdp->status |= TXBD_WRAP;
1024 rxbdp = priv->rx_bd_base;
1025 for (i = 0; i < priv->rx_ring_size; i++) {
1026 struct sk_buff *skb;
1028 skb = gfar_new_skb(dev);
1031 printk(KERN_ERR "%s: Can't allocate RX buffers\n",
1034 goto err_rxalloc_fail;
1037 priv->rx_skbuff[i] = skb;
1039 gfar_new_rxbdp(dev, rxbdp, skb);
1044 /* Set the last descriptor in the ring to wrap */
1046 rxbdp->status |= RXBD_WRAP;
1048 /* If the device has multiple interrupts, register for
1049 * them. Otherwise, only register for the one */
1050 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1051 /* Install our interrupt handlers for Error,
1052 * Transmit, and Receive */
1053 if (request_irq(priv->interruptError, gfar_error,
1054 0, priv->int_name_er, dev) < 0) {
1055 if (netif_msg_intr(priv))
1056 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1057 dev->name, priv->interruptError);
1063 if (request_irq(priv->interruptTransmit, gfar_transmit,
1064 0, priv->int_name_tx, dev) < 0) {
1065 if (netif_msg_intr(priv))
1066 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1067 dev->name, priv->interruptTransmit);
1074 if (request_irq(priv->interruptReceive, gfar_receive,
1075 0, priv->int_name_rx, dev) < 0) {
1076 if (netif_msg_intr(priv))
1077 printk(KERN_ERR "%s: Can't get IRQ %d (receive0)\n",
1078 dev->name, priv->interruptReceive);
1084 if (request_irq(priv->interruptTransmit, gfar_interrupt,
1085 0, priv->int_name_tx, dev) < 0) {
1086 if (netif_msg_intr(priv))
1087 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1088 dev->name, priv->interruptTransmit);
1095 phy_start(priv->phydev);
1097 /* Configure the coalescing support */
1098 gfar_write(®s->txic, 0);
1099 if (priv->txcoalescing)
1100 gfar_write(®s->txic, priv->txic);
1102 gfar_write(®s->rxic, 0);
1103 if (priv->rxcoalescing)
1104 gfar_write(®s->rxic, priv->rxic);
1106 if (priv->rx_csum_enable)
1107 rctrl |= RCTRL_CHECKSUMMING;
1109 if (priv->extended_hash) {
1110 rctrl |= RCTRL_EXTHASH;
1112 gfar_clear_exact_match(dev);
1113 rctrl |= RCTRL_EMEN;
1116 if (priv->padding) {
1117 rctrl &= ~RCTRL_PAL_MASK;
1118 rctrl |= RCTRL_PADDING(priv->padding);
1121 /* Init rctrl based on our settings */
1122 gfar_write(&priv->regs->rctrl, rctrl);
1124 if (dev->features & NETIF_F_IP_CSUM)
1125 gfar_write(&priv->regs->tctrl, TCTRL_INIT_CSUM);
1127 /* Set the extraction length and index */
1128 attrs = ATTRELI_EL(priv->rx_stash_size) |
1129 ATTRELI_EI(priv->rx_stash_index);
1131 gfar_write(&priv->regs->attreli, attrs);
1133 /* Start with defaults, and add stashing or locking
1134 * depending on the approprate variables */
1135 attrs = ATTR_INIT_SETTINGS;
1137 if (priv->bd_stash_en)
1138 attrs |= ATTR_BDSTASH;
1140 if (priv->rx_stash_size != 0)
1141 attrs |= ATTR_BUFSTASH;
1143 gfar_write(&priv->regs->attr, attrs);
1145 gfar_write(&priv->regs->fifo_tx_thr, priv->fifo_threshold);
1146 gfar_write(&priv->regs->fifo_tx_starve, priv->fifo_starve);
1147 gfar_write(&priv->regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
1149 /* Start the controller */
1155 free_irq(priv->interruptTransmit, dev);
1157 free_irq(priv->interruptError, dev);
1161 free_skb_resources(priv);
1163 dma_free_coherent(&priv->ofdev->dev,
1164 sizeof(struct txbd8)*priv->tx_ring_size
1165 + sizeof(struct rxbd8)*priv->rx_ring_size,
1167 gfar_read(®s->tbase0));
1172 /* Called when something needs to use the ethernet device */
1173 /* Returns 0 for success. */
1174 static int gfar_enet_open(struct net_device *dev)
1176 struct gfar_private *priv = netdev_priv(dev);
1179 napi_enable(&priv->napi);
1181 skb_queue_head_init(&priv->rx_recycle);
1183 /* Initialize a bunch of registers */
1184 init_registers(dev);
1186 gfar_set_mac_address(dev);
1188 err = init_phy(dev);
1191 napi_disable(&priv->napi);
1195 err = startup_gfar(dev);
1197 napi_disable(&priv->napi);
1201 netif_start_queue(dev);
1203 device_set_wakeup_enable(&dev->dev, priv->wol_en);
1208 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
1210 struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
1212 memset(fcb, 0, GMAC_FCB_LEN);
1217 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
1221 /* If we're here, it's a IP packet with a TCP or UDP
1222 * payload. We set it to checksum, using a pseudo-header
1225 flags = TXFCB_DEFAULT;
1227 /* Tell the controller what the protocol is */
1228 /* And provide the already calculated phcs */
1229 if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
1231 fcb->phcs = udp_hdr(skb)->check;
1233 fcb->phcs = tcp_hdr(skb)->check;
1235 /* l3os is the distance between the start of the
1236 * frame (skb->data) and the start of the IP hdr.
1237 * l4os is the distance between the start of the
1238 * l3 hdr and the l4 hdr */
1239 fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
1240 fcb->l4os = skb_network_header_len(skb);
1245 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
1247 fcb->flags |= TXFCB_VLN;
1248 fcb->vlctl = vlan_tx_tag_get(skb);
1251 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
1252 struct txbd8 *base, int ring_size)
1254 struct txbd8 *new_bd = bdp + stride;
1256 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
1259 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
1262 return skip_txbd(bdp, 1, base, ring_size);
1265 /* This is called by the kernel when a frame is ready for transmission. */
1266 /* It is pointed to by the dev->hard_start_xmit function pointer */
1267 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
1269 struct gfar_private *priv = netdev_priv(dev);
1270 struct txfcb *fcb = NULL;
1271 struct txbd8 *txbdp, *txbdp_start, *base;
1275 unsigned long flags;
1276 unsigned int nr_frags, length;
1278 base = priv->tx_bd_base;
1280 /* make space for additional header when fcb is needed */
1281 if (((skb->ip_summed == CHECKSUM_PARTIAL) ||
1282 (priv->vlgrp && vlan_tx_tag_present(skb))) &&
1283 (skb_headroom(skb) < GMAC_FCB_LEN)) {
1284 struct sk_buff *skb_new;
1286 skb_new = skb_realloc_headroom(skb, GMAC_FCB_LEN);
1288 dev->stats.tx_errors++;
1290 return NETDEV_TX_OK;
1296 /* total number of fragments in the SKB */
1297 nr_frags = skb_shinfo(skb)->nr_frags;
1299 spin_lock_irqsave(&priv->txlock, flags);
1301 /* check if there is space to queue this packet */
1302 if ((nr_frags+1) > priv->num_txbdfree) {
1303 /* no space, stop the queue */
1304 netif_stop_queue(dev);
1305 dev->stats.tx_fifo_errors++;
1306 spin_unlock_irqrestore(&priv->txlock, flags);
1307 return NETDEV_TX_BUSY;
1310 /* Update transmit stats */
1311 dev->stats.tx_bytes += skb->len;
1313 txbdp = txbdp_start = priv->cur_tx;
1315 if (nr_frags == 0) {
1316 lstatus = txbdp->lstatus | BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1318 /* Place the fragment addresses and lengths into the TxBDs */
1319 for (i = 0; i < nr_frags; i++) {
1320 /* Point at the next BD, wrapping as needed */
1321 txbdp = next_txbd(txbdp, base, priv->tx_ring_size);
1323 length = skb_shinfo(skb)->frags[i].size;
1325 lstatus = txbdp->lstatus | length |
1326 BD_LFLAG(TXBD_READY);
1328 /* Handle the last BD specially */
1329 if (i == nr_frags - 1)
1330 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1332 bufaddr = dma_map_page(&priv->ofdev->dev,
1333 skb_shinfo(skb)->frags[i].page,
1334 skb_shinfo(skb)->frags[i].page_offset,
1338 /* set the TxBD length and buffer pointer */
1339 txbdp->bufPtr = bufaddr;
1340 txbdp->lstatus = lstatus;
1343 lstatus = txbdp_start->lstatus;
1346 /* Set up checksumming */
1347 if (CHECKSUM_PARTIAL == skb->ip_summed) {
1348 fcb = gfar_add_fcb(skb);
1349 lstatus |= BD_LFLAG(TXBD_TOE);
1350 gfar_tx_checksum(skb, fcb);
1353 if (priv->vlgrp && vlan_tx_tag_present(skb)) {
1354 if (unlikely(NULL == fcb)) {
1355 fcb = gfar_add_fcb(skb);
1356 lstatus |= BD_LFLAG(TXBD_TOE);
1359 gfar_tx_vlan(skb, fcb);
1362 /* setup the TxBD length and buffer pointer for the first BD */
1363 priv->tx_skbuff[priv->skb_curtx] = skb;
1364 txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
1365 skb_headlen(skb), DMA_TO_DEVICE);
1367 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
1370 * The powerpc-specific eieio() is used, as wmb() has too strong
1371 * semantics (it requires synchronization between cacheable and
1372 * uncacheable mappings, which eieio doesn't provide and which we
1373 * don't need), thus requiring a more expensive sync instruction. At
1374 * some point, the set of architecture-independent barrier functions
1375 * should be expanded to include weaker barriers.
1379 txbdp_start->lstatus = lstatus;
1381 /* Update the current skb pointer to the next entry we will use
1382 * (wrapping if necessary) */
1383 priv->skb_curtx = (priv->skb_curtx + 1) &
1384 TX_RING_MOD_MASK(priv->tx_ring_size);
1386 priv->cur_tx = next_txbd(txbdp, base, priv->tx_ring_size);
1388 /* reduce TxBD free count */
1389 priv->num_txbdfree -= (nr_frags + 1);
1391 dev->trans_start = jiffies;
1393 /* If the next BD still needs to be cleaned up, then the bds
1394 are full. We need to tell the kernel to stop sending us stuff. */
1395 if (!priv->num_txbdfree) {
1396 netif_stop_queue(dev);
1398 dev->stats.tx_fifo_errors++;
1401 /* Tell the DMA to go go go */
1402 gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1405 spin_unlock_irqrestore(&priv->txlock, flags);
1407 return NETDEV_TX_OK;
1410 /* Stops the kernel queue, and halts the controller */
1411 static int gfar_close(struct net_device *dev)
1413 struct gfar_private *priv = netdev_priv(dev);
1415 napi_disable(&priv->napi);
1417 skb_queue_purge(&priv->rx_recycle);
1418 cancel_work_sync(&priv->reset_task);
1421 /* Disconnect from the PHY */
1422 phy_disconnect(priv->phydev);
1423 priv->phydev = NULL;
1425 netif_stop_queue(dev);
1430 /* Changes the mac address if the controller is not running. */
1431 static int gfar_set_mac_address(struct net_device *dev)
1433 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1439 /* Enables and disables VLAN insertion/extraction */
1440 static void gfar_vlan_rx_register(struct net_device *dev,
1441 struct vlan_group *grp)
1443 struct gfar_private *priv = netdev_priv(dev);
1444 unsigned long flags;
1447 spin_lock_irqsave(&priv->rxlock, flags);
1452 /* Enable VLAN tag insertion */
1453 tempval = gfar_read(&priv->regs->tctrl);
1454 tempval |= TCTRL_VLINS;
1456 gfar_write(&priv->regs->tctrl, tempval);
1458 /* Enable VLAN tag extraction */
1459 tempval = gfar_read(&priv->regs->rctrl);
1460 tempval |= RCTRL_VLEX;
1461 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
1462 gfar_write(&priv->regs->rctrl, tempval);
1464 /* Disable VLAN tag insertion */
1465 tempval = gfar_read(&priv->regs->tctrl);
1466 tempval &= ~TCTRL_VLINS;
1467 gfar_write(&priv->regs->tctrl, tempval);
1469 /* Disable VLAN tag extraction */
1470 tempval = gfar_read(&priv->regs->rctrl);
1471 tempval &= ~RCTRL_VLEX;
1472 /* If parse is no longer required, then disable parser */
1473 if (tempval & RCTRL_REQ_PARSER)
1474 tempval |= RCTRL_PRSDEP_INIT;
1476 tempval &= ~RCTRL_PRSDEP_INIT;
1477 gfar_write(&priv->regs->rctrl, tempval);
1480 gfar_change_mtu(dev, dev->mtu);
1482 spin_unlock_irqrestore(&priv->rxlock, flags);
1485 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
1487 int tempsize, tempval;
1488 struct gfar_private *priv = netdev_priv(dev);
1489 int oldsize = priv->rx_buffer_size;
1490 int frame_size = new_mtu + ETH_HLEN;
1493 frame_size += VLAN_HLEN;
1495 if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
1496 if (netif_msg_drv(priv))
1497 printk(KERN_ERR "%s: Invalid MTU setting\n",
1502 if (gfar_uses_fcb(priv))
1503 frame_size += GMAC_FCB_LEN;
1505 frame_size += priv->padding;
1508 (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
1509 INCREMENTAL_BUFFER_SIZE;
1511 /* Only stop and start the controller if it isn't already
1512 * stopped, and we changed something */
1513 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1516 priv->rx_buffer_size = tempsize;
1520 gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
1521 gfar_write(&priv->regs->maxfrm, priv->rx_buffer_size);
1523 /* If the mtu is larger than the max size for standard
1524 * ethernet frames (ie, a jumbo frame), then set maccfg2
1525 * to allow huge frames, and to check the length */
1526 tempval = gfar_read(&priv->regs->maccfg2);
1528 if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
1529 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1531 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1533 gfar_write(&priv->regs->maccfg2, tempval);
1535 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1541 /* gfar_reset_task gets scheduled when a packet has not been
1542 * transmitted after a set amount of time.
1543 * For now, assume that clearing out all the structures, and
1544 * starting over will fix the problem.
1546 static void gfar_reset_task(struct work_struct *work)
1548 struct gfar_private *priv = container_of(work, struct gfar_private,
1550 struct net_device *dev = priv->ndev;
1552 if (dev->flags & IFF_UP) {
1553 netif_stop_queue(dev);
1556 netif_start_queue(dev);
1559 netif_tx_schedule_all(dev);
1562 static void gfar_timeout(struct net_device *dev)
1564 struct gfar_private *priv = netdev_priv(dev);
1566 dev->stats.tx_errors++;
1567 schedule_work(&priv->reset_task);
1570 /* Interrupt Handler for Transmit complete */
1571 static int gfar_clean_tx_ring(struct net_device *dev)
1573 struct gfar_private *priv = netdev_priv(dev);
1575 struct txbd8 *lbdp = NULL;
1576 struct txbd8 *base = priv->tx_bd_base;
1577 struct sk_buff *skb;
1579 int tx_ring_size = priv->tx_ring_size;
1585 bdp = priv->dirty_tx;
1586 skb_dirtytx = priv->skb_dirtytx;
1588 while ((skb = priv->tx_skbuff[skb_dirtytx])) {
1589 frags = skb_shinfo(skb)->nr_frags;
1590 lbdp = skip_txbd(bdp, frags, base, tx_ring_size);
1592 lstatus = lbdp->lstatus;
1594 /* Only clean completed frames */
1595 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
1596 (lstatus & BD_LENGTH_MASK))
1599 dma_unmap_single(&priv->ofdev->dev,
1604 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
1605 bdp = next_txbd(bdp, base, tx_ring_size);
1607 for (i = 0; i < frags; i++) {
1608 dma_unmap_page(&priv->ofdev->dev,
1612 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
1613 bdp = next_txbd(bdp, base, tx_ring_size);
1617 * If there's room in the queue (limit it to rx_buffer_size)
1618 * we add this skb back into the pool, if it's the right size
1620 if (skb_queue_len(&priv->rx_recycle) < priv->rx_ring_size &&
1621 skb_recycle_check(skb, priv->rx_buffer_size +
1623 __skb_queue_head(&priv->rx_recycle, skb);
1625 dev_kfree_skb_any(skb);
1627 priv->tx_skbuff[skb_dirtytx] = NULL;
1629 skb_dirtytx = (skb_dirtytx + 1) &
1630 TX_RING_MOD_MASK(tx_ring_size);
1633 priv->num_txbdfree += frags + 1;
1636 /* If we freed a buffer, we can restart transmission, if necessary */
1637 if (netif_queue_stopped(dev) && priv->num_txbdfree)
1638 netif_wake_queue(dev);
1640 /* Update dirty indicators */
1641 priv->skb_dirtytx = skb_dirtytx;
1642 priv->dirty_tx = bdp;
1644 dev->stats.tx_packets += howmany;
1649 static void gfar_schedule_cleanup(struct net_device *dev)
1651 struct gfar_private *priv = netdev_priv(dev);
1652 unsigned long flags;
1654 spin_lock_irqsave(&priv->txlock, flags);
1655 spin_lock(&priv->rxlock);
1657 if (napi_schedule_prep(&priv->napi)) {
1658 gfar_write(&priv->regs->imask, IMASK_RTX_DISABLED);
1659 __napi_schedule(&priv->napi);
1662 * Clear IEVENT, so interrupts aren't called again
1663 * because of the packets that have already arrived.
1665 gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK);
1668 spin_unlock(&priv->rxlock);
1669 spin_unlock_irqrestore(&priv->txlock, flags);
1672 /* Interrupt Handler for Transmit complete */
1673 static irqreturn_t gfar_transmit(int irq, void *dev_id)
1675 gfar_schedule_cleanup((struct net_device *)dev_id);
1679 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
1680 struct sk_buff *skb)
1682 struct gfar_private *priv = netdev_priv(dev);
1685 bdp->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
1686 priv->rx_buffer_size, DMA_FROM_DEVICE);
1688 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
1690 if (bdp == priv->rx_bd_base + priv->rx_ring_size - 1)
1691 lstatus |= BD_LFLAG(RXBD_WRAP);
1695 bdp->lstatus = lstatus;
1699 struct sk_buff * gfar_new_skb(struct net_device *dev)
1701 unsigned int alignamount;
1702 struct gfar_private *priv = netdev_priv(dev);
1703 struct sk_buff *skb = NULL;
1705 skb = __skb_dequeue(&priv->rx_recycle);
1707 skb = netdev_alloc_skb(dev,
1708 priv->rx_buffer_size + RXBUF_ALIGNMENT);
1713 alignamount = RXBUF_ALIGNMENT -
1714 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1));
1716 /* We need the data buffer to be aligned properly. We will reserve
1717 * as many bytes as needed to align the data properly
1719 skb_reserve(skb, alignamount);
1724 static inline void count_errors(unsigned short status, struct net_device *dev)
1726 struct gfar_private *priv = netdev_priv(dev);
1727 struct net_device_stats *stats = &dev->stats;
1728 struct gfar_extra_stats *estats = &priv->extra_stats;
1730 /* If the packet was truncated, none of the other errors
1732 if (status & RXBD_TRUNCATED) {
1733 stats->rx_length_errors++;
1739 /* Count the errors, if there were any */
1740 if (status & (RXBD_LARGE | RXBD_SHORT)) {
1741 stats->rx_length_errors++;
1743 if (status & RXBD_LARGE)
1748 if (status & RXBD_NONOCTET) {
1749 stats->rx_frame_errors++;
1750 estats->rx_nonoctet++;
1752 if (status & RXBD_CRCERR) {
1753 estats->rx_crcerr++;
1754 stats->rx_crc_errors++;
1756 if (status & RXBD_OVERRUN) {
1757 estats->rx_overrun++;
1758 stats->rx_crc_errors++;
1762 irqreturn_t gfar_receive(int irq, void *dev_id)
1764 gfar_schedule_cleanup((struct net_device *)dev_id);
1768 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
1770 /* If valid headers were found, and valid sums
1771 * were verified, then we tell the kernel that no
1772 * checksumming is necessary. Otherwise, it is */
1773 if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
1774 skb->ip_summed = CHECKSUM_UNNECESSARY;
1776 skb->ip_summed = CHECKSUM_NONE;
1780 /* gfar_process_frame() -- handle one incoming packet if skb
1782 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
1785 struct gfar_private *priv = netdev_priv(dev);
1786 struct rxfcb *fcb = NULL;
1790 /* fcb is at the beginning if exists */
1791 fcb = (struct rxfcb *)skb->data;
1793 /* Remove the FCB from the skb */
1794 /* Remove the padded bytes, if there are any */
1796 skb_pull(skb, amount_pull);
1798 if (priv->rx_csum_enable)
1799 gfar_rx_checksum(skb, fcb);
1801 /* Tell the skb what kind of packet this is */
1802 skb->protocol = eth_type_trans(skb, dev);
1804 /* Send the packet up the stack */
1805 if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))
1806 ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp, fcb->vlctl);
1808 ret = netif_receive_skb(skb);
1810 if (NET_RX_DROP == ret)
1811 priv->extra_stats.kernel_dropped++;
1816 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1817 * until the budget/quota has been reached. Returns the number
1820 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit)
1822 struct rxbd8 *bdp, *base;
1823 struct sk_buff *skb;
1827 struct gfar_private *priv = netdev_priv(dev);
1829 /* Get the first full descriptor */
1831 base = priv->rx_bd_base;
1833 amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0) +
1836 while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
1837 struct sk_buff *newskb;
1840 /* Add another skb for the future */
1841 newskb = gfar_new_skb(dev);
1843 skb = priv->rx_skbuff[priv->skb_currx];
1845 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
1846 priv->rx_buffer_size, DMA_FROM_DEVICE);
1848 /* We drop the frame if we failed to allocate a new buffer */
1849 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
1850 bdp->status & RXBD_ERR)) {
1851 count_errors(bdp->status, dev);
1853 if (unlikely(!newskb))
1857 * We need to reset ->data to what it
1858 * was before gfar_new_skb() re-aligned
1859 * it to an RXBUF_ALIGNMENT boundary
1860 * before we put the skb back on the
1863 skb->data = skb->head + NET_SKB_PAD;
1864 __skb_queue_head(&priv->rx_recycle, skb);
1867 /* Increment the number of packets */
1868 dev->stats.rx_packets++;
1872 pkt_len = bdp->length - ETH_FCS_LEN;
1873 /* Remove the FCS from the packet length */
1874 skb_put(skb, pkt_len);
1875 dev->stats.rx_bytes += pkt_len;
1877 if (in_irq() || irqs_disabled())
1878 printk("Interrupt problem!\n");
1879 gfar_process_frame(dev, skb, amount_pull);
1882 if (netif_msg_rx_err(priv))
1884 "%s: Missing skb!\n", dev->name);
1885 dev->stats.rx_dropped++;
1886 priv->extra_stats.rx_skbmissing++;
1891 priv->rx_skbuff[priv->skb_currx] = newskb;
1893 /* Setup the new bdp */
1894 gfar_new_rxbdp(dev, bdp, newskb);
1896 /* Update to the next pointer */
1897 bdp = next_bd(bdp, base, priv->rx_ring_size);
1899 /* update to point at the next skb */
1901 (priv->skb_currx + 1) &
1902 RX_RING_MOD_MASK(priv->rx_ring_size);
1905 /* Update the current rxbd pointer to be the next one */
1911 static int gfar_poll(struct napi_struct *napi, int budget)
1913 struct gfar_private *priv = container_of(napi, struct gfar_private, napi);
1914 struct net_device *dev = priv->ndev;
1917 unsigned long flags;
1919 /* Clear IEVENT, so interrupts aren't called again
1920 * because of the packets that have already arrived */
1921 gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK);
1923 /* If we fail to get the lock, don't bother with the TX BDs */
1924 if (spin_trylock_irqsave(&priv->txlock, flags)) {
1925 tx_cleaned = gfar_clean_tx_ring(dev);
1926 spin_unlock_irqrestore(&priv->txlock, flags);
1929 rx_cleaned = gfar_clean_rx_ring(dev, budget);
1934 if (rx_cleaned < budget) {
1935 napi_complete(napi);
1937 /* Clear the halt bit in RSTAT */
1938 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1940 gfar_write(&priv->regs->imask, IMASK_DEFAULT);
1942 /* If we are coalescing interrupts, update the timer */
1943 /* Otherwise, clear it */
1944 if (likely(priv->rxcoalescing)) {
1945 gfar_write(&priv->regs->rxic, 0);
1946 gfar_write(&priv->regs->rxic, priv->rxic);
1948 if (likely(priv->txcoalescing)) {
1949 gfar_write(&priv->regs->txic, 0);
1950 gfar_write(&priv->regs->txic, priv->txic);
1957 #ifdef CONFIG_NET_POLL_CONTROLLER
1959 * Polling 'interrupt' - used by things like netconsole to send skbs
1960 * without having to re-enable interrupts. It's not called while
1961 * the interrupt routine is executing.
1963 static void gfar_netpoll(struct net_device *dev)
1965 struct gfar_private *priv = netdev_priv(dev);
1967 /* If the device has multiple interrupts, run tx/rx */
1968 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1969 disable_irq(priv->interruptTransmit);
1970 disable_irq(priv->interruptReceive);
1971 disable_irq(priv->interruptError);
1972 gfar_interrupt(priv->interruptTransmit, dev);
1973 enable_irq(priv->interruptError);
1974 enable_irq(priv->interruptReceive);
1975 enable_irq(priv->interruptTransmit);
1977 disable_irq(priv->interruptTransmit);
1978 gfar_interrupt(priv->interruptTransmit, dev);
1979 enable_irq(priv->interruptTransmit);
1984 /* The interrupt handler for devices with one interrupt */
1985 static irqreturn_t gfar_interrupt(int irq, void *dev_id)
1987 struct net_device *dev = dev_id;
1988 struct gfar_private *priv = netdev_priv(dev);
1990 /* Save ievent for future reference */
1991 u32 events = gfar_read(&priv->regs->ievent);
1993 /* Check for reception */
1994 if (events & IEVENT_RX_MASK)
1995 gfar_receive(irq, dev_id);
1997 /* Check for transmit completion */
1998 if (events & IEVENT_TX_MASK)
1999 gfar_transmit(irq, dev_id);
2001 /* Check for errors */
2002 if (events & IEVENT_ERR_MASK)
2003 gfar_error(irq, dev_id);
2008 /* Called every time the controller might need to be made
2009 * aware of new link state. The PHY code conveys this
2010 * information through variables in the phydev structure, and this
2011 * function converts those variables into the appropriate
2012 * register values, and can bring down the device if needed.
2014 static void adjust_link(struct net_device *dev)
2016 struct gfar_private *priv = netdev_priv(dev);
2017 struct gfar __iomem *regs = priv->regs;
2018 unsigned long flags;
2019 struct phy_device *phydev = priv->phydev;
2022 spin_lock_irqsave(&priv->txlock, flags);
2024 u32 tempval = gfar_read(®s->maccfg2);
2025 u32 ecntrl = gfar_read(®s->ecntrl);
2027 /* Now we make sure that we can be in full duplex mode.
2028 * If not, we operate in half-duplex mode. */
2029 if (phydev->duplex != priv->oldduplex) {
2031 if (!(phydev->duplex))
2032 tempval &= ~(MACCFG2_FULL_DUPLEX);
2034 tempval |= MACCFG2_FULL_DUPLEX;
2036 priv->oldduplex = phydev->duplex;
2039 if (phydev->speed != priv->oldspeed) {
2041 switch (phydev->speed) {
2044 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
2046 ecntrl &= ~(ECNTRL_R100);
2051 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
2053 /* Reduced mode distinguishes
2054 * between 10 and 100 */
2055 if (phydev->speed == SPEED_100)
2056 ecntrl |= ECNTRL_R100;
2058 ecntrl &= ~(ECNTRL_R100);
2061 if (netif_msg_link(priv))
2063 "%s: Ack! Speed (%d) is not 10/100/1000!\n",
2064 dev->name, phydev->speed);
2068 priv->oldspeed = phydev->speed;
2071 gfar_write(®s->maccfg2, tempval);
2072 gfar_write(®s->ecntrl, ecntrl);
2074 if (!priv->oldlink) {
2078 } else if (priv->oldlink) {
2082 priv->oldduplex = -1;
2085 if (new_state && netif_msg_link(priv))
2086 phy_print_status(phydev);
2088 spin_unlock_irqrestore(&priv->txlock, flags);
2091 /* Update the hash table based on the current list of multicast
2092 * addresses we subscribe to. Also, change the promiscuity of
2093 * the device based on the flags (this function is called
2094 * whenever dev->flags is changed */
2095 static void gfar_set_multi(struct net_device *dev)
2097 struct dev_mc_list *mc_ptr;
2098 struct gfar_private *priv = netdev_priv(dev);
2099 struct gfar __iomem *regs = priv->regs;
2102 if(dev->flags & IFF_PROMISC) {
2103 /* Set RCTRL to PROM */
2104 tempval = gfar_read(®s->rctrl);
2105 tempval |= RCTRL_PROM;
2106 gfar_write(®s->rctrl, tempval);
2108 /* Set RCTRL to not PROM */
2109 tempval = gfar_read(®s->rctrl);
2110 tempval &= ~(RCTRL_PROM);
2111 gfar_write(®s->rctrl, tempval);
2114 if(dev->flags & IFF_ALLMULTI) {
2115 /* Set the hash to rx all multicast frames */
2116 gfar_write(®s->igaddr0, 0xffffffff);
2117 gfar_write(®s->igaddr1, 0xffffffff);
2118 gfar_write(®s->igaddr2, 0xffffffff);
2119 gfar_write(®s->igaddr3, 0xffffffff);
2120 gfar_write(®s->igaddr4, 0xffffffff);
2121 gfar_write(®s->igaddr5, 0xffffffff);
2122 gfar_write(®s->igaddr6, 0xffffffff);
2123 gfar_write(®s->igaddr7, 0xffffffff);
2124 gfar_write(®s->gaddr0, 0xffffffff);
2125 gfar_write(®s->gaddr1, 0xffffffff);
2126 gfar_write(®s->gaddr2, 0xffffffff);
2127 gfar_write(®s->gaddr3, 0xffffffff);
2128 gfar_write(®s->gaddr4, 0xffffffff);
2129 gfar_write(®s->gaddr5, 0xffffffff);
2130 gfar_write(®s->gaddr6, 0xffffffff);
2131 gfar_write(®s->gaddr7, 0xffffffff);
2136 /* zero out the hash */
2137 gfar_write(®s->igaddr0, 0x0);
2138 gfar_write(®s->igaddr1, 0x0);
2139 gfar_write(®s->igaddr2, 0x0);
2140 gfar_write(®s->igaddr3, 0x0);
2141 gfar_write(®s->igaddr4, 0x0);
2142 gfar_write(®s->igaddr5, 0x0);
2143 gfar_write(®s->igaddr6, 0x0);
2144 gfar_write(®s->igaddr7, 0x0);
2145 gfar_write(®s->gaddr0, 0x0);
2146 gfar_write(®s->gaddr1, 0x0);
2147 gfar_write(®s->gaddr2, 0x0);
2148 gfar_write(®s->gaddr3, 0x0);
2149 gfar_write(®s->gaddr4, 0x0);
2150 gfar_write(®s->gaddr5, 0x0);
2151 gfar_write(®s->gaddr6, 0x0);
2152 gfar_write(®s->gaddr7, 0x0);
2154 /* If we have extended hash tables, we need to
2155 * clear the exact match registers to prepare for
2157 if (priv->extended_hash) {
2158 em_num = GFAR_EM_NUM + 1;
2159 gfar_clear_exact_match(dev);
2166 if(dev->mc_count == 0)
2169 /* Parse the list, and set the appropriate bits */
2170 for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
2172 gfar_set_mac_for_addr(dev, idx,
2176 gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr);
2184 /* Clears each of the exact match registers to zero, so they
2185 * don't interfere with normal reception */
2186 static void gfar_clear_exact_match(struct net_device *dev)
2189 u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
2191 for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
2192 gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
2195 /* Set the appropriate hash bit for the given addr */
2196 /* The algorithm works like so:
2197 * 1) Take the Destination Address (ie the multicast address), and
2198 * do a CRC on it (little endian), and reverse the bits of the
2200 * 2) Use the 8 most significant bits as a hash into a 256-entry
2201 * table. The table is controlled through 8 32-bit registers:
2202 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
2203 * gaddr7. This means that the 3 most significant bits in the
2204 * hash index which gaddr register to use, and the 5 other bits
2205 * indicate which bit (assuming an IBM numbering scheme, which
2206 * for PowerPC (tm) is usually the case) in the register holds
2208 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
2211 struct gfar_private *priv = netdev_priv(dev);
2212 u32 result = ether_crc(MAC_ADDR_LEN, addr);
2213 int width = priv->hash_width;
2214 u8 whichbit = (result >> (32 - width)) & 0x1f;
2215 u8 whichreg = result >> (32 - width + 5);
2216 u32 value = (1 << (31-whichbit));
2218 tempval = gfar_read(priv->hash_regs[whichreg]);
2220 gfar_write(priv->hash_regs[whichreg], tempval);
2226 /* There are multiple MAC Address register pairs on some controllers
2227 * This function sets the numth pair to a given address
2229 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
2231 struct gfar_private *priv = netdev_priv(dev);
2233 char tmpbuf[MAC_ADDR_LEN];
2235 u32 __iomem *macptr = &priv->regs->macstnaddr1;
2239 /* Now copy it into the mac registers backwards, cuz */
2240 /* little endian is silly */
2241 for (idx = 0; idx < MAC_ADDR_LEN; idx++)
2242 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
2244 gfar_write(macptr, *((u32 *) (tmpbuf)));
2246 tempval = *((u32 *) (tmpbuf + 4));
2248 gfar_write(macptr+1, tempval);
2251 /* GFAR error interrupt handler */
2252 static irqreturn_t gfar_error(int irq, void *dev_id)
2254 struct net_device *dev = dev_id;
2255 struct gfar_private *priv = netdev_priv(dev);
2257 /* Save ievent for future reference */
2258 u32 events = gfar_read(&priv->regs->ievent);
2261 gfar_write(&priv->regs->ievent, events & IEVENT_ERR_MASK);
2263 /* Magic Packet is not an error. */
2264 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
2265 (events & IEVENT_MAG))
2266 events &= ~IEVENT_MAG;
2269 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
2270 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
2271 dev->name, events, gfar_read(&priv->regs->imask));
2273 /* Update the error counters */
2274 if (events & IEVENT_TXE) {
2275 dev->stats.tx_errors++;
2277 if (events & IEVENT_LC)
2278 dev->stats.tx_window_errors++;
2279 if (events & IEVENT_CRL)
2280 dev->stats.tx_aborted_errors++;
2281 if (events & IEVENT_XFUN) {
2282 if (netif_msg_tx_err(priv))
2283 printk(KERN_DEBUG "%s: TX FIFO underrun, "
2284 "packet dropped.\n", dev->name);
2285 dev->stats.tx_dropped++;
2286 priv->extra_stats.tx_underrun++;
2288 /* Reactivate the Tx Queues */
2289 gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
2291 if (netif_msg_tx_err(priv))
2292 printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
2294 if (events & IEVENT_BSY) {
2295 dev->stats.rx_errors++;
2296 priv->extra_stats.rx_bsy++;
2298 gfar_receive(irq, dev_id);
2300 if (netif_msg_rx_err(priv))
2301 printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
2302 dev->name, gfar_read(&priv->regs->rstat));
2304 if (events & IEVENT_BABR) {
2305 dev->stats.rx_errors++;
2306 priv->extra_stats.rx_babr++;
2308 if (netif_msg_rx_err(priv))
2309 printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
2311 if (events & IEVENT_EBERR) {
2312 priv->extra_stats.eberr++;
2313 if (netif_msg_rx_err(priv))
2314 printk(KERN_DEBUG "%s: bus error\n", dev->name);
2316 if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
2317 printk(KERN_DEBUG "%s: control frame\n", dev->name);
2319 if (events & IEVENT_BABT) {
2320 priv->extra_stats.tx_babt++;
2321 if (netif_msg_tx_err(priv))
2322 printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
2327 /* work with hotplug and coldplug */
2328 MODULE_ALIAS("platform:fsl-gianfar");
2330 static struct of_device_id gfar_match[] =
2334 .compatible = "gianfar",
2339 /* Structure for a device driver */
2340 static struct of_platform_driver gfar_driver = {
2341 .name = "fsl-gianfar",
2342 .match_table = gfar_match,
2344 .probe = gfar_probe,
2345 .remove = gfar_remove,
2346 .suspend = gfar_suspend,
2347 .resume = gfar_resume,
2350 static int __init gfar_init(void)
2352 return of_register_platform_driver(&gfar_driver);
2355 static void __exit gfar_exit(void)
2357 of_unregister_platform_driver(&gfar_driver);
2360 module_init(gfar_init);
2361 module_exit(gfar_exit);