arch/sh/kernel/cpu/sh4a/setup-sh7722.c

   1 /*
   2  * SH7722 Setup
   3  *
   4  *  Copyright (C) 2006 - 2008  Paul Mundt
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10 #include <linux/platform_device.h>
  11 #include <linux/init.h>
  12 #include <linux/serial.h>
  13 #include <linux/serial_sci.h>
  14 #include <linux/mm.h>
  15 #include <linux/uio_driver.h>
  16 #include <linux/usb/m66592.h>
  17 #include <linux/sh_timer.h>
  18 #include <asm/clock.h>
  19 #include <asm/mmzone.h>
  20 #include <cpu/sh7722.h>
  21
  22 static struct resource rtc_resources[] = {
  23         [0] = {
  24                 .start  = 0xa465fec0,
  25                 .end    = 0xa465fec0 + 0x58 - 1,
  26                 .flags  = IORESOURCE_IO,
  27         },
  28         [1] = {
  29                 /* Period IRQ */
  30                 .start  = 45,
  31                 .flags  = IORESOURCE_IRQ,
  32         },
  33         [2] = {
  34                 /* Carry IRQ */
  35                 .start  = 46,
  36                 .flags  = IORESOURCE_IRQ,
  37         },
  38         [3] = {
  39                 /* Alarm IRQ */
  40                 .start  = 44,
  41                 .flags  = IORESOURCE_IRQ,
  42         },
  43 };
  44
  45 static struct platform_device rtc_device = {
  46         .name           = "sh-rtc",
  47         .id             = -1,
  48         .num_resources  = ARRAY_SIZE(rtc_resources),
  49         .resource       = rtc_resources,
  50         .archdata = {
  51                 .hwblk_id = HWBLK_RTC,
  52         },
  53 };
  54
  55 static struct m66592_platdata usbf_platdata = {
  56         .on_chip = 1,
  57 };
  58
  59 static struct resource usbf_resources[] = {
  60         [0] = {
  61                 .name   = "USBF",
  62                 .start  = 0x04480000,
  63                 .end    = 0x044800FF,
  64                 .flags  = IORESOURCE_MEM,
  65         },
  66         [1] = {
  67                 .start  = 65,
  68                 .end    = 65,
  69                 .flags  = IORESOURCE_IRQ,
  70         },
  71 };
  72
  73 static struct platform_device usbf_device = {
  74         .name           = "m66592_udc",
  75         .id             = 0, /* "usbf0" clock */
  76         .dev = {
  77                 .dma_mask               = NULL,
  78                 .coherent_dma_mask      = 0xffffffff,
  79                 .platform_data          = &usbf_platdata,
  80         },
  81         .num_resources  = ARRAY_SIZE(usbf_resources),
  82         .resource       = usbf_resources,
  83         .archdata = {
  84                 .hwblk_id = HWBLK_USBF,
  85         },
  86 };
  87
  88 static struct resource iic_resources[] = {
  89         [0] = {
  90                 .name   = "IIC",
  91                 .start  = 0x04470000,
  92                 .end    = 0x04470017,
  93                 .flags  = IORESOURCE_MEM,
  94         },
  95         [1] = {
  96                 .start  = 96,
  97                 .end    = 99,
  98                 .flags  = IORESOURCE_IRQ,
  99        },
 100 };
 101
 102 static struct platform_device iic_device = {
 103         .name           = "i2c-sh_mobile",
 104         .id             = 0, /* "i2c0" clock */
 105         .num_resources  = ARRAY_SIZE(iic_resources),
 106         .resource       = iic_resources,
 107         .archdata = {
 108                 .hwblk_id = HWBLK_IIC,
 109         },
 110 };
 111
 112 static struct uio_info vpu_platform_data = {
 113         .name = "VPU4",
 114         .version = "0",
 115         .irq = 60,
 116 };
 117
 118 static struct resource vpu_resources[] = {
 119         [0] = {
 120                 .name   = "VPU",
 121                 .start  = 0xfe900000,
 122                 .end    = 0xfe9022eb,
 123                 .flags  = IORESOURCE_MEM,
 124         },
 125         [1] = {
 126                 /* place holder for contiguous memory */
 127         },
 128 };
 129
 130 static struct platform_device vpu_device = {
 131         .name           = "uio_pdrv_genirq",
 132         .id             = 0,
 133         .dev = {
 134                 .platform_data  = &vpu_platform_data,
 135         },
 136         .resource       = vpu_resources,
 137         .num_resources  = ARRAY_SIZE(vpu_resources),
 138         .archdata = {
 139                 .hwblk_id = HWBLK_VPU,
 140         },
 141 };
 142
 143 static struct uio_info veu_platform_data = {
 144         .name = "VEU",
 145         .version = "0",
 146         .irq = 54,
 147 };
 148
 149 static struct resource veu_resources[] = {
 150         [0] = {
 151                 .name   = "VEU",
 152                 .start  = 0xfe920000,
 153                 .end    = 0xfe9200b7,
 154                 .flags  = IORESOURCE_MEM,
 155         },
 156         [1] = {
 157                 /* place holder for contiguous memory */
 158         },
 159 };
 160
 161 static struct platform_device veu_device = {
 162         .name           = "uio_pdrv_genirq",
 163         .id             = 1,
 164         .dev = {
 165                 .platform_data  = &veu_platform_data,
 166         },
 167         .resource       = veu_resources,
 168         .num_resources  = ARRAY_SIZE(veu_resources),
 169         .archdata = {
 170                 .hwblk_id = HWBLK_VEU,
 171         },
 172 };
 173
 174 static struct uio_info jpu_platform_data = {
 175         .name = "JPU",
 176         .version = "0",
 177         .irq = 27,
 178 };
 179
 180 static struct resource jpu_resources[] = {
 181         [0] = {
 182                 .name   = "JPU",
 183                 .start  = 0xfea00000,
 184                 .end    = 0xfea102d3,
 185                 .flags  = IORESOURCE_MEM,
 186         },
 187         [1] = {
 188                 /* place holder for contiguous memory */
 189         },
 190 };
 191
 192 static struct platform_device jpu_device = {
 193         .name           = "uio_pdrv_genirq",
 194         .id             = 2,
 195         .dev = {
 196                 .platform_data  = &jpu_platform_data,
 197         },
 198         .resource       = jpu_resources,
 199         .num_resources  = ARRAY_SIZE(jpu_resources),
 200         .archdata = {
 201                 .hwblk_id = HWBLK_JPU,
 202         },
 203 };
 204
 205 static struct sh_timer_config cmt_platform_data = {
 206         .name = "CMT",
 207         .channel_offset = 0x60,
 208         .timer_bit = 5,
 209         .clk = "cmt0",
 210         .clockevent_rating = 125,
 211         .clocksource_rating = 125,
 212 };
 213
 214 static struct resource cmt_resources[] = {
 215         [0] = {
 216                 .name   = "CMT",
 217                 .start  = 0x044a0060,
 218                 .end    = 0x044a006b,
 219                 .flags  = IORESOURCE_MEM,
 220         },
 221         [1] = {
 222                 .start  = 104,
 223                 .flags  = IORESOURCE_IRQ,
 224         },
 225 };
 226
 227 static struct platform_device cmt_device = {
 228         .name           = "sh_cmt",
 229         .id             = 0,
 230         .dev = {
 231                 .platform_data  = &cmt_platform_data,
 232         },
 233         .resource       = cmt_resources,
 234         .num_resources  = ARRAY_SIZE(cmt_resources),
 235         .archdata = {
 236                 .hwblk_id = HWBLK_CMT,
 237         },
 238 };
 239
 240 static struct sh_timer_config tmu0_platform_data = {
 241         .name = "TMU0",
 242         .channel_offset = 0x04,
 243         .timer_bit = 0,
 244         .clk = "tmu0",
 245         .clockevent_rating = 200,
 246 };
 247
 248 static struct resource tmu0_resources[] = {
 249         [0] = {
 250                 .name   = "TMU0",
 251                 .start  = 0xffd80008,
 252                 .end    = 0xffd80013,
 253                 .flags  = IORESOURCE_MEM,
 254         },
 255         [1] = {
 256                 .start  = 16,
 257                 .flags  = IORESOURCE_IRQ,
 258         },
 259 };
 260
 261 static struct platform_device tmu0_device = {
 262         .name           = "sh_tmu",
 263         .id             = 0,
 264         .dev = {
 265                 .platform_data  = &tmu0_platform_data,
 266         },
 267         .resource       = tmu0_resources,
 268         .num_resources  = ARRAY_SIZE(tmu0_resources),
 269         .archdata = {
 270                 .hwblk_id = HWBLK_TMU,
 271         },
 272 };
 273
 274 static struct sh_timer_config tmu1_platform_data = {
 275         .name = "TMU1",
 276         .channel_offset = 0x10,
 277         .timer_bit = 1,
 278         .clk = "tmu0",
 279         .clocksource_rating = 200,
 280 };
 281
 282 static struct resource tmu1_resources[] = {
 283         [0] = {
 284                 .name   = "TMU1",
 285                 .start  = 0xffd80014,
 286                 .end    = 0xffd8001f,
 287                 .flags  = IORESOURCE_MEM,
 288         },
 289         [1] = {
 290                 .start  = 17,
 291                 .flags  = IORESOURCE_IRQ,
 292         },
 293 };
 294
 295 static struct platform_device tmu1_device = {
 296         .name           = "sh_tmu",
 297         .id             = 1,
 298         .dev = {
 299                 .platform_data  = &tmu1_platform_data,
 300         },
 301         .resource       = tmu1_resources,
 302         .num_resources  = ARRAY_SIZE(tmu1_resources),
 303         .archdata = {
 304                 .hwblk_id = HWBLK_TMU,
 305         },
 306 };
 307
 308 static struct sh_timer_config tmu2_platform_data = {
 309         .name = "TMU2",
 310         .channel_offset = 0x1c,
 311         .timer_bit = 2,
 312         .clk = "tmu0",
 313 };
 314
 315 static struct resource tmu2_resources[] = {
 316         [0] = {
 317                 .name   = "TMU2",
 318                 .start  = 0xffd80020,
 319                 .end    = 0xffd8002b,
 320                 .flags  = IORESOURCE_MEM,
 321         },
 322         [1] = {
 323                 .start  = 18,
 324                 .flags  = IORESOURCE_IRQ,
 325         },
 326 };
 327
 328 static struct platform_device tmu2_device = {
 329         .name           = "sh_tmu",
 330         .id             = 2,
 331         .dev = {
 332                 .platform_data  = &tmu2_platform_data,
 333         },
 334         .resource       = tmu2_resources,
 335         .num_resources  = ARRAY_SIZE(tmu2_resources),
 336         .archdata = {
 337                 .hwblk_id = HWBLK_TMU,
 338         },
 339 };
 340
 341 static struct plat_sci_port sci_platform_data[] = {
 342         {
 343                 .mapbase        = 0xffe00000,
 344                 .flags          = UPF_BOOT_AUTOCONF,
 345                 .type           = PORT_SCIF,
 346                 .irqs           = { 80, 80, 80, 80 },
 347                 .clk            = "scif0",
 348         },
 349         {
 350                 .mapbase        = 0xffe10000,
 351                 .flags          = UPF_BOOT_AUTOCONF,
 352                 .type           = PORT_SCIF,
 353                 .irqs           = { 81, 81, 81, 81 },
 354                 .clk            = "scif1",
 355         },
 356         {
 357                 .mapbase        = 0xffe20000,
 358                 .flags          = UPF_BOOT_AUTOCONF,
 359                 .type           = PORT_SCIF,
 360                 .irqs           = { 82, 82, 82, 82 },
 361                 .clk            = "scif2",
 362         },
 363         {
 364                 .flags = 0,
 365         }
 366 };
 367
 368 static struct platform_device sci_device = {
 369         .name           = "sh-sci",
 370         .id             = -1,
 371         .dev            = {
 372                 .platform_data  = sci_platform_data,
 373         },
 374 };
 375
 376 static struct platform_device *sh7722_devices[] __initdata = {
 377         &cmt_device,
 378         &tmu0_device,
 379         &tmu1_device,
 380         &tmu2_device,
 381         &rtc_device,
 382         &usbf_device,
 383         &iic_device,
 384         &sci_device,
 385         &vpu_device,
 386         &veu_device,
 387         &jpu_device,
 388 };
 389
 390 static int __init sh7722_devices_setup(void)
 391 {
 392         platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20);
 393         platform_resource_setup_memory(&veu_device, "veu", 2 << 20);
 394         platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20);
 395
 396         return platform_add_devices(sh7722_devices,
 397                                     ARRAY_SIZE(sh7722_devices));
 398 }
 399 arch_initcall(sh7722_devices_setup);
 400
 401 static struct platform_device *sh7722_early_devices[] __initdata = {
 402         &cmt_device,
 403         &tmu0_device,
 404         &tmu1_device,
 405         &tmu2_device,
 406 };
 407
 408 void __init plat_early_device_setup(void)
 409 {
 410         early_platform_add_devices(sh7722_early_devices,
 411                                    ARRAY_SIZE(sh7722_early_devices));
 412 }
 413
 414 enum {
 415         UNUSED=0,
 416
 417         /* interrupt sources */
 418         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
 419         HUDI,
 420         SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
 421         RTC_ATI, RTC_PRI, RTC_CUI,
 422         DMAC0, DMAC1, DMAC2, DMAC3,
 423         VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU,
 424         VPU, TPU,
 425         USB_USBI0, USB_USBI1,
 426         DMAC4, DMAC5, DMAC_DADERR,
 427         KEYSC,
 428         SCIF0, SCIF1, SCIF2, SIOF0, SIOF1, SIO,
 429         FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
 430         I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI,
 431         SDHI0, SDHI1, SDHI2, SDHI3,
 432         CMT, TSIF, SIU, TWODG,
 433         TMU0, TMU1, TMU2,
 434         IRDA, JPU, LCDC,
 435
 436         /* interrupt groups */
 437         SIM, RTC, DMAC0123, VIOVOU, USB, DMAC45, FLCTL, I2C, SDHI,
 438 };
 439
 440 static struct intc_vect vectors[] __initdata = {
 441         INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
 442         INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
 443         INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
 444         INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
 445         INTC_VECT(SIM_ERI, 0x700), INTC_VECT(SIM_RXI, 0x720),
 446         INTC_VECT(SIM_TXI, 0x740), INTC_VECT(SIM_TEI, 0x760),
 447         INTC_VECT(RTC_ATI, 0x780), INTC_VECT(RTC_PRI, 0x7a0),
 448         INTC_VECT(RTC_CUI, 0x7c0),
 449         INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
 450         INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860),
 451         INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0),
 452         INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0),
 453         INTC_VECT(VPU, 0x980), INTC_VECT(TPU, 0x9a0),
 454         INTC_VECT(USB_USBI0, 0xa20), INTC_VECT(USB_USBI1, 0xa40),
 455         INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0),
 456         INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0),
 457         INTC_VECT(SCIF0, 0xc00), INTC_VECT(SCIF1, 0xc20),
 458         INTC_VECT(SCIF2, 0xc40), INTC_VECT(SIOF0, 0xc80),
 459         INTC_VECT(SIOF1, 0xca0), INTC_VECT(SIO, 0xd00),
 460         INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0),
 461         INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
 462         INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20),
 463         INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60),
 464         INTC_VECT(SDHI0, 0xe80), INTC_VECT(SDHI1, 0xea0),
 465         INTC_VECT(SDHI2, 0xec0), INTC_VECT(SDHI3, 0xee0),
 466         INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
 467         INTC_VECT(SIU, 0xf80), INTC_VECT(TWODG, 0xfa0),
 468         INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
 469         INTC_VECT(TMU2, 0x440), INTC_VECT(IRDA, 0x480),
 470         INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),
 471 };
 472
 473 static struct intc_group groups[] __initdata = {
 474         INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI),
 475         INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
 476         INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
 477         INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU),
 478         INTC_GROUP(USB, USB_USBI0, USB_USBI1),
 479         INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR),
 480         INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
 481                    FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
 482         INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI),
 483         INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2, SDHI3),
 484 };
 485
 486 static struct intc_mask_reg mask_registers[] __initdata = {
 487         { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
 488           { } },
 489         { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
 490           { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } },
 491         { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
 492           { 0, 0, 0, VPU, } },
 493         { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
 494           { SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } },
 495         { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
 496           { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },
 497         { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
 498           { KEYSC, DMAC_DADERR, DMAC5, DMAC4, 0, SCIF2, SCIF1, SCIF0 } },
 499         { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
 500           { 0, 0, 0, SIO, 0, 0, SIOF1, SIOF0 } },
 501         { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
 502           { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
 503             FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
 504         { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
 505           { SDHI3, SDHI2, SDHI1, SDHI0, 0, 0, TWODG, SIU } },
 506         { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
 507           { 0, 0, 0, CMT, 0, USB_USBI1, USB_USBI0, } },
 508         { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
 509           { } },
 510         { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
 511           { 0, RTC_CUI, RTC_PRI, RTC_ATI, 0, TPU, 0, TSIF } },
 512         { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
 513           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 514 };
 515
 516 static struct intc_prio_reg prio_registers[] __initdata = {
 517         { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, IRDA } },
 518         { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
 519         { 0xa4080008, 0, 16, 4, /* IPRC */ { } },
 520         { 0xa408000c, 0, 16, 4, /* IPRD */ { } },
 521         { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, 0, VPU } },
 522         { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } },
 523         { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, SCIF2 } },
 524         { 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C } },
 525         { 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, RTC } },
 526         { 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } },
 527         { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, 0, 0, SDHI } },
 528         { 0xa408002c, 0, 16, 4, /* IPRL */ { TWODG, 0, TPU } },
 529         { 0xa4140010, 0, 32, 4, /* INTPRI00 */
 530           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 531 };
 532
 533 static struct intc_sense_reg sense_registers[] __initdata = {
 534         { 0xa414001c, 16, 2, /* ICR1 */
 535           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 536 };
 537
 538 static struct intc_mask_reg ack_registers[] __initdata = {
 539         { 0xa4140024, 0, 8, /* INTREQ00 */
 540           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 541 };
 542
 543 static DECLARE_INTC_DESC_ACK(intc_desc, "sh7722", vectors, groups,
 544                              mask_registers, prio_registers, sense_registers,
 545                              ack_registers);
 546
 547 void __init plat_irq_setup(void)
 548 {
 549         register_intc_controller(&intc_desc);
 550 }
 551
 552 void __init plat_mem_setup(void)
 553 {
 554         /* Register the URAM space as Node 1 */
 555         setup_bootmem_node(1, 0x055f0000, 0x05610000);
 556 }