arm64: dts: renesas: r8a77990: Add OPPs table for cpu devices

This patch define OOP tables for all CPUs.
This allows CPUFreq to function.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Tested-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
index 786178cf1ffd1304c1e5faa4ad0c24fd757b14e1..b42b9c7609082da6c9f5e8358835ad6d6f17aa42 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
@@ -55,6 +55,27 @@
                clock-frequency = <0>;
        };
 
+       cluster1_opp: opp_table10 {
+               compatible = "operating-points-v2";
+               opp-shared;
+               opp-800000000 {
+                       opp-hz = /bits/ 64 <800000000>;
+                       opp-microvolt = <820000>;
+                       clock-latency-ns = <300000>;
+               };
+               opp-1000000000 {
+                       opp-hz = /bits/ 64 <1000000000>;
+                       opp-microvolt = <820000>;
+                       clock-latency-ns = <300000>;
+               };
+               opp-1200000000 {
+                       opp-hz = /bits/ 64 <1200000000>;
+                       opp-microvolt = <820000>;
+                       clock-latency-ns = <300000>;
+                       opp-suspend;
+               };
+       };
+
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
@@ -66,6 +87,8 @@
                        power-domains = <&sysc R8A77990_PD_CA53_CPU0>;
                        next-level-cache = <&L2_CA53>;
                        enable-method = "psci";
+                       clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>;
+                       operating-points-v2 = <&cluster1_opp>;
                };
 
                a53_1: cpu@1 {
@@ -75,6 +98,8 @@
                        power-domains = <&sysc R8A77990_PD_CA53_CPU1>;
                        next-level-cache = <&L2_CA53>;
                        enable-method = "psci";
+                       clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>;
+                       operating-points-v2 = <&cluster1_opp>;
                };
 
                L2_CA53: cache-controller-0 {