clocksource/drivers/arc_timer: Update some comments

TIMER0 interrupt ACK is different for ARC700 and HS3x cores.

This came to light in some internal discussions and it is nice to have this
documented rather than digging up the PRM (Programmers Reference Manual).

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Vineet Gupta <Vineet.Gupta1@synopsys.com>
Cc: linux-snps-arc@lists.infradead.org
Link: https://lkml.kernel.org/r/1519241491-12570-1-git-send-email-vgupta@synopsys.com

diff --git a/drivers/clocksource/arc_timer.c b/drivers/clocksource/arc_timer.c
index 4927355f9cbe51e086db1a144190c0bda1944733..471b428d8034ce5af3e2fc8993fca63df27b68f9 100644 (file)
--- a/drivers/clocksource/arc_timer.c
+++ b/drivers/clocksource/arc_timer.c
@@ -251,9 +251,14 @@ static irqreturn_t timer_irq_handler(int irq, void *dev_id)
        int irq_reenable = clockevent_state_periodic(evt);
 
        /*
-        * Any write to CTRL reg ACks the interrupt, we rewrite the
-        * Count when [N]ot [H]alted bit.
-        * And re-arm it if perioid by [I]nterrupt [E]nable bit
+        * 1. ACK the interrupt
+        *    - For ARC700, any write to CTRL reg ACKs it, so just rewrite
+        *      Count when [N]ot [H]alted bit.
+        *    - For HS3x, it is a bit subtle. On taken count-down interrupt,
+        *      IP bit [3] is set, which needs to be cleared for ACK'ing.
+        *      The write below can only update the other two bits, hence
+        *      explicitly clears IP bit
+        * 2. Re-arm interrupt if periodic by writing to IE bit [0]
         */
        write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | TIMER_CTRL_NH);