Revert "drm/amd/display: enable S/G for RAVEN chip"
authorAlex Deucher <alexander.deucher@amd.com>
Fri, 15 Nov 2019 15:26:52 +0000 (10:26 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 20 Nov 2019 23:40:21 +0000 (18:40 -0500)
This reverts commit 1c4259159132ae4ceaf7c6db37a6cf76417f73d9.

S/G display is not stable with the IOMMU enabled on some
platforms.

Bug: https://bugzilla.kernel.org/show_bug.cgi?id=205523
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

index 1d4aaa9580f4b50ec4ffb8d86ea082f313b29877..82efc1e22e6113878d9b3e0edfc3bcd86b593483 100644 (file)
@@ -511,7 +511,7 @@ uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev,
         * Also, don't allow GTT domain if the BO doens't have USWC falg set.
         */
        if (adev->asic_type >= CHIP_CARRIZO &&
-           adev->asic_type <= CHIP_RAVEN &&
+           adev->asic_type < CHIP_RAVEN &&
            (adev->flags & AMD_IS_APU) &&
            (bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) &&
            amdgpu_bo_support_uswc(bo_flags) &&
index a52f0b13a2c8a1e6ea8f6682fffc74a2bb114319..4139f129eafb4062a66f743dc536e89a9daa6c6e 100644 (file)
@@ -688,7 +688,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
         */
        if (adev->flags & AMD_IS_APU &&
            adev->asic_type >= CHIP_CARRIZO &&
-           adev->asic_type <= CHIP_RAVEN)
+           adev->asic_type < CHIP_RAVEN)
                init_data.flags.gpu_vm_support = true;
 
        if (amdgpu_dc_feature_mask & DC_FBC_MASK)