drm/amdgpu/powerplay: split out common smu7 BACO code
authorAlex Deucher <alexander.deucher@amd.com>
Fri, 15 Feb 2019 22:39:33 +0000 (17:39 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 15 Oct 2019 19:55:31 +0000 (15:55 -0400)
Several of the BACO functions are common across smu7-based
asics.  Split the common code out.

Reviewed-by: Evan Quan <evan.quan@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.c
drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.h
drivers/gpu/drm/amd/powerplay/hwmgr/fiji_baco.c
drivers/gpu/drm/amd/powerplay/hwmgr/fiji_baco.h
drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.c
drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.h
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_baco.c [new file with mode: 0644]
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_baco.h [new file with mode: 0644]
drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.c
drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.h

index 5ad5893bdae17251aa82a4f64ae10a8b3f253417..2773966ae4342e90bf84a5b371b5812c2922e03e 100644 (file)
@@ -37,7 +37,7 @@ HARDWARE_MGR = hwmgr.o processpptables.o \
                vega20_processpptables.o vega20_hwmgr.o vega20_powertune.o \
                vega20_thermal.o common_baco.o vega10_baco.o  vega20_baco.o \
                vega12_baco.o smu9_baco.o tonga_baco.o polaris_baco.o fiji_baco.o \
-               ci_baco.o
+               ci_baco.o smu7_baco.o
 
 AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR))
 
index f1a8c9cc0d1f4a7ead338624d7dcf5a28eb851d8..3be40114e63d2e274ac17006961570becaa1cd78 100644 (file)
@@ -158,43 +158,11 @@ static const struct baco_cmd_entry clean_baco_tbl[] =
        { CMD_WRITE, mmCP_PFP_UCODE_ADDR, 0, 0, 0, 0 }
 };
 
-int ci_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap)
-{
-       struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
-       uint32_t reg;
-
-       *cap = false;
-       if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO))
-               return 0;
-
-       reg = RREG32(mmCC_BIF_BX_FUSESTRAP0);
-
-       if (reg & CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK)
-               *cap = true;
-
-       return 0;
-}
-
-int ci_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state)
-{
-       struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
-       uint32_t reg;
-
-       reg = RREG32(mmBACO_CNTL);
-
-       if (reg & BACO_CNTL__BACO_MODE_MASK)
-               /* gfx has already entered BACO state */
-               *state = BACO_STATE_IN;
-       else
-               *state = BACO_STATE_OUT;
-       return 0;
-}
-
 int ci_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
 {
        enum BACO_STATE cur_state;
 
-       ci_baco_get_state(hwmgr, &cur_state);
+       smu7_baco_get_state(hwmgr, &cur_state);
 
        if (cur_state == state)
                /* aisc already in the target state */
index c9bedb51cb256b1c69408167d658ece4a04f231e..17041f187020b2f6e083d44dea939562eb8c0b0f 100644 (file)
  */
 #ifndef __CI_BACO_H__
 #define __CI_BACO_H__
-#include "hwmgr.h"
-#include "common_baco.h"
+#include "smu7_baco.h"
 
-extern int ci_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap);
-extern int ci_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state);
 extern int ci_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state);
 
 #endif
index ad01919ccb276c31facc43ec7f7cc29ae21e853f..c0368f2dfb218271aee4a89723ad87b74b2f8467 100644 (file)
@@ -158,43 +158,11 @@ static const struct baco_cmd_entry clean_baco_tbl[] =
        { CMD_WRITE, mmBIOS_SCRATCH_15, 0, 0, 0, 0 }
 };
 
-int fiji_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap)
-{
-       struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
-       uint32_t reg;
-
-       *cap = false;
-       if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO))
-               return 0;
-
-       reg = RREG32(mmCC_BIF_BX_FUSESTRAP0);
-
-       if (reg & CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK)
-               *cap = true;
-
-       return 0;
-}
-
-int fiji_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state)
-{
-       struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
-       uint32_t reg;
-
-       reg = RREG32(mmBACO_CNTL);
-
-       if (reg & BACO_CNTL__BACO_MODE_MASK)
-               /* gfx has already entered BACO state */
-               *state = BACO_STATE_IN;
-       else
-               *state = BACO_STATE_OUT;
-       return 0;
-}
-
 int fiji_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
 {
        enum BACO_STATE cur_state;
 
-       fiji_baco_get_state(hwmgr, &cur_state);
+       smu7_baco_get_state(hwmgr, &cur_state);
 
        if (cur_state == state)
                /* aisc already in the target state */
index 2f7c8388667ed3b0584158ca7621726543187402..47f402900bdb033216e5704883fbfd85013b7a85 100644 (file)
  */
 #ifndef __FIJI_BACO_H__
 #define __FIJI_BACO_H__
-#include "hwmgr.h"
-#include "common_baco.h"
+#include "smu7_baco.h"
 
-extern int fiji_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap);
-extern int fiji_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state);
 extern int fiji_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state);
 
 #endif
index a9abe53df475a5c10a8713983af740fbd95ec41a..8f8e296f2fe9ec1b33acaf77aa776832f4850526 100644 (file)
@@ -178,43 +178,11 @@ static const struct baco_cmd_entry turn_off_plls_tbl_vg[] =
        { CMD_DELAY_US, 0, 0, 0, 5, 0x0 }
 };
 
-int polaris_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap)
-{
-       struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
-       uint32_t reg;
-
-       *cap = false;
-       if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO))
-               return 0;
-
-       reg = RREG32(mmCC_BIF_BX_FUSESTRAP0);
-
-       if (reg & CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK)
-               *cap = true;
-
-       return 0;
-}
-
-int polaris_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state)
-{
-       struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
-       uint32_t reg;
-
-       reg = RREG32(mmBACO_CNTL);
-
-       if (reg & BACO_CNTL__BACO_MODE_MASK)
-               /* gfx has already entered BACO state */
-               *state = BACO_STATE_IN;
-       else
-               *state = BACO_STATE_OUT;
-       return 0;
-}
-
 int polaris_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
 {
        enum BACO_STATE cur_state;
 
-       polaris_baco_get_state(hwmgr, &cur_state);
+       smu7_baco_get_state(hwmgr, &cur_state);
 
        if (cur_state == state)
                /* aisc already in the target state */
index e48bfb1c5c6ac3d1f93754de6cec94b1adbe5abf..87a5fa0a157a7c2f51301dcdd025e23668b41bfb 100644 (file)
  */
 #ifndef __POLARIS_BACO_H__
 #define __POLARIS_BACO_H__
-#include "hwmgr.h"
-#include "common_baco.h"
+#include "smu7_baco.h"
 
-extern int polaris_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap);
-extern int polaris_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state);
 extern int polaris_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state);
 
 #endif
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_baco.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_baco.c
new file mode 100644 (file)
index 0000000..044cda0
--- /dev/null
@@ -0,0 +1,91 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#include "amdgpu.h"
+#include "smu7_baco.h"
+#include "tonga_baco.h"
+#include "fiji_baco.h"
+#include "polaris_baco.h"
+#include "ci_baco.h"
+
+#include "bif/bif_5_0_d.h"
+#include "bif/bif_5_0_sh_mask.h"
+
+#include "smu/smu_7_1_2_d.h"
+#include "smu/smu_7_1_2_sh_mask.h"
+
+int smu7_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap)
+{
+       struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
+       uint32_t reg;
+
+       *cap = false;
+       if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO))
+               return 0;
+
+       reg = RREG32(mmCC_BIF_BX_FUSESTRAP0);
+
+       if (reg & CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK)
+               *cap = true;
+
+       return 0;
+}
+
+int smu7_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state)
+{
+       struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
+       uint32_t reg;
+
+       reg = RREG32(mmBACO_CNTL);
+
+       if (reg & BACO_CNTL__BACO_MODE_MASK)
+               /* gfx has already entered BACO state */
+               *state = BACO_STATE_IN;
+       else
+               *state = BACO_STATE_OUT;
+       return 0;
+}
+
+int smu7_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
+{
+       struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
+
+       switch (adev->asic_type) {
+       case CHIP_TOPAZ:
+       case CHIP_TONGA:
+               return tonga_baco_set_state(hwmgr, state);
+       case CHIP_FIJI:
+               return fiji_baco_set_state(hwmgr, state);
+       case CHIP_POLARIS10:
+       case CHIP_POLARIS11:
+       case CHIP_POLARIS12:
+       case CHIP_VEGAM:
+               return polaris_baco_set_state(hwmgr, state);
+#ifdef CONFIG_DRM_AMDGPU_CIK
+       case CHIP_BONAIRE:
+       case CHIP_HAWAII:
+               return ci_baco_set_state(hwmgr, state);
+#endif
+       default:
+               return -EINVAL;
+       }
+}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_baco.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_baco.h
new file mode 100644 (file)
index 0000000..be0d98a
--- /dev/null
@@ -0,0 +1,32 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef __SMU7_BACO_H__
+#define __SMU7_BACO_H__
+#include "hwmgr.h"
+#include "common_baco.h"
+
+extern int smu7_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap);
+extern int smu7_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state);
+extern int smu7_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state);
+
+#endif
index 84b7217b7bdae8a1a6fe7a806aa9ebfef9d9ae88..ea743bea8e29de5539b6f863015c64eb842a0092 100644 (file)
@@ -182,43 +182,11 @@ static const struct baco_cmd_entry clean_baco_tbl_iceland[] =
        { CMD_WRITE, mmBIOS_SCRATCH_7, 0, 0, 0, 0 }
 };
 
-int tonga_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap)
-{
-       struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
-       uint32_t reg;
-
-       *cap = false;
-       if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO))
-               return 0;
-
-       reg = RREG32(mmCC_BIF_BX_FUSESTRAP0);
-
-       if (reg & CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK)
-               *cap = true;
-
-       return 0;
-}
-
-int tonga_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state)
-{
-       struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
-       uint32_t reg;
-
-       reg = RREG32(mmBACO_CNTL);
-
-       if (reg & BACO_CNTL__BACO_MODE_MASK)
-               /* gfx has already entered BACO state */
-               *state = BACO_STATE_IN;
-       else
-               *state = BACO_STATE_OUT;
-       return 0;
-}
-
 int tonga_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
 {
        enum BACO_STATE cur_state;
 
-       tonga_baco_get_state(hwmgr, &cur_state);
+       smu7_baco_get_state(hwmgr, &cur_state);
 
        if (cur_state == state)
                /* aisc already in the target state */
index 21301b04325598674614cacbc1c49d273438b939..5dc16cc8a2956a24dea545979578df16d14c734f 100644 (file)
  */
 #ifndef __TONGA_BACO_H__
 #define __TONGA_BACO_H__
-#include "hwmgr.h"
-#include "common_baco.h"
+#include "smu7_baco.h"
 
-extern int tonga_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap);
-extern int tonga_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state);
 extern int tonga_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state);
 
 #endif