clk: renesas: r8a77990: Correct parent clock of DU

According to the R-Car Gen3 Hardware Manual Rev 1.00, the parent clock
of the DU module clocks on R-Car E3 is S1D1.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Fixes: 3570a2af473789c5 ("clk: renesas: cpg-mssr: Add support for R-Car E3")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c
index 9eb80180eea0b1a627ace5e586656f53a26a6472..9a278c75c918cfa8cc095163510b407883b919d0 100644 (file)
--- a/drivers/clk/renesas/r8a77990-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c
@@ -183,8 +183,8 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = {
        DEF_MOD("ehci0",                 703,   R8A77990_CLK_S3D4),
        DEF_MOD("hsusb",                 704,   R8A77990_CLK_S3D4),
        DEF_MOD("csi40",                 716,   R8A77990_CLK_CSI0),
-       DEF_MOD("du1",                   723,   R8A77990_CLK_S2D1),
-       DEF_MOD("du0",                   724,   R8A77990_CLK_S2D1),
+       DEF_MOD("du1",                   723,   R8A77990_CLK_S1D1),
+       DEF_MOD("du0",                   724,   R8A77990_CLK_S1D1),
        DEF_MOD("lvds",                  727,   R8A77990_CLK_S2D1),
 
        DEF_MOD("vin5",                  806,   R8A77990_CLK_S1D2),