ARM64: dts: hisilicon: Add all CPUs in cooling maps

Each CPU can (and does) participate in cooling down the system but the
DT only captures a handful of them, normally CPU0, in the cooling maps.
Things work by chance currently as under normal circumstances its the
first CPU of each cluster which is used by the operating systems to
probe the cooling devices. But as soon as this CPU ordering changes and
any other CPU is used to bring up the cooling device, we will start
seeing failures.

Also the DT is rather incomplete when we list only one CPU in the
cooling maps, as the hardware doesn't have any such limitations.

Update cooling maps to include all devices affected by individual trip
points.

Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>

diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
index d943a96eedee2ae654eafddc99a6d505995fda54..20ae40df61d5098c1ed94826a41d0e6d070bb0f6 100644 (file)
--- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
@@ -1118,12 +1118,18 @@
                                        map0 {
                                                trip = <&target>;
                                                contribution = <1024>;
-                                               cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+                                               cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                                                <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                                                <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                                                <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
                                        };
                                        map1 {
                                                trip = <&target>;
                                                contribution = <512>;
-                                               cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+                                               cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                                                <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                                                <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                                                <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
                                        };
                                };
                        };

diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
index 97d5bf2c6ec587273dc11a3bb4ef0683378096d3..aec9e371c2a7b3072be0319ce669a563e075f912 100644 (file)
--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -893,7 +893,14 @@
                                cooling-maps {
                                        map0 {
                                                trip = <&target>;
-                                               cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+                                               cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                                                <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                                                <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                                                <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                                                <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                                                <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                                                <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                                                <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
                                        };
                                };
                        };