Revert "drm/amd/display: enable S/G for RAVEN chip"
authorAlex Deucher <alexander.deucher@amd.com>
Fri, 15 Nov 2019 15:26:52 +0000 (10:26 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 22 Nov 2019 19:35:11 +0000 (14:35 -0500)
This reverts commit 1c4259159132ae4ceaf7c6db37a6cf76417f73d9.

S/G display is not stable with the IOMMU enabled on some
platforms.

Bug: https://bugzilla.kernel.org/show_bug.cgi?id=205523
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

index d2dd59a95e8a360fe7e9596d6248b481ffd4b81a..3cadb0b76f221c026611a89c605944afeb6205cb 100644 (file)
@@ -514,7 +514,7 @@ uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev,
         * Also, don't allow GTT domain if the BO doens't have USWC falg set.
         */
        if (adev->asic_type >= CHIP_CARRIZO &&
-           adev->asic_type <= CHIP_RAVEN &&
+           adev->asic_type < CHIP_RAVEN &&
            (adev->flags & AMD_IS_APU) &&
            (bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) &&
            amdgpu_bo_support_uswc(bo_flags) &&
index caba9ecac723528241bac5df9e83123031ea170f..7aac9568d3bec2a95e5ef422a567a27f970ab83d 100644 (file)
@@ -719,7 +719,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
         */
        if (adev->flags & AMD_IS_APU &&
            adev->asic_type >= CHIP_CARRIZO &&
-           adev->asic_type <= CHIP_RAVEN)
+           adev->asic_type < CHIP_RAVEN)
                init_data.flags.gpu_vm_support = true;
 
        if (amdgpu_dc_feature_mask & DC_FBC_MASK)