clk: renesas: rcar-gen3: Rename DRIF clocks

According to the R-Car Gen3 Hardware Manual Errata for Rev. 1.50 of Feb
12, 2019, the DRIF clocks have been renamed as follows:

    DRIF0 to DRIF00
    DRIF1 to DRIF01
    DRIF2 to DRIF10
    DRIF3 to DRIF11
    DRIF4 to DRIF20
    DRIF5 to DRIF21
    DRIF6 to DRIF30
    DRIF7 to DRIF31

Therefore, this patch renames the DRIF clocks from DRIFn to DRIFmm.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>

diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c
index e5fa9f6c1ec4b9cb052c065ad8ffcc3349da932f..9e9a6f2c31e808eb25cfeb800bc5772978deb2bb 100644 (file)
--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
@@ -3,7 +3,7 @@
  * r8a7795 Clock Pulse Generator / Module Standby and Software Reset
  *
  * Copyright (C) 2015 Glider bvba
- * Copyright (C) 2018 Renesas Electronics Corp.
+ * Copyright (C) 2018-2019 Renesas Electronics Corp.
  *
  * Based on clk-rcar-gen3.c
  *
@@ -156,14 +156,14 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {
        DEF_MOD("intc-ap",               408,   R8A7795_CLK_S0D3),
        DEF_MOD("audmac1",               501,   R8A7795_CLK_S1D2),
        DEF_MOD("audmac0",               502,   R8A7795_CLK_S1D2),
-       DEF_MOD("drif7",                 508,   R8A7795_CLK_S3D2),
-       DEF_MOD("drif6",                 509,   R8A7795_CLK_S3D2),
-       DEF_MOD("drif5",                 510,   R8A7795_CLK_S3D2),
-       DEF_MOD("drif4",                 511,   R8A7795_CLK_S3D2),
-       DEF_MOD("drif3",                 512,   R8A7795_CLK_S3D2),
-       DEF_MOD("drif2",                 513,   R8A7795_CLK_S3D2),
-       DEF_MOD("drif1",                 514,   R8A7795_CLK_S3D2),
-       DEF_MOD("drif0",                 515,   R8A7795_CLK_S3D2),
+       DEF_MOD("drif31",                508,   R8A7795_CLK_S3D2),
+       DEF_MOD("drif30",                509,   R8A7795_CLK_S3D2),
+       DEF_MOD("drif21",                510,   R8A7795_CLK_S3D2),
+       DEF_MOD("drif20",                511,   R8A7795_CLK_S3D2),
+       DEF_MOD("drif11",                512,   R8A7795_CLK_S3D2),
+       DEF_MOD("drif10",                513,   R8A7795_CLK_S3D2),
+       DEF_MOD("drif01",                514,   R8A7795_CLK_S3D2),
+       DEF_MOD("drif00",                515,   R8A7795_CLK_S3D2),
        DEF_MOD("hscif4",                516,   R8A7795_CLK_S3D1),
        DEF_MOD("hscif3",                517,   R8A7795_CLK_S3D1),
        DEF_MOD("hscif2",                518,   R8A7795_CLK_S3D1),

diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c
index 73c69152c77b02ed0d431c3695a5eb713c978ef8..d8e9af5d9ae9cf6e12b282eb9a10f3f169b4d07e 100644 (file)
--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
@@ -149,14 +149,14 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
        DEF_MOD("intc-ap",               408,   R8A7796_CLK_S0D3),
        DEF_MOD("audmac1",               501,   R8A7796_CLK_S1D2),
        DEF_MOD("audmac0",               502,   R8A7796_CLK_S1D2),
-       DEF_MOD("drif7",                 508,   R8A7796_CLK_S3D2),
-       DEF_MOD("drif6",                 509,   R8A7796_CLK_S3D2),
-       DEF_MOD("drif5",                 510,   R8A7796_CLK_S3D2),
-       DEF_MOD("drif4",                 511,   R8A7796_CLK_S3D2),
-       DEF_MOD("drif3",                 512,   R8A7796_CLK_S3D2),
-       DEF_MOD("drif2",                 513,   R8A7796_CLK_S3D2),
-       DEF_MOD("drif1",                 514,   R8A7796_CLK_S3D2),
-       DEF_MOD("drif0",                 515,   R8A7796_CLK_S3D2),
+       DEF_MOD("drif31",                508,   R8A7796_CLK_S3D2),
+       DEF_MOD("drif30",                509,   R8A7796_CLK_S3D2),
+       DEF_MOD("drif21",                510,   R8A7796_CLK_S3D2),
+       DEF_MOD("drif20",                511,   R8A7796_CLK_S3D2),
+       DEF_MOD("drif11",                512,   R8A7796_CLK_S3D2),
+       DEF_MOD("drif10",                513,   R8A7796_CLK_S3D2),
+       DEF_MOD("drif01",                514,   R8A7796_CLK_S3D2),
+       DEF_MOD("drif00",                515,   R8A7796_CLK_S3D2),
        DEF_MOD("hscif4",                516,   R8A7796_CLK_S3D1),
        DEF_MOD("hscif3",                517,   R8A7796_CLK_S3D1),
        DEF_MOD("hscif2",                518,   R8A7796_CLK_S3D1),

diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c b/drivers/clk/renesas/r8a77965-cpg-mssr.c
index a0ce2ecb656d3d48e1956079b94bf1e9e7e28d3f..8f87e314d94904986baf1234413786c82ff81c3f 100644 (file)
--- a/drivers/clk/renesas/r8a77965-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c
@@ -3,6 +3,7 @@
  * r8a77965 Clock Pulse Generator / Module Standby and Software Reset
  *
  * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
+ * Copyright (C) 2019 Renesas Electronics Corp.
  *
  * Based on r8a7795-cpg-mssr.c
  *
@@ -148,14 +149,14 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
 
        DEF_MOD("audmac1",              501,    R8A77965_CLK_S1D2),
        DEF_MOD("audmac0",              502,    R8A77965_CLK_S1D2),
-       DEF_MOD("drif7",                508,    R8A77965_CLK_S3D2),
-       DEF_MOD("drif6",                509,    R8A77965_CLK_S3D2),
-       DEF_MOD("drif5",                510,    R8A77965_CLK_S3D2),
-       DEF_MOD("drif4",                511,    R8A77965_CLK_S3D2),
-       DEF_MOD("drif3",                512,    R8A77965_CLK_S3D2),
-       DEF_MOD("drif2",                513,    R8A77965_CLK_S3D2),
-       DEF_MOD("drif1",                514,    R8A77965_CLK_S3D2),
-       DEF_MOD("drif0",                515,    R8A77965_CLK_S3D2),
+       DEF_MOD("drif31",               508,    R8A77965_CLK_S3D2),
+       DEF_MOD("drif30",               509,    R8A77965_CLK_S3D2),
+       DEF_MOD("drif21",               510,    R8A77965_CLK_S3D2),
+       DEF_MOD("drif20",               511,    R8A77965_CLK_S3D2),
+       DEF_MOD("drif11",               512,    R8A77965_CLK_S3D2),
+       DEF_MOD("drif10",               513,    R8A77965_CLK_S3D2),
+       DEF_MOD("drif01",               514,    R8A77965_CLK_S3D2),
+       DEF_MOD("drif00",               515,    R8A77965_CLK_S3D2),
        DEF_MOD("hscif4",               516,    R8A77965_CLK_S3D1),
        DEF_MOD("hscif3",               517,    R8A77965_CLK_S3D1),
        DEF_MOD("hscif2",               518,    R8A77965_CLK_S3D1),

diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c
index 53973201a9f576ad8862b5bb508f279e17aa64d7..9570404baa583a8f501ec3a9d47dad733cf60114 100644 (file)
--- a/drivers/clk/renesas/r8a77990-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c
@@ -2,7 +2,7 @@
 /*
  * r8a77990 Clock Pulse Generator / Module Standby and Software Reset
  *
- * Copyright (C) 2018 Renesas Electronics Corp.
+ * Copyright (C) 2018-2019 Renesas Electronics Corp.
  *
  * Based on r8a7795-cpg-mssr.c
  *
@@ -154,14 +154,14 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = {
        DEF_MOD("intc-ap",               408,   R8A77990_CLK_S0D3),
 
        DEF_MOD("audmac0",               502,   R8A77990_CLK_S1D2),
-       DEF_MOD("drif7",                 508,   R8A77990_CLK_S3D2),
-       DEF_MOD("drif6",                 509,   R8A77990_CLK_S3D2),
-       DEF_MOD("drif5",                 510,   R8A77990_CLK_S3D2),
-       DEF_MOD("drif4",                 511,   R8A77990_CLK_S3D2),
-       DEF_MOD("drif3",                 512,   R8A77990_CLK_S3D2),
-       DEF_MOD("drif2",                 513,   R8A77990_CLK_S3D2),
-       DEF_MOD("drif1",                 514,   R8A77990_CLK_S3D2),
-       DEF_MOD("drif0",                 515,   R8A77990_CLK_S3D2),
+       DEF_MOD("drif31",                508,   R8A77990_CLK_S3D2),
+       DEF_MOD("drif30",                509,   R8A77990_CLK_S3D2),
+       DEF_MOD("drif21",                510,   R8A77990_CLK_S3D2),
+       DEF_MOD("drif20",                511,   R8A77990_CLK_S3D2),
+       DEF_MOD("drif11",                512,   R8A77990_CLK_S3D2),
+       DEF_MOD("drif10",                513,   R8A77990_CLK_S3D2),
+       DEF_MOD("drif01",                514,   R8A77990_CLK_S3D2),
+       DEF_MOD("drif00",                515,   R8A77990_CLK_S3D2),
        DEF_MOD("hscif4",                516,   R8A77990_CLK_S3D1C),
        DEF_MOD("hscif3",                517,   R8A77990_CLK_S3D1C),
        DEF_MOD("hscif2",                518,   R8A77990_CLK_S3D1C),