virt/kvm/arm/vgic/vgic-mmio-v3.c

   1 /*
   2  * VGICv3 MMIO handling functions
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/irqchip/arm-gic-v3.h>
  15 #include <linux/kvm.h>
  16 #include <linux/kvm_host.h>
  17 #include <kvm/iodev.h>
  18 #include <kvm/arm_vgic.h>
  19
  20 #include <asm/kvm_emulate.h>
  21
  22 #include "vgic.h"
  23 #include "vgic-mmio.h"
  24
  25 /* extract @num bytes at @offset bytes offset in data */
  26 static unsigned long extract_bytes(unsigned long data, unsigned int offset,
  27                                    unsigned int num)
  28 {
  29         return (data >> (offset * 8)) & GENMASK_ULL(num * 8 - 1, 0);
  30 }
  31
  32 static unsigned long vgic_mmio_read_v3_misc(struct kvm_vcpu *vcpu,
  33                                             gpa_t addr, unsigned int len)
  34 {
  35         u32 value = 0;
  36
  37         switch (addr & 0x0c) {
  38         case GICD_CTLR:
  39                 if (vcpu->kvm->arch.vgic.enabled)
  40                         value |= GICD_CTLR_ENABLE_SS_G1;
  41                 value |= GICD_CTLR_ARE_NS | GICD_CTLR_DS;
  42                 break;
  43         case GICD_TYPER:
  44                 value = vcpu->kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS;
  45                 value = (value >> 5) - 1;
  46                 value |= (INTERRUPT_ID_BITS_SPIS - 1) << 19;
  47                 break;
  48         case GICD_IIDR:
  49                 value = (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0);
  50                 break;
  51         default:
  52                 return 0;
  53         }
  54
  55         return value;
  56 }
  57
  58 static void vgic_mmio_write_v3_misc(struct kvm_vcpu *vcpu,
  59                                     gpa_t addr, unsigned int len,
  60                                     unsigned long val)
  61 {
  62         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
  63         bool was_enabled = dist->enabled;
  64
  65         switch (addr & 0x0c) {
  66         case GICD_CTLR:
  67                 dist->enabled = val & GICD_CTLR_ENABLE_SS_G1;
  68
  69                 if (!was_enabled && dist->enabled)
  70                         vgic_kick_vcpus(vcpu->kvm);
  71                 break;
  72         case GICD_TYPER:
  73         case GICD_IIDR:
  74                 return;
  75         }
  76 }
  77
  78 static unsigned long vgic_mmio_read_v3r_typer(struct kvm_vcpu *vcpu,
  79                                               gpa_t addr, unsigned int len)
  80 {
  81         unsigned long mpidr = kvm_vcpu_get_mpidr_aff(vcpu);
  82         int target_vcpu_id = vcpu->vcpu_id;
  83         u64 value;
  84
  85         value = (mpidr & GENMASK(23, 0)) << 32;
  86         value |= ((target_vcpu_id & 0xffff) << 8);
  87         if (target_vcpu_id == atomic_read(&vcpu->kvm->online_vcpus) - 1)
  88                 value |= GICR_TYPER_LAST;
  89
  90         return extract_bytes(value, addr & 7, len);
  91 }
  92
  93 static unsigned long vgic_mmio_read_v3r_iidr(struct kvm_vcpu *vcpu,
  94                                              gpa_t addr, unsigned int len)
  95 {
  96         return (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0);
  97 }
  98
  99 /*
 100  * The GICv3 per-IRQ registers are split to control PPIs and SGIs in the
 101  * redistributors, while SPIs are covered by registers in the distributor
 102  * block. Trying to set private IRQs in this block gets ignored.
 103  * We take some special care here to fix the calculation of the register
 104  * offset.
 105  */
 106 #define REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(off, rd, wr, bpi, acc)   \
 107         {                                                               \
 108                 .reg_offset = off,                                      \
 109                 .bits_per_irq = bpi,                                    \
 110                 .len = (bpi * VGIC_NR_PRIVATE_IRQS) / 8,                \
 111                 .access_flags = acc,                                    \
 112                 .read = vgic_mmio_read_raz,                             \
 113                 .write = vgic_mmio_write_wi,                            \
 114         }, {                                                            \
 115                 .reg_offset = off + (bpi * VGIC_NR_PRIVATE_IRQS) / 8,   \
 116                 .bits_per_irq = bpi,                                    \
 117                 .len = (bpi * (1024 - VGIC_NR_PRIVATE_IRQS)) / 8,       \
 118                 .access_flags = acc,                                    \
 119                 .read = rd,                                             \
 120                 .write = wr,                                            \
 121         }
 122
 123 static const struct vgic_register_region vgic_v3_dist_registers[] = {
 124         REGISTER_DESC_WITH_LENGTH(GICD_CTLR,
 125                 vgic_mmio_read_v3_misc, vgic_mmio_write_v3_misc, 16,
 126                 VGIC_ACCESS_32bit),
 127         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGROUPR,
 128                 vgic_mmio_read_rao, vgic_mmio_write_wi, 1,
 129                 VGIC_ACCESS_32bit),
 130         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISENABLER,
 131                 vgic_mmio_read_enable, vgic_mmio_write_senable, 1,
 132                 VGIC_ACCESS_32bit),
 133         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICENABLER,
 134                 vgic_mmio_read_enable, vgic_mmio_write_cenable, 1,
 135                 VGIC_ACCESS_32bit),
 136         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISPENDR,
 137                 vgic_mmio_read_pending, vgic_mmio_write_spending, 1,
 138                 VGIC_ACCESS_32bit),
 139         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICPENDR,
 140                 vgic_mmio_read_pending, vgic_mmio_write_cpending, 1,
 141                 VGIC_ACCESS_32bit),
 142         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISACTIVER,
 143                 vgic_mmio_read_active, vgic_mmio_write_sactive, 1,
 144                 VGIC_ACCESS_32bit),
 145         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICACTIVER,
 146                 vgic_mmio_read_active, vgic_mmio_write_cactive, 1,
 147                 VGIC_ACCESS_32bit),
 148         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IPRIORITYR,
 149                 vgic_mmio_read_priority, vgic_mmio_write_priority, 8,
 150                 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
 151         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ITARGETSR,
 152                 vgic_mmio_read_raz, vgic_mmio_write_wi, 8,
 153                 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
 154         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICFGR,
 155                 vgic_mmio_read_config, vgic_mmio_write_config, 2,
 156                 VGIC_ACCESS_32bit),
 157         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGRPMODR,
 158                 vgic_mmio_read_raz, vgic_mmio_write_wi, 1,
 159                 VGIC_ACCESS_32bit),
 160         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IROUTER,
 161                 vgic_mmio_read_raz, vgic_mmio_write_wi, 64,
 162                 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
 163         REGISTER_DESC_WITH_LENGTH(GICD_IDREGS,
 164                 vgic_mmio_read_raz, vgic_mmio_write_wi, 48,
 165                 VGIC_ACCESS_32bit),
 166 };
 167
 168 static const struct vgic_register_region vgic_v3_rdbase_registers[] = {
 169         REGISTER_DESC_WITH_LENGTH(GICR_CTLR,
 170                 vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
 171                 VGIC_ACCESS_32bit),
 172         REGISTER_DESC_WITH_LENGTH(GICR_IIDR,
 173                 vgic_mmio_read_v3r_iidr, vgic_mmio_write_wi, 4,
 174                 VGIC_ACCESS_32bit),
 175         REGISTER_DESC_WITH_LENGTH(GICR_TYPER,
 176                 vgic_mmio_read_v3r_typer, vgic_mmio_write_wi, 8,
 177                 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
 178         REGISTER_DESC_WITH_LENGTH(GICR_PROPBASER,
 179                 vgic_mmio_read_raz, vgic_mmio_write_wi, 8,
 180                 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
 181         REGISTER_DESC_WITH_LENGTH(GICR_PENDBASER,
 182                 vgic_mmio_read_raz, vgic_mmio_write_wi, 8,
 183                 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
 184         REGISTER_DESC_WITH_LENGTH(GICR_IDREGS,
 185                 vgic_mmio_read_raz, vgic_mmio_write_wi, 48,
 186                 VGIC_ACCESS_32bit),
 187 };
 188
 189 static const struct vgic_register_region vgic_v3_sgibase_registers[] = {
 190         REGISTER_DESC_WITH_LENGTH(GICR_IGROUPR0,
 191                 vgic_mmio_read_rao, vgic_mmio_write_wi, 4,
 192                 VGIC_ACCESS_32bit),
 193         REGISTER_DESC_WITH_LENGTH(GICR_ISENABLER0,
 194                 vgic_mmio_read_enable, vgic_mmio_write_senable, 4,
 195                 VGIC_ACCESS_32bit),
 196         REGISTER_DESC_WITH_LENGTH(GICR_ICENABLER0,
 197                 vgic_mmio_read_enable, vgic_mmio_write_cenable, 4,
 198                 VGIC_ACCESS_32bit),
 199         REGISTER_DESC_WITH_LENGTH(GICR_ISPENDR0,
 200                 vgic_mmio_read_pending, vgic_mmio_write_spending, 4,
 201                 VGIC_ACCESS_32bit),
 202         REGISTER_DESC_WITH_LENGTH(GICR_ICPENDR0,
 203                 vgic_mmio_read_pending, vgic_mmio_write_cpending, 4,
 204                 VGIC_ACCESS_32bit),
 205         REGISTER_DESC_WITH_LENGTH(GICR_ISACTIVER0,
 206                 vgic_mmio_read_active, vgic_mmio_write_sactive, 4,
 207                 VGIC_ACCESS_32bit),
 208         REGISTER_DESC_WITH_LENGTH(GICR_ICACTIVER0,
 209                 vgic_mmio_read_active, vgic_mmio_write_cactive, 4,
 210                 VGIC_ACCESS_32bit),
 211         REGISTER_DESC_WITH_LENGTH(GICR_IPRIORITYR0,
 212                 vgic_mmio_read_priority, vgic_mmio_write_priority, 32,
 213                 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
 214         REGISTER_DESC_WITH_LENGTH(GICR_ICFGR0,
 215                 vgic_mmio_read_config, vgic_mmio_write_config, 8,
 216                 VGIC_ACCESS_32bit),
 217         REGISTER_DESC_WITH_LENGTH(GICR_IGRPMODR0,
 218                 vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
 219                 VGIC_ACCESS_32bit),
 220         REGISTER_DESC_WITH_LENGTH(GICR_NSACR,
 221                 vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
 222                 VGIC_ACCESS_32bit),
 223 };
 224
 225 unsigned int vgic_v3_init_dist_iodev(struct vgic_io_device *dev)
 226 {
 227         dev->regions = vgic_v3_dist_registers;
 228         dev->nr_regions = ARRAY_SIZE(vgic_v3_dist_registers);
 229
 230         kvm_iodevice_init(&dev->dev, &kvm_io_gic_ops);
 231
 232         return SZ_64K;
 233 }
 234
 235 int vgic_register_redist_iodevs(struct kvm *kvm, gpa_t redist_base_address)
 236 {
 237         int nr_vcpus = atomic_read(&kvm->online_vcpus);
 238         struct kvm_vcpu *vcpu;
 239         struct vgic_io_device *devices;
 240         int c, ret = 0;
 241
 242         devices = kmalloc(sizeof(struct vgic_io_device) * nr_vcpus * 2,
 243                           GFP_KERNEL);
 244         if (!devices)
 245                 return -ENOMEM;
 246
 247         kvm_for_each_vcpu(c, vcpu, kvm) {
 248                 gpa_t rd_base = redist_base_address + c * SZ_64K * 2;
 249                 gpa_t sgi_base = rd_base + SZ_64K;
 250                 struct vgic_io_device *rd_dev = &devices[c * 2];
 251                 struct vgic_io_device *sgi_dev = &devices[c * 2 + 1];
 252
 253                 kvm_iodevice_init(&rd_dev->dev, &kvm_io_gic_ops);
 254                 rd_dev->base_addr = rd_base;
 255                 rd_dev->regions = vgic_v3_rdbase_registers;
 256                 rd_dev->nr_regions = ARRAY_SIZE(vgic_v3_rdbase_registers);
 257                 rd_dev->redist_vcpu = vcpu;
 258
 259                 mutex_lock(&kvm->slots_lock);
 260                 ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, rd_base,
 261                                               SZ_64K, &rd_dev->dev);
 262                 mutex_unlock(&kvm->slots_lock);
 263
 264                 if (ret)
 265                         break;
 266
 267                 kvm_iodevice_init(&sgi_dev->dev, &kvm_io_gic_ops);
 268                 sgi_dev->base_addr = sgi_base;
 269                 sgi_dev->regions = vgic_v3_sgibase_registers;
 270                 sgi_dev->nr_regions = ARRAY_SIZE(vgic_v3_sgibase_registers);
 271                 sgi_dev->redist_vcpu = vcpu;
 272
 273                 mutex_lock(&kvm->slots_lock);
 274                 ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, sgi_base,
 275                                               SZ_64K, &sgi_dev->dev);
 276                 mutex_unlock(&kvm->slots_lock);
 277                 if (ret) {
 278                         kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS,
 279                                                   &rd_dev->dev);
 280                         break;
 281                 }
 282         }
 283
 284         if (ret) {
 285                 /* The current c failed, so we start with the previous one. */
 286                 for (c--; c >= 0; c--) {
 287                         kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS,
 288                                                   &devices[c * 2].dev);
 289                         kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS,
 290                                                   &devices[c * 2 + 1].dev);
 291                 }
 292                 kfree(devices);
 293         } else {
 294                 kvm->arch.vgic.redist_iodevs = devices;
 295         }
 296
 297         return ret;
 298 }