2 * VGICv3 MMIO handling functions
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/irqchip/arm-gic-v3.h>
15 #include <linux/kvm.h>
16 #include <linux/kvm_host.h>
17 #include <kvm/iodev.h>
18 #include <kvm/arm_vgic.h>
20 #include <asm/kvm_emulate.h>
23 #include "vgic-mmio.h"
25 /* extract @num bytes at @offset bytes offset in data */
26 static unsigned long extract_bytes(unsigned long data, unsigned int offset,
29 return (data >> (offset * 8)) & GENMASK_ULL(num * 8 - 1, 0);
32 static unsigned long vgic_mmio_read_v3_misc(struct kvm_vcpu *vcpu,
33 gpa_t addr, unsigned int len)
37 switch (addr & 0x0c) {
39 if (vcpu->kvm->arch.vgic.enabled)
40 value |= GICD_CTLR_ENABLE_SS_G1;
41 value |= GICD_CTLR_ARE_NS | GICD_CTLR_DS;
44 value = vcpu->kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS;
45 value = (value >> 5) - 1;
46 value |= (INTERRUPT_ID_BITS_SPIS - 1) << 19;
49 value = (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0);
58 static void vgic_mmio_write_v3_misc(struct kvm_vcpu *vcpu,
59 gpa_t addr, unsigned int len,
62 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
63 bool was_enabled = dist->enabled;
65 switch (addr & 0x0c) {
67 dist->enabled = val & GICD_CTLR_ENABLE_SS_G1;
69 if (!was_enabled && dist->enabled)
70 vgic_kick_vcpus(vcpu->kvm);
78 static unsigned long vgic_mmio_read_v3r_typer(struct kvm_vcpu *vcpu,
79 gpa_t addr, unsigned int len)
81 unsigned long mpidr = kvm_vcpu_get_mpidr_aff(vcpu);
82 int target_vcpu_id = vcpu->vcpu_id;
85 value = (mpidr & GENMASK(23, 0)) << 32;
86 value |= ((target_vcpu_id & 0xffff) << 8);
87 if (target_vcpu_id == atomic_read(&vcpu->kvm->online_vcpus) - 1)
88 value |= GICR_TYPER_LAST;
90 return extract_bytes(value, addr & 7, len);
93 static unsigned long vgic_mmio_read_v3r_iidr(struct kvm_vcpu *vcpu,
94 gpa_t addr, unsigned int len)
96 return (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0);
99 static unsigned long vgic_mmio_read_v3_idregs(struct kvm_vcpu *vcpu,
100 gpa_t addr, unsigned int len)
102 switch (addr & 0xffff) {
104 /* report a GICv3 compliant implementation */
112 * The GICv3 per-IRQ registers are split to control PPIs and SGIs in the
113 * redistributors, while SPIs are covered by registers in the distributor
114 * block. Trying to set private IRQs in this block gets ignored.
115 * We take some special care here to fix the calculation of the register
118 #define REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(off, rd, wr, bpi, acc) \
121 .bits_per_irq = bpi, \
122 .len = (bpi * VGIC_NR_PRIVATE_IRQS) / 8, \
123 .access_flags = acc, \
124 .read = vgic_mmio_read_raz, \
125 .write = vgic_mmio_write_wi, \
127 .reg_offset = off + (bpi * VGIC_NR_PRIVATE_IRQS) / 8, \
128 .bits_per_irq = bpi, \
129 .len = (bpi * (1024 - VGIC_NR_PRIVATE_IRQS)) / 8, \
130 .access_flags = acc, \
135 static const struct vgic_register_region vgic_v3_dist_registers[] = {
136 REGISTER_DESC_WITH_LENGTH(GICD_CTLR,
137 vgic_mmio_read_v3_misc, vgic_mmio_write_v3_misc, 16,
139 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGROUPR,
140 vgic_mmio_read_rao, vgic_mmio_write_wi, 1,
142 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISENABLER,
143 vgic_mmio_read_enable, vgic_mmio_write_senable, 1,
145 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICENABLER,
146 vgic_mmio_read_enable, vgic_mmio_write_cenable, 1,
148 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISPENDR,
149 vgic_mmio_read_pending, vgic_mmio_write_spending, 1,
151 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICPENDR,
152 vgic_mmio_read_pending, vgic_mmio_write_cpending, 1,
154 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISACTIVER,
155 vgic_mmio_read_active, vgic_mmio_write_sactive, 1,
157 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICACTIVER,
158 vgic_mmio_read_active, vgic_mmio_write_cactive, 1,
160 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IPRIORITYR,
161 vgic_mmio_read_priority, vgic_mmio_write_priority, 8,
162 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
163 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ITARGETSR,
164 vgic_mmio_read_raz, vgic_mmio_write_wi, 8,
165 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
166 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICFGR,
167 vgic_mmio_read_config, vgic_mmio_write_config, 2,
169 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGRPMODR,
170 vgic_mmio_read_raz, vgic_mmio_write_wi, 1,
172 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IROUTER,
173 vgic_mmio_read_raz, vgic_mmio_write_wi, 64,
174 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
175 REGISTER_DESC_WITH_LENGTH(GICD_IDREGS,
176 vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48,
180 static const struct vgic_register_region vgic_v3_rdbase_registers[] = {
181 REGISTER_DESC_WITH_LENGTH(GICR_CTLR,
182 vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
184 REGISTER_DESC_WITH_LENGTH(GICR_IIDR,
185 vgic_mmio_read_v3r_iidr, vgic_mmio_write_wi, 4,
187 REGISTER_DESC_WITH_LENGTH(GICR_TYPER,
188 vgic_mmio_read_v3r_typer, vgic_mmio_write_wi, 8,
189 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
190 REGISTER_DESC_WITH_LENGTH(GICR_PROPBASER,
191 vgic_mmio_read_raz, vgic_mmio_write_wi, 8,
192 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
193 REGISTER_DESC_WITH_LENGTH(GICR_PENDBASER,
194 vgic_mmio_read_raz, vgic_mmio_write_wi, 8,
195 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
196 REGISTER_DESC_WITH_LENGTH(GICR_IDREGS,
197 vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48,
201 static const struct vgic_register_region vgic_v3_sgibase_registers[] = {
202 REGISTER_DESC_WITH_LENGTH(GICR_IGROUPR0,
203 vgic_mmio_read_rao, vgic_mmio_write_wi, 4,
205 REGISTER_DESC_WITH_LENGTH(GICR_ISENABLER0,
206 vgic_mmio_read_enable, vgic_mmio_write_senable, 4,
208 REGISTER_DESC_WITH_LENGTH(GICR_ICENABLER0,
209 vgic_mmio_read_enable, vgic_mmio_write_cenable, 4,
211 REGISTER_DESC_WITH_LENGTH(GICR_ISPENDR0,
212 vgic_mmio_read_pending, vgic_mmio_write_spending, 4,
214 REGISTER_DESC_WITH_LENGTH(GICR_ICPENDR0,
215 vgic_mmio_read_pending, vgic_mmio_write_cpending, 4,
217 REGISTER_DESC_WITH_LENGTH(GICR_ISACTIVER0,
218 vgic_mmio_read_active, vgic_mmio_write_sactive, 4,
220 REGISTER_DESC_WITH_LENGTH(GICR_ICACTIVER0,
221 vgic_mmio_read_active, vgic_mmio_write_cactive, 4,
223 REGISTER_DESC_WITH_LENGTH(GICR_IPRIORITYR0,
224 vgic_mmio_read_priority, vgic_mmio_write_priority, 32,
225 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
226 REGISTER_DESC_WITH_LENGTH(GICR_ICFGR0,
227 vgic_mmio_read_config, vgic_mmio_write_config, 8,
229 REGISTER_DESC_WITH_LENGTH(GICR_IGRPMODR0,
230 vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
232 REGISTER_DESC_WITH_LENGTH(GICR_NSACR,
233 vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
237 unsigned int vgic_v3_init_dist_iodev(struct vgic_io_device *dev)
239 dev->regions = vgic_v3_dist_registers;
240 dev->nr_regions = ARRAY_SIZE(vgic_v3_dist_registers);
242 kvm_iodevice_init(&dev->dev, &kvm_io_gic_ops);
247 int vgic_register_redist_iodevs(struct kvm *kvm, gpa_t redist_base_address)
249 int nr_vcpus = atomic_read(&kvm->online_vcpus);
250 struct kvm_vcpu *vcpu;
251 struct vgic_io_device *devices;
254 devices = kmalloc(sizeof(struct vgic_io_device) * nr_vcpus * 2,
259 kvm_for_each_vcpu(c, vcpu, kvm) {
260 gpa_t rd_base = redist_base_address + c * SZ_64K * 2;
261 gpa_t sgi_base = rd_base + SZ_64K;
262 struct vgic_io_device *rd_dev = &devices[c * 2];
263 struct vgic_io_device *sgi_dev = &devices[c * 2 + 1];
265 kvm_iodevice_init(&rd_dev->dev, &kvm_io_gic_ops);
266 rd_dev->base_addr = rd_base;
267 rd_dev->regions = vgic_v3_rdbase_registers;
268 rd_dev->nr_regions = ARRAY_SIZE(vgic_v3_rdbase_registers);
269 rd_dev->redist_vcpu = vcpu;
271 mutex_lock(&kvm->slots_lock);
272 ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, rd_base,
273 SZ_64K, &rd_dev->dev);
274 mutex_unlock(&kvm->slots_lock);
279 kvm_iodevice_init(&sgi_dev->dev, &kvm_io_gic_ops);
280 sgi_dev->base_addr = sgi_base;
281 sgi_dev->regions = vgic_v3_sgibase_registers;
282 sgi_dev->nr_regions = ARRAY_SIZE(vgic_v3_sgibase_registers);
283 sgi_dev->redist_vcpu = vcpu;
285 mutex_lock(&kvm->slots_lock);
286 ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, sgi_base,
287 SZ_64K, &sgi_dev->dev);
288 mutex_unlock(&kvm->slots_lock);
290 kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS,
297 /* The current c failed, so we start with the previous one. */
298 for (c--; c >= 0; c--) {
299 kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS,
300 &devices[c * 2].dev);
301 kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS,
302 &devices[c * 2 + 1].dev);
306 kvm->arch.vgic.redist_iodevs = devices;