sound/pci/hda/hda_intel.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *
   4  *  hda_intel.c - Implementation of primary alsa driver code base
   5  *                for Intel HD Audio.
   6  *
   7  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   8  *
   9  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
  10  *                     PeiSen Hou <pshou@realtek.com.tw>
  11  *
  12  *  CONTACTS:
  13  *
  14  *  Matt Jared          matt.jared@intel.com
  15  *  Andy Kopp           andy.kopp@intel.com
  16  *  Dan Kogan           dan.d.kogan@intel.com
  17  *
  18  *  CHANGES:
  19  *
  20  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  21  */
  22
  23 #include <linux/delay.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/moduleparam.h>
  29 #include <linux/init.h>
  30 #include <linux/slab.h>
  31 #include <linux/pci.h>
  32 #include <linux/mutex.h>
  33 #include <linux/io.h>
  34 #include <linux/pm_runtime.h>
  35 #include <linux/clocksource.h>
  36 #include <linux/time.h>
  37 #include <linux/completion.h>
  38
  39 #ifdef CONFIG_X86
  40 /* for snoop control */
  41 #include <asm/pgtable.h>
  42 #include <asm/set_memory.h>
  43 #include <asm/cpufeature.h>
  44 #endif
  45 #include <sound/core.h>
  46 #include <sound/initval.h>
  47 #include <sound/hdaudio.h>
  48 #include <sound/hda_i915.h>
  49 #include <sound/intel-nhlt.h>
  50 #include <linux/vgaarb.h>
  51 #include <linux/vga_switcheroo.h>
  52 #include <linux/firmware.h>
  53 #include <sound/hda_codec.h>
  54 #include "hda_controller.h"
  55 #include "hda_intel.h"
  56
  57 #define CREATE_TRACE_POINTS
  58 #include "hda_intel_trace.h"
  59
  60 /* position fix mode */
  61 enum {
  62         POS_FIX_AUTO,
  63         POS_FIX_LPIB,
  64         POS_FIX_POSBUF,
  65         POS_FIX_VIACOMBO,
  66         POS_FIX_COMBO,
  67         POS_FIX_SKL,
  68         POS_FIX_FIFO,
  69 };
  70
  71 /* Defines for ATI HD Audio support in SB450 south bridge */
  72 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
  73 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
  74
  75 /* Defines for Nvidia HDA support */
  76 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
  77 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
  78 #define NVIDIA_HDA_ISTRM_COH          0x4d
  79 #define NVIDIA_HDA_OSTRM_COH          0x4c
  80 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
  81
  82 /* Defines for Intel SCH HDA snoop control */
  83 #define INTEL_HDA_CGCTL  0x48
  84 #define INTEL_HDA_CGCTL_MISCBDCGE        (0x1 << 6)
  85 #define INTEL_SCH_HDA_DEVC      0x78
  86 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
  87
  88 /* Define VIA HD Audio Device ID*/
  89 #define VIA_HDAC_DEVICE_ID              0x3288
  90
  91 /* max number of SDs */
  92 /* ICH, ATI and VIA have 4 playback and 4 capture */
  93 #define ICH6_NUM_CAPTURE        4
  94 #define ICH6_NUM_PLAYBACK       4
  95
  96 /* ULI has 6 playback and 5 capture */
  97 #define ULI_NUM_CAPTURE         5
  98 #define ULI_NUM_PLAYBACK        6
  99
 100 /* ATI HDMI may have up to 8 playbacks and 0 capture */
 101 #define ATIHDMI_NUM_CAPTURE     0
 102 #define ATIHDMI_NUM_PLAYBACK    8
 103
 104 /* TERA has 4 playback and 3 capture */
 105 #define TERA_NUM_CAPTURE        3
 106 #define TERA_NUM_PLAYBACK       4
 107
 108
 109 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
 110 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
 111 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
 112 static char *model[SNDRV_CARDS];
 113 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 114 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 115 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 116 static int probe_only[SNDRV_CARDS];
 117 static int jackpoll_ms[SNDRV_CARDS];
 118 static int single_cmd = -1;
 119 static int enable_msi = -1;
 120 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 121 static char *patch[SNDRV_CARDS];
 122 #endif
 123 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 124 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
 125                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
 126 #endif
 127 static bool dmic_detect = IS_ENABLED(CONFIG_SND_HDA_INTEL_DETECT_DMIC);
 128
 129 module_param_array(index, int, NULL, 0444);
 130 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
 131 module_param_array(id, charp, NULL, 0444);
 132 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
 133 module_param_array(enable, bool, NULL, 0444);
 134 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
 135 module_param_array(model, charp, NULL, 0444);
 136 MODULE_PARM_DESC(model, "Use the given board model.");
 137 module_param_array(position_fix, int, NULL, 0444);
 138 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
 139                  "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO).");
 140 module_param_array(bdl_pos_adj, int, NULL, 0644);
 141 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
 142 module_param_array(probe_mask, int, NULL, 0444);
 143 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
 144 module_param_array(probe_only, int, NULL, 0444);
 145 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
 146 module_param_array(jackpoll_ms, int, NULL, 0444);
 147 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
 148 module_param(single_cmd, bint, 0444);
 149 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
 150                  "(for debugging only).");
 151 module_param(enable_msi, bint, 0444);
 152 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
 153 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 154 module_param_array(patch, charp, NULL, 0444);
 155 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
 156 #endif
 157 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 158 module_param_array(beep_mode, bool, NULL, 0444);
 159 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
 160                             "(0=off, 1=on) (default=1).");
 161 #endif
 162 module_param(dmic_detect, bool, 0444);
 163 MODULE_PARM_DESC(dmic_detect, "DMIC detect on SKL+ platforms");
 164
 165 #ifdef CONFIG_PM
 166 static int param_set_xint(const char *val, const struct kernel_param *kp);
 167 static const struct kernel_param_ops param_ops_xint = {
 168         .set = param_set_xint,
 169         .get = param_get_int,
 170 };
 171 #define param_check_xint param_check_int
 172
 173 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
 174 module_param(power_save, xint, 0644);
 175 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
 176                  "(in second, 0 = disable).");
 177
 178 static bool pm_blacklist = true;
 179 module_param(pm_blacklist, bool, 0644);
 180 MODULE_PARM_DESC(pm_blacklist, "Enable power-management blacklist");
 181
 182 /* reset the HD-audio controller in power save mode.
 183  * this may give more power-saving, but will take longer time to
 184  * wake up.
 185  */
 186 static bool power_save_controller = 1;
 187 module_param(power_save_controller, bool, 0644);
 188 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 189 #else
 190 #define power_save      0
 191 #endif /* CONFIG_PM */
 192
 193 static int align_buffer_size = -1;
 194 module_param(align_buffer_size, bint, 0644);
 195 MODULE_PARM_DESC(align_buffer_size,
 196                 "Force buffer and period sizes to be multiple of 128 bytes.");
 197
 198 #ifdef CONFIG_X86
 199 static int hda_snoop = -1;
 200 module_param_named(snoop, hda_snoop, bint, 0444);
 201 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
 202 #else
 203 #define hda_snoop               true
 204 #endif
 205
 206
 207 MODULE_LICENSE("GPL");
 208 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
 209                          "{Intel, ICH6M},"
 210                          "{Intel, ICH7},"
 211                          "{Intel, ESB2},"
 212                          "{Intel, ICH8},"
 213                          "{Intel, ICH9},"
 214                          "{Intel, ICH10},"
 215                          "{Intel, PCH},"
 216                          "{Intel, CPT},"
 217                          "{Intel, PPT},"
 218                          "{Intel, LPT},"
 219                          "{Intel, LPT_LP},"
 220                          "{Intel, WPT_LP},"
 221                          "{Intel, SPT},"
 222                          "{Intel, SPT_LP},"
 223                          "{Intel, HPT},"
 224                          "{Intel, PBG},"
 225                          "{Intel, SCH},"
 226                          "{ATI, SB450},"
 227                          "{ATI, SB600},"
 228                          "{ATI, RS600},"
 229                          "{ATI, RS690},"
 230                          "{ATI, RS780},"
 231                          "{ATI, R600},"
 232                          "{ATI, RV630},"
 233                          "{ATI, RV610},"
 234                          "{ATI, RV670},"
 235                          "{ATI, RV635},"
 236                          "{ATI, RV620},"
 237                          "{ATI, RV770},"
 238                          "{VIA, VT8251},"
 239                          "{VIA, VT8237A},"
 240                          "{SiS, SIS966},"
 241                          "{ULI, M5461}}");
 242 MODULE_DESCRIPTION("Intel HDA driver");
 243
 244 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
 245 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
 246 #define SUPPORT_VGA_SWITCHEROO
 247 #endif
 248 #endif
 249
 250
 251 /*
 252  */
 253
 254 /* driver types */
 255 enum {
 256         AZX_DRIVER_ICH,
 257         AZX_DRIVER_PCH,
 258         AZX_DRIVER_SCH,
 259         AZX_DRIVER_SKL,
 260         AZX_DRIVER_HDMI,
 261         AZX_DRIVER_ATI,
 262         AZX_DRIVER_ATIHDMI,
 263         AZX_DRIVER_ATIHDMI_NS,
 264         AZX_DRIVER_VIA,
 265         AZX_DRIVER_SIS,
 266         AZX_DRIVER_ULI,
 267         AZX_DRIVER_NVIDIA,
 268         AZX_DRIVER_TERA,
 269         AZX_DRIVER_CTX,
 270         AZX_DRIVER_CTHDA,
 271         AZX_DRIVER_CMEDIA,
 272         AZX_DRIVER_ZHAOXIN,
 273         AZX_DRIVER_GENERIC,
 274         AZX_NUM_DRIVERS, /* keep this as last entry */
 275 };
 276
 277 #define azx_get_snoop_type(chip) \
 278         (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
 279 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
 280
 281 /* quirks for old Intel chipsets */
 282 #define AZX_DCAPS_INTEL_ICH \
 283         (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
 284
 285 /* quirks for Intel PCH */
 286 #define AZX_DCAPS_INTEL_PCH_BASE \
 287         (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
 288          AZX_DCAPS_SNOOP_TYPE(SCH))
 289
 290 /* PCH up to IVB; no runtime PM; bind with i915 gfx */
 291 #define AZX_DCAPS_INTEL_PCH_NOPM \
 292         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
 293
 294 /* PCH for HSW/BDW; with runtime PM */
 295 /* no i915 binding for this as HSW/BDW has another controller for HDMI */
 296 #define AZX_DCAPS_INTEL_PCH \
 297         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
 298
 299 /* HSW HDMI */
 300 #define AZX_DCAPS_INTEL_HASWELL \
 301         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
 302          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
 303          AZX_DCAPS_SNOOP_TYPE(SCH))
 304
 305 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
 306 #define AZX_DCAPS_INTEL_BROADWELL \
 307         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
 308          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
 309          AZX_DCAPS_SNOOP_TYPE(SCH))
 310
 311 #define AZX_DCAPS_INTEL_BAYTRAIL \
 312         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
 313
 314 #define AZX_DCAPS_INTEL_BRASWELL \
 315         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 316          AZX_DCAPS_I915_COMPONENT)
 317
 318 #define AZX_DCAPS_INTEL_SKYLAKE \
 319         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 320          AZX_DCAPS_SYNC_WRITE |\
 321          AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)
 322
 323 #define AZX_DCAPS_INTEL_BROXTON         AZX_DCAPS_INTEL_SKYLAKE
 324
 325 /* quirks for ATI SB / AMD Hudson */
 326 #define AZX_DCAPS_PRESET_ATI_SB \
 327         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
 328          AZX_DCAPS_SNOOP_TYPE(ATI))
 329
 330 /* quirks for ATI/AMD HDMI */
 331 #define AZX_DCAPS_PRESET_ATI_HDMI \
 332         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
 333          AZX_DCAPS_NO_MSI64)
 334
 335 /* quirks for ATI HDMI with snoop off */
 336 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
 337         (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
 338
 339 /* quirks for AMD SB */
 340 #define AZX_DCAPS_PRESET_AMD_SB \
 341         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_AMD_WORKAROUND |\
 342          AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME)
 343
 344 /* quirks for Nvidia */
 345 #define AZX_DCAPS_PRESET_NVIDIA \
 346         (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
 347          AZX_DCAPS_SNOOP_TYPE(NVIDIA))
 348
 349 #define AZX_DCAPS_PRESET_CTHDA \
 350         (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
 351          AZX_DCAPS_NO_64BIT |\
 352          AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
 353
 354 /*
 355  * vga_switcheroo support
 356  */
 357 #ifdef SUPPORT_VGA_SWITCHEROO
 358 #define use_vga_switcheroo(chip)        ((chip)->use_vga_switcheroo)
 359 #define needs_eld_notify_link(chip)     ((chip)->bus.keep_power)
 360 #else
 361 #define use_vga_switcheroo(chip)        0
 362 #define needs_eld_notify_link(chip)     false
 363 #endif
 364
 365 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
 366                                         ((pci)->device == 0x0c0c) || \
 367                                         ((pci)->device == 0x0d0c) || \
 368                                         ((pci)->device == 0x160c))
 369
 370 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
 371 #define IS_CFL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa348)
 372 #define IS_CNL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9dc8)
 373
 374 static char *driver_short_names[] = {
 375         [AZX_DRIVER_ICH] = "HDA Intel",
 376         [AZX_DRIVER_PCH] = "HDA Intel PCH",
 377         [AZX_DRIVER_SCH] = "HDA Intel MID",
 378         [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
 379         [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
 380         [AZX_DRIVER_ATI] = "HDA ATI SB",
 381         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 382         [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
 383         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 384         [AZX_DRIVER_SIS] = "HDA SIS966",
 385         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 386         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 387         [AZX_DRIVER_TERA] = "HDA Teradici",
 388         [AZX_DRIVER_CTX] = "HDA Creative",
 389         [AZX_DRIVER_CTHDA] = "HDA Creative",
 390         [AZX_DRIVER_CMEDIA] = "HDA C-Media",
 391         [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin",
 392         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 393 };
 394
 395 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 396 static void set_default_power_save(struct azx *chip);
 397
 398 /*
 399  * initialize the PCI registers
 400  */
 401 /* update bits in a PCI register byte */
 402 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
 403                             unsigned char mask, unsigned char val)
 404 {
 405         unsigned char data;
 406
 407         pci_read_config_byte(pci, reg, &data);
 408         data &= ~mask;
 409         data |= (val & mask);
 410         pci_write_config_byte(pci, reg, data);
 411 }
 412
 413 static void azx_init_pci(struct azx *chip)
 414 {
 415         int snoop_type = azx_get_snoop_type(chip);
 416
 417         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
 418          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
 419          * Ensuring these bits are 0 clears playback static on some HD Audio
 420          * codecs.
 421          * The PCI register TCSEL is defined in the Intel manuals.
 422          */
 423         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
 424                 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
 425                 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
 426         }
 427
 428         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
 429          * we need to enable snoop.
 430          */
 431         if (snoop_type == AZX_SNOOP_TYPE_ATI) {
 432                 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
 433                         azx_snoop(chip));
 434                 update_pci_byte(chip->pci,
 435                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
 436                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
 437         }
 438
 439         /* For NVIDIA HDA, enable snoop */
 440         if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
 441                 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
 442                         azx_snoop(chip));
 443                 update_pci_byte(chip->pci,
 444                                 NVIDIA_HDA_TRANSREG_ADDR,
 445                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
 446                 update_pci_byte(chip->pci,
 447                                 NVIDIA_HDA_ISTRM_COH,
 448                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 449                 update_pci_byte(chip->pci,
 450                                 NVIDIA_HDA_OSTRM_COH,
 451                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 452         }
 453
 454         /* Enable SCH/PCH snoop if needed */
 455         if (snoop_type == AZX_SNOOP_TYPE_SCH) {
 456                 unsigned short snoop;
 457                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
 458                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
 459                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
 460                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
 461                         if (!azx_snoop(chip))
 462                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
 463                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
 464                         pci_read_config_word(chip->pci,
 465                                 INTEL_SCH_HDA_DEVC, &snoop);
 466                 }
 467                 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
 468                         (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
 469                         "Disabled" : "Enabled");
 470         }
 471 }
 472
 473 /*
 474  * In BXT-P A0, HD-Audio DMA requests is later than expected,
 475  * and makes an audio stream sensitive to system latencies when
 476  * 24/32 bits are playing.
 477  * Adjusting threshold of DMA fifo to force the DMA request
 478  * sooner to improve latency tolerance at the expense of power.
 479  */
 480 static void bxt_reduce_dma_latency(struct azx *chip)
 481 {
 482         u32 val;
 483
 484         val = azx_readl(chip, VS_EM4L);
 485         val &= (0x3 << 20);
 486         azx_writel(chip, VS_EM4L, val);
 487 }
 488
 489 /*
 490  * ML_LCAP bits:
 491  *  bit 0: 6 MHz Supported
 492  *  bit 1: 12 MHz Supported
 493  *  bit 2: 24 MHz Supported
 494  *  bit 3: 48 MHz Supported
 495  *  bit 4: 96 MHz Supported
 496  *  bit 5: 192 MHz Supported
 497  */
 498 static int intel_get_lctl_scf(struct azx *chip)
 499 {
 500         struct hdac_bus *bus = azx_bus(chip);
 501         static int preferred_bits[] = { 2, 3, 1, 4, 5 };
 502         u32 val, t;
 503         int i;
 504
 505         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
 506
 507         for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
 508                 t = preferred_bits[i];
 509                 if (val & (1 << t))
 510                         return t;
 511         }
 512
 513         dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
 514         return 0;
 515 }
 516
 517 static int intel_ml_lctl_set_power(struct azx *chip, int state)
 518 {
 519         struct hdac_bus *bus = azx_bus(chip);
 520         u32 val;
 521         int timeout;
 522
 523         /*
 524          * the codecs are sharing the first link setting by default
 525          * If other links are enabled for stream, they need similar fix
 526          */
 527         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 528         val &= ~AZX_MLCTL_SPA;
 529         val |= state << AZX_MLCTL_SPA_SHIFT;
 530         writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 531         /* wait for CPA */
 532         timeout = 50;
 533         while (timeout) {
 534                 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
 535                     AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT))
 536                         return 0;
 537                 timeout--;
 538                 udelay(10);
 539         }
 540
 541         return -1;
 542 }
 543
 544 static void intel_init_lctl(struct azx *chip)
 545 {
 546         struct hdac_bus *bus = azx_bus(chip);
 547         u32 val;
 548         int ret;
 549
 550         /* 0. check lctl register value is correct or not */
 551         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 552         /* if SCF is already set, let's use it */
 553         if ((val & ML_LCTL_SCF_MASK) != 0)
 554                 return;
 555
 556         /*
 557          * Before operating on SPA, CPA must match SPA.
 558          * Any deviation may result in undefined behavior.
 559          */
 560         if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) !=
 561                 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT))
 562                 return;
 563
 564         /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
 565         ret = intel_ml_lctl_set_power(chip, 0);
 566         udelay(100);
 567         if (ret)
 568                 goto set_spa;
 569
 570         /* 2. update SCF to select a properly audio clock*/
 571         val &= ~ML_LCTL_SCF_MASK;
 572         val |= intel_get_lctl_scf(chip);
 573         writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 574
 575 set_spa:
 576         /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
 577         intel_ml_lctl_set_power(chip, 1);
 578         udelay(100);
 579 }
 580
 581 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
 582 {
 583         struct hdac_bus *bus = azx_bus(chip);
 584         struct pci_dev *pci = chip->pci;
 585         u32 val;
 586
 587         snd_hdac_set_codec_wakeup(bus, true);
 588         if (chip->driver_type == AZX_DRIVER_SKL) {
 589                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 590                 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
 591                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 592         }
 593         azx_init_chip(chip, full_reset);
 594         if (chip->driver_type == AZX_DRIVER_SKL) {
 595                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 596                 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
 597                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 598         }
 599
 600         snd_hdac_set_codec_wakeup(bus, false);
 601
 602         /* reduce dma latency to avoid noise */
 603         if (IS_BXT(pci))
 604                 bxt_reduce_dma_latency(chip);
 605
 606         if (bus->mlcap != NULL)
 607                 intel_init_lctl(chip);
 608 }
 609
 610 /* calculate runtime delay from LPIB */
 611 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
 612                                    unsigned int pos)
 613 {
 614         struct snd_pcm_substream *substream = azx_dev->core.substream;
 615         int stream = substream->stream;
 616         unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
 617         int delay;
 618
 619         if (stream == SNDRV_PCM_STREAM_PLAYBACK)
 620                 delay = pos - lpib_pos;
 621         else
 622                 delay = lpib_pos - pos;
 623         if (delay < 0) {
 624                 if (delay >= azx_dev->core.delay_negative_threshold)
 625                         delay = 0;
 626                 else
 627                         delay += azx_dev->core.bufsize;
 628         }
 629
 630         if (delay >= azx_dev->core.period_bytes) {
 631                 dev_info(chip->card->dev,
 632                          "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
 633                          delay, azx_dev->core.period_bytes);
 634                 delay = 0;
 635                 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
 636                 chip->get_delay[stream] = NULL;
 637         }
 638
 639         return bytes_to_frames(substream->runtime, delay);
 640 }
 641
 642 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
 643
 644 /* called from IRQ */
 645 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
 646 {
 647         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 648         int ok;
 649
 650         ok = azx_position_ok(chip, azx_dev);
 651         if (ok == 1) {
 652                 azx_dev->irq_pending = 0;
 653                 return ok;
 654         } else if (ok == 0) {
 655                 /* bogus IRQ, process it later */
 656                 azx_dev->irq_pending = 1;
 657                 schedule_work(&hda->irq_pending_work);
 658         }
 659         return 0;
 660 }
 661
 662 #define display_power(chip, enable) \
 663         snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable)
 664
 665 /*
 666  * Check whether the current DMA position is acceptable for updating
 667  * periods.  Returns non-zero if it's OK.
 668  *
 669  * Many HD-audio controllers appear pretty inaccurate about
 670  * the update-IRQ timing.  The IRQ is issued before actually the
 671  * data is processed.  So, we need to process it afterwords in a
 672  * workqueue.
 673  */
 674 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
 675 {
 676         struct snd_pcm_substream *substream = azx_dev->core.substream;
 677         int stream = substream->stream;
 678         u32 wallclk;
 679         unsigned int pos;
 680
 681         wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
 682         if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
 683                 return -1;      /* bogus (too early) interrupt */
 684
 685         if (chip->get_position[stream])
 686                 pos = chip->get_position[stream](chip, azx_dev);
 687         else { /* use the position buffer as default */
 688                 pos = azx_get_pos_posbuf(chip, azx_dev);
 689                 if (!pos || pos == (u32)-1) {
 690                         dev_info(chip->card->dev,
 691                                  "Invalid position buffer, using LPIB read method instead.\n");
 692                         chip->get_position[stream] = azx_get_pos_lpib;
 693                         if (chip->get_position[0] == azx_get_pos_lpib &&
 694                             chip->get_position[1] == azx_get_pos_lpib)
 695                                 azx_bus(chip)->use_posbuf = false;
 696                         pos = azx_get_pos_lpib(chip, azx_dev);
 697                         chip->get_delay[stream] = NULL;
 698                 } else {
 699                         chip->get_position[stream] = azx_get_pos_posbuf;
 700                         if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
 701                                 chip->get_delay[stream] = azx_get_delay_from_lpib;
 702                 }
 703         }
 704
 705         if (pos >= azx_dev->core.bufsize)
 706                 pos = 0;
 707
 708         if (WARN_ONCE(!azx_dev->core.period_bytes,
 709                       "hda-intel: zero azx_dev->period_bytes"))
 710                 return -1; /* this shouldn't happen! */
 711         if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
 712             pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
 713                 /* NG - it's below the first next period boundary */
 714                 return chip->bdl_pos_adj ? 0 : -1;
 715         azx_dev->core.start_wallclk += wallclk;
 716         return 1; /* OK, it's fine */
 717 }
 718
 719 /*
 720  * The work for pending PCM period updates.
 721  */
 722 static void azx_irq_pending_work(struct work_struct *work)
 723 {
 724         struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
 725         struct azx *chip = &hda->chip;
 726         struct hdac_bus *bus = azx_bus(chip);
 727         struct hdac_stream *s;
 728         int pending, ok;
 729
 730         if (!hda->irq_pending_warned) {
 731                 dev_info(chip->card->dev,
 732                          "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
 733                          chip->card->number);
 734                 hda->irq_pending_warned = 1;
 735         }
 736
 737         for (;;) {
 738                 pending = 0;
 739                 spin_lock_irq(&bus->reg_lock);
 740                 list_for_each_entry(s, &bus->stream_list, list) {
 741                         struct azx_dev *azx_dev = stream_to_azx_dev(s);
 742                         if (!azx_dev->irq_pending ||
 743                             !s->substream ||
 744                             !s->running)
 745                                 continue;
 746                         ok = azx_position_ok(chip, azx_dev);
 747                         if (ok > 0) {
 748                                 azx_dev->irq_pending = 0;
 749                                 spin_unlock(&bus->reg_lock);
 750                                 snd_pcm_period_elapsed(s->substream);
 751                                 spin_lock(&bus->reg_lock);
 752                         } else if (ok < 0) {
 753                                 pending = 0;    /* too early */
 754                         } else
 755                                 pending++;
 756                 }
 757                 spin_unlock_irq(&bus->reg_lock);
 758                 if (!pending)
 759                         return;
 760                 msleep(1);
 761         }
 762 }
 763
 764 /* clear irq_pending flags and assure no on-going workq */
 765 static void azx_clear_irq_pending(struct azx *chip)
 766 {
 767         struct hdac_bus *bus = azx_bus(chip);
 768         struct hdac_stream *s;
 769
 770         spin_lock_irq(&bus->reg_lock);
 771         list_for_each_entry(s, &bus->stream_list, list) {
 772                 struct azx_dev *azx_dev = stream_to_azx_dev(s);
 773                 azx_dev->irq_pending = 0;
 774         }
 775         spin_unlock_irq(&bus->reg_lock);
 776 }
 777
 778 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
 779 {
 780         struct hdac_bus *bus = azx_bus(chip);
 781
 782         if (request_irq(chip->pci->irq, azx_interrupt,
 783                         chip->msi ? 0 : IRQF_SHARED,
 784                         chip->card->irq_descr, chip)) {
 785                 dev_err(chip->card->dev,
 786                         "unable to grab IRQ %d, disabling device\n",
 787                         chip->pci->irq);
 788                 if (do_disconnect)
 789                         snd_card_disconnect(chip->card);
 790                 return -1;
 791         }
 792         bus->irq = chip->pci->irq;
 793         pci_intx(chip->pci, !chip->msi);
 794         return 0;
 795 }
 796
 797 /* get the current DMA position with correction on VIA chips */
 798 static unsigned int azx_via_get_position(struct azx *chip,
 799                                          struct azx_dev *azx_dev)
 800 {
 801         unsigned int link_pos, mini_pos, bound_pos;
 802         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
 803         unsigned int fifo_size;
 804
 805         link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
 806         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 807                 /* Playback, no problem using link position */
 808                 return link_pos;
 809         }
 810
 811         /* Capture */
 812         /* For new chipset,
 813          * use mod to get the DMA position just like old chipset
 814          */
 815         mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
 816         mod_dma_pos %= azx_dev->core.period_bytes;
 817
 818         fifo_size = azx_stream(azx_dev)->fifo_size - 1;
 819
 820         if (azx_dev->insufficient) {
 821                 /* Link position never gather than FIFO size */
 822                 if (link_pos <= fifo_size)
 823                         return 0;
 824
 825                 azx_dev->insufficient = 0;
 826         }
 827
 828         if (link_pos <= fifo_size)
 829                 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
 830         else
 831                 mini_pos = link_pos - fifo_size;
 832
 833         /* Find nearest previous boudary */
 834         mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
 835         mod_link_pos = link_pos % azx_dev->core.period_bytes;
 836         if (mod_link_pos >= fifo_size)
 837                 bound_pos = link_pos - mod_link_pos;
 838         else if (mod_dma_pos >= mod_mini_pos)
 839                 bound_pos = mini_pos - mod_mini_pos;
 840         else {
 841                 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
 842                 if (bound_pos >= azx_dev->core.bufsize)
 843                         bound_pos = 0;
 844         }
 845
 846         /* Calculate real DMA position we want */
 847         return bound_pos + mod_dma_pos;
 848 }
 849
 850 #define AMD_FIFO_SIZE   32
 851
 852 /* get the current DMA position with FIFO size correction */
 853 static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev)
 854 {
 855         struct snd_pcm_substream *substream = azx_dev->core.substream;
 856         struct snd_pcm_runtime *runtime = substream->runtime;
 857         unsigned int pos, delay;
 858
 859         pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
 860         if (!runtime)
 861                 return pos;
 862
 863         runtime->delay = AMD_FIFO_SIZE;
 864         delay = frames_to_bytes(runtime, AMD_FIFO_SIZE);
 865         if (azx_dev->insufficient) {
 866                 if (pos < delay) {
 867                         delay = pos;
 868                         runtime->delay = bytes_to_frames(runtime, pos);
 869                 } else {
 870                         azx_dev->insufficient = 0;
 871                 }
 872         }
 873
 874         /* correct the DMA position for capture stream */
 875         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
 876                 if (pos < delay)
 877                         pos += azx_dev->core.bufsize;
 878                 pos -= delay;
 879         }
 880
 881         return pos;
 882 }
 883
 884 static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev,
 885                                    unsigned int pos)
 886 {
 887         struct snd_pcm_substream *substream = azx_dev->core.substream;
 888
 889         /* just read back the calculated value in the above */
 890         return substream->runtime->delay;
 891 }
 892
 893 static unsigned int azx_skl_get_dpib_pos(struct azx *chip,
 894                                          struct azx_dev *azx_dev)
 895 {
 896         return _snd_hdac_chip_readl(azx_bus(chip),
 897                                     AZX_REG_VS_SDXDPIB_XBASE +
 898                                     (AZX_REG_VS_SDXDPIB_XINTERVAL *
 899                                      azx_dev->core.index));
 900 }
 901
 902 /* get the current DMA position with correction on SKL+ chips */
 903 static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev)
 904 {
 905         /* DPIB register gives a more accurate position for playback */
 906         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 907                 return azx_skl_get_dpib_pos(chip, azx_dev);
 908
 909         /* For capture, we need to read posbuf, but it requires a delay
 910          * for the possible boundary overlap; the read of DPIB fetches the
 911          * actual posbuf
 912          */
 913         udelay(20);
 914         azx_skl_get_dpib_pos(chip, azx_dev);
 915         return azx_get_pos_posbuf(chip, azx_dev);
 916 }
 917
 918 #ifdef CONFIG_PM
 919 static DEFINE_MUTEX(card_list_lock);
 920 static LIST_HEAD(card_list);
 921
 922 static void azx_add_card_list(struct azx *chip)
 923 {
 924         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 925         mutex_lock(&card_list_lock);
 926         list_add(&hda->list, &card_list);
 927         mutex_unlock(&card_list_lock);
 928 }
 929
 930 static void azx_del_card_list(struct azx *chip)
 931 {
 932         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 933         mutex_lock(&card_list_lock);
 934         list_del_init(&hda->list);
 935         mutex_unlock(&card_list_lock);
 936 }
 937
 938 /* trigger power-save check at writing parameter */
 939 static int param_set_xint(const char *val, const struct kernel_param *kp)
 940 {
 941         struct hda_intel *hda;
 942         struct azx *chip;
 943         int prev = power_save;
 944         int ret = param_set_int(val, kp);
 945
 946         if (ret || prev == power_save)
 947                 return ret;
 948
 949         mutex_lock(&card_list_lock);
 950         list_for_each_entry(hda, &card_list, list) {
 951                 chip = &hda->chip;
 952                 if (!hda->probe_continued || chip->disabled)
 953                         continue;
 954                 snd_hda_set_power_save(&chip->bus, power_save * 1000);
 955         }
 956         mutex_unlock(&card_list_lock);
 957         return 0;
 958 }
 959
 960 /*
 961  * power management
 962  */
 963 static bool azx_is_pm_ready(struct snd_card *card)
 964 {
 965         struct azx *chip;
 966         struct hda_intel *hda;
 967
 968         if (!card)
 969                 return false;
 970         chip = card->private_data;
 971         hda = container_of(chip, struct hda_intel, chip);
 972         if (chip->disabled || hda->init_failed || !chip->running)
 973                 return false;
 974         return true;
 975 }
 976
 977 static void __azx_runtime_suspend(struct azx *chip)
 978 {
 979         azx_stop_chip(chip);
 980         azx_enter_link_reset(chip);
 981         azx_clear_irq_pending(chip);
 982         display_power(chip, false);
 983 }
 984
 985 static void __azx_runtime_resume(struct azx *chip, bool from_rt)
 986 {
 987         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 988         struct hdac_bus *bus = azx_bus(chip);
 989         struct hda_codec *codec;
 990         int status;
 991
 992         display_power(chip, true);
 993         if (hda->need_i915_power)
 994                 snd_hdac_i915_set_bclk(bus);
 995
 996         /* Read STATESTS before controller reset */
 997         status = azx_readw(chip, STATESTS);
 998
 999         azx_init_pci(chip);
1000         hda_intel_init_chip(chip, true);
1001
1002         if (status && from_rt) {
1003                 list_for_each_codec(codec, &chip->bus)
1004                         if (status & (1 << codec->addr))
1005                                 schedule_delayed_work(&codec->jackpoll_work,
1006                                                       codec->jackpoll_interval);
1007         }
1008
1009         /* power down again for link-controlled chips */
1010         if (!hda->need_i915_power)
1011                 display_power(chip, false);
1012 }
1013
1014 #ifdef CONFIG_PM_SLEEP
1015 static int azx_suspend(struct device *dev)
1016 {
1017         struct snd_card *card = dev_get_drvdata(dev);
1018         struct azx *chip;
1019         struct hdac_bus *bus;
1020
1021         if (!azx_is_pm_ready(card))
1022                 return 0;
1023
1024         chip = card->private_data;
1025         bus = azx_bus(chip);
1026         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1027         __azx_runtime_suspend(chip);
1028         if (bus->irq >= 0) {
1029                 free_irq(bus->irq, chip);
1030                 bus->irq = -1;
1031         }
1032
1033         if (chip->msi)
1034                 pci_disable_msi(chip->pci);
1035
1036         trace_azx_suspend(chip);
1037         return 0;
1038 }
1039
1040 static int azx_resume(struct device *dev)
1041 {
1042         struct snd_card *card = dev_get_drvdata(dev);
1043         struct azx *chip;
1044
1045         if (!azx_is_pm_ready(card))
1046                 return 0;
1047
1048         chip = card->private_data;
1049         if (chip->msi)
1050                 if (pci_enable_msi(chip->pci) < 0)
1051                         chip->msi = 0;
1052         if (azx_acquire_irq(chip, 1) < 0)
1053                 return -EIO;
1054         __azx_runtime_resume(chip, false);
1055         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1056
1057         trace_azx_resume(chip);
1058         return 0;
1059 }
1060
1061 /* put codec down to D3 at hibernation for Intel SKL+;
1062  * otherwise BIOS may still access the codec and screw up the driver
1063  */
1064 static int azx_freeze_noirq(struct device *dev)
1065 {
1066         struct snd_card *card = dev_get_drvdata(dev);
1067         struct azx *chip = card->private_data;
1068         struct pci_dev *pci = to_pci_dev(dev);
1069
1070         if (chip->driver_type == AZX_DRIVER_SKL)
1071                 pci_set_power_state(pci, PCI_D3hot);
1072
1073         return 0;
1074 }
1075
1076 static int azx_thaw_noirq(struct device *dev)
1077 {
1078         struct snd_card *card = dev_get_drvdata(dev);
1079         struct azx *chip = card->private_data;
1080         struct pci_dev *pci = to_pci_dev(dev);
1081
1082         if (chip->driver_type == AZX_DRIVER_SKL)
1083                 pci_set_power_state(pci, PCI_D0);
1084
1085         return 0;
1086 }
1087 #endif /* CONFIG_PM_SLEEP */
1088
1089 static int azx_runtime_suspend(struct device *dev)
1090 {
1091         struct snd_card *card = dev_get_drvdata(dev);
1092         struct azx *chip;
1093
1094         if (!azx_is_pm_ready(card))
1095                 return 0;
1096         chip = card->private_data;
1097         if (!azx_has_pm_runtime(chip))
1098                 return 0;
1099
1100         /* enable controller wake up event */
1101         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
1102                   STATESTS_INT_MASK);
1103
1104         __azx_runtime_suspend(chip);
1105         trace_azx_runtime_suspend(chip);
1106         return 0;
1107 }
1108
1109 static int azx_runtime_resume(struct device *dev)
1110 {
1111         struct snd_card *card = dev_get_drvdata(dev);
1112         struct azx *chip;
1113
1114         if (!azx_is_pm_ready(card))
1115                 return 0;
1116         chip = card->private_data;
1117         if (!azx_has_pm_runtime(chip))
1118                 return 0;
1119         __azx_runtime_resume(chip, true);
1120
1121         /* disable controller Wake Up event*/
1122         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1123                         ~STATESTS_INT_MASK);
1124
1125         trace_azx_runtime_resume(chip);
1126         return 0;
1127 }
1128
1129 static int azx_runtime_idle(struct device *dev)
1130 {
1131         struct snd_card *card = dev_get_drvdata(dev);
1132         struct azx *chip;
1133         struct hda_intel *hda;
1134
1135         if (!card)
1136                 return 0;
1137
1138         chip = card->private_data;
1139         hda = container_of(chip, struct hda_intel, chip);
1140         if (chip->disabled || hda->init_failed)
1141                 return 0;
1142
1143         if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1144             azx_bus(chip)->codec_powered || !chip->running)
1145                 return -EBUSY;
1146
1147         /* ELD notification gets broken when HD-audio bus is off */
1148         if (needs_eld_notify_link(chip))
1149                 return -EBUSY;
1150
1151         return 0;
1152 }
1153
1154 static const struct dev_pm_ops azx_pm = {
1155         SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1156 #ifdef CONFIG_PM_SLEEP
1157         .freeze_noirq = azx_freeze_noirq,
1158         .thaw_noirq = azx_thaw_noirq,
1159 #endif
1160         SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1161 };
1162
1163 #define AZX_PM_OPS      &azx_pm
1164 #else
1165 #define azx_add_card_list(chip) /* NOP */
1166 #define azx_del_card_list(chip) /* NOP */
1167 #define AZX_PM_OPS      NULL
1168 #endif /* CONFIG_PM */
1169
1170
1171 static int azx_probe_continue(struct azx *chip);
1172
1173 #ifdef SUPPORT_VGA_SWITCHEROO
1174 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1175
1176 static void azx_vs_set_state(struct pci_dev *pci,
1177                              enum vga_switcheroo_state state)
1178 {
1179         struct snd_card *card = pci_get_drvdata(pci);
1180         struct azx *chip = card->private_data;
1181         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1182         struct hda_codec *codec;
1183         bool disabled;
1184
1185         wait_for_completion(&hda->probe_wait);
1186         if (hda->init_failed)
1187                 return;
1188
1189         disabled = (state == VGA_SWITCHEROO_OFF);
1190         if (chip->disabled == disabled)
1191                 return;
1192
1193         if (!hda->probe_continued) {
1194                 chip->disabled = disabled;
1195                 if (!disabled) {
1196                         dev_info(chip->card->dev,
1197                                  "Start delayed initialization\n");
1198                         if (azx_probe_continue(chip) < 0) {
1199                                 dev_err(chip->card->dev, "initialization error\n");
1200                                 hda->init_failed = true;
1201                         }
1202                 }
1203         } else {
1204                 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1205                          disabled ? "Disabling" : "Enabling");
1206                 if (disabled) {
1207                         list_for_each_codec(codec, &chip->bus) {
1208                                 pm_runtime_suspend(hda_codec_dev(codec));
1209                                 pm_runtime_disable(hda_codec_dev(codec));
1210                         }
1211                         pm_runtime_suspend(card->dev);
1212                         pm_runtime_disable(card->dev);
1213                         /* when we get suspended by vga_switcheroo we end up in D3cold,
1214                          * however we have no ACPI handle, so pci/acpi can't put us there,
1215                          * put ourselves there */
1216                         pci->current_state = PCI_D3cold;
1217                         chip->disabled = true;
1218                         if (snd_hda_lock_devices(&chip->bus))
1219                                 dev_warn(chip->card->dev,
1220                                          "Cannot lock devices!\n");
1221                 } else {
1222                         snd_hda_unlock_devices(&chip->bus);
1223                         chip->disabled = false;
1224                         pm_runtime_enable(card->dev);
1225                         list_for_each_codec(codec, &chip->bus) {
1226                                 pm_runtime_enable(hda_codec_dev(codec));
1227                                 pm_runtime_resume(hda_codec_dev(codec));
1228                         }
1229                 }
1230         }
1231 }
1232
1233 static bool azx_vs_can_switch(struct pci_dev *pci)
1234 {
1235         struct snd_card *card = pci_get_drvdata(pci);
1236         struct azx *chip = card->private_data;
1237         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1238
1239         wait_for_completion(&hda->probe_wait);
1240         if (hda->init_failed)
1241                 return false;
1242         if (chip->disabled || !hda->probe_continued)
1243                 return true;
1244         if (snd_hda_lock_devices(&chip->bus))
1245                 return false;
1246         snd_hda_unlock_devices(&chip->bus);
1247         return true;
1248 }
1249
1250 /*
1251  * The discrete GPU cannot power down unless the HDA controller runtime
1252  * suspends, so activate runtime PM on codecs even if power_save == 0.
1253  */
1254 static void setup_vga_switcheroo_runtime_pm(struct azx *chip)
1255 {
1256         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1257         struct hda_codec *codec;
1258
1259         if (hda->use_vga_switcheroo && !needs_eld_notify_link(chip)) {
1260                 list_for_each_codec(codec, &chip->bus)
1261                         codec->auto_runtime_pm = 1;
1262                 /* reset the power save setup */
1263                 if (chip->running)
1264                         set_default_power_save(chip);
1265         }
1266 }
1267
1268 static void azx_vs_gpu_bound(struct pci_dev *pci,
1269                              enum vga_switcheroo_client_id client_id)
1270 {
1271         struct snd_card *card = pci_get_drvdata(pci);
1272         struct azx *chip = card->private_data;
1273
1274         if (client_id == VGA_SWITCHEROO_DIS)
1275                 chip->bus.keep_power = 0;
1276         setup_vga_switcheroo_runtime_pm(chip);
1277 }
1278
1279 static void init_vga_switcheroo(struct azx *chip)
1280 {
1281         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1282         struct pci_dev *p = get_bound_vga(chip->pci);
1283         if (p) {
1284                 dev_info(chip->card->dev,
1285                          "Handle vga_switcheroo audio client\n");
1286                 hda->use_vga_switcheroo = 1;
1287                 chip->bus.keep_power = 1; /* cleared in either gpu_bound op or codec probe */
1288                 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME;
1289                 pci_dev_put(p);
1290         }
1291 }
1292
1293 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1294         .set_gpu_state = azx_vs_set_state,
1295         .can_switch = azx_vs_can_switch,
1296         .gpu_bound = azx_vs_gpu_bound,
1297 };
1298
1299 static int register_vga_switcheroo(struct azx *chip)
1300 {
1301         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1302         struct pci_dev *p;
1303         int err;
1304
1305         if (!hda->use_vga_switcheroo)
1306                 return 0;
1307
1308         p = get_bound_vga(chip->pci);
1309         err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p);
1310         pci_dev_put(p);
1311
1312         if (err < 0)
1313                 return err;
1314         hda->vga_switcheroo_registered = 1;
1315
1316         return 0;
1317 }
1318 #else
1319 #define init_vga_switcheroo(chip)               /* NOP */
1320 #define register_vga_switcheroo(chip)           0
1321 #define check_hdmi_disabled(pci)        false
1322 #define setup_vga_switcheroo_runtime_pm(chip)   /* NOP */
1323 #endif /* SUPPORT_VGA_SWITCHER */
1324
1325 /*
1326  * destructor
1327  */
1328 static int azx_free(struct azx *chip)
1329 {
1330         struct pci_dev *pci = chip->pci;
1331         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1332         struct hdac_bus *bus = azx_bus(chip);
1333
1334         if (azx_has_pm_runtime(chip) && chip->running)
1335                 pm_runtime_get_noresume(&pci->dev);
1336         chip->running = 0;
1337
1338         azx_del_card_list(chip);
1339
1340         hda->init_failed = 1; /* to be sure */
1341         complete_all(&hda->probe_wait);
1342
1343         if (use_vga_switcheroo(hda)) {
1344                 if (chip->disabled && hda->probe_continued)
1345                         snd_hda_unlock_devices(&chip->bus);
1346                 if (hda->vga_switcheroo_registered)
1347                         vga_switcheroo_unregister_client(chip->pci);
1348         }
1349
1350         if (bus->chip_init) {
1351                 azx_clear_irq_pending(chip);
1352                 azx_stop_all_streams(chip);
1353                 azx_stop_chip(chip);
1354         }
1355
1356         if (bus->irq >= 0)
1357                 free_irq(bus->irq, (void*)chip);
1358         if (chip->msi)
1359                 pci_disable_msi(chip->pci);
1360         iounmap(bus->remap_addr);
1361
1362         azx_free_stream_pages(chip);
1363         azx_free_streams(chip);
1364         snd_hdac_bus_exit(bus);
1365
1366         if (chip->region_requested)
1367                 pci_release_regions(chip->pci);
1368
1369         pci_disable_device(chip->pci);
1370 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1371         release_firmware(chip->fw);
1372 #endif
1373         display_power(chip, false);
1374
1375         if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
1376                 snd_hdac_i915_exit(bus);
1377         kfree(hda);
1378
1379         return 0;
1380 }
1381
1382 static int azx_dev_disconnect(struct snd_device *device)
1383 {
1384         struct azx *chip = device->device_data;
1385
1386         chip->bus.shutdown = 1;
1387         return 0;
1388 }
1389
1390 static int azx_dev_free(struct snd_device *device)
1391 {
1392         return azx_free(device->device_data);
1393 }
1394
1395 #ifdef SUPPORT_VGA_SWITCHEROO
1396 /*
1397  * Check of disabled HDMI controller by vga_switcheroo
1398  */
1399 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1400 {
1401         struct pci_dev *p;
1402
1403         /* check only discrete GPU */
1404         switch (pci->vendor) {
1405         case PCI_VENDOR_ID_ATI:
1406         case PCI_VENDOR_ID_AMD:
1407         case PCI_VENDOR_ID_NVIDIA:
1408                 if (pci->devfn == 1) {
1409                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1410                                                         pci->bus->number, 0);
1411                         if (p) {
1412                                 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY)
1413                                         return p;
1414                                 pci_dev_put(p);
1415                         }
1416                 }
1417                 break;
1418         }
1419         return NULL;
1420 }
1421
1422 static bool check_hdmi_disabled(struct pci_dev *pci)
1423 {
1424         bool vga_inactive = false;
1425         struct pci_dev *p = get_bound_vga(pci);
1426
1427         if (p) {
1428                 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1429                         vga_inactive = true;
1430                 pci_dev_put(p);
1431         }
1432         return vga_inactive;
1433 }
1434 #endif /* SUPPORT_VGA_SWITCHEROO */
1435
1436 /*
1437  * white/black-listing for position_fix
1438  */
1439 static struct snd_pci_quirk position_fix_list[] = {
1440         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1441         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1442         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1443         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1444         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1445         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1446         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1447         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1448         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1449         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1450         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1451         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1452         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1453         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1454         {}
1455 };
1456
1457 static int check_position_fix(struct azx *chip, int fix)
1458 {
1459         const struct snd_pci_quirk *q;
1460
1461         switch (fix) {
1462         case POS_FIX_AUTO:
1463         case POS_FIX_LPIB:
1464         case POS_FIX_POSBUF:
1465         case POS_FIX_VIACOMBO:
1466         case POS_FIX_COMBO:
1467         case POS_FIX_SKL:
1468         case POS_FIX_FIFO:
1469                 return fix;
1470         }
1471
1472         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1473         if (q) {
1474                 dev_info(chip->card->dev,
1475                          "position_fix set to %d for device %04x:%04x\n",
1476                          q->value, q->subvendor, q->subdevice);
1477                 return q->value;
1478         }
1479
1480         /* Check VIA/ATI HD Audio Controller exist */
1481         if (chip->driver_type == AZX_DRIVER_VIA) {
1482                 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1483                 return POS_FIX_VIACOMBO;
1484         }
1485         if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) {
1486                 dev_dbg(chip->card->dev, "Using FIFO position fix\n");
1487                 return POS_FIX_FIFO;
1488         }
1489         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1490                 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1491                 return POS_FIX_LPIB;
1492         }
1493         if (chip->driver_type == AZX_DRIVER_SKL) {
1494                 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1495                 return POS_FIX_SKL;
1496         }
1497         return POS_FIX_AUTO;
1498 }
1499
1500 static void assign_position_fix(struct azx *chip, int fix)
1501 {
1502         static azx_get_pos_callback_t callbacks[] = {
1503                 [POS_FIX_AUTO] = NULL,
1504                 [POS_FIX_LPIB] = azx_get_pos_lpib,
1505                 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1506                 [POS_FIX_VIACOMBO] = azx_via_get_position,
1507                 [POS_FIX_COMBO] = azx_get_pos_lpib,
1508                 [POS_FIX_SKL] = azx_get_pos_skl,
1509                 [POS_FIX_FIFO] = azx_get_pos_fifo,
1510         };
1511
1512         chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1513
1514         /* combo mode uses LPIB only for playback */
1515         if (fix == POS_FIX_COMBO)
1516                 chip->get_position[1] = NULL;
1517
1518         if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
1519             (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1520                 chip->get_delay[0] = chip->get_delay[1] =
1521                         azx_get_delay_from_lpib;
1522         }
1523
1524         if (fix == POS_FIX_FIFO)
1525                 chip->get_delay[0] = chip->get_delay[1] =
1526                         azx_get_delay_from_fifo;
1527 }
1528
1529 /*
1530  * black-lists for probe_mask
1531  */
1532 static struct snd_pci_quirk probe_mask_list[] = {
1533         /* Thinkpad often breaks the controller communication when accessing
1534          * to the non-working (or non-existing) modem codec slot.
1535          */
1536         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1537         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1538         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1539         /* broken BIOS */
1540         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1541         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1542         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1543         /* forced codec slots */
1544         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1545         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1546         /* WinFast VP200 H (Teradici) user reported broken communication */
1547         SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1548         {}
1549 };
1550
1551 #define AZX_FORCE_CODEC_MASK    0x100
1552
1553 static void check_probe_mask(struct azx *chip, int dev)
1554 {
1555         const struct snd_pci_quirk *q;
1556
1557         chip->codec_probe_mask = probe_mask[dev];
1558         if (chip->codec_probe_mask == -1) {
1559                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1560                 if (q) {
1561                         dev_info(chip->card->dev,
1562                                  "probe_mask set to 0x%x for device %04x:%04x\n",
1563                                  q->value, q->subvendor, q->subdevice);
1564                         chip->codec_probe_mask = q->value;
1565                 }
1566         }
1567
1568         /* check forced option */
1569         if (chip->codec_probe_mask != -1 &&
1570             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1571                 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1572                 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1573                          (int)azx_bus(chip)->codec_mask);
1574         }
1575 }
1576
1577 /*
1578  * white/black-list for enable_msi
1579  */
1580 static struct snd_pci_quirk msi_black_list[] = {
1581         SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1582         SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1583         SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1584         SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1585         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1586         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1587         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1588         SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1589         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1590         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1591         {}
1592 };
1593
1594 static void check_msi(struct azx *chip)
1595 {
1596         const struct snd_pci_quirk *q;
1597
1598         if (enable_msi >= 0) {
1599                 chip->msi = !!enable_msi;
1600                 return;
1601         }
1602         chip->msi = 1;  /* enable MSI as default */
1603         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
1604         if (q) {
1605                 dev_info(chip->card->dev,
1606                          "msi for device %04x:%04x set to %d\n",
1607                          q->subvendor, q->subdevice, q->value);
1608                 chip->msi = q->value;
1609                 return;
1610         }
1611
1612         /* NVidia chipsets seem to cause troubles with MSI */
1613         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1614                 dev_info(chip->card->dev, "Disabling MSI\n");
1615                 chip->msi = 0;
1616         }
1617 }
1618
1619 /* check the snoop mode availability */
1620 static void azx_check_snoop_available(struct azx *chip)
1621 {
1622         int snoop = hda_snoop;
1623
1624         if (snoop >= 0) {
1625                 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1626                          snoop ? "snoop" : "non-snoop");
1627                 chip->snoop = snoop;
1628                 chip->uc_buffer = !snoop;
1629                 return;
1630         }
1631
1632         snoop = true;
1633         if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1634             chip->driver_type == AZX_DRIVER_VIA) {
1635                 /* force to non-snoop mode for a new VIA controller
1636                  * when BIOS is set
1637                  */
1638                 u8 val;
1639                 pci_read_config_byte(chip->pci, 0x42, &val);
1640                 if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
1641                                       chip->pci->revision == 0x20))
1642                         snoop = false;
1643         }
1644
1645         if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1646                 snoop = false;
1647
1648         chip->snoop = snoop;
1649         if (!snoop) {
1650                 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1651                 /* C-Media requires non-cached pages only for CORB/RIRB */
1652                 if (chip->driver_type != AZX_DRIVER_CMEDIA)
1653                         chip->uc_buffer = true;
1654         }
1655 }
1656
1657 static void azx_probe_work(struct work_struct *work)
1658 {
1659         struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1660         azx_probe_continue(&hda->chip);
1661 }
1662
1663 static int default_bdl_pos_adj(struct azx *chip)
1664 {
1665         /* some exceptions: Atoms seem problematic with value 1 */
1666         if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1667                 switch (chip->pci->device) {
1668                 case 0x0f04: /* Baytrail */
1669                 case 0x2284: /* Braswell */
1670                         return 32;
1671                 }
1672         }
1673
1674         switch (chip->driver_type) {
1675         case AZX_DRIVER_ICH:
1676         case AZX_DRIVER_PCH:
1677                 return 1;
1678         default:
1679                 return 32;
1680         }
1681 }
1682
1683 /*
1684  * constructor
1685  */
1686 static const struct hda_controller_ops pci_hda_ops;
1687
1688 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1689                       int dev, unsigned int driver_caps,
1690                       struct azx **rchip)
1691 {
1692         static struct snd_device_ops ops = {
1693                 .dev_disconnect = azx_dev_disconnect,
1694                 .dev_free = azx_dev_free,
1695         };
1696         struct hda_intel *hda;
1697         struct azx *chip;
1698         int err;
1699
1700         *rchip = NULL;
1701
1702         err = pci_enable_device(pci);
1703         if (err < 0)
1704                 return err;
1705
1706         hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1707         if (!hda) {
1708                 pci_disable_device(pci);
1709                 return -ENOMEM;
1710         }
1711
1712         chip = &hda->chip;
1713         mutex_init(&chip->open_mutex);
1714         chip->card = card;
1715         chip->pci = pci;
1716         chip->ops = &pci_hda_ops;
1717         chip->driver_caps = driver_caps;
1718         chip->driver_type = driver_caps & 0xff;
1719         check_msi(chip);
1720         chip->dev_index = dev;
1721         if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000)
1722                 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]);
1723         INIT_LIST_HEAD(&chip->pcm_list);
1724         INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1725         INIT_LIST_HEAD(&hda->list);
1726         init_vga_switcheroo(chip);
1727         init_completion(&hda->probe_wait);
1728
1729         assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1730
1731         check_probe_mask(chip, dev);
1732
1733         if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1734                 chip->fallback_to_single_cmd = 1;
1735         else /* explicitly set to single_cmd or not */
1736                 chip->single_cmd = single_cmd;
1737
1738         azx_check_snoop_available(chip);
1739
1740         if (bdl_pos_adj[dev] < 0)
1741                 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1742         else
1743                 chip->bdl_pos_adj = bdl_pos_adj[dev];
1744
1745         err = azx_bus_init(chip, model[dev]);
1746         if (err < 0) {
1747                 kfree(hda);
1748                 pci_disable_device(pci);
1749                 return err;
1750         }
1751
1752         /* use the non-cached pages in non-snoop mode */
1753         if (!azx_snoop(chip))
1754                 azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_UC;
1755
1756         /* Workaround for a communication error on CFL (bko#199007) and CNL */
1757         if (IS_CFL(pci) || IS_CNL(pci))
1758                 azx_bus(chip)->polling_mode = 1;
1759
1760         if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1761                 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1762                 chip->bus.needs_damn_long_delay = 1;
1763         }
1764
1765         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1766         if (err < 0) {
1767                 dev_err(card->dev, "Error creating device [card]!\n");
1768                 azx_free(chip);
1769                 return err;
1770         }
1771
1772         /* continue probing in work context as may trigger request module */
1773         INIT_WORK(&hda->probe_work, azx_probe_work);
1774
1775         *rchip = chip;
1776
1777         return 0;
1778 }
1779
1780 static int azx_first_init(struct azx *chip)
1781 {
1782         int dev = chip->dev_index;
1783         struct pci_dev *pci = chip->pci;
1784         struct snd_card *card = chip->card;
1785         struct hdac_bus *bus = azx_bus(chip);
1786         int err;
1787         unsigned short gcap;
1788         unsigned int dma_bits = 64;
1789
1790 #if BITS_PER_LONG != 64
1791         /* Fix up base address on ULI M5461 */
1792         if (chip->driver_type == AZX_DRIVER_ULI) {
1793                 u16 tmp3;
1794                 pci_read_config_word(pci, 0x40, &tmp3);
1795                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1796                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1797         }
1798 #endif
1799
1800         err = pci_request_regions(pci, "ICH HD audio");
1801         if (err < 0)
1802                 return err;
1803         chip->region_requested = 1;
1804
1805         bus->addr = pci_resource_start(pci, 0);
1806         bus->remap_addr = pci_ioremap_bar(pci, 0);
1807         if (bus->remap_addr == NULL) {
1808                 dev_err(card->dev, "ioremap error\n");
1809                 return -ENXIO;
1810         }
1811
1812         if (chip->driver_type == AZX_DRIVER_SKL)
1813                 snd_hdac_bus_parse_capabilities(bus);
1814
1815         /*
1816          * Some Intel CPUs has always running timer (ART) feature and
1817          * controller may have Global time sync reporting capability, so
1818          * check both of these before declaring synchronized time reporting
1819          * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1820          */
1821         chip->gts_present = false;
1822
1823 #ifdef CONFIG_X86
1824         if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1825                 chip->gts_present = true;
1826 #endif
1827
1828         if (chip->msi) {
1829                 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1830                         dev_dbg(card->dev, "Disabling 64bit MSI\n");
1831                         pci->no_64bit_msi = true;
1832                 }
1833                 if (pci_enable_msi(pci) < 0)
1834                         chip->msi = 0;
1835         }
1836
1837         pci_set_master(pci);
1838         synchronize_irq(bus->irq);
1839
1840         gcap = azx_readw(chip, GCAP);
1841         dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1842
1843         /* AMD devices support 40 or 48bit DMA, take the safe one */
1844         if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1845                 dma_bits = 40;
1846
1847         /* disable SB600 64bit support for safety */
1848         if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1849                 struct pci_dev *p_smbus;
1850                 dma_bits = 40;
1851                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1852                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1853                                          NULL);
1854                 if (p_smbus) {
1855                         if (p_smbus->revision < 0x30)
1856                                 gcap &= ~AZX_GCAP_64OK;
1857                         pci_dev_put(p_smbus);
1858                 }
1859         }
1860
1861         /* NVidia hardware normally only supports up to 40 bits of DMA */
1862         if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1863                 dma_bits = 40;
1864
1865         /* disable 64bit DMA address on some devices */
1866         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1867                 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1868                 gcap &= ~AZX_GCAP_64OK;
1869         }
1870
1871         /* disable buffer size rounding to 128-byte multiples if supported */
1872         if (align_buffer_size >= 0)
1873                 chip->align_buffer_size = !!align_buffer_size;
1874         else {
1875                 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1876                         chip->align_buffer_size = 0;
1877                 else
1878                         chip->align_buffer_size = 1;
1879         }
1880
1881         /* allow 64bit DMA address if supported by H/W */
1882         if (!(gcap & AZX_GCAP_64OK))
1883                 dma_bits = 32;
1884         if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1885                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
1886         } else {
1887                 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1888                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
1889         }
1890
1891         /* read number of streams from GCAP register instead of using
1892          * hardcoded value
1893          */
1894         chip->capture_streams = (gcap >> 8) & 0x0f;
1895         chip->playback_streams = (gcap >> 12) & 0x0f;
1896         if (!chip->playback_streams && !chip->capture_streams) {
1897                 /* gcap didn't give any info, switching to old method */
1898
1899                 switch (chip->driver_type) {
1900                 case AZX_DRIVER_ULI:
1901                         chip->playback_streams = ULI_NUM_PLAYBACK;
1902                         chip->capture_streams = ULI_NUM_CAPTURE;
1903                         break;
1904                 case AZX_DRIVER_ATIHDMI:
1905                 case AZX_DRIVER_ATIHDMI_NS:
1906                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1907                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1908                         break;
1909                 case AZX_DRIVER_GENERIC:
1910                 default:
1911                         chip->playback_streams = ICH6_NUM_PLAYBACK;
1912                         chip->capture_streams = ICH6_NUM_CAPTURE;
1913                         break;
1914                 }
1915         }
1916         chip->capture_index_offset = 0;
1917         chip->playback_index_offset = chip->capture_streams;
1918         chip->num_streams = chip->playback_streams + chip->capture_streams;
1919
1920         /* sanity check for the SDxCTL.STRM field overflow */
1921         if (chip->num_streams > 15 &&
1922             (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
1923                 dev_warn(chip->card->dev, "number of I/O streams is %d, "
1924                          "forcing separate stream tags", chip->num_streams);
1925                 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
1926         }
1927
1928         /* initialize streams */
1929         err = azx_init_streams(chip);
1930         if (err < 0)
1931                 return err;
1932
1933         err = azx_alloc_stream_pages(chip);
1934         if (err < 0)
1935                 return err;
1936
1937         /* initialize chip */
1938         azx_init_pci(chip);
1939
1940         snd_hdac_i915_set_bclk(bus);
1941
1942         hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1943
1944         /* codec detection */
1945         if (!azx_bus(chip)->codec_mask) {
1946                 dev_err(card->dev, "no codecs found!\n");
1947                 return -ENODEV;
1948         }
1949
1950         if (azx_acquire_irq(chip, 0) < 0)
1951                 return -EBUSY;
1952
1953         strcpy(card->driver, "HDA-Intel");
1954         strlcpy(card->shortname, driver_short_names[chip->driver_type],
1955                 sizeof(card->shortname));
1956         snprintf(card->longname, sizeof(card->longname),
1957                  "%s at 0x%lx irq %i",
1958                  card->shortname, bus->addr, bus->irq);
1959
1960         return 0;
1961 }
1962
1963 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1964 /* callback from request_firmware_nowait() */
1965 static void azx_firmware_cb(const struct firmware *fw, void *context)
1966 {
1967         struct snd_card *card = context;
1968         struct azx *chip = card->private_data;
1969         struct pci_dev *pci = chip->pci;
1970
1971         if (!fw) {
1972                 dev_err(card->dev, "Cannot load firmware, aborting\n");
1973                 goto error;
1974         }
1975
1976         chip->fw = fw;
1977         if (!chip->disabled) {
1978                 /* continue probing */
1979                 if (azx_probe_continue(chip))
1980                         goto error;
1981         }
1982         return; /* OK */
1983
1984  error:
1985         snd_card_free(card);
1986         pci_set_drvdata(pci, NULL);
1987 }
1988 #endif
1989
1990 static int disable_msi_reset_irq(struct azx *chip)
1991 {
1992         struct hdac_bus *bus = azx_bus(chip);
1993         int err;
1994
1995         free_irq(bus->irq, chip);
1996         bus->irq = -1;
1997         pci_disable_msi(chip->pci);
1998         chip->msi = 0;
1999         err = azx_acquire_irq(chip, 1);
2000         if (err < 0)
2001                 return err;
2002
2003         return 0;
2004 }
2005
2006 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
2007                              struct vm_area_struct *area)
2008 {
2009 #ifdef CONFIG_X86
2010         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2011         struct azx *chip = apcm->chip;
2012         if (chip->uc_buffer)
2013                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2014 #endif
2015 }
2016
2017 static const struct hda_controller_ops pci_hda_ops = {
2018         .disable_msi_reset_irq = disable_msi_reset_irq,
2019         .pcm_mmap_prepare = pcm_mmap_prepare,
2020         .position_check = azx_position_check,
2021 };
2022
2023 static int azx_check_dmic(struct pci_dev *pci, struct azx *chip)
2024 {
2025         struct nhlt_acpi_table *nhlt;
2026         int ret = 0;
2027
2028         if (chip->driver_type == AZX_DRIVER_SKL &&
2029             pci->class != 0x040300) {
2030                 nhlt = intel_nhlt_init(&pci->dev);
2031                 if (nhlt) {
2032                         if (intel_nhlt_get_dmic_geo(&pci->dev, nhlt)) {
2033                                 ret = -ENODEV;
2034                                 dev_info(&pci->dev, "Digital mics found on Skylake+ platform, aborting probe\n");
2035                         }
2036                         intel_nhlt_free(nhlt);
2037                 }
2038         }
2039         return ret;
2040 }
2041
2042 static int azx_probe(struct pci_dev *pci,
2043                      const struct pci_device_id *pci_id)
2044 {
2045         static int dev;
2046         struct snd_card *card;
2047         struct hda_intel *hda;
2048         struct azx *chip;
2049         bool schedule_probe;
2050         int err;
2051
2052         if (dev >= SNDRV_CARDS)
2053                 return -ENODEV;
2054         if (!enable[dev]) {
2055                 dev++;
2056                 return -ENOENT;
2057         }
2058
2059         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2060                            0, &card);
2061         if (err < 0) {
2062                 dev_err(&pci->dev, "Error creating card!\n");
2063                 return err;
2064         }
2065
2066         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2067         if (err < 0)
2068                 goto out_free;
2069         card->private_data = chip;
2070         hda = container_of(chip, struct hda_intel, chip);
2071
2072         /*
2073          * stop probe if digital microphones detected on Skylake+ platform
2074          * with the DSP enabled. This is an opt-in behavior defined at build
2075          * time or at run-time with a module parameter
2076          */
2077         if (dmic_detect) {
2078                 err = azx_check_dmic(pci, chip);
2079                 if (err < 0)
2080                         goto out_free;
2081         }
2082
2083         pci_set_drvdata(pci, card);
2084
2085         err = register_vga_switcheroo(chip);
2086         if (err < 0) {
2087                 dev_err(card->dev, "Error registering vga_switcheroo client\n");
2088                 goto out_free;
2089         }
2090
2091         if (check_hdmi_disabled(pci)) {
2092                 dev_info(card->dev, "VGA controller is disabled\n");
2093                 dev_info(card->dev, "Delaying initialization\n");
2094                 chip->disabled = true;
2095         }
2096
2097         schedule_probe = !chip->disabled;
2098
2099 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2100         if (patch[dev] && *patch[dev]) {
2101                 dev_info(card->dev, "Applying patch firmware '%s'\n",
2102                          patch[dev]);
2103                 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2104                                               &pci->dev, GFP_KERNEL, card,
2105                                               azx_firmware_cb);
2106                 if (err < 0)
2107                         goto out_free;
2108                 schedule_probe = false; /* continued in azx_firmware_cb() */
2109         }
2110 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2111
2112 #ifndef CONFIG_SND_HDA_I915
2113         if (CONTROLLER_IN_GPU(pci))
2114                 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
2115 #endif
2116
2117         if (schedule_probe)
2118                 schedule_work(&hda->probe_work);
2119
2120         dev++;
2121         if (chip->disabled)
2122                 complete_all(&hda->probe_wait);
2123         return 0;
2124
2125 out_free:
2126         snd_card_free(card);
2127         return err;
2128 }
2129
2130 #ifdef CONFIG_PM
2131 /* On some boards setting power_save to a non 0 value leads to clicking /
2132  * popping sounds when ever we enter/leave powersaving mode. Ideally we would
2133  * figure out how to avoid these sounds, but that is not always feasible.
2134  * So we keep a list of devices where we disable powersaving as its known
2135  * to causes problems on these devices.
2136  */
2137 static struct snd_pci_quirk power_save_blacklist[] = {
2138         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2139         SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0),
2140         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2141         SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0),
2142         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2143         SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0),
2144         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2145         SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
2146         /* https://bugzilla.redhat.com/show_bug.cgi?id=1581607 */
2147         SND_PCI_QUIRK(0x1558, 0x3501, "Clevo W35xSS_370SS", 0),
2148         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2149         SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0),
2150         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2151         /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */
2152         SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0),
2153         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2154         SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0),
2155         /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */
2156         SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0),
2157         /* https://bugs.launchpad.net/bugs/1821663 */
2158         SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0),
2159         /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */
2160         SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0),
2161         /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
2162         SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
2163         /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */
2164         SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0),
2165         /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
2166         SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
2167         /* https://bugs.launchpad.net/bugs/1821663 */
2168         SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0),
2169         {}
2170 };
2171 #endif /* CONFIG_PM */
2172
2173 static void set_default_power_save(struct azx *chip)
2174 {
2175         int val = power_save;
2176
2177 #ifdef CONFIG_PM
2178         if (pm_blacklist) {
2179                 const struct snd_pci_quirk *q;
2180
2181                 q = snd_pci_quirk_lookup(chip->pci, power_save_blacklist);
2182                 if (q && val) {
2183                         dev_info(chip->card->dev, "device %04x:%04x is on the power_save blacklist, forcing power_save to 0\n",
2184                                  q->subvendor, q->subdevice);
2185                         val = 0;
2186                 }
2187         }
2188 #endif /* CONFIG_PM */
2189         snd_hda_set_power_save(&chip->bus, val * 1000);
2190 }
2191
2192 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2193 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2194         [AZX_DRIVER_NVIDIA] = 8,
2195         [AZX_DRIVER_TERA] = 1,
2196 };
2197
2198 static int azx_probe_continue(struct azx *chip)
2199 {
2200         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2201         struct hdac_bus *bus = azx_bus(chip);
2202         struct pci_dev *pci = chip->pci;
2203         int dev = chip->dev_index;
2204         int err;
2205
2206         to_hda_bus(bus)->bus_probing = 1;
2207         hda->probe_continued = 1;
2208
2209         /* bind with i915 if needed */
2210         if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
2211                 err = snd_hdac_i915_init(bus);
2212                 if (err < 0) {
2213                         /* if the controller is bound only with HDMI/DP
2214                          * (for HSW and BDW), we need to abort the probe;
2215                          * for other chips, still continue probing as other
2216                          * codecs can be on the same link.
2217                          */
2218                         if (CONTROLLER_IN_GPU(pci)) {
2219                                 dev_err(chip->card->dev,
2220                                         "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
2221                                 goto out_free;
2222                         } else {
2223                                 /* don't bother any longer */
2224                                 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT;
2225                         }
2226                 }
2227
2228                 /* HSW/BDW controllers need this power */
2229                 if (CONTROLLER_IN_GPU(pci))
2230                         hda->need_i915_power = 1;
2231         }
2232
2233         /* Request display power well for the HDA controller or codec. For
2234          * Haswell/Broadwell, both the display HDA controller and codec need
2235          * this power. For other platforms, like Baytrail/Braswell, only the
2236          * display codec needs the power and it can be released after probe.
2237          */
2238         display_power(chip, true);
2239
2240         err = azx_first_init(chip);
2241         if (err < 0)
2242                 goto out_free;
2243
2244 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2245         chip->beep_mode = beep_mode[dev];
2246 #endif
2247
2248         /* create codec instances */
2249         err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2250         if (err < 0)
2251                 goto out_free;
2252
2253 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2254         if (chip->fw) {
2255                 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2256                                          chip->fw->data);
2257                 if (err < 0)
2258                         goto out_free;
2259 #ifndef CONFIG_PM
2260                 release_firmware(chip->fw); /* no longer needed */
2261                 chip->fw = NULL;
2262 #endif
2263         }
2264 #endif
2265         if ((probe_only[dev] & 1) == 0) {
2266                 err = azx_codec_configure(chip);
2267                 if (err < 0)
2268                         goto out_free;
2269         }
2270
2271         err = snd_card_register(chip->card);
2272         if (err < 0)
2273                 goto out_free;
2274
2275         setup_vga_switcheroo_runtime_pm(chip);
2276
2277         chip->running = 1;
2278         azx_add_card_list(chip);
2279
2280         set_default_power_save(chip);
2281
2282         if (azx_has_pm_runtime(chip))
2283                 pm_runtime_put_autosuspend(&pci->dev);
2284
2285 out_free:
2286         if (err < 0 || !hda->need_i915_power)
2287                 display_power(chip, false);
2288         if (err < 0)
2289                 hda->init_failed = 1;
2290         complete_all(&hda->probe_wait);
2291         to_hda_bus(bus)->bus_probing = 0;
2292         return err;
2293 }
2294
2295 static void azx_remove(struct pci_dev *pci)
2296 {
2297         struct snd_card *card = pci_get_drvdata(pci);
2298         struct azx *chip;
2299         struct hda_intel *hda;
2300
2301         if (card) {
2302                 /* cancel the pending probing work */
2303                 chip = card->private_data;
2304                 hda = container_of(chip, struct hda_intel, chip);
2305                 /* FIXME: below is an ugly workaround.
2306                  * Both device_release_driver() and driver_probe_device()
2307                  * take *both* the device's and its parent's lock before
2308                  * calling the remove() and probe() callbacks.  The codec
2309                  * probe takes the locks of both the codec itself and its
2310                  * parent, i.e. the PCI controller dev.  Meanwhile, when
2311                  * the PCI controller is unbound, it takes its lock, too
2312                  * ==> ouch, a deadlock!
2313                  * As a workaround, we unlock temporarily here the controller
2314                  * device during cancel_work_sync() call.
2315                  */
2316                 device_unlock(&pci->dev);
2317                 cancel_work_sync(&hda->probe_work);
2318                 device_lock(&pci->dev);
2319
2320                 snd_card_free(card);
2321         }
2322 }
2323
2324 static void azx_shutdown(struct pci_dev *pci)
2325 {
2326         struct snd_card *card = pci_get_drvdata(pci);
2327         struct azx *chip;
2328
2329         if (!card)
2330                 return;
2331         chip = card->private_data;
2332         if (chip && chip->running)
2333                 azx_stop_chip(chip);
2334 }
2335
2336 /* PCI IDs */
2337 static const struct pci_device_id azx_ids[] = {
2338         /* CPT */
2339         { PCI_DEVICE(0x8086, 0x1c20),
2340           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2341         /* PBG */
2342         { PCI_DEVICE(0x8086, 0x1d20),
2343           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2344         /* Panther Point */
2345         { PCI_DEVICE(0x8086, 0x1e20),
2346           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2347         /* Lynx Point */
2348         { PCI_DEVICE(0x8086, 0x8c20),
2349           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2350         /* 9 Series */
2351         { PCI_DEVICE(0x8086, 0x8ca0),
2352           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2353         /* Wellsburg */
2354         { PCI_DEVICE(0x8086, 0x8d20),
2355           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2356         { PCI_DEVICE(0x8086, 0x8d21),
2357           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2358         /* Lewisburg */
2359         { PCI_DEVICE(0x8086, 0xa1f0),
2360           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2361         { PCI_DEVICE(0x8086, 0xa270),
2362           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2363         /* Lynx Point-LP */
2364         { PCI_DEVICE(0x8086, 0x9c20),
2365           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2366         /* Lynx Point-LP */
2367         { PCI_DEVICE(0x8086, 0x9c21),
2368           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2369         /* Wildcat Point-LP */
2370         { PCI_DEVICE(0x8086, 0x9ca0),
2371           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2372         /* Sunrise Point */
2373         { PCI_DEVICE(0x8086, 0xa170),
2374           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2375         /* Sunrise Point-LP */
2376         { PCI_DEVICE(0x8086, 0x9d70),
2377           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2378         /* Kabylake */
2379         { PCI_DEVICE(0x8086, 0xa171),
2380           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2381         /* Kabylake-LP */
2382         { PCI_DEVICE(0x8086, 0x9d71),
2383           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2384         /* Kabylake-H */
2385         { PCI_DEVICE(0x8086, 0xa2f0),
2386           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2387         /* Coffelake */
2388         { PCI_DEVICE(0x8086, 0xa348),
2389           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2390         /* Cannonlake */
2391         { PCI_DEVICE(0x8086, 0x9dc8),
2392           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2393         /* CometLake-LP */
2394         { PCI_DEVICE(0x8086, 0x02C8),
2395           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2396         /* CometLake-H */
2397         { PCI_DEVICE(0x8086, 0x06C8),
2398           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2399         /* Icelake */
2400         { PCI_DEVICE(0x8086, 0x34c8),
2401           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2402         /* Jasperlake */
2403         { PCI_DEVICE(0x8086, 0x38c8),
2404           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2405         /* Tigerlake */
2406         { PCI_DEVICE(0x8086, 0xa0c8),
2407           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2408         /* Elkhart Lake */
2409         { PCI_DEVICE(0x8086, 0x4b55),
2410           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2411         /* Broxton-P(Apollolake) */
2412         { PCI_DEVICE(0x8086, 0x5a98),
2413           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2414         /* Broxton-T */
2415         { PCI_DEVICE(0x8086, 0x1a98),
2416           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2417         /* Gemini-Lake */
2418         { PCI_DEVICE(0x8086, 0x3198),
2419           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2420         /* Haswell */
2421         { PCI_DEVICE(0x8086, 0x0a0c),
2422           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2423         { PCI_DEVICE(0x8086, 0x0c0c),
2424           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2425         { PCI_DEVICE(0x8086, 0x0d0c),
2426           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2427         /* Broadwell */
2428         { PCI_DEVICE(0x8086, 0x160c),
2429           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2430         /* 5 Series/3400 */
2431         { PCI_DEVICE(0x8086, 0x3b56),
2432           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2433         /* Poulsbo */
2434         { PCI_DEVICE(0x8086, 0x811b),
2435           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2436         /* Oaktrail */
2437         { PCI_DEVICE(0x8086, 0x080a),
2438           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2439         /* BayTrail */
2440         { PCI_DEVICE(0x8086, 0x0f04),
2441           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2442         /* Braswell */
2443         { PCI_DEVICE(0x8086, 0x2284),
2444           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2445         /* ICH6 */
2446         { PCI_DEVICE(0x8086, 0x2668),
2447           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2448         /* ICH7 */
2449         { PCI_DEVICE(0x8086, 0x27d8),
2450           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2451         /* ESB2 */
2452         { PCI_DEVICE(0x8086, 0x269a),
2453           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2454         /* ICH8 */
2455         { PCI_DEVICE(0x8086, 0x284b),
2456           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2457         /* ICH9 */
2458         { PCI_DEVICE(0x8086, 0x293e),
2459           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2460         /* ICH9 */
2461         { PCI_DEVICE(0x8086, 0x293f),
2462           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2463         /* ICH10 */
2464         { PCI_DEVICE(0x8086, 0x3a3e),
2465           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2466         /* ICH10 */
2467         { PCI_DEVICE(0x8086, 0x3a6e),
2468           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2469         /* Generic Intel */
2470         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2471           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2472           .class_mask = 0xffffff,
2473           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2474         /* ATI SB 450/600/700/800/900 */
2475         { PCI_DEVICE(0x1002, 0x437b),
2476           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2477         { PCI_DEVICE(0x1002, 0x4383),
2478           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2479         /* AMD Hudson */
2480         { PCI_DEVICE(0x1022, 0x780d),
2481           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2482         /* AMD, X370 & co */
2483         { PCI_DEVICE(0x1022, 0x1457),
2484           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2485         /* AMD, X570 & co */
2486         { PCI_DEVICE(0x1022, 0x1487),
2487           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2488         /* AMD Stoney */
2489         { PCI_DEVICE(0x1022, 0x157a),
2490           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2491                          AZX_DCAPS_PM_RUNTIME },
2492         /* AMD Raven */
2493         { PCI_DEVICE(0x1022, 0x15e3),
2494           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2495         /* ATI HDMI */
2496         { PCI_DEVICE(0x1002, 0x0002),
2497           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2498         { PCI_DEVICE(0x1002, 0x1308),
2499           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2500         { PCI_DEVICE(0x1002, 0x157a),
2501           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2502         { PCI_DEVICE(0x1002, 0x15b3),
2503           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2504         { PCI_DEVICE(0x1002, 0x793b),
2505           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2506         { PCI_DEVICE(0x1002, 0x7919),
2507           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2508         { PCI_DEVICE(0x1002, 0x960f),
2509           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2510         { PCI_DEVICE(0x1002, 0x970f),
2511           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2512         { PCI_DEVICE(0x1002, 0x9840),
2513           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2514         { PCI_DEVICE(0x1002, 0xaa00),
2515           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2516         { PCI_DEVICE(0x1002, 0xaa08),
2517           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2518         { PCI_DEVICE(0x1002, 0xaa10),
2519           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2520         { PCI_DEVICE(0x1002, 0xaa18),
2521           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2522         { PCI_DEVICE(0x1002, 0xaa20),
2523           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2524         { PCI_DEVICE(0x1002, 0xaa28),
2525           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2526         { PCI_DEVICE(0x1002, 0xaa30),
2527           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2528         { PCI_DEVICE(0x1002, 0xaa38),
2529           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2530         { PCI_DEVICE(0x1002, 0xaa40),
2531           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2532         { PCI_DEVICE(0x1002, 0xaa48),
2533           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2534         { PCI_DEVICE(0x1002, 0xaa50),
2535           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2536         { PCI_DEVICE(0x1002, 0xaa58),
2537           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2538         { PCI_DEVICE(0x1002, 0xaa60),
2539           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2540         { PCI_DEVICE(0x1002, 0xaa68),
2541           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2542         { PCI_DEVICE(0x1002, 0xaa80),
2543           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2544         { PCI_DEVICE(0x1002, 0xaa88),
2545           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2546         { PCI_DEVICE(0x1002, 0xaa90),
2547           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2548         { PCI_DEVICE(0x1002, 0xaa98),
2549           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2550         { PCI_DEVICE(0x1002, 0x9902),
2551           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2552         { PCI_DEVICE(0x1002, 0xaaa0),
2553           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2554         { PCI_DEVICE(0x1002, 0xaaa8),
2555           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2556         { PCI_DEVICE(0x1002, 0xaab0),
2557           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2558         { PCI_DEVICE(0x1002, 0xaac0),
2559           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2560         { PCI_DEVICE(0x1002, 0xaac8),
2561           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2562         { PCI_DEVICE(0x1002, 0xaad8),
2563           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2564         { PCI_DEVICE(0x1002, 0xaae8),
2565           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2566         { PCI_DEVICE(0x1002, 0xaae0),
2567           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2568         { PCI_DEVICE(0x1002, 0xaaf0),
2569           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2570         /* VIA VT8251/VT8237A */
2571         { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2572         /* VIA GFX VT7122/VX900 */
2573         { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2574         /* VIA GFX VT6122/VX11 */
2575         { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2576         /* SIS966 */
2577         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2578         /* ULI M5461 */
2579         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2580         /* NVIDIA MCP */
2581         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2582           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2583           .class_mask = 0xffffff,
2584           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2585         /* Teradici */
2586         { PCI_DEVICE(0x6549, 0x1200),
2587           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2588         { PCI_DEVICE(0x6549, 0x2200),
2589           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2590         /* Creative X-Fi (CA0110-IBG) */
2591         /* CTHDA chips */
2592         { PCI_DEVICE(0x1102, 0x0010),
2593           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2594         { PCI_DEVICE(0x1102, 0x0012),
2595           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2596 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2597         /* the following entry conflicts with snd-ctxfi driver,
2598          * as ctxfi driver mutates from HD-audio to native mode with
2599          * a special command sequence.
2600          */
2601         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2602           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2603           .class_mask = 0xffffff,
2604           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2605           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2606 #else
2607         /* this entry seems still valid -- i.e. without emu20kx chip */
2608         { PCI_DEVICE(0x1102, 0x0009),
2609           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2610           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2611 #endif
2612         /* CM8888 */
2613         { PCI_DEVICE(0x13f6, 0x5011),
2614           .driver_data = AZX_DRIVER_CMEDIA |
2615           AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2616         /* Vortex86MX */
2617         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2618         /* VMware HDAudio */
2619         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2620         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2621         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2622           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2623           .class_mask = 0xffffff,
2624           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2625         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2626           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2627           .class_mask = 0xffffff,
2628           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2629         /* Zhaoxin */
2630         { PCI_DEVICE(0x1d17, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN },
2631         { 0, }
2632 };
2633 MODULE_DEVICE_TABLE(pci, azx_ids);
2634
2635 /* pci_driver definition */
2636 static struct pci_driver azx_driver = {
2637         .name = KBUILD_MODNAME,
2638         .id_table = azx_ids,
2639         .probe = azx_probe,
2640         .remove = azx_remove,
2641         .shutdown = azx_shutdown,
2642         .driver = {
2643                 .pm = AZX_PM_OPS,
2644         },
2645 };
2646
2647 module_pci_driver(azx_driver);