drivers/tty/serial/xilinx_uartps.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Cadence UART driver (found in Xilinx Zynq)
   4  *
   5  * 2011 - 2014 (C) Xilinx Inc.
   6  *
   7  * This driver has originally been pushed by Xilinx using a Zynq-branding. This
   8  * still shows in the naming of this file, the kconfig symbols and some symbols
   9  * in the code.
  10  */
  11
  12 #if defined(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  13 #define SUPPORT_SYSRQ
  14 #endif
  15
  16 #include <linux/platform_device.h>
  17 #include <linux/serial.h>
  18 #include <linux/console.h>
  19 #include <linux/serial_core.h>
  20 #include <linux/slab.h>
  21 #include <linux/tty.h>
  22 #include <linux/tty_flip.h>
  23 #include <linux/clk.h>
  24 #include <linux/irq.h>
  25 #include <linux/io.h>
  26 #include <linux/of.h>
  27 #include <linux/module.h>
  28 #include <linux/pm_runtime.h>
  29
  30 #define CDNS_UART_TTY_NAME      "ttyPS"
  31 #define CDNS_UART_NAME          "xuartps"
  32 #define CDNS_UART_MAJOR         0       /* use dynamic node allocation */
  33 #define CDNS_UART_NR_PORTS      2
  34 #define CDNS_UART_FIFO_SIZE     64      /* FIFO size */
  35 #define CDNS_UART_REGISTER_SPACE        0x1000
  36
  37 /* Rx Trigger level */
  38 static int rx_trigger_level = 56;
  39 module_param(rx_trigger_level, uint, S_IRUGO);
  40 MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes");
  41
  42 /* Rx Timeout */
  43 static int rx_timeout = 10;
  44 module_param(rx_timeout, uint, S_IRUGO);
  45 MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
  46
  47 /* Register offsets for the UART. */
  48 #define CDNS_UART_CR            0x00  /* Control Register */
  49 #define CDNS_UART_MR            0x04  /* Mode Register */
  50 #define CDNS_UART_IER           0x08  /* Interrupt Enable */
  51 #define CDNS_UART_IDR           0x0C  /* Interrupt Disable */
  52 #define CDNS_UART_IMR           0x10  /* Interrupt Mask */
  53 #define CDNS_UART_ISR           0x14  /* Interrupt Status */
  54 #define CDNS_UART_BAUDGEN       0x18  /* Baud Rate Generator */
  55 #define CDNS_UART_RXTOUT        0x1C  /* RX Timeout */
  56 #define CDNS_UART_RXWM          0x20  /* RX FIFO Trigger Level */
  57 #define CDNS_UART_MODEMCR       0x24  /* Modem Control */
  58 #define CDNS_UART_MODEMSR       0x28  /* Modem Status */
  59 #define CDNS_UART_SR            0x2C  /* Channel Status */
  60 #define CDNS_UART_FIFO          0x30  /* FIFO */
  61 #define CDNS_UART_BAUDDIV       0x34  /* Baud Rate Divider */
  62 #define CDNS_UART_FLOWDEL       0x38  /* Flow Delay */
  63 #define CDNS_UART_IRRX_PWIDTH   0x3C  /* IR Min Received Pulse Width */
  64 #define CDNS_UART_IRTX_PWIDTH   0x40  /* IR Transmitted pulse Width */
  65 #define CDNS_UART_TXWM          0x44  /* TX FIFO Trigger Level */
  66 #define CDNS_UART_RXBS          0x48  /* RX FIFO byte status register */
  67
  68 /* Control Register Bit Definitions */
  69 #define CDNS_UART_CR_STOPBRK    0x00000100  /* Stop TX break */
  70 #define CDNS_UART_CR_STARTBRK   0x00000080  /* Set TX break */
  71 #define CDNS_UART_CR_TX_DIS     0x00000020  /* TX disabled. */
  72 #define CDNS_UART_CR_TX_EN      0x00000010  /* TX enabled */
  73 #define CDNS_UART_CR_RX_DIS     0x00000008  /* RX disabled. */
  74 #define CDNS_UART_CR_RX_EN      0x00000004  /* RX enabled */
  75 #define CDNS_UART_CR_TXRST      0x00000002  /* TX logic reset */
  76 #define CDNS_UART_CR_RXRST      0x00000001  /* RX logic reset */
  77 #define CDNS_UART_CR_RST_TO     0x00000040  /* Restart Timeout Counter */
  78 #define CDNS_UART_RXBS_PARITY    0x00000001 /* Parity error status */
  79 #define CDNS_UART_RXBS_FRAMING   0x00000002 /* Framing error status */
  80 #define CDNS_UART_RXBS_BRK       0x00000004 /* Overrun error status */
  81
  82 /*
  83  * Mode Register:
  84  * The mode register (MR) defines the mode of transfer as well as the data
  85  * format. If this register is modified during transmission or reception,
  86  * data validity cannot be guaranteed.
  87  */
  88 #define CDNS_UART_MR_CLKSEL             0x00000001  /* Pre-scalar selection */
  89 #define CDNS_UART_MR_CHMODE_L_LOOP      0x00000200  /* Local loop back mode */
  90 #define CDNS_UART_MR_CHMODE_NORM        0x00000000  /* Normal mode */
  91 #define CDNS_UART_MR_CHMODE_MASK        0x00000300  /* Mask for mode bits */
  92
  93 #define CDNS_UART_MR_STOPMODE_2_BIT     0x00000080  /* 2 stop bits */
  94 #define CDNS_UART_MR_STOPMODE_1_BIT     0x00000000  /* 1 stop bit */
  95
  96 #define CDNS_UART_MR_PARITY_NONE        0x00000020  /* No parity mode */
  97 #define CDNS_UART_MR_PARITY_MARK        0x00000018  /* Mark parity mode */
  98 #define CDNS_UART_MR_PARITY_SPACE       0x00000010  /* Space parity mode */
  99 #define CDNS_UART_MR_PARITY_ODD         0x00000008  /* Odd parity mode */
 100 #define CDNS_UART_MR_PARITY_EVEN        0x00000000  /* Even parity mode */
 101
 102 #define CDNS_UART_MR_CHARLEN_6_BIT      0x00000006  /* 6 bits data */
 103 #define CDNS_UART_MR_CHARLEN_7_BIT      0x00000004  /* 7 bits data */
 104 #define CDNS_UART_MR_CHARLEN_8_BIT      0x00000000  /* 8 bits data */
 105
 106 /*
 107  * Interrupt Registers:
 108  * Interrupt control logic uses the interrupt enable register (IER) and the
 109  * interrupt disable register (IDR) to set the value of the bits in the
 110  * interrupt mask register (IMR). The IMR determines whether to pass an
 111  * interrupt to the interrupt status register (ISR).
 112  * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an
 113  * interrupt. IMR and ISR are read only, and IER and IDR are write only.
 114  * Reading either IER or IDR returns 0x00.
 115  * All four registers have the same bit definitions.
 116  */
 117 #define CDNS_UART_IXR_TOUT      0x00000100 /* RX Timeout error interrupt */
 118 #define CDNS_UART_IXR_PARITY    0x00000080 /* Parity error interrupt */
 119 #define CDNS_UART_IXR_FRAMING   0x00000040 /* Framing error interrupt */
 120 #define CDNS_UART_IXR_OVERRUN   0x00000020 /* Overrun error interrupt */
 121 #define CDNS_UART_IXR_TXFULL    0x00000010 /* TX FIFO Full interrupt */
 122 #define CDNS_UART_IXR_TXEMPTY   0x00000008 /* TX FIFO empty interrupt */
 123 #define CDNS_UART_ISR_RXEMPTY   0x00000002 /* RX FIFO empty interrupt */
 124 #define CDNS_UART_IXR_RXTRIG    0x00000001 /* RX FIFO trigger interrupt */
 125 #define CDNS_UART_IXR_RXFULL    0x00000004 /* RX FIFO full interrupt. */
 126 #define CDNS_UART_IXR_RXEMPTY   0x00000002 /* RX FIFO empty interrupt. */
 127 #define CDNS_UART_IXR_MASK      0x00001FFF /* Valid bit mask */
 128
 129         /*
 130          * Do not enable parity error interrupt for the following
 131          * reason: When parity error interrupt is enabled, each Rx
 132          * parity error always results in 2 events. The first one
 133          * being parity error interrupt and the second one with a
 134          * proper Rx interrupt with the incoming data.  Disabling
 135          * parity error interrupt ensures better handling of parity
 136          * error events. With this change, for a parity error case, we
 137          * get a Rx interrupt with parity error set in ISR register
 138          * and we still handle parity errors in the desired way.
 139          */
 140
 141 #define CDNS_UART_RX_IRQS       (CDNS_UART_IXR_FRAMING | \
 142                                  CDNS_UART_IXR_OVERRUN | \
 143                                  CDNS_UART_IXR_RXTRIG |  \
 144                                  CDNS_UART_IXR_TOUT)
 145
 146 /* Goes in read_status_mask for break detection as the HW doesn't do it*/
 147 #define CDNS_UART_IXR_BRK       0x00002000
 148
 149 #define CDNS_UART_RXBS_SUPPORT BIT(1)
 150 /*
 151  * Modem Control register:
 152  * The read/write Modem Control register controls the interface with the modem
 153  * or data set, or a peripheral device emulating a modem.
 154  */
 155 #define CDNS_UART_MODEMCR_FCM   0x00000020 /* Automatic flow control mode */
 156 #define CDNS_UART_MODEMCR_RTS   0x00000002 /* Request to send output control */
 157 #define CDNS_UART_MODEMCR_DTR   0x00000001 /* Data Terminal Ready */
 158
 159 /*
 160  * Channel Status Register:
 161  * The channel status register (CSR) is provided to enable the control logic
 162  * to monitor the status of bits in the channel interrupt status register,
 163  * even if these are masked out by the interrupt mask register.
 164  */
 165 #define CDNS_UART_SR_RXEMPTY    0x00000002 /* RX FIFO empty */
 166 #define CDNS_UART_SR_TXEMPTY    0x00000008 /* TX FIFO empty */
 167 #define CDNS_UART_SR_TXFULL     0x00000010 /* TX FIFO full */
 168 #define CDNS_UART_SR_RXTRIG     0x00000001 /* Rx Trigger */
 169 #define CDNS_UART_SR_TACTIVE    0x00000800 /* TX state machine active */
 170
 171 /* baud dividers min/max values */
 172 #define CDNS_UART_BDIV_MIN      4
 173 #define CDNS_UART_BDIV_MAX      255
 174 #define CDNS_UART_CD_MAX        65535
 175 #define UART_AUTOSUSPEND_TIMEOUT        3000
 176
 177 /**
 178  * struct cdns_uart - device data
 179  * @port:               Pointer to the UART port
 180  * @uartclk:            Reference clock
 181  * @pclk:               APB clock
 182  * @cdns_uart_driver:   Pointer to UART driver
 183  * @baud:               Current baud rate
 184  * @id:                 Port ID
 185  * @clk_rate_change_nb: Notifier block for clock changes
 186  * @quirks:             Flags for RXBS support.
 187  */
 188 struct cdns_uart {
 189         struct uart_port        *port;
 190         struct clk              *uartclk;
 191         struct clk              *pclk;
 192         struct uart_driver      *cdns_uart_driver;
 193         unsigned int            baud;
 194         int                     id;
 195         struct notifier_block   clk_rate_change_nb;
 196         u32                     quirks;
 197 };
 198 struct cdns_platform_data {
 199         u32 quirks;
 200 };
 201 #define to_cdns_uart(_nb) container_of(_nb, struct cdns_uart, \
 202                 clk_rate_change_nb);
 203
 204 /**
 205  * cdns_uart_handle_rx - Handle the received bytes along with Rx errors.
 206  * @dev_id: Id of the UART port
 207  * @isrstatus: The interrupt status register value as read
 208  * Return: None
 209  */
 210 static void cdns_uart_handle_rx(void *dev_id, unsigned int isrstatus)
 211 {
 212         struct uart_port *port = (struct uart_port *)dev_id;
 213         struct cdns_uart *cdns_uart = port->private_data;
 214         unsigned int data;
 215         unsigned int rxbs_status = 0;
 216         unsigned int status_mask;
 217         unsigned int framerrprocessed = 0;
 218         char status = TTY_NORMAL;
 219         bool is_rxbs_support;
 220
 221         is_rxbs_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;
 222
 223         while ((readl(port->membase + CDNS_UART_SR) &
 224                 CDNS_UART_SR_RXEMPTY) != CDNS_UART_SR_RXEMPTY) {
 225                 if (is_rxbs_support)
 226                         rxbs_status = readl(port->membase + CDNS_UART_RXBS);
 227                 data = readl(port->membase + CDNS_UART_FIFO);
 228                 port->icount.rx++;
 229                 /*
 230                  * There is no hardware break detection in Zynq, so we interpret
 231                  * framing error with all-zeros data as a break sequence.
 232                  * Most of the time, there's another non-zero byte at the
 233                  * end of the sequence.
 234                  */
 235                 if (!is_rxbs_support && (isrstatus & CDNS_UART_IXR_FRAMING)) {
 236                         if (!data) {
 237                                 port->read_status_mask |= CDNS_UART_IXR_BRK;
 238                                 framerrprocessed = 1;
 239                                 continue;
 240                         }
 241                 }
 242                 if (is_rxbs_support && (rxbs_status & CDNS_UART_RXBS_BRK)) {
 243                         port->icount.brk++;
 244                         status = TTY_BREAK;
 245                         if (uart_handle_break(port))
 246                                 continue;
 247                 }
 248
 249                 isrstatus &= port->read_status_mask;
 250                 isrstatus &= ~port->ignore_status_mask;
 251                 status_mask = port->read_status_mask;
 252                 status_mask &= ~port->ignore_status_mask;
 253
 254                 if (data &&
 255                     (port->read_status_mask & CDNS_UART_IXR_BRK)) {
 256                         port->read_status_mask &= ~CDNS_UART_IXR_BRK;
 257                         port->icount.brk++;
 258                         if (uart_handle_break(port))
 259                                 continue;
 260                 }
 261
 262                 if (uart_handle_sysrq_char(port, data))
 263                         continue;
 264
 265                 if (is_rxbs_support) {
 266                         if ((rxbs_status & CDNS_UART_RXBS_PARITY)
 267                             && (status_mask & CDNS_UART_IXR_PARITY)) {
 268                                 port->icount.parity++;
 269                                 status = TTY_PARITY;
 270                         }
 271                         if ((rxbs_status & CDNS_UART_RXBS_FRAMING)
 272                             && (status_mask & CDNS_UART_IXR_PARITY)) {
 273                                 port->icount.frame++;
 274                                 status = TTY_FRAME;
 275                         }
 276                 } else {
 277                         if (isrstatus & CDNS_UART_IXR_PARITY) {
 278                                 port->icount.parity++;
 279                                 status = TTY_PARITY;
 280                         }
 281                         if ((isrstatus & CDNS_UART_IXR_FRAMING) &&
 282                             !framerrprocessed) {
 283                                 port->icount.frame++;
 284                                 status = TTY_FRAME;
 285                         }
 286                 }
 287                 if (isrstatus & CDNS_UART_IXR_OVERRUN) {
 288                         port->icount.overrun++;
 289                         tty_insert_flip_char(&port->state->port, 0,
 290                                              TTY_OVERRUN);
 291                 }
 292                 tty_insert_flip_char(&port->state->port, data, status);
 293                 isrstatus = 0;
 294         }
 295         spin_unlock(&port->lock);
 296         tty_flip_buffer_push(&port->state->port);
 297         spin_lock(&port->lock);
 298 }
 299
 300 /**
 301  * cdns_uart_handle_tx - Handle the bytes to be Txed.
 302  * @dev_id: Id of the UART port
 303  * Return: None
 304  */
 305 static void cdns_uart_handle_tx(void *dev_id)
 306 {
 307         struct uart_port *port = (struct uart_port *)dev_id;
 308         unsigned int numbytes;
 309
 310         if (uart_circ_empty(&port->state->xmit)) {
 311                 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IDR);
 312         } else {
 313                 numbytes = port->fifosize;
 314                 while (numbytes && !uart_circ_empty(&port->state->xmit) &&
 315                        !(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXFULL)) {
 316                         /*
 317                          * Get the data from the UART circular buffer
 318                          * and write it to the cdns_uart's TX_FIFO
 319                          * register.
 320                          */
 321                         writel(
 322                                 port->state->xmit.buf[port->state->xmit.
 323                                 tail], port->membase + CDNS_UART_FIFO);
 324
 325                         port->icount.tx++;
 326
 327                         /*
 328                          * Adjust the tail of the UART buffer and wrap
 329                          * the buffer if it reaches limit.
 330                          */
 331                         port->state->xmit.tail =
 332                                 (port->state->xmit.tail + 1) &
 333                                         (UART_XMIT_SIZE - 1);
 334
 335                         numbytes--;
 336                 }
 337
 338                 if (uart_circ_chars_pending(
 339                                 &port->state->xmit) < WAKEUP_CHARS)
 340                         uart_write_wakeup(port);
 341         }
 342 }
 343
 344 /**
 345  * cdns_uart_isr - Interrupt handler
 346  * @irq: Irq number
 347  * @dev_id: Id of the port
 348  *
 349  * Return: IRQHANDLED
 350  */
 351 static irqreturn_t cdns_uart_isr(int irq, void *dev_id)
 352 {
 353         struct uart_port *port = (struct uart_port *)dev_id;
 354         unsigned int isrstatus;
 355
 356         spin_lock(&port->lock);
 357
 358         /* Read the interrupt status register to determine which
 359          * interrupt(s) is/are active and clear them.
 360          */
 361         isrstatus = readl(port->membase + CDNS_UART_ISR);
 362         writel(isrstatus, port->membase + CDNS_UART_ISR);
 363
 364         if (isrstatus & CDNS_UART_IXR_TXEMPTY) {
 365                 cdns_uart_handle_tx(dev_id);
 366                 isrstatus &= ~CDNS_UART_IXR_TXEMPTY;
 367         }
 368         if (isrstatus & CDNS_UART_IXR_MASK)
 369                 cdns_uart_handle_rx(dev_id, isrstatus);
 370
 371         spin_unlock(&port->lock);
 372         return IRQ_HANDLED;
 373 }
 374
 375 /**
 376  * cdns_uart_calc_baud_divs - Calculate baud rate divisors
 377  * @clk: UART module input clock
 378  * @baud: Desired baud rate
 379  * @rbdiv: BDIV value (return value)
 380  * @rcd: CD value (return value)
 381  * @div8: Value for clk_sel bit in mod (return value)
 382  * Return: baud rate, requested baud when possible, or actual baud when there
 383  *      was too much error, zero if no valid divisors are found.
 384  *
 385  * Formula to obtain baud rate is
 386  *      baud_tx/rx rate = clk/CD * (BDIV + 1)
 387  *      input_clk = (Uart User Defined Clock or Apb Clock)
 388  *              depends on UCLKEN in MR Reg
 389  *      clk = input_clk or input_clk/8;
 390  *              depends on CLKS in MR reg
 391  *      CD and BDIV depends on values in
 392  *                      baud rate generate register
 393  *                      baud rate clock divisor register
 394  */
 395 static unsigned int cdns_uart_calc_baud_divs(unsigned int clk,
 396                 unsigned int baud, u32 *rbdiv, u32 *rcd, int *div8)
 397 {
 398         u32 cd, bdiv;
 399         unsigned int calc_baud;
 400         unsigned int bestbaud = 0;
 401         unsigned int bauderror;
 402         unsigned int besterror = ~0;
 403
 404         if (baud < clk / ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX)) {
 405                 *div8 = 1;
 406                 clk /= 8;
 407         } else {
 408                 *div8 = 0;
 409         }
 410
 411         for (bdiv = CDNS_UART_BDIV_MIN; bdiv <= CDNS_UART_BDIV_MAX; bdiv++) {
 412                 cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1));
 413                 if (cd < 1 || cd > CDNS_UART_CD_MAX)
 414                         continue;
 415
 416                 calc_baud = clk / (cd * (bdiv + 1));
 417
 418                 if (baud > calc_baud)
 419                         bauderror = baud - calc_baud;
 420                 else
 421                         bauderror = calc_baud - baud;
 422
 423                 if (besterror > bauderror) {
 424                         *rbdiv = bdiv;
 425                         *rcd = cd;
 426                         bestbaud = calc_baud;
 427                         besterror = bauderror;
 428                 }
 429         }
 430         /* use the values when percent error is acceptable */
 431         if (((besterror * 100) / baud) < 3)
 432                 bestbaud = baud;
 433
 434         return bestbaud;
 435 }
 436
 437 /**
 438  * cdns_uart_set_baud_rate - Calculate and set the baud rate
 439  * @port: Handle to the uart port structure
 440  * @baud: Baud rate to set
 441  * Return: baud rate, requested baud when possible, or actual baud when there
 442  *         was too much error, zero if no valid divisors are found.
 443  */
 444 static unsigned int cdns_uart_set_baud_rate(struct uart_port *port,
 445                 unsigned int baud)
 446 {
 447         unsigned int calc_baud;
 448         u32 cd = 0, bdiv = 0;
 449         u32 mreg;
 450         int div8;
 451         struct cdns_uart *cdns_uart = port->private_data;
 452
 453         calc_baud = cdns_uart_calc_baud_divs(port->uartclk, baud, &bdiv, &cd,
 454                         &div8);
 455
 456         /* Write new divisors to hardware */
 457         mreg = readl(port->membase + CDNS_UART_MR);
 458         if (div8)
 459                 mreg |= CDNS_UART_MR_CLKSEL;
 460         else
 461                 mreg &= ~CDNS_UART_MR_CLKSEL;
 462         writel(mreg, port->membase + CDNS_UART_MR);
 463         writel(cd, port->membase + CDNS_UART_BAUDGEN);
 464         writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
 465         cdns_uart->baud = baud;
 466
 467         return calc_baud;
 468 }
 469
 470 #ifdef CONFIG_COMMON_CLK
 471 /**
 472  * cdns_uart_clk_notitifer_cb - Clock notifier callback
 473  * @nb:         Notifier block
 474  * @event:      Notify event
 475  * @data:       Notifier data
 476  * Return:      NOTIFY_OK or NOTIFY_DONE on success, NOTIFY_BAD on error.
 477  */
 478 static int cdns_uart_clk_notifier_cb(struct notifier_block *nb,
 479                 unsigned long event, void *data)
 480 {
 481         u32 ctrl_reg;
 482         struct uart_port *port;
 483         int locked = 0;
 484         struct clk_notifier_data *ndata = data;
 485         unsigned long flags = 0;
 486         struct cdns_uart *cdns_uart = to_cdns_uart(nb);
 487
 488         port = cdns_uart->port;
 489         if (port->suspended)
 490                 return NOTIFY_OK;
 491
 492         switch (event) {
 493         case PRE_RATE_CHANGE:
 494         {
 495                 u32 bdiv, cd;
 496                 int div8;
 497
 498                 /*
 499                  * Find out if current baud-rate can be achieved with new clock
 500                  * frequency.
 501                  */
 502                 if (!cdns_uart_calc_baud_divs(ndata->new_rate, cdns_uart->baud,
 503                                         &bdiv, &cd, &div8)) {
 504                         dev_warn(port->dev, "clock rate change rejected\n");
 505                         return NOTIFY_BAD;
 506                 }
 507
 508                 spin_lock_irqsave(&cdns_uart->port->lock, flags);
 509
 510                 /* Disable the TX and RX to set baud rate */
 511                 ctrl_reg = readl(port->membase + CDNS_UART_CR);
 512                 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
 513                 writel(ctrl_reg, port->membase + CDNS_UART_CR);
 514
 515                 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
 516
 517                 return NOTIFY_OK;
 518         }
 519         case POST_RATE_CHANGE:
 520                 /*
 521                  * Set clk dividers to generate correct baud with new clock
 522                  * frequency.
 523                  */
 524
 525                 spin_lock_irqsave(&cdns_uart->port->lock, flags);
 526
 527                 locked = 1;
 528                 port->uartclk = ndata->new_rate;
 529
 530                 cdns_uart->baud = cdns_uart_set_baud_rate(cdns_uart->port,
 531                                 cdns_uart->baud);
 532                 /* fall through */
 533         case ABORT_RATE_CHANGE:
 534                 if (!locked)
 535                         spin_lock_irqsave(&cdns_uart->port->lock, flags);
 536
 537                 /* Set TX/RX Reset */
 538                 ctrl_reg = readl(port->membase + CDNS_UART_CR);
 539                 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
 540                 writel(ctrl_reg, port->membase + CDNS_UART_CR);
 541
 542                 while (readl(port->membase + CDNS_UART_CR) &
 543                                 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
 544                         cpu_relax();
 545
 546                 /*
 547                  * Clear the RX disable and TX disable bits and then set the TX
 548                  * enable bit and RX enable bit to enable the transmitter and
 549                  * receiver.
 550                  */
 551                 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
 552                 ctrl_reg = readl(port->membase + CDNS_UART_CR);
 553                 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
 554                 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
 555                 writel(ctrl_reg, port->membase + CDNS_UART_CR);
 556
 557                 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
 558
 559                 return NOTIFY_OK;
 560         default:
 561                 return NOTIFY_DONE;
 562         }
 563 }
 564 #endif
 565
 566 /**
 567  * cdns_uart_start_tx -  Start transmitting bytes
 568  * @port: Handle to the uart port structure
 569  */
 570 static void cdns_uart_start_tx(struct uart_port *port)
 571 {
 572         unsigned int status;
 573
 574         if (uart_tx_stopped(port))
 575                 return;
 576
 577         /*
 578          * Set the TX enable bit and clear the TX disable bit to enable the
 579          * transmitter.
 580          */
 581         status = readl(port->membase + CDNS_UART_CR);
 582         status &= ~CDNS_UART_CR_TX_DIS;
 583         status |= CDNS_UART_CR_TX_EN;
 584         writel(status, port->membase + CDNS_UART_CR);
 585
 586         if (uart_circ_empty(&port->state->xmit))
 587                 return;
 588
 589         cdns_uart_handle_tx(port);
 590
 591         writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_ISR);
 592         /* Enable the TX Empty interrupt */
 593         writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IER);
 594 }
 595
 596 /**
 597  * cdns_uart_stop_tx - Stop TX
 598  * @port: Handle to the uart port structure
 599  */
 600 static void cdns_uart_stop_tx(struct uart_port *port)
 601 {
 602         unsigned int regval;
 603
 604         regval = readl(port->membase + CDNS_UART_CR);
 605         regval |= CDNS_UART_CR_TX_DIS;
 606         /* Disable the transmitter */
 607         writel(regval, port->membase + CDNS_UART_CR);
 608 }
 609
 610 /**
 611  * cdns_uart_stop_rx - Stop RX
 612  * @port: Handle to the uart port structure
 613  */
 614 static void cdns_uart_stop_rx(struct uart_port *port)
 615 {
 616         unsigned int regval;
 617
 618         /* Disable RX IRQs */
 619         writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IDR);
 620
 621         /* Disable the receiver */
 622         regval = readl(port->membase + CDNS_UART_CR);
 623         regval |= CDNS_UART_CR_RX_DIS;
 624         writel(regval, port->membase + CDNS_UART_CR);
 625 }
 626
 627 /**
 628  * cdns_uart_tx_empty -  Check whether TX is empty
 629  * @port: Handle to the uart port structure
 630  *
 631  * Return: TIOCSER_TEMT on success, 0 otherwise
 632  */
 633 static unsigned int cdns_uart_tx_empty(struct uart_port *port)
 634 {
 635         unsigned int status;
 636
 637         status = readl(port->membase + CDNS_UART_SR) &
 638                                 CDNS_UART_SR_TXEMPTY;
 639         return status ? TIOCSER_TEMT : 0;
 640 }
 641
 642 /**
 643  * cdns_uart_break_ctl - Based on the input ctl we have to start or stop
 644  *                      transmitting char breaks
 645  * @port: Handle to the uart port structure
 646  * @ctl: Value based on which start or stop decision is taken
 647  */
 648 static void cdns_uart_break_ctl(struct uart_port *port, int ctl)
 649 {
 650         unsigned int status;
 651         unsigned long flags;
 652
 653         spin_lock_irqsave(&port->lock, flags);
 654
 655         status = readl(port->membase + CDNS_UART_CR);
 656
 657         if (ctl == -1)
 658                 writel(CDNS_UART_CR_STARTBRK | status,
 659                                 port->membase + CDNS_UART_CR);
 660         else {
 661                 if ((status & CDNS_UART_CR_STOPBRK) == 0)
 662                         writel(CDNS_UART_CR_STOPBRK | status,
 663                                         port->membase + CDNS_UART_CR);
 664         }
 665         spin_unlock_irqrestore(&port->lock, flags);
 666 }
 667
 668 /**
 669  * cdns_uart_set_termios - termios operations, handling data length, parity,
 670  *                              stop bits, flow control, baud rate
 671  * @port: Handle to the uart port structure
 672  * @termios: Handle to the input termios structure
 673  * @old: Values of the previously saved termios structure
 674  */
 675 static void cdns_uart_set_termios(struct uart_port *port,
 676                                 struct ktermios *termios, struct ktermios *old)
 677 {
 678         unsigned int cval = 0;
 679         unsigned int baud, minbaud, maxbaud;
 680         unsigned long flags;
 681         unsigned int ctrl_reg, mode_reg;
 682
 683         spin_lock_irqsave(&port->lock, flags);
 684
 685         /* Wait for the transmit FIFO to empty before making changes */
 686         if (!(readl(port->membase + CDNS_UART_CR) &
 687                                 CDNS_UART_CR_TX_DIS)) {
 688                 while (!(readl(port->membase + CDNS_UART_SR) &
 689                                 CDNS_UART_SR_TXEMPTY)) {
 690                         cpu_relax();
 691                 }
 692         }
 693
 694         /* Disable the TX and RX to set baud rate */
 695         ctrl_reg = readl(port->membase + CDNS_UART_CR);
 696         ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
 697         writel(ctrl_reg, port->membase + CDNS_UART_CR);
 698
 699         /*
 700          * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk
 701          * min and max baud should be calculated here based on port->uartclk.
 702          * this way we get a valid baud and can safely call set_baud()
 703          */
 704         minbaud = port->uartclk /
 705                         ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX * 8);
 706         maxbaud = port->uartclk / (CDNS_UART_BDIV_MIN + 1);
 707         baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud);
 708         baud = cdns_uart_set_baud_rate(port, baud);
 709         if (tty_termios_baud_rate(termios))
 710                 tty_termios_encode_baud_rate(termios, baud, baud);
 711
 712         /* Update the per-port timeout. */
 713         uart_update_timeout(port, termios->c_cflag, baud);
 714
 715         /* Set TX/RX Reset */
 716         ctrl_reg = readl(port->membase + CDNS_UART_CR);
 717         ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
 718         writel(ctrl_reg, port->membase + CDNS_UART_CR);
 719
 720         while (readl(port->membase + CDNS_UART_CR) &
 721                 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
 722                 cpu_relax();
 723
 724         /*
 725          * Clear the RX disable and TX disable bits and then set the TX enable
 726          * bit and RX enable bit to enable the transmitter and receiver.
 727          */
 728         ctrl_reg = readl(port->membase + CDNS_UART_CR);
 729         ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
 730         ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
 731         writel(ctrl_reg, port->membase + CDNS_UART_CR);
 732
 733         writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
 734
 735         port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG |
 736                         CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT;
 737         port->ignore_status_mask = 0;
 738
 739         if (termios->c_iflag & INPCK)
 740                 port->read_status_mask |= CDNS_UART_IXR_PARITY |
 741                 CDNS_UART_IXR_FRAMING;
 742
 743         if (termios->c_iflag & IGNPAR)
 744                 port->ignore_status_mask |= CDNS_UART_IXR_PARITY |
 745                         CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
 746
 747         /* ignore all characters if CREAD is not set */
 748         if ((termios->c_cflag & CREAD) == 0)
 749                 port->ignore_status_mask |= CDNS_UART_IXR_RXTRIG |
 750                         CDNS_UART_IXR_TOUT | CDNS_UART_IXR_PARITY |
 751                         CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
 752
 753         mode_reg = readl(port->membase + CDNS_UART_MR);
 754
 755         /* Handling Data Size */
 756         switch (termios->c_cflag & CSIZE) {
 757         case CS6:
 758                 cval |= CDNS_UART_MR_CHARLEN_6_BIT;
 759                 break;
 760         case CS7:
 761                 cval |= CDNS_UART_MR_CHARLEN_7_BIT;
 762                 break;
 763         default:
 764         case CS8:
 765                 cval |= CDNS_UART_MR_CHARLEN_8_BIT;
 766                 termios->c_cflag &= ~CSIZE;
 767                 termios->c_cflag |= CS8;
 768                 break;
 769         }
 770
 771         /* Handling Parity and Stop Bits length */
 772         if (termios->c_cflag & CSTOPB)
 773                 cval |= CDNS_UART_MR_STOPMODE_2_BIT; /* 2 STOP bits */
 774         else
 775                 cval |= CDNS_UART_MR_STOPMODE_1_BIT; /* 1 STOP bit */
 776
 777         if (termios->c_cflag & PARENB) {
 778                 /* Mark or Space parity */
 779                 if (termios->c_cflag & CMSPAR) {
 780                         if (termios->c_cflag & PARODD)
 781                                 cval |= CDNS_UART_MR_PARITY_MARK;
 782                         else
 783                                 cval |= CDNS_UART_MR_PARITY_SPACE;
 784                 } else {
 785                         if (termios->c_cflag & PARODD)
 786                                 cval |= CDNS_UART_MR_PARITY_ODD;
 787                         else
 788                                 cval |= CDNS_UART_MR_PARITY_EVEN;
 789                 }
 790         } else {
 791                 cval |= CDNS_UART_MR_PARITY_NONE;
 792         }
 793         cval |= mode_reg & 1;
 794         writel(cval, port->membase + CDNS_UART_MR);
 795
 796         spin_unlock_irqrestore(&port->lock, flags);
 797 }
 798
 799 /**
 800  * cdns_uart_startup - Called when an application opens a cdns_uart port
 801  * @port: Handle to the uart port structure
 802  *
 803  * Return: 0 on success, negative errno otherwise
 804  */
 805 static int cdns_uart_startup(struct uart_port *port)
 806 {
 807         struct cdns_uart *cdns_uart = port->private_data;
 808         bool is_brk_support;
 809         int ret;
 810         unsigned long flags;
 811         unsigned int status = 0;
 812
 813         is_brk_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;
 814
 815         spin_lock_irqsave(&port->lock, flags);
 816
 817         /* Disable the TX and RX */
 818         writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
 819                         port->membase + CDNS_UART_CR);
 820
 821         /* Set the Control Register with TX/RX Enable, TX/RX Reset,
 822          * no break chars.
 823          */
 824         writel(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST,
 825                         port->membase + CDNS_UART_CR);
 826
 827         while (readl(port->membase + CDNS_UART_CR) &
 828                 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
 829                 cpu_relax();
 830
 831         /*
 832          * Clear the RX disable bit and then set the RX enable bit to enable
 833          * the receiver.
 834          */
 835         status = readl(port->membase + CDNS_UART_CR);
 836         status &= ~CDNS_UART_CR_RX_DIS;
 837         status |= CDNS_UART_CR_RX_EN;
 838         writel(status, port->membase + CDNS_UART_CR);
 839
 840         /* Set the Mode Register with normal mode,8 data bits,1 stop bit,
 841          * no parity.
 842          */
 843         writel(CDNS_UART_MR_CHMODE_NORM | CDNS_UART_MR_STOPMODE_1_BIT
 844                 | CDNS_UART_MR_PARITY_NONE | CDNS_UART_MR_CHARLEN_8_BIT,
 845                 port->membase + CDNS_UART_MR);
 846
 847         /*
 848          * Set the RX FIFO Trigger level to use most of the FIFO, but it
 849          * can be tuned with a module parameter
 850          */
 851         writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
 852
 853         /*
 854          * Receive Timeout register is enabled but it
 855          * can be tuned with a module parameter
 856          */
 857         writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
 858
 859         /* Clear out any pending interrupts before enabling them */
 860         writel(readl(port->membase + CDNS_UART_ISR),
 861                         port->membase + CDNS_UART_ISR);
 862
 863         spin_unlock_irqrestore(&port->lock, flags);
 864
 865         ret = request_irq(port->irq, cdns_uart_isr, 0, CDNS_UART_NAME, port);
 866         if (ret) {
 867                 dev_err(port->dev, "request_irq '%d' failed with %d\n",
 868                         port->irq, ret);
 869                 return ret;
 870         }
 871
 872         /* Set the Interrupt Registers with desired interrupts */
 873         if (is_brk_support)
 874                 writel(CDNS_UART_RX_IRQS | CDNS_UART_IXR_BRK,
 875                                         port->membase + CDNS_UART_IER);
 876         else
 877                 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IER);
 878
 879         return 0;
 880 }
 881
 882 /**
 883  * cdns_uart_shutdown - Called when an application closes a cdns_uart port
 884  * @port: Handle to the uart port structure
 885  */
 886 static void cdns_uart_shutdown(struct uart_port *port)
 887 {
 888         int status;
 889         unsigned long flags;
 890
 891         spin_lock_irqsave(&port->lock, flags);
 892
 893         /* Disable interrupts */
 894         status = readl(port->membase + CDNS_UART_IMR);
 895         writel(status, port->membase + CDNS_UART_IDR);
 896         writel(0xffffffff, port->membase + CDNS_UART_ISR);
 897
 898         /* Disable the TX and RX */
 899         writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
 900                         port->membase + CDNS_UART_CR);
 901
 902         spin_unlock_irqrestore(&port->lock, flags);
 903
 904         free_irq(port->irq, port);
 905 }
 906
 907 /**
 908  * cdns_uart_type - Set UART type to cdns_uart port
 909  * @port: Handle to the uart port structure
 910  *
 911  * Return: string on success, NULL otherwise
 912  */
 913 static const char *cdns_uart_type(struct uart_port *port)
 914 {
 915         return port->type == PORT_XUARTPS ? CDNS_UART_NAME : NULL;
 916 }
 917
 918 /**
 919  * cdns_uart_verify_port - Verify the port params
 920  * @port: Handle to the uart port structure
 921  * @ser: Handle to the structure whose members are compared
 922  *
 923  * Return: 0 on success, negative errno otherwise.
 924  */
 925 static int cdns_uart_verify_port(struct uart_port *port,
 926                                         struct serial_struct *ser)
 927 {
 928         if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS)
 929                 return -EINVAL;
 930         if (port->irq != ser->irq)
 931                 return -EINVAL;
 932         if (ser->io_type != UPIO_MEM)
 933                 return -EINVAL;
 934         if (port->iobase != ser->port)
 935                 return -EINVAL;
 936         if (ser->hub6 != 0)
 937                 return -EINVAL;
 938         return 0;
 939 }
 940
 941 /**
 942  * cdns_uart_request_port - Claim the memory region attached to cdns_uart port,
 943  *                              called when the driver adds a cdns_uart port via
 944  *                              uart_add_one_port()
 945  * @port: Handle to the uart port structure
 946  *
 947  * Return: 0 on success, negative errno otherwise.
 948  */
 949 static int cdns_uart_request_port(struct uart_port *port)
 950 {
 951         if (!request_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE,
 952                                          CDNS_UART_NAME)) {
 953                 return -ENOMEM;
 954         }
 955
 956         port->membase = ioremap(port->mapbase, CDNS_UART_REGISTER_SPACE);
 957         if (!port->membase) {
 958                 dev_err(port->dev, "Unable to map registers\n");
 959                 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
 960                 return -ENOMEM;
 961         }
 962         return 0;
 963 }
 964
 965 /**
 966  * cdns_uart_release_port - Release UART port
 967  * @port: Handle to the uart port structure
 968  *
 969  * Release the memory region attached to a cdns_uart port. Called when the
 970  * driver removes a cdns_uart port via uart_remove_one_port().
 971  */
 972 static void cdns_uart_release_port(struct uart_port *port)
 973 {
 974         release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
 975         iounmap(port->membase);
 976         port->membase = NULL;
 977 }
 978
 979 /**
 980  * cdns_uart_config_port - Configure UART port
 981  * @port: Handle to the uart port structure
 982  * @flags: If any
 983  */
 984 static void cdns_uart_config_port(struct uart_port *port, int flags)
 985 {
 986         if (flags & UART_CONFIG_TYPE && cdns_uart_request_port(port) == 0)
 987                 port->type = PORT_XUARTPS;
 988 }
 989
 990 /**
 991  * cdns_uart_get_mctrl - Get the modem control state
 992  * @port: Handle to the uart port structure
 993  *
 994  * Return: the modem control state
 995  */
 996 static unsigned int cdns_uart_get_mctrl(struct uart_port *port)
 997 {
 998         return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
 999 }
1000
1001 static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1002 {
1003         u32 val;
1004         u32 mode_reg;
1005
1006         val = readl(port->membase + CDNS_UART_MODEMCR);
1007         mode_reg = readl(port->membase + CDNS_UART_MR);
1008
1009         val &= ~(CDNS_UART_MODEMCR_RTS | CDNS_UART_MODEMCR_DTR |
1010                  CDNS_UART_MODEMCR_FCM);
1011         mode_reg &= ~CDNS_UART_MR_CHMODE_MASK;
1012
1013         if (mctrl & TIOCM_RTS || mctrl & TIOCM_DTR)
1014                 val |= CDNS_UART_MODEMCR_FCM;
1015         if (mctrl & TIOCM_LOOP)
1016                 mode_reg |= CDNS_UART_MR_CHMODE_L_LOOP;
1017         else
1018                 mode_reg |= CDNS_UART_MR_CHMODE_NORM;
1019
1020         writel(val, port->membase + CDNS_UART_MODEMCR);
1021         writel(mode_reg, port->membase + CDNS_UART_MR);
1022 }
1023
1024 #ifdef CONFIG_CONSOLE_POLL
1025 static int cdns_uart_poll_get_char(struct uart_port *port)
1026 {
1027         int c;
1028         unsigned long flags;
1029
1030         spin_lock_irqsave(&port->lock, flags);
1031
1032         /* Check if FIFO is empty */
1033         if (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_RXEMPTY)
1034                 c = NO_POLL_CHAR;
1035         else /* Read a character */
1036                 c = (unsigned char) readl(port->membase + CDNS_UART_FIFO);
1037
1038         spin_unlock_irqrestore(&port->lock, flags);
1039
1040         return c;
1041 }
1042
1043 static void cdns_uart_poll_put_char(struct uart_port *port, unsigned char c)
1044 {
1045         unsigned long flags;
1046
1047         spin_lock_irqsave(&port->lock, flags);
1048
1049         /* Wait until FIFO is empty */
1050         while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1051                 cpu_relax();
1052
1053         /* Write a character */
1054         writel(c, port->membase + CDNS_UART_FIFO);
1055
1056         /* Wait until FIFO is empty */
1057         while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1058                 cpu_relax();
1059
1060         spin_unlock_irqrestore(&port->lock, flags);
1061
1062         return;
1063 }
1064 #endif
1065
1066 static void cdns_uart_pm(struct uart_port *port, unsigned int state,
1067                    unsigned int oldstate)
1068 {
1069         switch (state) {
1070         case UART_PM_STATE_OFF:
1071                 pm_runtime_mark_last_busy(port->dev);
1072                 pm_runtime_put_autosuspend(port->dev);
1073                 break;
1074         default:
1075                 pm_runtime_get_sync(port->dev);
1076                 break;
1077         }
1078 }
1079
1080 static const struct uart_ops cdns_uart_ops = {
1081         .set_mctrl      = cdns_uart_set_mctrl,
1082         .get_mctrl      = cdns_uart_get_mctrl,
1083         .start_tx       = cdns_uart_start_tx,
1084         .stop_tx        = cdns_uart_stop_tx,
1085         .stop_rx        = cdns_uart_stop_rx,
1086         .tx_empty       = cdns_uart_tx_empty,
1087         .break_ctl      = cdns_uart_break_ctl,
1088         .set_termios    = cdns_uart_set_termios,
1089         .startup        = cdns_uart_startup,
1090         .shutdown       = cdns_uart_shutdown,
1091         .pm             = cdns_uart_pm,
1092         .type           = cdns_uart_type,
1093         .verify_port    = cdns_uart_verify_port,
1094         .request_port   = cdns_uart_request_port,
1095         .release_port   = cdns_uart_release_port,
1096         .config_port    = cdns_uart_config_port,
1097 #ifdef CONFIG_CONSOLE_POLL
1098         .poll_get_char  = cdns_uart_poll_get_char,
1099         .poll_put_char  = cdns_uart_poll_put_char,
1100 #endif
1101 };
1102
1103 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1104 /**
1105  * cdns_uart_console_putchar - write the character to the FIFO buffer
1106  * @port: Handle to the uart port structure
1107  * @ch: Character to be written
1108  */
1109 static void cdns_uart_console_putchar(struct uart_port *port, int ch)
1110 {
1111         while (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXFULL)
1112                 cpu_relax();
1113         writel(ch, port->membase + CDNS_UART_FIFO);
1114 }
1115
1116 static void cdns_early_write(struct console *con, const char *s,
1117                                     unsigned n)
1118 {
1119         struct earlycon_device *dev = con->data;
1120
1121         uart_console_write(&dev->port, s, n, cdns_uart_console_putchar);
1122 }
1123
1124 static int __init cdns_early_console_setup(struct earlycon_device *device,
1125                                            const char *opt)
1126 {
1127         struct uart_port *port = &device->port;
1128
1129         if (!port->membase)
1130                 return -ENODEV;
1131
1132         /* initialise control register */
1133         writel(CDNS_UART_CR_TX_EN|CDNS_UART_CR_TXRST|CDNS_UART_CR_RXRST,
1134                port->membase + CDNS_UART_CR);
1135
1136         /* only set baud if specified on command line - otherwise
1137          * assume it has been initialized by a boot loader.
1138          */
1139         if (port->uartclk && device->baud) {
1140                 u32 cd = 0, bdiv = 0;
1141                 u32 mr;
1142                 int div8;
1143
1144                 cdns_uart_calc_baud_divs(port->uartclk, device->baud,
1145                                          &bdiv, &cd, &div8);
1146                 mr = CDNS_UART_MR_PARITY_NONE;
1147                 if (div8)
1148                         mr |= CDNS_UART_MR_CLKSEL;
1149
1150                 writel(mr,   port->membase + CDNS_UART_MR);
1151                 writel(cd,   port->membase + CDNS_UART_BAUDGEN);
1152                 writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
1153         }
1154
1155         device->con->write = cdns_early_write;
1156
1157         return 0;
1158 }
1159 OF_EARLYCON_DECLARE(cdns, "xlnx,xuartps", cdns_early_console_setup);
1160 OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p8", cdns_early_console_setup);
1161 OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p12", cdns_early_console_setup);
1162 OF_EARLYCON_DECLARE(cdns, "xlnx,zynqmp-uart", cdns_early_console_setup);
1163
1164
1165 /* Static pointer to console port */
1166 static struct uart_port *console_port;
1167
1168 /**
1169  * cdns_uart_console_write - perform write operation
1170  * @co: Console handle
1171  * @s: Pointer to character array
1172  * @count: No of characters
1173  */
1174 static void cdns_uart_console_write(struct console *co, const char *s,
1175                                 unsigned int count)
1176 {
1177         struct uart_port *port = console_port;
1178         unsigned long flags;
1179         unsigned int imr, ctrl;
1180         int locked = 1;
1181
1182         if (port->sysrq)
1183                 locked = 0;
1184         else if (oops_in_progress)
1185                 locked = spin_trylock_irqsave(&port->lock, flags);
1186         else
1187                 spin_lock_irqsave(&port->lock, flags);
1188
1189         /* save and disable interrupt */
1190         imr = readl(port->membase + CDNS_UART_IMR);
1191         writel(imr, port->membase + CDNS_UART_IDR);
1192
1193         /*
1194          * Make sure that the tx part is enabled. Set the TX enable bit and
1195          * clear the TX disable bit to enable the transmitter.
1196          */
1197         ctrl = readl(port->membase + CDNS_UART_CR);
1198         ctrl &= ~CDNS_UART_CR_TX_DIS;
1199         ctrl |= CDNS_UART_CR_TX_EN;
1200         writel(ctrl, port->membase + CDNS_UART_CR);
1201
1202         uart_console_write(port, s, count, cdns_uart_console_putchar);
1203         while ((readl(port->membase + CDNS_UART_SR) &
1204                         (CDNS_UART_SR_TXEMPTY | CDNS_UART_SR_TACTIVE)) !=
1205                         CDNS_UART_SR_TXEMPTY)
1206                 cpu_relax();
1207
1208         /* restore interrupt state */
1209         writel(imr, port->membase + CDNS_UART_IER);
1210
1211         if (locked)
1212                 spin_unlock_irqrestore(&port->lock, flags);
1213 }
1214
1215 /**
1216  * cdns_uart_console_setup - Initialize the uart to default config
1217  * @co: Console handle
1218  * @options: Initial settings of uart
1219  *
1220  * Return: 0 on success, negative errno otherwise.
1221  */
1222 static int cdns_uart_console_setup(struct console *co, char *options)
1223 {
1224         struct uart_port *port = console_port;
1225
1226         int baud = 9600;
1227         int bits = 8;
1228         int parity = 'n';
1229         int flow = 'n';
1230
1231         if (!port->membase) {
1232                 pr_debug("console on " CDNS_UART_TTY_NAME "%i not present\n",
1233                          co->index);
1234                 return -ENODEV;
1235         }
1236
1237         if (options)
1238                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1239
1240         return uart_set_options(port, co, baud, parity, bits, flow);
1241 }
1242 #endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */
1243
1244 #ifdef CONFIG_PM_SLEEP
1245 /**
1246  * cdns_uart_suspend - suspend event
1247  * @device: Pointer to the device structure
1248  *
1249  * Return: 0
1250  */
1251 static int cdns_uart_suspend(struct device *device)
1252 {
1253         struct uart_port *port = dev_get_drvdata(device);
1254         struct cdns_uart *cdns_uart = port->private_data;
1255         int may_wake;
1256
1257         may_wake = device_may_wakeup(device);
1258
1259         if (console_suspend_enabled && may_wake) {
1260                 unsigned long flags = 0;
1261
1262                 spin_lock_irqsave(&port->lock, flags);
1263                 /* Empty the receive FIFO 1st before making changes */
1264                 while (!(readl(port->membase + CDNS_UART_SR) &
1265                                         CDNS_UART_SR_RXEMPTY))
1266                         readl(port->membase + CDNS_UART_FIFO);
1267                 /* set RX trigger level to 1 */
1268                 writel(1, port->membase + CDNS_UART_RXWM);
1269                 /* disable RX timeout interrups */
1270                 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IDR);
1271                 spin_unlock_irqrestore(&port->lock, flags);
1272         }
1273
1274         /*
1275          * Call the API provided in serial_core.c file which handles
1276          * the suspend.
1277          */
1278         return uart_suspend_port(cdns_uart->cdns_uart_driver, port);
1279 }
1280
1281 /**
1282  * cdns_uart_resume - Resume after a previous suspend
1283  * @device: Pointer to the device structure
1284  *
1285  * Return: 0
1286  */
1287 static int cdns_uart_resume(struct device *device)
1288 {
1289         struct uart_port *port = dev_get_drvdata(device);
1290         struct cdns_uart *cdns_uart = port->private_data;
1291         unsigned long flags = 0;
1292         u32 ctrl_reg;
1293         int may_wake;
1294
1295         may_wake = device_may_wakeup(device);
1296
1297         if (console_suspend_enabled && !may_wake) {
1298                 clk_enable(cdns_uart->pclk);
1299                 clk_enable(cdns_uart->uartclk);
1300
1301                 spin_lock_irqsave(&port->lock, flags);
1302
1303                 /* Set TX/RX Reset */
1304                 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1305                 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
1306                 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1307                 while (readl(port->membase + CDNS_UART_CR) &
1308                                 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
1309                         cpu_relax();
1310
1311                 /* restore rx timeout value */
1312                 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
1313                 /* Enable Tx/Rx */
1314                 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1315                 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
1316                 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
1317                 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1318
1319                 clk_disable(cdns_uart->uartclk);
1320                 clk_disable(cdns_uart->pclk);
1321                 spin_unlock_irqrestore(&port->lock, flags);
1322         } else {
1323                 spin_lock_irqsave(&port->lock, flags);
1324                 /* restore original rx trigger level */
1325                 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
1326                 /* enable RX timeout interrupt */
1327                 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IER);
1328                 spin_unlock_irqrestore(&port->lock, flags);
1329         }
1330
1331         return uart_resume_port(cdns_uart->cdns_uart_driver, port);
1332 }
1333 #endif /* ! CONFIG_PM_SLEEP */
1334 static int __maybe_unused cdns_runtime_suspend(struct device *dev)
1335 {
1336         struct uart_port *port = dev_get_drvdata(dev);
1337         struct cdns_uart *cdns_uart = port->private_data;
1338
1339         clk_disable(cdns_uart->uartclk);
1340         clk_disable(cdns_uart->pclk);
1341         return 0;
1342 };
1343
1344 static int __maybe_unused cdns_runtime_resume(struct device *dev)
1345 {
1346         struct uart_port *port = dev_get_drvdata(dev);
1347         struct cdns_uart *cdns_uart = port->private_data;
1348
1349         clk_enable(cdns_uart->pclk);
1350         clk_enable(cdns_uart->uartclk);
1351         return 0;
1352 };
1353
1354 static const struct dev_pm_ops cdns_uart_dev_pm_ops = {
1355         SET_SYSTEM_SLEEP_PM_OPS(cdns_uart_suspend, cdns_uart_resume)
1356         SET_RUNTIME_PM_OPS(cdns_runtime_suspend,
1357                            cdns_runtime_resume, NULL)
1358 };
1359
1360 static const struct cdns_platform_data zynqmp_uart_def = {
1361                                 .quirks = CDNS_UART_RXBS_SUPPORT, };
1362
1363 /* Match table for of_platform binding */
1364 static const struct of_device_id cdns_uart_of_match[] = {
1365         { .compatible = "xlnx,xuartps", },
1366         { .compatible = "cdns,uart-r1p8", },
1367         { .compatible = "cdns,uart-r1p12", .data = &zynqmp_uart_def },
1368         { .compatible = "xlnx,zynqmp-uart", .data = &zynqmp_uart_def },
1369         {}
1370 };
1371 MODULE_DEVICE_TABLE(of, cdns_uart_of_match);
1372
1373 /**
1374  * cdns_uart_probe - Platform driver probe
1375  * @pdev: Pointer to the platform device structure
1376  *
1377  * Return: 0 on success, negative errno otherwise
1378  */
1379 static int cdns_uart_probe(struct platform_device *pdev)
1380 {
1381         int rc, irq;
1382         struct uart_port *port;
1383         struct resource *res;
1384         struct cdns_uart *cdns_uart_data;
1385         const struct of_device_id *match;
1386         struct uart_driver *cdns_uart_uart_driver;
1387         char *driver_name;
1388 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1389         struct console *cdns_uart_console;
1390 #endif
1391
1392         cdns_uart_data = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_data),
1393                         GFP_KERNEL);
1394         if (!cdns_uart_data)
1395                 return -ENOMEM;
1396         port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
1397         if (!port)
1398                 return -ENOMEM;
1399
1400         cdns_uart_uart_driver = devm_kzalloc(&pdev->dev,
1401                                              sizeof(*cdns_uart_uart_driver),
1402                                              GFP_KERNEL);
1403         if (!cdns_uart_uart_driver)
1404                 return -ENOMEM;
1405
1406         /* Look for a serialN alias */
1407         cdns_uart_data->id = of_alias_get_id(pdev->dev.of_node, "serial");
1408         if (cdns_uart_data->id < 0)
1409                 cdns_uart_data->id = 0;
1410
1411         if (cdns_uart_data->id >= CDNS_UART_NR_PORTS) {
1412                 dev_err(&pdev->dev, "Cannot get uart_port structure\n");
1413                 return -ENODEV;
1414         }
1415
1416         /* There is a need to use unique driver name */
1417         driver_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s%d",
1418                                      CDNS_UART_NAME, cdns_uart_data->id);
1419         if (!driver_name)
1420                 return -ENOMEM;
1421
1422         cdns_uart_uart_driver->owner = THIS_MODULE;
1423         cdns_uart_uart_driver->driver_name = driver_name;
1424         cdns_uart_uart_driver->dev_name = CDNS_UART_TTY_NAME;
1425         cdns_uart_uart_driver->major = CDNS_UART_MAJOR;
1426         cdns_uart_uart_driver->minor = cdns_uart_data->id;
1427         cdns_uart_uart_driver->nr = 1;
1428
1429 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1430         cdns_uart_console = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_console),
1431                                          GFP_KERNEL);
1432         if (!cdns_uart_console)
1433                 return -ENOMEM;
1434
1435         strncpy(cdns_uart_console->name, CDNS_UART_TTY_NAME,
1436                 sizeof(cdns_uart_console->name));
1437         cdns_uart_console->index = cdns_uart_data->id;
1438         cdns_uart_console->write = cdns_uart_console_write;
1439         cdns_uart_console->device = uart_console_device;
1440         cdns_uart_console->setup = cdns_uart_console_setup;
1441         cdns_uart_console->flags = CON_PRINTBUFFER;
1442         cdns_uart_console->data = cdns_uart_uart_driver;
1443         cdns_uart_uart_driver->cons = cdns_uart_console;
1444 #endif
1445
1446         rc = uart_register_driver(cdns_uart_uart_driver);
1447         if (rc < 0) {
1448                 dev_err(&pdev->dev, "Failed to register driver\n");
1449                 return rc;
1450         }
1451
1452         cdns_uart_data->cdns_uart_driver = cdns_uart_uart_driver;
1453
1454         /*
1455          * Setting up proper name_base needs to be done after uart
1456          * registration because tty_driver structure is not filled.
1457          * name_base is 0 by default.
1458          */
1459         cdns_uart_uart_driver->tty_driver->name_base = cdns_uart_data->id;
1460
1461         match = of_match_node(cdns_uart_of_match, pdev->dev.of_node);
1462         if (match && match->data) {
1463                 const struct cdns_platform_data *data = match->data;
1464
1465                 cdns_uart_data->quirks = data->quirks;
1466         }
1467
1468         cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "pclk");
1469         if (IS_ERR(cdns_uart_data->pclk)) {
1470                 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "aper_clk");
1471                 if (!IS_ERR(cdns_uart_data->pclk))
1472                         dev_err(&pdev->dev, "clock name 'aper_clk' is deprecated.\n");
1473         }
1474         if (IS_ERR(cdns_uart_data->pclk)) {
1475                 dev_err(&pdev->dev, "pclk clock not found.\n");
1476                 rc = PTR_ERR(cdns_uart_data->pclk);
1477                 goto err_out_unregister_driver;
1478         }
1479
1480         cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "uart_clk");
1481         if (IS_ERR(cdns_uart_data->uartclk)) {
1482                 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "ref_clk");
1483                 if (!IS_ERR(cdns_uart_data->uartclk))
1484                         dev_err(&pdev->dev, "clock name 'ref_clk' is deprecated.\n");
1485         }
1486         if (IS_ERR(cdns_uart_data->uartclk)) {
1487                 dev_err(&pdev->dev, "uart_clk clock not found.\n");
1488                 rc = PTR_ERR(cdns_uart_data->uartclk);
1489                 goto err_out_unregister_driver;
1490         }
1491
1492         rc = clk_prepare_enable(cdns_uart_data->pclk);
1493         if (rc) {
1494                 dev_err(&pdev->dev, "Unable to enable pclk clock.\n");
1495                 goto err_out_unregister_driver;
1496         }
1497         rc = clk_prepare_enable(cdns_uart_data->uartclk);
1498         if (rc) {
1499                 dev_err(&pdev->dev, "Unable to enable device clock.\n");
1500                 goto err_out_clk_dis_pclk;
1501         }
1502
1503         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1504         if (!res) {
1505                 rc = -ENODEV;
1506                 goto err_out_clk_disable;
1507         }
1508
1509         irq = platform_get_irq(pdev, 0);
1510         if (irq <= 0) {
1511                 rc = -ENXIO;
1512                 goto err_out_clk_disable;
1513         }
1514
1515 #ifdef CONFIG_COMMON_CLK
1516         cdns_uart_data->clk_rate_change_nb.notifier_call =
1517                         cdns_uart_clk_notifier_cb;
1518         if (clk_notifier_register(cdns_uart_data->uartclk,
1519                                 &cdns_uart_data->clk_rate_change_nb))
1520                 dev_warn(&pdev->dev, "Unable to register clock notifier.\n");
1521 #endif
1522
1523         /* At this point, we've got an empty uart_port struct, initialize it */
1524         spin_lock_init(&port->lock);
1525         port->type      = PORT_UNKNOWN;
1526         port->iotype    = UPIO_MEM32;
1527         port->flags     = UPF_BOOT_AUTOCONF;
1528         port->ops       = &cdns_uart_ops;
1529         port->fifosize  = CDNS_UART_FIFO_SIZE;
1530
1531         /*
1532          * Register the port.
1533          * This function also registers this device with the tty layer
1534          * and triggers invocation of the config_port() entry point.
1535          */
1536         port->mapbase = res->start;
1537         port->irq = irq;
1538         port->dev = &pdev->dev;
1539         port->uartclk = clk_get_rate(cdns_uart_data->uartclk);
1540         port->private_data = cdns_uart_data;
1541         cdns_uart_data->port = port;
1542         platform_set_drvdata(pdev, port);
1543
1544         pm_runtime_use_autosuspend(&pdev->dev);
1545         pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT);
1546         pm_runtime_set_active(&pdev->dev);
1547         pm_runtime_enable(&pdev->dev);
1548
1549 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1550         /*
1551          * If console hasn't been found yet try to assign this port
1552          * because it is required to be assigned for console setup function.
1553          * If register_console() don't assign value, then console_port pointer
1554          * is cleanup.
1555          */
1556         if (!console_port)
1557                 console_port = port;
1558 #endif
1559
1560         rc = uart_add_one_port(cdns_uart_uart_driver, port);
1561         if (rc) {
1562                 dev_err(&pdev->dev,
1563                         "uart_add_one_port() failed; err=%i\n", rc);
1564                 goto err_out_pm_disable;
1565         }
1566
1567 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1568         /* This is not port which is used for console that's why clean it up */
1569         if (console_port == port &&
1570             !(cdns_uart_uart_driver->cons->flags & CON_ENABLED))
1571                 console_port = NULL;
1572 #endif
1573
1574         return 0;
1575
1576 err_out_pm_disable:
1577         pm_runtime_disable(&pdev->dev);
1578         pm_runtime_set_suspended(&pdev->dev);
1579         pm_runtime_dont_use_autosuspend(&pdev->dev);
1580 #ifdef CONFIG_COMMON_CLK
1581         clk_notifier_unregister(cdns_uart_data->uartclk,
1582                         &cdns_uart_data->clk_rate_change_nb);
1583 #endif
1584 err_out_clk_disable:
1585         clk_disable_unprepare(cdns_uart_data->uartclk);
1586 err_out_clk_dis_pclk:
1587         clk_disable_unprepare(cdns_uart_data->pclk);
1588 err_out_unregister_driver:
1589         uart_unregister_driver(cdns_uart_data->cdns_uart_driver);
1590
1591         return rc;
1592 }
1593
1594 /**
1595  * cdns_uart_remove - called when the platform driver is unregistered
1596  * @pdev: Pointer to the platform device structure
1597  *
1598  * Return: 0 on success, negative errno otherwise
1599  */
1600 static int cdns_uart_remove(struct platform_device *pdev)
1601 {
1602         struct uart_port *port = platform_get_drvdata(pdev);
1603         struct cdns_uart *cdns_uart_data = port->private_data;
1604         int rc;
1605
1606         /* Remove the cdns_uart port from the serial core */
1607 #ifdef CONFIG_COMMON_CLK
1608         clk_notifier_unregister(cdns_uart_data->uartclk,
1609                         &cdns_uart_data->clk_rate_change_nb);
1610 #endif
1611         rc = uart_remove_one_port(cdns_uart_data->cdns_uart_driver, port);
1612         port->mapbase = 0;
1613         clk_disable_unprepare(cdns_uart_data->uartclk);
1614         clk_disable_unprepare(cdns_uart_data->pclk);
1615         pm_runtime_disable(&pdev->dev);
1616         pm_runtime_set_suspended(&pdev->dev);
1617         pm_runtime_dont_use_autosuspend(&pdev->dev);
1618
1619 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1620         if (console_port == port)
1621                 console_port = NULL;
1622 #endif
1623
1624         uart_unregister_driver(cdns_uart_data->cdns_uart_driver);
1625         return rc;
1626 }
1627
1628 static struct platform_driver cdns_uart_platform_driver = {
1629         .probe   = cdns_uart_probe,
1630         .remove  = cdns_uart_remove,
1631         .driver  = {
1632                 .name = CDNS_UART_NAME,
1633                 .of_match_table = cdns_uart_of_match,
1634                 .pm = &cdns_uart_dev_pm_ops,
1635                 },
1636 };
1637
1638 static int __init cdns_uart_init(void)
1639 {
1640         /* Register the platform driver */
1641         return platform_driver_register(&cdns_uart_platform_driver);
1642 }
1643
1644 static void __exit cdns_uart_exit(void)
1645 {
1646         /* Unregister the platform driver */
1647         platform_driver_unregister(&cdns_uart_platform_driver);
1648 }
1649
1650 arch_initcall(cdns_uart_init);
1651 module_exit(cdns_uart_exit);
1652
1653 MODULE_DESCRIPTION("Driver for Cadence UART");
1654 MODULE_AUTHOR("Xilinx Inc.");
1655 MODULE_LICENSE("GPL");