drivers/tty/serial/fsl_lpuart.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  *  Freescale lpuart serial port driver
   4  *
   5  *  Copyright 2012-2014 Freescale Semiconductor, Inc.
   6  */
   7
   8 #if defined(CONFIG_SERIAL_FSL_LPUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
   9 #define SUPPORT_SYSRQ
  10 #endif
  11
  12 #include <linux/clk.h>
  13 #include <linux/console.h>
  14 #include <linux/dma-mapping.h>
  15 #include <linux/dmaengine.h>
  16 #include <linux/dmapool.h>
  17 #include <linux/io.h>
  18 #include <linux/irq.h>
  19 #include <linux/module.h>
  20 #include <linux/of.h>
  21 #include <linux/of_device.h>
  22 #include <linux/of_dma.h>
  23 #include <linux/serial_core.h>
  24 #include <linux/slab.h>
  25 #include <linux/tty_flip.h>
  26
  27 /* All registers are 8-bit width */
  28 #define UARTBDH                 0x00
  29 #define UARTBDL                 0x01
  30 #define UARTCR1                 0x02
  31 #define UARTCR2                 0x03
  32 #define UARTSR1                 0x04
  33 #define UARTCR3                 0x06
  34 #define UARTDR                  0x07
  35 #define UARTCR4                 0x0a
  36 #define UARTCR5                 0x0b
  37 #define UARTMODEM               0x0d
  38 #define UARTPFIFO               0x10
  39 #define UARTCFIFO               0x11
  40 #define UARTSFIFO               0x12
  41 #define UARTTWFIFO              0x13
  42 #define UARTTCFIFO              0x14
  43 #define UARTRWFIFO              0x15
  44
  45 #define UARTBDH_LBKDIE          0x80
  46 #define UARTBDH_RXEDGIE         0x40
  47 #define UARTBDH_SBR_MASK        0x1f
  48
  49 #define UARTCR1_LOOPS           0x80
  50 #define UARTCR1_RSRC            0x20
  51 #define UARTCR1_M               0x10
  52 #define UARTCR1_WAKE            0x08
  53 #define UARTCR1_ILT             0x04
  54 #define UARTCR1_PE              0x02
  55 #define UARTCR1_PT              0x01
  56
  57 #define UARTCR2_TIE             0x80
  58 #define UARTCR2_TCIE            0x40
  59 #define UARTCR2_RIE             0x20
  60 #define UARTCR2_ILIE            0x10
  61 #define UARTCR2_TE              0x08
  62 #define UARTCR2_RE              0x04
  63 #define UARTCR2_RWU             0x02
  64 #define UARTCR2_SBK             0x01
  65
  66 #define UARTSR1_TDRE            0x80
  67 #define UARTSR1_TC              0x40
  68 #define UARTSR1_RDRF            0x20
  69 #define UARTSR1_IDLE            0x10
  70 #define UARTSR1_OR              0x08
  71 #define UARTSR1_NF              0x04
  72 #define UARTSR1_FE              0x02
  73 #define UARTSR1_PE              0x01
  74
  75 #define UARTCR3_R8              0x80
  76 #define UARTCR3_T8              0x40
  77 #define UARTCR3_TXDIR           0x20
  78 #define UARTCR3_TXINV           0x10
  79 #define UARTCR3_ORIE            0x08
  80 #define UARTCR3_NEIE            0x04
  81 #define UARTCR3_FEIE            0x02
  82 #define UARTCR3_PEIE            0x01
  83
  84 #define UARTCR4_MAEN1           0x80
  85 #define UARTCR4_MAEN2           0x40
  86 #define UARTCR4_M10             0x20
  87 #define UARTCR4_BRFA_MASK       0x1f
  88 #define UARTCR4_BRFA_OFF        0
  89
  90 #define UARTCR5_TDMAS           0x80
  91 #define UARTCR5_RDMAS           0x20
  92
  93 #define UARTMODEM_RXRTSE        0x08
  94 #define UARTMODEM_TXRTSPOL      0x04
  95 #define UARTMODEM_TXRTSE        0x02
  96 #define UARTMODEM_TXCTSE        0x01
  97
  98 #define UARTPFIFO_TXFE          0x80
  99 #define UARTPFIFO_FIFOSIZE_MASK 0x7
 100 #define UARTPFIFO_TXSIZE_OFF    4
 101 #define UARTPFIFO_RXFE          0x08
 102 #define UARTPFIFO_RXSIZE_OFF    0
 103
 104 #define UARTCFIFO_TXFLUSH       0x80
 105 #define UARTCFIFO_RXFLUSH       0x40
 106 #define UARTCFIFO_RXOFE         0x04
 107 #define UARTCFIFO_TXOFE         0x02
 108 #define UARTCFIFO_RXUFE         0x01
 109
 110 #define UARTSFIFO_TXEMPT        0x80
 111 #define UARTSFIFO_RXEMPT        0x40
 112 #define UARTSFIFO_RXOF          0x04
 113 #define UARTSFIFO_TXOF          0x02
 114 #define UARTSFIFO_RXUF          0x01
 115
 116 /* 32-bit register definition */
 117 #define UARTBAUD                0x00
 118 #define UARTSTAT                0x04
 119 #define UARTCTRL                0x08
 120 #define UARTDATA                0x0C
 121 #define UARTMATCH               0x10
 122 #define UARTMODIR               0x14
 123 #define UARTFIFO                0x18
 124 #define UARTWATER               0x1c
 125
 126 #define UARTBAUD_MAEN1          0x80000000
 127 #define UARTBAUD_MAEN2          0x40000000
 128 #define UARTBAUD_M10            0x20000000
 129 #define UARTBAUD_TDMAE          0x00800000
 130 #define UARTBAUD_RDMAE          0x00200000
 131 #define UARTBAUD_MATCFG         0x00400000
 132 #define UARTBAUD_BOTHEDGE       0x00020000
 133 #define UARTBAUD_RESYNCDIS      0x00010000
 134 #define UARTBAUD_LBKDIE         0x00008000
 135 #define UARTBAUD_RXEDGIE        0x00004000
 136 #define UARTBAUD_SBNS           0x00002000
 137 #define UARTBAUD_SBR            0x00000000
 138 #define UARTBAUD_SBR_MASK       0x1fff
 139 #define UARTBAUD_OSR_MASK       0x1f
 140 #define UARTBAUD_OSR_SHIFT      24
 141
 142 #define UARTSTAT_LBKDIF         0x80000000
 143 #define UARTSTAT_RXEDGIF        0x40000000
 144 #define UARTSTAT_MSBF           0x20000000
 145 #define UARTSTAT_RXINV          0x10000000
 146 #define UARTSTAT_RWUID          0x08000000
 147 #define UARTSTAT_BRK13          0x04000000
 148 #define UARTSTAT_LBKDE          0x02000000
 149 #define UARTSTAT_RAF            0x01000000
 150 #define UARTSTAT_TDRE           0x00800000
 151 #define UARTSTAT_TC             0x00400000
 152 #define UARTSTAT_RDRF           0x00200000
 153 #define UARTSTAT_IDLE           0x00100000
 154 #define UARTSTAT_OR             0x00080000
 155 #define UARTSTAT_NF             0x00040000
 156 #define UARTSTAT_FE             0x00020000
 157 #define UARTSTAT_PE             0x00010000
 158 #define UARTSTAT_MA1F           0x00008000
 159 #define UARTSTAT_M21F           0x00004000
 160
 161 #define UARTCTRL_R8T9           0x80000000
 162 #define UARTCTRL_R9T8           0x40000000
 163 #define UARTCTRL_TXDIR          0x20000000
 164 #define UARTCTRL_TXINV          0x10000000
 165 #define UARTCTRL_ORIE           0x08000000
 166 #define UARTCTRL_NEIE           0x04000000
 167 #define UARTCTRL_FEIE           0x02000000
 168 #define UARTCTRL_PEIE           0x01000000
 169 #define UARTCTRL_TIE            0x00800000
 170 #define UARTCTRL_TCIE           0x00400000
 171 #define UARTCTRL_RIE            0x00200000
 172 #define UARTCTRL_ILIE           0x00100000
 173 #define UARTCTRL_TE             0x00080000
 174 #define UARTCTRL_RE             0x00040000
 175 #define UARTCTRL_RWU            0x00020000
 176 #define UARTCTRL_SBK            0x00010000
 177 #define UARTCTRL_MA1IE          0x00008000
 178 #define UARTCTRL_MA2IE          0x00004000
 179 #define UARTCTRL_IDLECFG        0x00000100
 180 #define UARTCTRL_LOOPS          0x00000080
 181 #define UARTCTRL_DOZEEN         0x00000040
 182 #define UARTCTRL_RSRC           0x00000020
 183 #define UARTCTRL_M              0x00000010
 184 #define UARTCTRL_WAKE           0x00000008
 185 #define UARTCTRL_ILT            0x00000004
 186 #define UARTCTRL_PE             0x00000002
 187 #define UARTCTRL_PT             0x00000001
 188
 189 #define UARTDATA_NOISY          0x00008000
 190 #define UARTDATA_PARITYE        0x00004000
 191 #define UARTDATA_FRETSC         0x00002000
 192 #define UARTDATA_RXEMPT         0x00001000
 193 #define UARTDATA_IDLINE         0x00000800
 194 #define UARTDATA_MASK           0x3ff
 195
 196 #define UARTMODIR_IREN          0x00020000
 197 #define UARTMODIR_TXCTSSRC      0x00000020
 198 #define UARTMODIR_TXCTSC        0x00000010
 199 #define UARTMODIR_RXRTSE        0x00000008
 200 #define UARTMODIR_TXRTSPOL      0x00000004
 201 #define UARTMODIR_TXRTSE        0x00000002
 202 #define UARTMODIR_TXCTSE        0x00000001
 203
 204 #define UARTFIFO_TXEMPT         0x00800000
 205 #define UARTFIFO_RXEMPT         0x00400000
 206 #define UARTFIFO_TXOF           0x00020000
 207 #define UARTFIFO_RXUF           0x00010000
 208 #define UARTFIFO_TXFLUSH        0x00008000
 209 #define UARTFIFO_RXFLUSH        0x00004000
 210 #define UARTFIFO_TXOFE          0x00000200
 211 #define UARTFIFO_RXUFE          0x00000100
 212 #define UARTFIFO_TXFE           0x00000080
 213 #define UARTFIFO_FIFOSIZE_MASK  0x7
 214 #define UARTFIFO_TXSIZE_OFF     4
 215 #define UARTFIFO_RXFE           0x00000008
 216 #define UARTFIFO_RXSIZE_OFF     0
 217
 218 #define UARTWATER_COUNT_MASK    0xff
 219 #define UARTWATER_TXCNT_OFF     8
 220 #define UARTWATER_RXCNT_OFF     24
 221 #define UARTWATER_WATER_MASK    0xff
 222 #define UARTWATER_TXWATER_OFF   0
 223 #define UARTWATER_RXWATER_OFF   16
 224
 225 /* Rx DMA timeout in ms, which is used to calculate Rx ring buffer size */
 226 #define DMA_RX_TIMEOUT          (10)
 227
 228 #define DRIVER_NAME     "fsl-lpuart"
 229 #define DEV_NAME        "ttyLP"
 230 #define UART_NR         6
 231
 232 /* IMX lpuart has four extra unused regs located at the beginning */
 233 #define IMX_REG_OFF     0x10
 234
 235 static DEFINE_IDA(fsl_lpuart_ida);
 236
 237 struct lpuart_port {
 238         struct uart_port        port;
 239         struct clk              *clk;
 240         unsigned int            txfifo_size;
 241         unsigned int            rxfifo_size;
 242
 243         bool                    lpuart_dma_tx_use;
 244         bool                    lpuart_dma_rx_use;
 245         struct dma_chan         *dma_tx_chan;
 246         struct dma_chan         *dma_rx_chan;
 247         struct dma_async_tx_descriptor  *dma_tx_desc;
 248         struct dma_async_tx_descriptor  *dma_rx_desc;
 249         dma_cookie_t            dma_tx_cookie;
 250         dma_cookie_t            dma_rx_cookie;
 251         unsigned int            dma_tx_bytes;
 252         unsigned int            dma_rx_bytes;
 253         bool                    dma_tx_in_progress;
 254         unsigned int            dma_rx_timeout;
 255         struct timer_list       lpuart_timer;
 256         struct scatterlist      rx_sgl, tx_sgl[2];
 257         struct circ_buf         rx_ring;
 258         int                     rx_dma_rng_buf_len;
 259         unsigned int            dma_tx_nents;
 260         wait_queue_head_t       dma_wait;
 261 };
 262
 263 struct lpuart_soc_data {
 264         char    iotype;
 265         u8      reg_off;
 266 };
 267
 268 static const struct lpuart_soc_data vf_data = {
 269         .iotype = UPIO_MEM,
 270 };
 271
 272 static const struct lpuart_soc_data ls_data = {
 273         .iotype = UPIO_MEM32BE,
 274 };
 275
 276 static struct lpuart_soc_data imx_data = {
 277         .iotype = UPIO_MEM32,
 278         .reg_off = IMX_REG_OFF,
 279 };
 280
 281 static const struct of_device_id lpuart_dt_ids[] = {
 282         { .compatible = "fsl,vf610-lpuart",     .data = &vf_data, },
 283         { .compatible = "fsl,ls1021a-lpuart",   .data = &ls_data, },
 284         { .compatible = "fsl,imx7ulp-lpuart",   .data = &imx_data, },
 285         { /* sentinel */ }
 286 };
 287 MODULE_DEVICE_TABLE(of, lpuart_dt_ids);
 288
 289 /* Forward declare this for the dma callbacks*/
 290 static void lpuart_dma_tx_complete(void *arg);
 291
 292 static inline u32 lpuart32_read(struct uart_port *port, u32 off)
 293 {
 294         switch (port->iotype) {
 295         case UPIO_MEM32:
 296                 return readl(port->membase + off);
 297         case UPIO_MEM32BE:
 298                 return ioread32be(port->membase + off);
 299         default:
 300                 return 0;
 301         }
 302 }
 303
 304 static inline void lpuart32_write(struct uart_port *port, u32 val,
 305                                   u32 off)
 306 {
 307         switch (port->iotype) {
 308         case UPIO_MEM32:
 309                 writel(val, port->membase + off);
 310                 break;
 311         case UPIO_MEM32BE:
 312                 iowrite32be(val, port->membase + off);
 313                 break;
 314         }
 315 }
 316
 317 static void lpuart_stop_tx(struct uart_port *port)
 318 {
 319         unsigned char temp;
 320
 321         temp = readb(port->membase + UARTCR2);
 322         temp &= ~(UARTCR2_TIE | UARTCR2_TCIE);
 323         writeb(temp, port->membase + UARTCR2);
 324 }
 325
 326 static void lpuart32_stop_tx(struct uart_port *port)
 327 {
 328         unsigned long temp;
 329
 330         temp = lpuart32_read(port, UARTCTRL);
 331         temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE);
 332         lpuart32_write(port, temp, UARTCTRL);
 333 }
 334
 335 static void lpuart_stop_rx(struct uart_port *port)
 336 {
 337         unsigned char temp;
 338
 339         temp = readb(port->membase + UARTCR2);
 340         writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2);
 341 }
 342
 343 static void lpuart32_stop_rx(struct uart_port *port)
 344 {
 345         unsigned long temp;
 346
 347         temp = lpuart32_read(port, UARTCTRL);
 348         lpuart32_write(port, temp & ~UARTCTRL_RE, UARTCTRL);
 349 }
 350
 351 static void lpuart_dma_tx(struct lpuart_port *sport)
 352 {
 353         struct circ_buf *xmit = &sport->port.state->xmit;
 354         struct scatterlist *sgl = sport->tx_sgl;
 355         struct device *dev = sport->port.dev;
 356         int ret;
 357
 358         if (sport->dma_tx_in_progress)
 359                 return;
 360
 361         sport->dma_tx_bytes = uart_circ_chars_pending(xmit);
 362
 363         if (xmit->tail < xmit->head || xmit->head == 0) {
 364                 sport->dma_tx_nents = 1;
 365                 sg_init_one(sgl, xmit->buf + xmit->tail, sport->dma_tx_bytes);
 366         } else {
 367                 sport->dma_tx_nents = 2;
 368                 sg_init_table(sgl, 2);
 369                 sg_set_buf(sgl, xmit->buf + xmit->tail,
 370                                 UART_XMIT_SIZE - xmit->tail);
 371                 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
 372         }
 373
 374         ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
 375         if (!ret) {
 376                 dev_err(dev, "DMA mapping error for TX.\n");
 377                 return;
 378         }
 379
 380         sport->dma_tx_desc = dmaengine_prep_slave_sg(sport->dma_tx_chan, sgl,
 381                                         sport->dma_tx_nents,
 382                                         DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
 383         if (!sport->dma_tx_desc) {
 384                 dma_unmap_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
 385                 dev_err(dev, "Cannot prepare TX slave DMA!\n");
 386                 return;
 387         }
 388
 389         sport->dma_tx_desc->callback = lpuart_dma_tx_complete;
 390         sport->dma_tx_desc->callback_param = sport;
 391         sport->dma_tx_in_progress = true;
 392         sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc);
 393         dma_async_issue_pending(sport->dma_tx_chan);
 394 }
 395
 396 static void lpuart_dma_tx_complete(void *arg)
 397 {
 398         struct lpuart_port *sport = arg;
 399         struct scatterlist *sgl = &sport->tx_sgl[0];
 400         struct circ_buf *xmit = &sport->port.state->xmit;
 401         unsigned long flags;
 402
 403         spin_lock_irqsave(&sport->port.lock, flags);
 404
 405         dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
 406
 407         xmit->tail = (xmit->tail + sport->dma_tx_bytes) & (UART_XMIT_SIZE - 1);
 408
 409         sport->port.icount.tx += sport->dma_tx_bytes;
 410         sport->dma_tx_in_progress = false;
 411         spin_unlock_irqrestore(&sport->port.lock, flags);
 412
 413         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 414                 uart_write_wakeup(&sport->port);
 415
 416         if (waitqueue_active(&sport->dma_wait)) {
 417                 wake_up(&sport->dma_wait);
 418                 return;
 419         }
 420
 421         spin_lock_irqsave(&sport->port.lock, flags);
 422
 423         if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
 424                 lpuart_dma_tx(sport);
 425
 426         spin_unlock_irqrestore(&sport->port.lock, flags);
 427 }
 428
 429 static dma_addr_t lpuart_dma_datareg_addr(struct lpuart_port *sport)
 430 {
 431         switch (sport->port.iotype) {
 432         case UPIO_MEM32:
 433                 return sport->port.mapbase + UARTDATA;
 434         case UPIO_MEM32BE:
 435                 return sport->port.mapbase + UARTDATA + sizeof(u32) - 1;
 436         }
 437         return sport->port.mapbase + UARTDR;
 438 }
 439
 440 static int lpuart_dma_tx_request(struct uart_port *port)
 441 {
 442         struct lpuart_port *sport = container_of(port,
 443                                         struct lpuart_port, port);
 444         struct dma_slave_config dma_tx_sconfig = {};
 445         int ret;
 446
 447         dma_tx_sconfig.dst_addr = lpuart_dma_datareg_addr(sport);
 448         dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 449         dma_tx_sconfig.dst_maxburst = 1;
 450         dma_tx_sconfig.direction = DMA_MEM_TO_DEV;
 451         ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig);
 452
 453         if (ret) {
 454                 dev_err(sport->port.dev,
 455                                 "DMA slave config failed, err = %d\n", ret);
 456                 return ret;
 457         }
 458
 459         return 0;
 460 }
 461
 462 static void lpuart_flush_buffer(struct uart_port *port)
 463 {
 464         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
 465
 466         if (sport->lpuart_dma_tx_use) {
 467                 if (sport->dma_tx_in_progress) {
 468                         dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0],
 469                                 sport->dma_tx_nents, DMA_TO_DEVICE);
 470                         sport->dma_tx_in_progress = false;
 471                 }
 472                 dmaengine_terminate_all(sport->dma_tx_chan);
 473         }
 474 }
 475
 476 #if defined(CONFIG_CONSOLE_POLL)
 477
 478 static int lpuart_poll_init(struct uart_port *port)
 479 {
 480         struct lpuart_port *sport = container_of(port,
 481                                         struct lpuart_port, port);
 482         unsigned long flags;
 483         unsigned char temp;
 484
 485         sport->port.fifosize = 0;
 486
 487         spin_lock_irqsave(&sport->port.lock, flags);
 488         /* Disable Rx & Tx */
 489         writeb(0, sport->port.membase + UARTCR2);
 490
 491         temp = readb(sport->port.membase + UARTPFIFO);
 492         /* Enable Rx and Tx FIFO */
 493         writeb(temp | UARTPFIFO_RXFE | UARTPFIFO_TXFE,
 494                         sport->port.membase + UARTPFIFO);
 495
 496         /* flush Tx and Rx FIFO */
 497         writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
 498                         sport->port.membase + UARTCFIFO);
 499
 500         /* explicitly clear RDRF */
 501         if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
 502                 readb(sport->port.membase + UARTDR);
 503                 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
 504         }
 505
 506         writeb(0, sport->port.membase + UARTTWFIFO);
 507         writeb(1, sport->port.membase + UARTRWFIFO);
 508
 509         /* Enable Rx and Tx */
 510         writeb(UARTCR2_RE | UARTCR2_TE, sport->port.membase + UARTCR2);
 511         spin_unlock_irqrestore(&sport->port.lock, flags);
 512
 513         return 0;
 514 }
 515
 516 static void lpuart_poll_put_char(struct uart_port *port, unsigned char c)
 517 {
 518         /* drain */
 519         while (!(readb(port->membase + UARTSR1) & UARTSR1_TDRE))
 520                 barrier();
 521
 522         writeb(c, port->membase + UARTDR);
 523 }
 524
 525 static int lpuart_poll_get_char(struct uart_port *port)
 526 {
 527         if (!(readb(port->membase + UARTSR1) & UARTSR1_RDRF))
 528                 return NO_POLL_CHAR;
 529
 530         return readb(port->membase + UARTDR);
 531 }
 532
 533 static int lpuart32_poll_init(struct uart_port *port)
 534 {
 535         unsigned long flags;
 536         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
 537         u32 temp;
 538
 539         sport->port.fifosize = 0;
 540
 541         spin_lock_irqsave(&sport->port.lock, flags);
 542
 543         /* Disable Rx & Tx */
 544         writel(0, sport->port.membase + UARTCTRL);
 545
 546         temp = readl(sport->port.membase + UARTFIFO);
 547
 548         /* Enable Rx and Tx FIFO */
 549         writel(temp | UARTFIFO_RXFE | UARTFIFO_TXFE,
 550                    sport->port.membase + UARTFIFO);
 551
 552         /* flush Tx and Rx FIFO */
 553         writel(UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH,
 554                         sport->port.membase + UARTFIFO);
 555
 556         /* explicitly clear RDRF */
 557         if (readl(sport->port.membase + UARTSTAT) & UARTSTAT_RDRF) {
 558                 readl(sport->port.membase + UARTDATA);
 559                 writel(UARTFIFO_RXUF, sport->port.membase + UARTFIFO);
 560         }
 561
 562         /* Enable Rx and Tx */
 563         writel(UARTCTRL_RE | UARTCTRL_TE, sport->port.membase + UARTCTRL);
 564         spin_unlock_irqrestore(&sport->port.lock, flags);
 565
 566         return 0;
 567 }
 568
 569 static void lpuart32_poll_put_char(struct uart_port *port, unsigned char c)
 570 {
 571         while (!(readl(port->membase + UARTSTAT) & UARTSTAT_TDRE))
 572                 barrier();
 573
 574         writel(c, port->membase + UARTDATA);
 575 }
 576
 577 static int lpuart32_poll_get_char(struct uart_port *port)
 578 {
 579         if (!(readl(port->membase + UARTSTAT) & UARTSTAT_RDRF))
 580                 return NO_POLL_CHAR;
 581
 582         return readl(port->membase + UARTDATA);
 583 }
 584 #endif
 585
 586 static inline void lpuart_transmit_buffer(struct lpuart_port *sport)
 587 {
 588         struct circ_buf *xmit = &sport->port.state->xmit;
 589
 590         while (!uart_circ_empty(xmit) &&
 591                 (readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) {
 592                 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR);
 593                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 594                 sport->port.icount.tx++;
 595         }
 596
 597         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 598                 uart_write_wakeup(&sport->port);
 599
 600         if (uart_circ_empty(xmit))
 601                 lpuart_stop_tx(&sport->port);
 602 }
 603
 604 static inline void lpuart32_transmit_buffer(struct lpuart_port *sport)
 605 {
 606         struct circ_buf *xmit = &sport->port.state->xmit;
 607         unsigned long txcnt;
 608
 609         txcnt = lpuart32_read(&sport->port, UARTWATER);
 610         txcnt = txcnt >> UARTWATER_TXCNT_OFF;
 611         txcnt &= UARTWATER_COUNT_MASK;
 612         while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) {
 613                 lpuart32_write(&sport->port, xmit->buf[xmit->tail], UARTDATA);
 614                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 615                 sport->port.icount.tx++;
 616                 txcnt = lpuart32_read(&sport->port, UARTWATER);
 617                 txcnt = txcnt >> UARTWATER_TXCNT_OFF;
 618                 txcnt &= UARTWATER_COUNT_MASK;
 619         }
 620
 621         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 622                 uart_write_wakeup(&sport->port);
 623
 624         if (uart_circ_empty(xmit))
 625                 lpuart32_stop_tx(&sport->port);
 626 }
 627
 628 static void lpuart_start_tx(struct uart_port *port)
 629 {
 630         struct lpuart_port *sport = container_of(port,
 631                         struct lpuart_port, port);
 632         struct circ_buf *xmit = &sport->port.state->xmit;
 633         unsigned char temp;
 634
 635         temp = readb(port->membase + UARTCR2);
 636         writeb(temp | UARTCR2_TIE, port->membase + UARTCR2);
 637
 638         if (sport->lpuart_dma_tx_use) {
 639                 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port))
 640                         lpuart_dma_tx(sport);
 641         } else {
 642                 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE)
 643                         lpuart_transmit_buffer(sport);
 644         }
 645 }
 646
 647 static void lpuart32_start_tx(struct uart_port *port)
 648 {
 649         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
 650         struct circ_buf *xmit = &sport->port.state->xmit;
 651         unsigned long temp;
 652
 653         if (sport->lpuart_dma_tx_use) {
 654                 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port))
 655                         lpuart_dma_tx(sport);
 656         } else {
 657                 temp = lpuart32_read(port, UARTCTRL);
 658                 lpuart32_write(port, temp | UARTCTRL_TIE, UARTCTRL);
 659
 660                 if (lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE)
 661                         lpuart32_transmit_buffer(sport);
 662         }
 663 }
 664
 665 /* return TIOCSER_TEMT when transmitter is not busy */
 666 static unsigned int lpuart_tx_empty(struct uart_port *port)
 667 {
 668         struct lpuart_port *sport = container_of(port,
 669                         struct lpuart_port, port);
 670         unsigned char sr1 = readb(port->membase + UARTSR1);
 671         unsigned char sfifo = readb(port->membase + UARTSFIFO);
 672
 673         if (sport->dma_tx_in_progress)
 674                 return 0;
 675
 676         if (sr1 & UARTSR1_TC && sfifo & UARTSFIFO_TXEMPT)
 677                 return TIOCSER_TEMT;
 678
 679         return 0;
 680 }
 681
 682 static unsigned int lpuart32_tx_empty(struct uart_port *port)
 683 {
 684         struct lpuart_port *sport = container_of(port,
 685                         struct lpuart_port, port);
 686         unsigned long stat = lpuart32_read(port, UARTSTAT);
 687         unsigned long sfifo = lpuart32_read(port, UARTFIFO);
 688
 689         if (sport->dma_tx_in_progress)
 690                 return 0;
 691
 692         if (stat & UARTSTAT_TC && sfifo & UARTFIFO_TXEMPT)
 693                 return TIOCSER_TEMT;
 694
 695         return 0;
 696 }
 697
 698 static bool lpuart_is_32(struct lpuart_port *sport)
 699 {
 700         return sport->port.iotype == UPIO_MEM32 ||
 701                sport->port.iotype ==  UPIO_MEM32BE;
 702 }
 703
 704 static irqreturn_t lpuart_txint(int irq, void *dev_id)
 705 {
 706         struct lpuart_port *sport = dev_id;
 707         struct circ_buf *xmit = &sport->port.state->xmit;
 708         unsigned long flags;
 709
 710         spin_lock_irqsave(&sport->port.lock, flags);
 711         if (sport->port.x_char) {
 712                 if (lpuart_is_32(sport))
 713                         lpuart32_write(&sport->port, sport->port.x_char, UARTDATA);
 714                 else
 715                         writeb(sport->port.x_char, sport->port.membase + UARTDR);
 716                 goto out;
 717         }
 718
 719         if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
 720                 if (lpuart_is_32(sport))
 721                         lpuart32_stop_tx(&sport->port);
 722                 else
 723                         lpuart_stop_tx(&sport->port);
 724                 goto out;
 725         }
 726
 727         if (lpuart_is_32(sport))
 728                 lpuart32_transmit_buffer(sport);
 729         else
 730                 lpuart_transmit_buffer(sport);
 731
 732         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 733                 uart_write_wakeup(&sport->port);
 734
 735 out:
 736         spin_unlock_irqrestore(&sport->port.lock, flags);
 737         return IRQ_HANDLED;
 738 }
 739
 740 static irqreturn_t lpuart_rxint(int irq, void *dev_id)
 741 {
 742         struct lpuart_port *sport = dev_id;
 743         unsigned int flg, ignored = 0;
 744         struct tty_port *port = &sport->port.state->port;
 745         unsigned long flags;
 746         unsigned char rx, sr;
 747
 748         spin_lock_irqsave(&sport->port.lock, flags);
 749
 750         while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) {
 751                 flg = TTY_NORMAL;
 752                 sport->port.icount.rx++;
 753                 /*
 754                  * to clear the FE, OR, NF, FE, PE flags,
 755                  * read SR1 then read DR
 756                  */
 757                 sr = readb(sport->port.membase + UARTSR1);
 758                 rx = readb(sport->port.membase + UARTDR);
 759
 760                 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
 761                         continue;
 762
 763                 if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) {
 764                         if (sr & UARTSR1_PE)
 765                                 sport->port.icount.parity++;
 766                         else if (sr & UARTSR1_FE)
 767                                 sport->port.icount.frame++;
 768
 769                         if (sr & UARTSR1_OR)
 770                                 sport->port.icount.overrun++;
 771
 772                         if (sr & sport->port.ignore_status_mask) {
 773                                 if (++ignored > 100)
 774                                         goto out;
 775                                 continue;
 776                         }
 777
 778                         sr &= sport->port.read_status_mask;
 779
 780                         if (sr & UARTSR1_PE)
 781                                 flg = TTY_PARITY;
 782                         else if (sr & UARTSR1_FE)
 783                                 flg = TTY_FRAME;
 784
 785                         if (sr & UARTSR1_OR)
 786                                 flg = TTY_OVERRUN;
 787
 788 #ifdef SUPPORT_SYSRQ
 789                         sport->port.sysrq = 0;
 790 #endif
 791                 }
 792
 793                 tty_insert_flip_char(port, rx, flg);
 794         }
 795
 796 out:
 797         spin_unlock_irqrestore(&sport->port.lock, flags);
 798
 799         tty_flip_buffer_push(port);
 800         return IRQ_HANDLED;
 801 }
 802
 803 static irqreturn_t lpuart32_rxint(int irq, void *dev_id)
 804 {
 805         struct lpuart_port *sport = dev_id;
 806         unsigned int flg, ignored = 0;
 807         struct tty_port *port = &sport->port.state->port;
 808         unsigned long flags;
 809         unsigned long rx, sr;
 810
 811         spin_lock_irqsave(&sport->port.lock, flags);
 812
 813         while (!(lpuart32_read(&sport->port, UARTFIFO) & UARTFIFO_RXEMPT)) {
 814                 flg = TTY_NORMAL;
 815                 sport->port.icount.rx++;
 816                 /*
 817                  * to clear the FE, OR, NF, FE, PE flags,
 818                  * read STAT then read DATA reg
 819                  */
 820                 sr = lpuart32_read(&sport->port, UARTSTAT);
 821                 rx = lpuart32_read(&sport->port, UARTDATA);
 822                 rx &= 0x3ff;
 823
 824                 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
 825                         continue;
 826
 827                 if (sr & (UARTSTAT_PE | UARTSTAT_OR | UARTSTAT_FE)) {
 828                         if (sr & UARTSTAT_PE)
 829                                 sport->port.icount.parity++;
 830                         else if (sr & UARTSTAT_FE)
 831                                 sport->port.icount.frame++;
 832
 833                         if (sr & UARTSTAT_OR)
 834                                 sport->port.icount.overrun++;
 835
 836                         if (sr & sport->port.ignore_status_mask) {
 837                                 if (++ignored > 100)
 838                                         goto out;
 839                                 continue;
 840                         }
 841
 842                         sr &= sport->port.read_status_mask;
 843
 844                         if (sr & UARTSTAT_PE)
 845                                 flg = TTY_PARITY;
 846                         else if (sr & UARTSTAT_FE)
 847                                 flg = TTY_FRAME;
 848
 849                         if (sr & UARTSTAT_OR)
 850                                 flg = TTY_OVERRUN;
 851
 852 #ifdef SUPPORT_SYSRQ
 853                         sport->port.sysrq = 0;
 854 #endif
 855                 }
 856
 857                 tty_insert_flip_char(port, rx, flg);
 858         }
 859
 860 out:
 861         spin_unlock_irqrestore(&sport->port.lock, flags);
 862
 863         tty_flip_buffer_push(port);
 864         return IRQ_HANDLED;
 865 }
 866
 867 static irqreturn_t lpuart_int(int irq, void *dev_id)
 868 {
 869         struct lpuart_port *sport = dev_id;
 870         unsigned char sts;
 871
 872         sts = readb(sport->port.membase + UARTSR1);
 873
 874         if (sts & UARTSR1_RDRF)
 875                 lpuart_rxint(irq, dev_id);
 876
 877         if (sts & UARTSR1_TDRE)
 878                 lpuart_txint(irq, dev_id);
 879
 880         return IRQ_HANDLED;
 881 }
 882
 883 static irqreturn_t lpuart32_int(int irq, void *dev_id)
 884 {
 885         struct lpuart_port *sport = dev_id;
 886         unsigned long sts, rxcount;
 887
 888         sts = lpuart32_read(&sport->port, UARTSTAT);
 889         rxcount = lpuart32_read(&sport->port, UARTWATER);
 890         rxcount = rxcount >> UARTWATER_RXCNT_OFF;
 891
 892         if ((sts & UARTSTAT_RDRF || rxcount > 0) && !sport->lpuart_dma_rx_use)
 893                 lpuart32_rxint(irq, dev_id);
 894
 895         if ((sts & UARTSTAT_TDRE) && !sport->lpuart_dma_tx_use)
 896                 lpuart_txint(irq, dev_id);
 897
 898         lpuart32_write(&sport->port, sts, UARTSTAT);
 899         return IRQ_HANDLED;
 900 }
 901
 902 static void lpuart_copy_rx_to_tty(struct lpuart_port *sport)
 903 {
 904         struct tty_port *port = &sport->port.state->port;
 905         struct dma_tx_state state;
 906         enum dma_status dmastat;
 907         struct circ_buf *ring = &sport->rx_ring;
 908         unsigned long flags;
 909         int count = 0;
 910
 911         if (lpuart_is_32(sport)) {
 912                 unsigned long sr = lpuart32_read(&sport->port, UARTSTAT);
 913
 914                 if (sr & (UARTSTAT_PE | UARTSTAT_FE)) {
 915                         /* Read DR to clear the error flags */
 916                         lpuart32_read(&sport->port, UARTDATA);
 917
 918                         if (sr & UARTSTAT_PE)
 919                                 sport->port.icount.parity++;
 920                         else if (sr & UARTSTAT_FE)
 921                                 sport->port.icount.frame++;
 922                 }
 923         } else {
 924                 unsigned char sr = readb(sport->port.membase + UARTSR1);
 925
 926                 if (sr & (UARTSR1_PE | UARTSR1_FE)) {
 927                         /* Read DR to clear the error flags */
 928                         readb(sport->port.membase + UARTDR);
 929
 930                         if (sr & UARTSR1_PE)
 931                                 sport->port.icount.parity++;
 932                         else if (sr & UARTSR1_FE)
 933                                 sport->port.icount.frame++;
 934                 }
 935         }
 936
 937         async_tx_ack(sport->dma_rx_desc);
 938
 939         spin_lock_irqsave(&sport->port.lock, flags);
 940
 941         dmastat = dmaengine_tx_status(sport->dma_rx_chan,
 942                                 sport->dma_rx_cookie,
 943                                 &state);
 944
 945         if (dmastat == DMA_ERROR) {
 946                 dev_err(sport->port.dev, "Rx DMA transfer failed!\n");
 947                 spin_unlock_irqrestore(&sport->port.lock, flags);
 948                 return;
 949         }
 950
 951         /* CPU claims ownership of RX DMA buffer */
 952         dma_sync_sg_for_cpu(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
 953
 954         /*
 955          * ring->head points to the end of data already written by the DMA.
 956          * ring->tail points to the beginning of data to be read by the
 957          * framework.
 958          * The current transfer size should not be larger than the dma buffer
 959          * length.
 960          */
 961         ring->head = sport->rx_sgl.length - state.residue;
 962         BUG_ON(ring->head > sport->rx_sgl.length);
 963         /*
 964          * At this point ring->head may point to the first byte right after the
 965          * last byte of the dma buffer:
 966          * 0 <= ring->head <= sport->rx_sgl.length
 967          *
 968          * However ring->tail must always points inside the dma buffer:
 969          * 0 <= ring->tail <= sport->rx_sgl.length - 1
 970          *
 971          * Since we use a ring buffer, we have to handle the case
 972          * where head is lower than tail. In such a case, we first read from
 973          * tail to the end of the buffer then reset tail.
 974          */
 975         if (ring->head < ring->tail) {
 976                 count = sport->rx_sgl.length - ring->tail;
 977
 978                 tty_insert_flip_string(port, ring->buf + ring->tail, count);
 979                 ring->tail = 0;
 980                 sport->port.icount.rx += count;
 981         }
 982
 983         /* Finally we read data from tail to head */
 984         if (ring->tail < ring->head) {
 985                 count = ring->head - ring->tail;
 986                 tty_insert_flip_string(port, ring->buf + ring->tail, count);
 987                 /* Wrap ring->head if needed */
 988                 if (ring->head >= sport->rx_sgl.length)
 989                         ring->head = 0;
 990                 ring->tail = ring->head;
 991                 sport->port.icount.rx += count;
 992         }
 993
 994         dma_sync_sg_for_device(sport->port.dev, &sport->rx_sgl, 1,
 995                                DMA_FROM_DEVICE);
 996
 997         spin_unlock_irqrestore(&sport->port.lock, flags);
 998
 999         tty_flip_buffer_push(port);
1000         mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout);
1001 }
1002
1003 static void lpuart_dma_rx_complete(void *arg)
1004 {
1005         struct lpuart_port *sport = arg;
1006
1007         lpuart_copy_rx_to_tty(sport);
1008 }
1009
1010 static void lpuart_timer_func(struct timer_list *t)
1011 {
1012         struct lpuart_port *sport = from_timer(sport, t, lpuart_timer);
1013
1014         lpuart_copy_rx_to_tty(sport);
1015 }
1016
1017 static inline int lpuart_start_rx_dma(struct lpuart_port *sport)
1018 {
1019         struct dma_slave_config dma_rx_sconfig = {};
1020         struct circ_buf *ring = &sport->rx_ring;
1021         int ret, nent;
1022         int bits, baud;
1023         struct tty_port *port = &sport->port.state->port;
1024         struct tty_struct *tty = port->tty;
1025         struct ktermios *termios = &tty->termios;
1026
1027         baud = tty_get_baud_rate(tty);
1028
1029         bits = (termios->c_cflag & CSIZE) == CS7 ? 9 : 10;
1030         if (termios->c_cflag & PARENB)
1031                 bits++;
1032
1033         /*
1034          * Calculate length of one DMA buffer size to keep latency below
1035          * 10ms at any baud rate.
1036          */
1037         sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud /  bits / 1000) * 2;
1038         sport->rx_dma_rng_buf_len = (1 << (fls(sport->rx_dma_rng_buf_len) - 1));
1039         if (sport->rx_dma_rng_buf_len < 16)
1040                 sport->rx_dma_rng_buf_len = 16;
1041
1042         ring->buf = kmalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC);
1043         if (!ring->buf)
1044                 return -ENOMEM;
1045
1046         sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len);
1047         sg_set_buf(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len);
1048         nent = dma_map_sg(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
1049
1050         if (!nent) {
1051                 dev_err(sport->port.dev, "DMA Rx mapping error\n");
1052                 return -EINVAL;
1053         }
1054
1055         dma_rx_sconfig.src_addr = lpuart_dma_datareg_addr(sport);
1056         dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1057         dma_rx_sconfig.src_maxburst = 1;
1058         dma_rx_sconfig.direction = DMA_DEV_TO_MEM;
1059         ret = dmaengine_slave_config(sport->dma_rx_chan, &dma_rx_sconfig);
1060
1061         if (ret < 0) {
1062                 dev_err(sport->port.dev,
1063                                 "DMA Rx slave config failed, err = %d\n", ret);
1064                 return ret;
1065         }
1066
1067         sport->dma_rx_desc = dmaengine_prep_dma_cyclic(sport->dma_rx_chan,
1068                                  sg_dma_address(&sport->rx_sgl),
1069                                  sport->rx_sgl.length,
1070                                  sport->rx_sgl.length / 2,
1071                                  DMA_DEV_TO_MEM,
1072                                  DMA_PREP_INTERRUPT);
1073         if (!sport->dma_rx_desc) {
1074                 dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n");
1075                 return -EFAULT;
1076         }
1077
1078         sport->dma_rx_desc->callback = lpuart_dma_rx_complete;
1079         sport->dma_rx_desc->callback_param = sport;
1080         sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc);
1081         dma_async_issue_pending(sport->dma_rx_chan);
1082
1083         if (lpuart_is_32(sport)) {
1084                 unsigned long temp = lpuart32_read(&sport->port, UARTBAUD);
1085
1086                 lpuart32_write(&sport->port, temp | UARTBAUD_RDMAE, UARTBAUD);
1087         } else {
1088                 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS,
1089                        sport->port.membase + UARTCR5);
1090         }
1091
1092         return 0;
1093 }
1094
1095 static void lpuart_dma_rx_free(struct uart_port *port)
1096 {
1097         struct lpuart_port *sport = container_of(port,
1098                                         struct lpuart_port, port);
1099
1100         if (sport->dma_rx_chan)
1101                 dmaengine_terminate_all(sport->dma_rx_chan);
1102
1103         dma_unmap_sg(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
1104         kfree(sport->rx_ring.buf);
1105         sport->rx_ring.tail = 0;
1106         sport->rx_ring.head = 0;
1107         sport->dma_rx_desc = NULL;
1108         sport->dma_rx_cookie = -EINVAL;
1109 }
1110
1111 static int lpuart_config_rs485(struct uart_port *port,
1112                         struct serial_rs485 *rs485)
1113 {
1114         struct lpuart_port *sport = container_of(port,
1115                         struct lpuart_port, port);
1116
1117         u8 modem = readb(sport->port.membase + UARTMODEM) &
1118                 ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE);
1119         writeb(modem, sport->port.membase + UARTMODEM);
1120
1121         /* clear unsupported configurations */
1122         rs485->delay_rts_before_send = 0;
1123         rs485->delay_rts_after_send = 0;
1124         rs485->flags &= ~SER_RS485_RX_DURING_TX;
1125
1126         if (rs485->flags & SER_RS485_ENABLED) {
1127                 /* Enable auto RS-485 RTS mode */
1128                 modem |= UARTMODEM_TXRTSE;
1129
1130                 /*
1131                  * RTS needs to be logic HIGH either during transer _or_ after
1132                  * transfer, other variants are not supported by the hardware.
1133                  */
1134
1135                 if (!(rs485->flags & (SER_RS485_RTS_ON_SEND |
1136                                 SER_RS485_RTS_AFTER_SEND)))
1137                         rs485->flags |= SER_RS485_RTS_ON_SEND;
1138
1139                 if (rs485->flags & SER_RS485_RTS_ON_SEND &&
1140                                 rs485->flags & SER_RS485_RTS_AFTER_SEND)
1141                         rs485->flags &= ~SER_RS485_RTS_AFTER_SEND;
1142
1143                 /*
1144                  * The hardware defaults to RTS logic HIGH while transfer.
1145                  * Switch polarity in case RTS shall be logic HIGH
1146                  * after transfer.
1147                  * Note: UART is assumed to be active high.
1148                  */
1149                 if (rs485->flags & SER_RS485_RTS_ON_SEND)
1150                         modem &= ~UARTMODEM_TXRTSPOL;
1151                 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
1152                         modem |= UARTMODEM_TXRTSPOL;
1153         }
1154
1155         /* Store the new configuration */
1156         sport->port.rs485 = *rs485;
1157
1158         writeb(modem, sport->port.membase + UARTMODEM);
1159         return 0;
1160 }
1161
1162 static unsigned int lpuart_get_mctrl(struct uart_port *port)
1163 {
1164         unsigned int temp = 0;
1165         unsigned char reg;
1166
1167         reg = readb(port->membase + UARTMODEM);
1168         if (reg & UARTMODEM_TXCTSE)
1169                 temp |= TIOCM_CTS;
1170
1171         if (reg & UARTMODEM_RXRTSE)
1172                 temp |= TIOCM_RTS;
1173
1174         return temp;
1175 }
1176
1177 static unsigned int lpuart32_get_mctrl(struct uart_port *port)
1178 {
1179         unsigned int temp = 0;
1180         unsigned long reg;
1181
1182         reg = lpuart32_read(port, UARTMODIR);
1183         if (reg & UARTMODIR_TXCTSE)
1184                 temp |= TIOCM_CTS;
1185
1186         if (reg & UARTMODIR_RXRTSE)
1187                 temp |= TIOCM_RTS;
1188
1189         return temp;
1190 }
1191
1192 static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1193 {
1194         unsigned char temp;
1195         struct lpuart_port *sport = container_of(port,
1196                                 struct lpuart_port, port);
1197
1198         /* Make sure RXRTSE bit is not set when RS485 is enabled */
1199         if (!(sport->port.rs485.flags & SER_RS485_ENABLED)) {
1200                 temp = readb(sport->port.membase + UARTMODEM) &
1201                         ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1202
1203                 if (mctrl & TIOCM_RTS)
1204                         temp |= UARTMODEM_RXRTSE;
1205
1206                 if (mctrl & TIOCM_CTS)
1207                         temp |= UARTMODEM_TXCTSE;
1208
1209                 writeb(temp, port->membase + UARTMODEM);
1210         }
1211 }
1212
1213 static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl)
1214 {
1215         unsigned long temp;
1216
1217         temp = lpuart32_read(port, UARTMODIR) &
1218                         ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE);
1219
1220         if (mctrl & TIOCM_RTS)
1221                 temp |= UARTMODIR_RXRTSE;
1222
1223         if (mctrl & TIOCM_CTS)
1224                 temp |= UARTMODIR_TXCTSE;
1225
1226         lpuart32_write(port, temp, UARTMODIR);
1227 }
1228
1229 static void lpuart_break_ctl(struct uart_port *port, int break_state)
1230 {
1231         unsigned char temp;
1232
1233         temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK;
1234
1235         if (break_state != 0)
1236                 temp |= UARTCR2_SBK;
1237
1238         writeb(temp, port->membase + UARTCR2);
1239 }
1240
1241 static void lpuart32_break_ctl(struct uart_port *port, int break_state)
1242 {
1243         unsigned long temp;
1244
1245         temp = lpuart32_read(port, UARTCTRL) & ~UARTCTRL_SBK;
1246
1247         if (break_state != 0)
1248                 temp |= UARTCTRL_SBK;
1249
1250         lpuart32_write(port, temp, UARTCTRL);
1251 }
1252
1253 static void lpuart_setup_watermark(struct lpuart_port *sport)
1254 {
1255         unsigned char val, cr2;
1256         unsigned char cr2_saved;
1257
1258         cr2 = readb(sport->port.membase + UARTCR2);
1259         cr2_saved = cr2;
1260         cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE |
1261                         UARTCR2_RIE | UARTCR2_RE);
1262         writeb(cr2, sport->port.membase + UARTCR2);
1263
1264         val = readb(sport->port.membase + UARTPFIFO);
1265         writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE,
1266                         sport->port.membase + UARTPFIFO);
1267
1268         /* flush Tx and Rx FIFO */
1269         writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
1270                         sport->port.membase + UARTCFIFO);
1271
1272         /* explicitly clear RDRF */
1273         if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
1274                 readb(sport->port.membase + UARTDR);
1275                 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
1276         }
1277
1278         writeb(0, sport->port.membase + UARTTWFIFO);
1279         writeb(1, sport->port.membase + UARTRWFIFO);
1280
1281         /* Restore cr2 */
1282         writeb(cr2_saved, sport->port.membase + UARTCR2);
1283 }
1284
1285 static void lpuart32_setup_watermark(struct lpuart_port *sport)
1286 {
1287         unsigned long val, ctrl;
1288         unsigned long ctrl_saved;
1289
1290         ctrl = lpuart32_read(&sport->port, UARTCTRL);
1291         ctrl_saved = ctrl;
1292         ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE |
1293                         UARTCTRL_RIE | UARTCTRL_RE);
1294         lpuart32_write(&sport->port, ctrl, UARTCTRL);
1295
1296         /* enable FIFO mode */
1297         val = lpuart32_read(&sport->port, UARTFIFO);
1298         val |= UARTFIFO_TXFE | UARTFIFO_RXFE;
1299         val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;
1300         lpuart32_write(&sport->port, val, UARTFIFO);
1301
1302         /* set the watermark */
1303         val = (0x1 << UARTWATER_RXWATER_OFF) | (0x0 << UARTWATER_TXWATER_OFF);
1304         lpuart32_write(&sport->port, val, UARTWATER);
1305
1306         /* Restore cr2 */
1307         lpuart32_write(&sport->port, ctrl_saved, UARTCTRL);
1308 }
1309
1310 static void rx_dma_timer_init(struct lpuart_port *sport)
1311 {
1312                 timer_setup(&sport->lpuart_timer, lpuart_timer_func, 0);
1313                 sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout;
1314                 add_timer(&sport->lpuart_timer);
1315 }
1316
1317 static int lpuart_startup(struct uart_port *port)
1318 {
1319         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1320         unsigned long flags;
1321         unsigned char temp;
1322
1323         /* determine FIFO size and enable FIFO mode */
1324         temp = readb(sport->port.membase + UARTPFIFO);
1325
1326         sport->txfifo_size = 0x1 << (((temp >> UARTPFIFO_TXSIZE_OFF) &
1327                 UARTPFIFO_FIFOSIZE_MASK) + 1);
1328
1329         sport->port.fifosize = sport->txfifo_size;
1330
1331         sport->rxfifo_size = 0x1 << (((temp >> UARTPFIFO_RXSIZE_OFF) &
1332                 UARTPFIFO_FIFOSIZE_MASK) + 1);
1333
1334         spin_lock_irqsave(&sport->port.lock, flags);
1335
1336         lpuart_setup_watermark(sport);
1337
1338         temp = readb(sport->port.membase + UARTCR2);
1339         temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE);
1340         writeb(temp, sport->port.membase + UARTCR2);
1341
1342         if (sport->dma_rx_chan && !lpuart_start_rx_dma(sport)) {
1343                 /* set Rx DMA timeout */
1344                 sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT);
1345                 if (!sport->dma_rx_timeout)
1346                      sport->dma_rx_timeout = 1;
1347
1348                 sport->lpuart_dma_rx_use = true;
1349                 rx_dma_timer_init(sport);
1350         } else {
1351                 sport->lpuart_dma_rx_use = false;
1352         }
1353
1354         if (sport->dma_tx_chan && !lpuart_dma_tx_request(port)) {
1355                 init_waitqueue_head(&sport->dma_wait);
1356                 sport->lpuart_dma_tx_use = true;
1357                 temp = readb(port->membase + UARTCR5);
1358                 writeb(temp | UARTCR5_TDMAS, port->membase + UARTCR5);
1359         } else {
1360                 sport->lpuart_dma_tx_use = false;
1361         }
1362
1363         spin_unlock_irqrestore(&sport->port.lock, flags);
1364
1365         return 0;
1366 }
1367
1368 static int lpuart32_startup(struct uart_port *port)
1369 {
1370         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1371         unsigned long flags;
1372         unsigned long temp;
1373
1374         /* determine FIFO size */
1375         temp = lpuart32_read(&sport->port, UARTFIFO);
1376
1377         sport->txfifo_size = 0x1 << (((temp >> UARTFIFO_TXSIZE_OFF) &
1378                 UARTFIFO_FIFOSIZE_MASK) - 1);
1379
1380         sport->port.fifosize = sport->txfifo_size;
1381
1382         sport->rxfifo_size = 0x1 << (((temp >> UARTFIFO_RXSIZE_OFF) &
1383                 UARTFIFO_FIFOSIZE_MASK) - 1);
1384
1385         spin_lock_irqsave(&sport->port.lock, flags);
1386
1387         lpuart32_setup_watermark(sport);
1388
1389         temp = lpuart32_read(&sport->port, UARTCTRL);
1390         temp |= UARTCTRL_RE | UARTCTRL_TE | UARTCTRL_ILIE;
1391         lpuart32_write(&sport->port, temp, UARTCTRL);
1392
1393         if (sport->dma_rx_chan && !lpuart_start_rx_dma(sport)) {
1394                 /* set Rx DMA timeout */
1395                 sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT);
1396                 if (!sport->dma_rx_timeout)
1397                         sport->dma_rx_timeout = 1;
1398
1399                 sport->lpuart_dma_rx_use = true;
1400                 rx_dma_timer_init(sport);
1401         } else {
1402                 sport->lpuart_dma_rx_use = false;
1403         }
1404
1405         if (sport->dma_tx_chan && !lpuart_dma_tx_request(port)) {
1406                 init_waitqueue_head(&sport->dma_wait);
1407                 sport->lpuart_dma_tx_use = true;
1408                 temp = lpuart32_read(&sport->port, UARTBAUD);
1409                 lpuart32_write(&sport->port, temp | UARTBAUD_TDMAE, UARTBAUD);
1410         } else {
1411                 sport->lpuart_dma_tx_use = false;
1412         }
1413
1414         if (sport->lpuart_dma_rx_use) {
1415                 /* RXWATER must be 0 */
1416                 temp = lpuart32_read(&sport->port, UARTWATER);
1417                 temp &= ~(UARTWATER_WATER_MASK << UARTWATER_RXWATER_OFF);
1418                 lpuart32_write(&sport->port, temp, UARTWATER);
1419         }
1420         temp = lpuart32_read(&sport->port, UARTCTRL);
1421         if (!sport->lpuart_dma_rx_use)
1422                 temp |= UARTCTRL_RIE;
1423         if (!sport->lpuart_dma_tx_use)
1424                 temp |= UARTCTRL_TIE;
1425         lpuart32_write(&sport->port, temp, UARTCTRL);
1426
1427         spin_unlock_irqrestore(&sport->port.lock, flags);
1428         return 0;
1429 }
1430
1431 static void lpuart_shutdown(struct uart_port *port)
1432 {
1433         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1434         unsigned char temp;
1435         unsigned long flags;
1436
1437         spin_lock_irqsave(&port->lock, flags);
1438
1439         /* disable Rx/Tx and interrupts */
1440         temp = readb(port->membase + UARTCR2);
1441         temp &= ~(UARTCR2_TE | UARTCR2_RE |
1442                         UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
1443         writeb(temp, port->membase + UARTCR2);
1444
1445         spin_unlock_irqrestore(&port->lock, flags);
1446
1447         if (sport->lpuart_dma_rx_use) {
1448                 del_timer_sync(&sport->lpuart_timer);
1449                 lpuart_dma_rx_free(&sport->port);
1450         }
1451
1452         if (sport->lpuart_dma_tx_use) {
1453                 if (wait_event_interruptible(sport->dma_wait,
1454                         !sport->dma_tx_in_progress) != false) {
1455                         sport->dma_tx_in_progress = false;
1456                         dmaengine_terminate_all(sport->dma_tx_chan);
1457                 }
1458
1459                 lpuart_stop_tx(port);
1460         }
1461 }
1462
1463 static void lpuart32_shutdown(struct uart_port *port)
1464 {
1465         struct lpuart_port *sport =
1466                 container_of(port, struct lpuart_port, port);
1467         unsigned long temp;
1468         unsigned long flags;
1469
1470         spin_lock_irqsave(&port->lock, flags);
1471
1472         /* disable Rx/Tx and interrupts */
1473         temp = lpuart32_read(port, UARTCTRL);
1474         temp &= ~(UARTCTRL_TE | UARTCTRL_RE |
1475                         UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
1476         lpuart32_write(port, temp, UARTCTRL);
1477
1478         spin_unlock_irqrestore(&port->lock, flags);
1479
1480         if (sport->lpuart_dma_rx_use) {
1481                 del_timer_sync(&sport->lpuart_timer);
1482                 lpuart_dma_rx_free(&sport->port);
1483         }
1484
1485         if (sport->lpuart_dma_tx_use) {
1486                 if (wait_event_interruptible(sport->dma_wait,
1487                                              !sport->dma_tx_in_progress)) {
1488                         sport->dma_tx_in_progress = false;
1489                         dmaengine_terminate_all(sport->dma_tx_chan);
1490                 }
1491
1492                 lpuart32_stop_tx(port);
1493         }
1494 }
1495
1496 static void
1497 lpuart_set_termios(struct uart_port *port, struct ktermios *termios,
1498                    struct ktermios *old)
1499 {
1500         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1501         unsigned long flags;
1502         unsigned char cr1, old_cr1, old_cr2, cr3, cr4, bdh, modem;
1503         unsigned int  baud;
1504         unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1505         unsigned int sbr, brfa;
1506
1507         cr1 = old_cr1 = readb(sport->port.membase + UARTCR1);
1508         old_cr2 = readb(sport->port.membase + UARTCR2);
1509         cr3 = readb(sport->port.membase + UARTCR3);
1510         cr4 = readb(sport->port.membase + UARTCR4);
1511         bdh = readb(sport->port.membase + UARTBDH);
1512         modem = readb(sport->port.membase + UARTMODEM);
1513         /*
1514          * only support CS8 and CS7, and for CS7 must enable PE.
1515          * supported mode:
1516          *  - (7,e/o,1)
1517          *  - (8,n,1)
1518          *  - (8,m/s,1)
1519          *  - (8,e/o,1)
1520          */
1521         while ((termios->c_cflag & CSIZE) != CS8 &&
1522                 (termios->c_cflag & CSIZE) != CS7) {
1523                 termios->c_cflag &= ~CSIZE;
1524                 termios->c_cflag |= old_csize;
1525                 old_csize = CS8;
1526         }
1527
1528         if ((termios->c_cflag & CSIZE) == CS8 ||
1529                 (termios->c_cflag & CSIZE) == CS7)
1530                 cr1 = old_cr1 & ~UARTCR1_M;
1531
1532         if (termios->c_cflag & CMSPAR) {
1533                 if ((termios->c_cflag & CSIZE) != CS8) {
1534                         termios->c_cflag &= ~CSIZE;
1535                         termios->c_cflag |= CS8;
1536                 }
1537                 cr1 |= UARTCR1_M;
1538         }
1539
1540         /*
1541          * When auto RS-485 RTS mode is enabled,
1542          * hardware flow control need to be disabled.
1543          */
1544         if (sport->port.rs485.flags & SER_RS485_ENABLED)
1545                 termios->c_cflag &= ~CRTSCTS;
1546
1547         if (termios->c_cflag & CRTSCTS) {
1548                 modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1549         } else {
1550                 termios->c_cflag &= ~CRTSCTS;
1551                 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1552         }
1553
1554         if (termios->c_cflag & CSTOPB)
1555                 termios->c_cflag &= ~CSTOPB;
1556
1557         /* parity must be enabled when CS7 to match 8-bits format */
1558         if ((termios->c_cflag & CSIZE) == CS7)
1559                 termios->c_cflag |= PARENB;
1560
1561         if ((termios->c_cflag & PARENB)) {
1562                 if (termios->c_cflag & CMSPAR) {
1563                         cr1 &= ~UARTCR1_PE;
1564                         if (termios->c_cflag & PARODD)
1565                                 cr3 |= UARTCR3_T8;
1566                         else
1567                                 cr3 &= ~UARTCR3_T8;
1568                 } else {
1569                         cr1 |= UARTCR1_PE;
1570                         if ((termios->c_cflag & CSIZE) == CS8)
1571                                 cr1 |= UARTCR1_M;
1572                         if (termios->c_cflag & PARODD)
1573                                 cr1 |= UARTCR1_PT;
1574                         else
1575                                 cr1 &= ~UARTCR1_PT;
1576                 }
1577         } else {
1578                 cr1 &= ~UARTCR1_PE;
1579         }
1580
1581         /* ask the core to calculate the divisor */
1582         baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1583
1584         /*
1585          * Need to update the Ring buffer length according to the selected
1586          * baud rate and restart Rx DMA path.
1587          *
1588          * Since timer function acqures sport->port.lock, need to stop before
1589          * acquring same lock because otherwise del_timer_sync() can deadlock.
1590          */
1591         if (old && sport->lpuart_dma_rx_use) {
1592                 del_timer_sync(&sport->lpuart_timer);
1593                 lpuart_dma_rx_free(&sport->port);
1594         }
1595
1596         spin_lock_irqsave(&sport->port.lock, flags);
1597
1598         sport->port.read_status_mask = 0;
1599         if (termios->c_iflag & INPCK)
1600                 sport->port.read_status_mask |= (UARTSR1_FE | UARTSR1_PE);
1601         if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1602                 sport->port.read_status_mask |= UARTSR1_FE;
1603
1604         /* characters to ignore */
1605         sport->port.ignore_status_mask = 0;
1606         if (termios->c_iflag & IGNPAR)
1607                 sport->port.ignore_status_mask |= UARTSR1_PE;
1608         if (termios->c_iflag & IGNBRK) {
1609                 sport->port.ignore_status_mask |= UARTSR1_FE;
1610                 /*
1611                  * if we're ignoring parity and break indicators,
1612                  * ignore overruns too (for real raw support).
1613                  */
1614                 if (termios->c_iflag & IGNPAR)
1615                         sport->port.ignore_status_mask |= UARTSR1_OR;
1616         }
1617
1618         /* update the per-port timeout */
1619         uart_update_timeout(port, termios->c_cflag, baud);
1620
1621         /* wait transmit engin complete */
1622         while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
1623                 barrier();
1624
1625         /* disable transmit and receive */
1626         writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE),
1627                         sport->port.membase + UARTCR2);
1628
1629         sbr = sport->port.uartclk / (16 * baud);
1630         brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud;
1631         bdh &= ~UARTBDH_SBR_MASK;
1632         bdh |= (sbr >> 8) & 0x1F;
1633         cr4 &= ~UARTCR4_BRFA_MASK;
1634         brfa &= UARTCR4_BRFA_MASK;
1635         writeb(cr4 | brfa, sport->port.membase + UARTCR4);
1636         writeb(bdh, sport->port.membase + UARTBDH);
1637         writeb(sbr & 0xFF, sport->port.membase + UARTBDL);
1638         writeb(cr3, sport->port.membase + UARTCR3);
1639         writeb(cr1, sport->port.membase + UARTCR1);
1640         writeb(modem, sport->port.membase + UARTMODEM);
1641
1642         /* restore control register */
1643         writeb(old_cr2, sport->port.membase + UARTCR2);
1644
1645         if (old && sport->lpuart_dma_rx_use) {
1646                 if (!lpuart_start_rx_dma(sport))
1647                         rx_dma_timer_init(sport);
1648                 else
1649                         sport->lpuart_dma_rx_use = false;
1650         }
1651
1652         spin_unlock_irqrestore(&sport->port.lock, flags);
1653 }
1654
1655 static void
1656 lpuart32_serial_setbrg(struct lpuart_port *sport, unsigned int baudrate)
1657 {
1658         u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp;
1659         u32 clk = sport->port.uartclk;
1660
1661         /*
1662          * The idea is to use the best OSR (over-sampling rate) possible.
1663          * Note, OSR is typically hard-set to 16 in other LPUART instantiations.
1664          * Loop to find the best OSR value possible, one that generates minimum
1665          * baud_diff iterate through the rest of the supported values of OSR.
1666          *
1667          * Calculation Formula:
1668          *  Baud Rate = baud clock / ((OSR+1) × SBR)
1669          */
1670         baud_diff = baudrate;
1671         osr = 0;
1672         sbr = 0;
1673
1674         for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) {
1675                 /* calculate the temporary sbr value  */
1676                 tmp_sbr = (clk / (baudrate * tmp_osr));
1677                 if (tmp_sbr == 0)
1678                         tmp_sbr = 1;
1679
1680                 /*
1681                  * calculate the baud rate difference based on the temporary
1682                  * osr and sbr values
1683                  */
1684                 tmp_diff = clk / (tmp_osr * tmp_sbr) - baudrate;
1685
1686                 /* select best values between sbr and sbr+1 */
1687                 tmp = clk / (tmp_osr * (tmp_sbr + 1));
1688                 if (tmp_diff > (baudrate - tmp)) {
1689                         tmp_diff = baudrate - tmp;
1690                         tmp_sbr++;
1691                 }
1692
1693                 if (tmp_diff <= baud_diff) {
1694                         baud_diff = tmp_diff;
1695                         osr = tmp_osr;
1696                         sbr = tmp_sbr;
1697
1698                         if (!baud_diff)
1699                                 break;
1700                 }
1701         }
1702
1703         /* handle buadrate outside acceptable rate */
1704         if (baud_diff > ((baudrate / 100) * 3))
1705                 dev_warn(sport->port.dev,
1706                          "unacceptable baud rate difference of more than 3%%\n");
1707
1708         tmp = lpuart32_read(&sport->port, UARTBAUD);
1709
1710         if ((osr > 3) && (osr < 8))
1711                 tmp |= UARTBAUD_BOTHEDGE;
1712
1713         tmp &= ~(UARTBAUD_OSR_MASK << UARTBAUD_OSR_SHIFT);
1714         tmp |= (((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT);
1715
1716         tmp &= ~UARTBAUD_SBR_MASK;
1717         tmp |= sbr & UARTBAUD_SBR_MASK;
1718
1719         if (!sport->lpuart_dma_rx_use)
1720                 tmp &= ~UARTBAUD_RDMAE;
1721         if (!sport->lpuart_dma_tx_use)
1722                 tmp &= ~UARTBAUD_TDMAE;
1723
1724         lpuart32_write(&sport->port, tmp, UARTBAUD);
1725 }
1726
1727 static void
1728 lpuart32_set_termios(struct uart_port *port, struct ktermios *termios,
1729                    struct ktermios *old)
1730 {
1731         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1732         unsigned long flags;
1733         unsigned long ctrl, old_ctrl, modem;
1734         unsigned int  baud;
1735         unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1736
1737         ctrl = old_ctrl = lpuart32_read(&sport->port, UARTCTRL);
1738         modem = lpuart32_read(&sport->port, UARTMODIR);
1739         /*
1740          * only support CS8 and CS7, and for CS7 must enable PE.
1741          * supported mode:
1742          *  - (7,e/o,1)
1743          *  - (8,n,1)
1744          *  - (8,m/s,1)
1745          *  - (8,e/o,1)
1746          */
1747         while ((termios->c_cflag & CSIZE) != CS8 &&
1748                 (termios->c_cflag & CSIZE) != CS7) {
1749                 termios->c_cflag &= ~CSIZE;
1750                 termios->c_cflag |= old_csize;
1751                 old_csize = CS8;
1752         }
1753
1754         if ((termios->c_cflag & CSIZE) == CS8 ||
1755                 (termios->c_cflag & CSIZE) == CS7)
1756                 ctrl = old_ctrl & ~UARTCTRL_M;
1757
1758         if (termios->c_cflag & CMSPAR) {
1759                 if ((termios->c_cflag & CSIZE) != CS8) {
1760                         termios->c_cflag &= ~CSIZE;
1761                         termios->c_cflag |= CS8;
1762                 }
1763                 ctrl |= UARTCTRL_M;
1764         }
1765
1766         if (termios->c_cflag & CRTSCTS) {
1767                 modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1768         } else {
1769                 termios->c_cflag &= ~CRTSCTS;
1770                 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1771         }
1772
1773         if (termios->c_cflag & CSTOPB)
1774                 termios->c_cflag &= ~CSTOPB;
1775
1776         /* parity must be enabled when CS7 to match 8-bits format */
1777         if ((termios->c_cflag & CSIZE) == CS7)
1778                 termios->c_cflag |= PARENB;
1779
1780         if ((termios->c_cflag & PARENB)) {
1781                 if (termios->c_cflag & CMSPAR) {
1782                         ctrl &= ~UARTCTRL_PE;
1783                         ctrl |= UARTCTRL_M;
1784                 } else {
1785                         ctrl |= UARTCTRL_PE;
1786                         if ((termios->c_cflag & CSIZE) == CS8)
1787                                 ctrl |= UARTCTRL_M;
1788                         if (termios->c_cflag & PARODD)
1789                                 ctrl |= UARTCTRL_PT;
1790                         else
1791                                 ctrl &= ~UARTCTRL_PT;
1792                 }
1793         } else {
1794                 ctrl &= ~UARTCTRL_PE;
1795         }
1796
1797         /* ask the core to calculate the divisor */
1798         baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 4);
1799
1800         /*
1801          * Need to update the Ring buffer length according to the selected
1802          * baud rate and restart Rx DMA path.
1803          *
1804          * Since timer function acqures sport->port.lock, need to stop before
1805          * acquring same lock because otherwise del_timer_sync() can deadlock.
1806          */
1807         if (old && sport->lpuart_dma_rx_use) {
1808                 del_timer_sync(&sport->lpuart_timer);
1809                 lpuart_dma_rx_free(&sport->port);
1810         }
1811
1812         spin_lock_irqsave(&sport->port.lock, flags);
1813
1814         sport->port.read_status_mask = 0;
1815         if (termios->c_iflag & INPCK)
1816                 sport->port.read_status_mask |= (UARTSTAT_FE | UARTSTAT_PE);
1817         if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1818                 sport->port.read_status_mask |= UARTSTAT_FE;
1819
1820         /* characters to ignore */
1821         sport->port.ignore_status_mask = 0;
1822         if (termios->c_iflag & IGNPAR)
1823                 sport->port.ignore_status_mask |= UARTSTAT_PE;
1824         if (termios->c_iflag & IGNBRK) {
1825                 sport->port.ignore_status_mask |= UARTSTAT_FE;
1826                 /*
1827                  * if we're ignoring parity and break indicators,
1828                  * ignore overruns too (for real raw support).
1829                  */
1830                 if (termios->c_iflag & IGNPAR)
1831                         sport->port.ignore_status_mask |= UARTSTAT_OR;
1832         }
1833
1834         /* update the per-port timeout */
1835         uart_update_timeout(port, termios->c_cflag, baud);
1836
1837         /* wait transmit engin complete */
1838         while (!(lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_TC))
1839                 barrier();
1840
1841         /* disable transmit and receive */
1842         lpuart32_write(&sport->port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE),
1843                        UARTCTRL);
1844
1845         lpuart32_serial_setbrg(sport, baud);
1846         lpuart32_write(&sport->port, modem, UARTMODIR);
1847         lpuart32_write(&sport->port, ctrl, UARTCTRL);
1848         /* restore control register */
1849
1850         if (old && sport->lpuart_dma_rx_use) {
1851                 if (!lpuart_start_rx_dma(sport))
1852                         rx_dma_timer_init(sport);
1853                 else
1854                         sport->lpuart_dma_rx_use = false;
1855         }
1856
1857         spin_unlock_irqrestore(&sport->port.lock, flags);
1858 }
1859
1860 static const char *lpuart_type(struct uart_port *port)
1861 {
1862         return "FSL_LPUART";
1863 }
1864
1865 static void lpuart_release_port(struct uart_port *port)
1866 {
1867         /* nothing to do */
1868 }
1869
1870 static int lpuart_request_port(struct uart_port *port)
1871 {
1872         return  0;
1873 }
1874
1875 /* configure/autoconfigure the port */
1876 static void lpuart_config_port(struct uart_port *port, int flags)
1877 {
1878         if (flags & UART_CONFIG_TYPE)
1879                 port->type = PORT_LPUART;
1880 }
1881
1882 static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser)
1883 {
1884         int ret = 0;
1885
1886         if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART)
1887                 ret = -EINVAL;
1888         if (port->irq != ser->irq)
1889                 ret = -EINVAL;
1890         if (ser->io_type != UPIO_MEM)
1891                 ret = -EINVAL;
1892         if (port->uartclk / 16 != ser->baud_base)
1893                 ret = -EINVAL;
1894         if (port->iobase != ser->port)
1895                 ret = -EINVAL;
1896         if (ser->hub6 != 0)
1897                 ret = -EINVAL;
1898         return ret;
1899 }
1900
1901 static const struct uart_ops lpuart_pops = {
1902         .tx_empty       = lpuart_tx_empty,
1903         .set_mctrl      = lpuart_set_mctrl,
1904         .get_mctrl      = lpuart_get_mctrl,
1905         .stop_tx        = lpuart_stop_tx,
1906         .start_tx       = lpuart_start_tx,
1907         .stop_rx        = lpuart_stop_rx,
1908         .break_ctl      = lpuart_break_ctl,
1909         .startup        = lpuart_startup,
1910         .shutdown       = lpuart_shutdown,
1911         .set_termios    = lpuart_set_termios,
1912         .type           = lpuart_type,
1913         .request_port   = lpuart_request_port,
1914         .release_port   = lpuart_release_port,
1915         .config_port    = lpuart_config_port,
1916         .verify_port    = lpuart_verify_port,
1917         .flush_buffer   = lpuart_flush_buffer,
1918 #if defined(CONFIG_CONSOLE_POLL)
1919         .poll_init      = lpuart_poll_init,
1920         .poll_get_char  = lpuart_poll_get_char,
1921         .poll_put_char  = lpuart_poll_put_char,
1922 #endif
1923 };
1924
1925 static const struct uart_ops lpuart32_pops = {
1926         .tx_empty       = lpuart32_tx_empty,
1927         .set_mctrl      = lpuart32_set_mctrl,
1928         .get_mctrl      = lpuart32_get_mctrl,
1929         .stop_tx        = lpuart32_stop_tx,
1930         .start_tx       = lpuart32_start_tx,
1931         .stop_rx        = lpuart32_stop_rx,
1932         .break_ctl      = lpuart32_break_ctl,
1933         .startup        = lpuart32_startup,
1934         .shutdown       = lpuart32_shutdown,
1935         .set_termios    = lpuart32_set_termios,
1936         .type           = lpuart_type,
1937         .request_port   = lpuart_request_port,
1938         .release_port   = lpuart_release_port,
1939         .config_port    = lpuart_config_port,
1940         .verify_port    = lpuart_verify_port,
1941         .flush_buffer   = lpuart_flush_buffer,
1942 #if defined(CONFIG_CONSOLE_POLL)
1943         .poll_init      = lpuart32_poll_init,
1944         .poll_get_char  = lpuart32_poll_get_char,
1945         .poll_put_char  = lpuart32_poll_put_char,
1946 #endif
1947 };
1948
1949 static struct lpuart_port *lpuart_ports[UART_NR];
1950
1951 #ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE
1952 static void lpuart_console_putchar(struct uart_port *port, int ch)
1953 {
1954         while (!(readb(port->membase + UARTSR1) & UARTSR1_TDRE))
1955                 barrier();
1956
1957         writeb(ch, port->membase + UARTDR);
1958 }
1959
1960 static void lpuart32_console_putchar(struct uart_port *port, int ch)
1961 {
1962         while (!(lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE))
1963                 barrier();
1964
1965         lpuart32_write(port, ch, UARTDATA);
1966 }
1967
1968 static void
1969 lpuart_console_write(struct console *co, const char *s, unsigned int count)
1970 {
1971         struct lpuart_port *sport = lpuart_ports[co->index];
1972         unsigned char  old_cr2, cr2;
1973         unsigned long flags;
1974         int locked = 1;
1975
1976         if (sport->port.sysrq || oops_in_progress)
1977                 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1978         else
1979                 spin_lock_irqsave(&sport->port.lock, flags);
1980
1981         /* first save CR2 and then disable interrupts */
1982         cr2 = old_cr2 = readb(sport->port.membase + UARTCR2);
1983         cr2 |= (UARTCR2_TE |  UARTCR2_RE);
1984         cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
1985         writeb(cr2, sport->port.membase + UARTCR2);
1986
1987         uart_console_write(&sport->port, s, count, lpuart_console_putchar);
1988
1989         /* wait for transmitter finish complete and restore CR2 */
1990         while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
1991                 barrier();
1992
1993         writeb(old_cr2, sport->port.membase + UARTCR2);
1994
1995         if (locked)
1996                 spin_unlock_irqrestore(&sport->port.lock, flags);
1997 }
1998
1999 static void
2000 lpuart32_console_write(struct console *co, const char *s, unsigned int count)
2001 {
2002         struct lpuart_port *sport = lpuart_ports[co->index];
2003         unsigned long  old_cr, cr;
2004         unsigned long flags;
2005         int locked = 1;
2006
2007         if (sport->port.sysrq || oops_in_progress)
2008                 locked = spin_trylock_irqsave(&sport->port.lock, flags);
2009         else
2010                 spin_lock_irqsave(&sport->port.lock, flags);
2011
2012         /* first save CR2 and then disable interrupts */
2013         cr = old_cr = lpuart32_read(&sport->port, UARTCTRL);
2014         cr |= (UARTCTRL_TE |  UARTCTRL_RE);
2015         cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
2016         lpuart32_write(&sport->port, cr, UARTCTRL);
2017
2018         uart_console_write(&sport->port, s, count, lpuart32_console_putchar);
2019
2020         /* wait for transmitter finish complete and restore CR2 */
2021         while (!(lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_TC))
2022                 barrier();
2023
2024         lpuart32_write(&sport->port, old_cr, UARTCTRL);
2025
2026         if (locked)
2027                 spin_unlock_irqrestore(&sport->port.lock, flags);
2028 }
2029
2030 /*
2031  * if the port was already initialised (eg, by a boot loader),
2032  * try to determine the current setup.
2033  */
2034 static void __init
2035 lpuart_console_get_options(struct lpuart_port *sport, int *baud,
2036                            int *parity, int *bits)
2037 {
2038         unsigned char cr, bdh, bdl, brfa;
2039         unsigned int sbr, uartclk, baud_raw;
2040
2041         cr = readb(sport->port.membase + UARTCR2);
2042         cr &= UARTCR2_TE | UARTCR2_RE;
2043         if (!cr)
2044                 return;
2045
2046         /* ok, the port was enabled */
2047
2048         cr = readb(sport->port.membase + UARTCR1);
2049
2050         *parity = 'n';
2051         if (cr & UARTCR1_PE) {
2052                 if (cr & UARTCR1_PT)
2053                         *parity = 'o';
2054                 else
2055                         *parity = 'e';
2056         }
2057
2058         if (cr & UARTCR1_M)
2059                 *bits = 9;
2060         else
2061                 *bits = 8;
2062
2063         bdh = readb(sport->port.membase + UARTBDH);
2064         bdh &= UARTBDH_SBR_MASK;
2065         bdl = readb(sport->port.membase + UARTBDL);
2066         sbr = bdh;
2067         sbr <<= 8;
2068         sbr |= bdl;
2069         brfa = readb(sport->port.membase + UARTCR4);
2070         brfa &= UARTCR4_BRFA_MASK;
2071
2072         uartclk = clk_get_rate(sport->clk);
2073         /*
2074          * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
2075          */
2076         baud_raw = uartclk / (16 * (sbr + brfa / 32));
2077
2078         if (*baud != baud_raw)
2079                 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate"
2080                                 "from %d to %d\n", baud_raw, *baud);
2081 }
2082
2083 static void __init
2084 lpuart32_console_get_options(struct lpuart_port *sport, int *baud,
2085                            int *parity, int *bits)
2086 {
2087         unsigned long cr, bd;
2088         unsigned int sbr, uartclk, baud_raw;
2089
2090         cr = lpuart32_read(&sport->port, UARTCTRL);
2091         cr &= UARTCTRL_TE | UARTCTRL_RE;
2092         if (!cr)
2093                 return;
2094
2095         /* ok, the port was enabled */
2096
2097         cr = lpuart32_read(&sport->port, UARTCTRL);
2098
2099         *parity = 'n';
2100         if (cr & UARTCTRL_PE) {
2101                 if (cr & UARTCTRL_PT)
2102                         *parity = 'o';
2103                 else
2104                         *parity = 'e';
2105         }
2106
2107         if (cr & UARTCTRL_M)
2108                 *bits = 9;
2109         else
2110                 *bits = 8;
2111
2112         bd = lpuart32_read(&sport->port, UARTBAUD);
2113         bd &= UARTBAUD_SBR_MASK;
2114         sbr = bd;
2115         uartclk = clk_get_rate(sport->clk);
2116         /*
2117          * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
2118          */
2119         baud_raw = uartclk / (16 * sbr);
2120
2121         if (*baud != baud_raw)
2122                 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate"
2123                                 "from %d to %d\n", baud_raw, *baud);
2124 }
2125
2126 static int __init lpuart_console_setup(struct console *co, char *options)
2127 {
2128         struct lpuart_port *sport;
2129         int baud = 115200;
2130         int bits = 8;
2131         int parity = 'n';
2132         int flow = 'n';
2133
2134         /*
2135          * check whether an invalid uart number has been specified, and
2136          * if so, search for the first available port that does have
2137          * console support.
2138          */
2139         if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports))
2140                 co->index = 0;
2141
2142         sport = lpuart_ports[co->index];
2143         if (sport == NULL)
2144                 return -ENODEV;
2145
2146         if (options)
2147                 uart_parse_options(options, &baud, &parity, &bits, &flow);
2148         else
2149                 if (lpuart_is_32(sport))
2150                         lpuart32_console_get_options(sport, &baud, &parity, &bits);
2151                 else
2152                         lpuart_console_get_options(sport, &baud, &parity, &bits);
2153
2154         if (lpuart_is_32(sport))
2155                 lpuart32_setup_watermark(sport);
2156         else
2157                 lpuart_setup_watermark(sport);
2158
2159         return uart_set_options(&sport->port, co, baud, parity, bits, flow);
2160 }
2161
2162 static struct uart_driver lpuart_reg;
2163 static struct console lpuart_console = {
2164         .name           = DEV_NAME,
2165         .write          = lpuart_console_write,
2166         .device         = uart_console_device,
2167         .setup          = lpuart_console_setup,
2168         .flags          = CON_PRINTBUFFER,
2169         .index          = -1,
2170         .data           = &lpuart_reg,
2171 };
2172
2173 static struct console lpuart32_console = {
2174         .name           = DEV_NAME,
2175         .write          = lpuart32_console_write,
2176         .device         = uart_console_device,
2177         .setup          = lpuart_console_setup,
2178         .flags          = CON_PRINTBUFFER,
2179         .index          = -1,
2180         .data           = &lpuart_reg,
2181 };
2182
2183 static void lpuart_early_write(struct console *con, const char *s, unsigned n)
2184 {
2185         struct earlycon_device *dev = con->data;
2186
2187         uart_console_write(&dev->port, s, n, lpuart_console_putchar);
2188 }
2189
2190 static void lpuart32_early_write(struct console *con, const char *s, unsigned n)
2191 {
2192         struct earlycon_device *dev = con->data;
2193
2194         uart_console_write(&dev->port, s, n, lpuart32_console_putchar);
2195 }
2196
2197 static int __init lpuart_early_console_setup(struct earlycon_device *device,
2198                                           const char *opt)
2199 {
2200         if (!device->port.membase)
2201                 return -ENODEV;
2202
2203         device->con->write = lpuart_early_write;
2204         return 0;
2205 }
2206
2207 static int __init lpuart32_early_console_setup(struct earlycon_device *device,
2208                                           const char *opt)
2209 {
2210         if (!device->port.membase)
2211                 return -ENODEV;
2212
2213         device->port.iotype = UPIO_MEM32BE;
2214         device->con->write = lpuart32_early_write;
2215         return 0;
2216 }
2217
2218 static int __init lpuart32_imx_early_console_setup(struct earlycon_device *device,
2219                                                    const char *opt)
2220 {
2221         if (!device->port.membase)
2222                 return -ENODEV;
2223
2224         device->port.iotype = UPIO_MEM32;
2225         device->port.membase += IMX_REG_OFF;
2226         device->con->write = lpuart32_early_write;
2227
2228         return 0;
2229 }
2230 OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup);
2231 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup);
2232 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup);
2233 EARLYCON_DECLARE(lpuart, lpuart_early_console_setup);
2234 EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup);
2235
2236 #define LPUART_CONSOLE  (&lpuart_console)
2237 #define LPUART32_CONSOLE        (&lpuart32_console)
2238 #else
2239 #define LPUART_CONSOLE  NULL
2240 #define LPUART32_CONSOLE        NULL
2241 #endif
2242
2243 static struct uart_driver lpuart_reg = {
2244         .owner          = THIS_MODULE,
2245         .driver_name    = DRIVER_NAME,
2246         .dev_name       = DEV_NAME,
2247         .nr             = ARRAY_SIZE(lpuart_ports),
2248         .cons           = LPUART_CONSOLE,
2249 };
2250
2251 static int lpuart_probe(struct platform_device *pdev)
2252 {
2253         const struct of_device_id *of_id = of_match_device(lpuart_dt_ids,
2254                                                            &pdev->dev);
2255         const struct lpuart_soc_data *sdata = of_id->data;
2256         struct device_node *np = pdev->dev.of_node;
2257         struct lpuart_port *sport;
2258         struct resource *res;
2259         int ret;
2260
2261         sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2262         if (!sport)
2263                 return -ENOMEM;
2264
2265         pdev->dev.coherent_dma_mask = 0;
2266
2267         ret = of_alias_get_id(np, "serial");
2268         if (ret < 0) {
2269                 ret = ida_simple_get(&fsl_lpuart_ida, 0, UART_NR, GFP_KERNEL);
2270                 if (ret < 0) {
2271                         dev_err(&pdev->dev, "port line is full, add device failed\n");
2272                         return ret;
2273                 }
2274         }
2275         if (ret >= ARRAY_SIZE(lpuart_ports)) {
2276                 dev_err(&pdev->dev, "serial%d out of range\n", ret);
2277                 return -EINVAL;
2278         }
2279         sport->port.line = ret;
2280         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2281         sport->port.membase = devm_ioremap_resource(&pdev->dev, res);
2282         if (IS_ERR(sport->port.membase))
2283                 return PTR_ERR(sport->port.membase);
2284
2285         sport->port.membase += sdata->reg_off;
2286         sport->port.mapbase = res->start;
2287         sport->port.dev = &pdev->dev;
2288         sport->port.type = PORT_LPUART;
2289         ret = platform_get_irq(pdev, 0);
2290         if (ret < 0) {
2291                 dev_err(&pdev->dev, "cannot obtain irq\n");
2292                 return ret;
2293         }
2294         sport->port.irq = ret;
2295         sport->port.iotype = sdata->iotype;
2296         if (lpuart_is_32(sport))
2297                 sport->port.ops = &lpuart32_pops;
2298         else
2299                 sport->port.ops = &lpuart_pops;
2300         sport->port.flags = UPF_BOOT_AUTOCONF;
2301
2302         sport->port.rs485_config = lpuart_config_rs485;
2303
2304         sport->clk = devm_clk_get(&pdev->dev, "ipg");
2305         if (IS_ERR(sport->clk)) {
2306                 ret = PTR_ERR(sport->clk);
2307                 dev_err(&pdev->dev, "failed to get uart clk: %d\n", ret);
2308                 return ret;
2309         }
2310
2311         ret = clk_prepare_enable(sport->clk);
2312         if (ret) {
2313                 dev_err(&pdev->dev, "failed to enable uart clk: %d\n", ret);
2314                 return ret;
2315         }
2316
2317         sport->port.uartclk = clk_get_rate(sport->clk);
2318
2319         lpuart_ports[sport->port.line] = sport;
2320
2321         platform_set_drvdata(pdev, &sport->port);
2322
2323         if (lpuart_is_32(sport)) {
2324                 lpuart_reg.cons = LPUART32_CONSOLE;
2325                 ret = devm_request_irq(&pdev->dev, sport->port.irq, lpuart32_int, 0,
2326                                         DRIVER_NAME, sport);
2327         } else {
2328                 lpuart_reg.cons = LPUART_CONSOLE;
2329                 ret = devm_request_irq(&pdev->dev, sport->port.irq, lpuart_int, 0,
2330                                         DRIVER_NAME, sport);
2331         }
2332
2333         if (ret)
2334                 goto failed_irq_request;
2335
2336         ret = uart_add_one_port(&lpuart_reg, &sport->port);
2337         if (ret)
2338                 goto failed_attach_port;
2339
2340         uart_get_rs485_mode(&pdev->dev, &sport->port.rs485);
2341
2342         if (sport->port.rs485.flags & SER_RS485_RX_DURING_TX)
2343                 dev_err(&pdev->dev, "driver doesn't support RX during TX\n");
2344
2345         if (sport->port.rs485.delay_rts_before_send ||
2346             sport->port.rs485.delay_rts_after_send)
2347                 dev_err(&pdev->dev, "driver doesn't support RTS delays\n");
2348
2349         lpuart_config_rs485(&sport->port, &sport->port.rs485);
2350
2351         sport->dma_tx_chan = dma_request_slave_channel(sport->port.dev, "tx");
2352         if (!sport->dma_tx_chan)
2353                 dev_info(sport->port.dev, "DMA tx channel request failed, "
2354                                 "operating without tx DMA\n");
2355
2356         sport->dma_rx_chan = dma_request_slave_channel(sport->port.dev, "rx");
2357         if (!sport->dma_rx_chan)
2358                 dev_info(sport->port.dev, "DMA rx channel request failed, "
2359                                 "operating without rx DMA\n");
2360
2361         return 0;
2362
2363 failed_attach_port:
2364 failed_irq_request:
2365         clk_disable_unprepare(sport->clk);
2366         return ret;
2367 }
2368
2369 static int lpuart_remove(struct platform_device *pdev)
2370 {
2371         struct lpuart_port *sport = platform_get_drvdata(pdev);
2372
2373         uart_remove_one_port(&lpuart_reg, &sport->port);
2374
2375         ida_simple_remove(&fsl_lpuart_ida, sport->port.line);
2376
2377         clk_disable_unprepare(sport->clk);
2378
2379         if (sport->dma_tx_chan)
2380                 dma_release_channel(sport->dma_tx_chan);
2381
2382         if (sport->dma_rx_chan)
2383                 dma_release_channel(sport->dma_rx_chan);
2384
2385         return 0;
2386 }
2387
2388 #ifdef CONFIG_PM_SLEEP
2389 static int lpuart_suspend(struct device *dev)
2390 {
2391         struct lpuart_port *sport = dev_get_drvdata(dev);
2392         unsigned long temp;
2393         bool irq_wake;
2394
2395         if (lpuart_is_32(sport)) {
2396                 /* disable Rx/Tx and interrupts */
2397                 temp = lpuart32_read(&sport->port, UARTCTRL);
2398                 temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE);
2399                 lpuart32_write(&sport->port, temp, UARTCTRL);
2400         } else {
2401                 /* disable Rx/Tx and interrupts */
2402                 temp = readb(sport->port.membase + UARTCR2);
2403                 temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE);
2404                 writeb(temp, sport->port.membase + UARTCR2);
2405         }
2406
2407         uart_suspend_port(&lpuart_reg, &sport->port);
2408
2409         /* uart_suspend_port() might set wakeup flag */
2410         irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq));
2411
2412         if (sport->lpuart_dma_rx_use) {
2413                 /*
2414                  * EDMA driver during suspend will forcefully release any
2415                  * non-idle DMA channels. If port wakeup is enabled or if port
2416                  * is console port or 'no_console_suspend' is set the Rx DMA
2417                  * cannot resume as as expected, hence gracefully release the
2418                  * Rx DMA path before suspend and start Rx DMA path on resume.
2419                  */
2420                 if (irq_wake) {
2421                         del_timer_sync(&sport->lpuart_timer);
2422                         lpuart_dma_rx_free(&sport->port);
2423                 }
2424
2425                 /* Disable Rx DMA to use UART port as wakeup source */
2426                 if (lpuart_is_32(sport)) {
2427                         temp = lpuart32_read(&sport->port, UARTBAUD);
2428                         lpuart32_write(&sport->port, temp & ~UARTBAUD_RDMAE,
2429                                        UARTBAUD);
2430                 } else {
2431                         writeb(readb(sport->port.membase + UARTCR5) &
2432                                ~UARTCR5_RDMAS, sport->port.membase + UARTCR5);
2433                 }
2434         }
2435
2436         if (sport->lpuart_dma_tx_use) {
2437                 sport->dma_tx_in_progress = false;
2438                 dmaengine_terminate_all(sport->dma_tx_chan);
2439         }
2440
2441         if (sport->port.suspended && !irq_wake)
2442                 clk_disable_unprepare(sport->clk);
2443
2444         return 0;
2445 }
2446
2447 static int lpuart_resume(struct device *dev)
2448 {
2449         struct lpuart_port *sport = dev_get_drvdata(dev);
2450         bool irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq));
2451         unsigned long temp;
2452
2453         if (sport->port.suspended && !irq_wake)
2454                 clk_prepare_enable(sport->clk);
2455
2456         if (lpuart_is_32(sport)) {
2457                 lpuart32_setup_watermark(sport);
2458                 temp = lpuart32_read(&sport->port, UARTCTRL);
2459                 temp |= UARTCTRL_RE | UARTCTRL_TE | UARTCTRL_ILIE;
2460                 lpuart32_write(&sport->port, temp, UARTCTRL);
2461         } else {
2462                 lpuart_setup_watermark(sport);
2463                 temp = readb(sport->port.membase + UARTCR2);
2464                 temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE);
2465                 writeb(temp, sport->port.membase + UARTCR2);
2466         }
2467
2468         if (sport->lpuart_dma_rx_use) {
2469                 if (irq_wake) {
2470                         if (!lpuart_start_rx_dma(sport))
2471                                 rx_dma_timer_init(sport);
2472                         else
2473                                 sport->lpuart_dma_rx_use = false;
2474                 }
2475         }
2476
2477         if (sport->dma_tx_chan && !lpuart_dma_tx_request(&sport->port)) {
2478                 init_waitqueue_head(&sport->dma_wait);
2479                 sport->lpuart_dma_tx_use = true;
2480                 if (lpuart_is_32(sport)) {
2481                         temp = lpuart32_read(&sport->port, UARTBAUD);
2482                         lpuart32_write(&sport->port,
2483                                        temp | UARTBAUD_TDMAE, UARTBAUD);
2484                 } else {
2485                         writeb(readb(sport->port.membase + UARTCR5) |
2486                                 UARTCR5_TDMAS, sport->port.membase + UARTCR5);
2487                 }
2488         } else {
2489                 sport->lpuart_dma_tx_use = false;
2490         }
2491
2492         if (lpuart_is_32(sport)) {
2493                 if (sport->lpuart_dma_rx_use) {
2494                         /* RXWATER must be 0 */
2495                         temp = lpuart32_read(&sport->port, UARTWATER);
2496                         temp &= ~(UARTWATER_WATER_MASK <<
2497                                   UARTWATER_RXWATER_OFF);
2498                         lpuart32_write(&sport->port, temp, UARTWATER);
2499                 }
2500                 temp = lpuart32_read(&sport->port, UARTCTRL);
2501                 if (!sport->lpuart_dma_rx_use)
2502                         temp |= UARTCTRL_RIE;
2503                 if (!sport->lpuart_dma_tx_use)
2504                         temp |= UARTCTRL_TIE;
2505                 lpuart32_write(&sport->port, temp, UARTCTRL);
2506         }
2507
2508         uart_resume_port(&lpuart_reg, &sport->port);
2509
2510         return 0;
2511 }
2512 #endif
2513
2514 static SIMPLE_DEV_PM_OPS(lpuart_pm_ops, lpuart_suspend, lpuart_resume);
2515
2516 static struct platform_driver lpuart_driver = {
2517         .probe          = lpuart_probe,
2518         .remove         = lpuart_remove,
2519         .driver         = {
2520                 .name   = "fsl-lpuart",
2521                 .of_match_table = lpuart_dt_ids,
2522                 .pm     = &lpuart_pm_ops,
2523         },
2524 };
2525
2526 static int __init lpuart_serial_init(void)
2527 {
2528         int ret = uart_register_driver(&lpuart_reg);
2529
2530         if (ret)
2531                 return ret;
2532
2533         ret = platform_driver_register(&lpuart_driver);
2534         if (ret)
2535                 uart_unregister_driver(&lpuart_reg);
2536
2537         return ret;
2538 }
2539
2540 static void __exit lpuart_serial_exit(void)
2541 {
2542         ida_destroy(&fsl_lpuart_ida);
2543         platform_driver_unregister(&lpuart_driver);
2544         uart_unregister_driver(&lpuart_reg);
2545 }
2546
2547 module_init(lpuart_serial_init);
2548 module_exit(lpuart_serial_exit);
2549
2550 MODULE_DESCRIPTION("Freescale lpuart serial port driver");
2551 MODULE_LICENSE("GPL v2");