drivers/tty/serial/8250/8250_pci.c

   1 /*
   2  *  Probe module for 8250/16550-type PCI serial ports.
   3  *
   4  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
   5  *
   6  *  Copyright (C) 2001 Russell King, All Rights Reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License.
  11  */
  12 #undef DEBUG
  13 #include <linux/module.h>
  14 #include <linux/pci.h>
  15 #include <linux/string.h>
  16 #include <linux/kernel.h>
  17 #include <linux/slab.h>
  18 #include <linux/delay.h>
  19 #include <linux/tty.h>
  20 #include <linux/serial_reg.h>
  21 #include <linux/serial_core.h>
  22 #include <linux/8250_pci.h>
  23 #include <linux/bitops.h>
  24 #include <linux/rational.h>
  25
  26 #include <asm/byteorder.h>
  27 #include <asm/io.h>
  28
  29 #include <linux/dmaengine.h>
  30 #include <linux/platform_data/dma-dw.h>
  31 #include <linux/platform_data/dma-hsu.h>
  32
  33 #include "8250.h"
  34
  35 /*
  36  * init function returns:
  37  *  > 0 - number of ports
  38  *  = 0 - use board->num_ports
  39  *  < 0 - error
  40  */
  41 struct pci_serial_quirk {
  42         u32     vendor;
  43         u32     device;
  44         u32     subvendor;
  45         u32     subdevice;
  46         int     (*probe)(struct pci_dev *dev);
  47         int     (*init)(struct pci_dev *dev);
  48         int     (*setup)(struct serial_private *,
  49                          const struct pciserial_board *,
  50                          struct uart_8250_port *, int);
  51         void    (*exit)(struct pci_dev *dev);
  52 };
  53
  54 #define PCI_NUM_BAR_RESOURCES   6
  55
  56 struct serial_private {
  57         struct pci_dev          *dev;
  58         unsigned int            nr;
  59         void __iomem            *remapped_bar[PCI_NUM_BAR_RESOURCES];
  60         struct pci_serial_quirk *quirk;
  61         int                     line[0];
  62 };
  63
  64 static int pci_default_setup(struct serial_private*,
  65           const struct pciserial_board*, struct uart_8250_port *, int);
  66
  67 static void moan_device(const char *str, struct pci_dev *dev)
  68 {
  69         dev_err(&dev->dev,
  70                "%s: %s\n"
  71                "Please send the output of lspci -vv, this\n"
  72                "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
  73                "manufacturer and name of serial board or\n"
  74                "modem board to <linux-serial@vger.kernel.org>.\n",
  75                pci_name(dev), str, dev->vendor, dev->device,
  76                dev->subsystem_vendor, dev->subsystem_device);
  77 }
  78
  79 static int
  80 setup_port(struct serial_private *priv, struct uart_8250_port *port,
  81            int bar, int offset, int regshift)
  82 {
  83         struct pci_dev *dev = priv->dev;
  84
  85         if (bar >= PCI_NUM_BAR_RESOURCES)
  86                 return -EINVAL;
  87
  88         if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
  89                 if (!priv->remapped_bar[bar])
  90                         priv->remapped_bar[bar] = pci_ioremap_bar(dev, bar);
  91                 if (!priv->remapped_bar[bar])
  92                         return -ENOMEM;
  93
  94                 port->port.iotype = UPIO_MEM;
  95                 port->port.iobase = 0;
  96                 port->port.mapbase = pci_resource_start(dev, bar) + offset;
  97                 port->port.membase = priv->remapped_bar[bar] + offset;
  98                 port->port.regshift = regshift;
  99         } else {
 100                 port->port.iotype = UPIO_PORT;
 101                 port->port.iobase = pci_resource_start(dev, bar) + offset;
 102                 port->port.mapbase = 0;
 103                 port->port.membase = NULL;
 104                 port->port.regshift = 0;
 105         }
 106         return 0;
 107 }
 108
 109 /*
 110  * ADDI-DATA GmbH communication cards <info@addi-data.com>
 111  */
 112 static int addidata_apci7800_setup(struct serial_private *priv,
 113                                 const struct pciserial_board *board,
 114                                 struct uart_8250_port *port, int idx)
 115 {
 116         unsigned int bar = 0, offset = board->first_offset;
 117         bar = FL_GET_BASE(board->flags);
 118
 119         if (idx < 2) {
 120                 offset += idx * board->uart_offset;
 121         } else if ((idx >= 2) && (idx < 4)) {
 122                 bar += 1;
 123                 offset += ((idx - 2) * board->uart_offset);
 124         } else if ((idx >= 4) && (idx < 6)) {
 125                 bar += 2;
 126                 offset += ((idx - 4) * board->uart_offset);
 127         } else if (idx >= 6) {
 128                 bar += 3;
 129                 offset += ((idx - 6) * board->uart_offset);
 130         }
 131
 132         return setup_port(priv, port, bar, offset, board->reg_shift);
 133 }
 134
 135 /*
 136  * AFAVLAB uses a different mixture of BARs and offsets
 137  * Not that ugly ;) -- HW
 138  */
 139 static int
 140 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
 141               struct uart_8250_port *port, int idx)
 142 {
 143         unsigned int bar, offset = board->first_offset;
 144
 145         bar = FL_GET_BASE(board->flags);
 146         if (idx < 4)
 147                 bar += idx;
 148         else {
 149                 bar = 4;
 150                 offset += (idx - 4) * board->uart_offset;
 151         }
 152
 153         return setup_port(priv, port, bar, offset, board->reg_shift);
 154 }
 155
 156 /*
 157  * HP's Remote Management Console.  The Diva chip came in several
 158  * different versions.  N-class, L2000 and A500 have two Diva chips, each
 159  * with 3 UARTs (the third UART on the second chip is unused).  Superdome
 160  * and Keystone have one Diva chip with 3 UARTs.  Some later machines have
 161  * one Diva chip, but it has been expanded to 5 UARTs.
 162  */
 163 static int pci_hp_diva_init(struct pci_dev *dev)
 164 {
 165         int rc = 0;
 166
 167         switch (dev->subsystem_device) {
 168         case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
 169         case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
 170         case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
 171         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 172                 rc = 3;
 173                 break;
 174         case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
 175                 rc = 2;
 176                 break;
 177         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 178                 rc = 4;
 179                 break;
 180         case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
 181         case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
 182                 rc = 1;
 183                 break;
 184         }
 185
 186         return rc;
 187 }
 188
 189 /*
 190  * HP's Diva chip puts the 4th/5th serial port further out, and
 191  * some serial ports are supposed to be hidden on certain models.
 192  */
 193 static int
 194 pci_hp_diva_setup(struct serial_private *priv,
 195                 const struct pciserial_board *board,
 196                 struct uart_8250_port *port, int idx)
 197 {
 198         unsigned int offset = board->first_offset;
 199         unsigned int bar = FL_GET_BASE(board->flags);
 200
 201         switch (priv->dev->subsystem_device) {
 202         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 203                 if (idx == 3)
 204                         idx++;
 205                 break;
 206         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 207                 if (idx > 0)
 208                         idx++;
 209                 if (idx > 2)
 210                         idx++;
 211                 break;
 212         }
 213         if (idx > 2)
 214                 offset = 0x18;
 215
 216         offset += idx * board->uart_offset;
 217
 218         return setup_port(priv, port, bar, offset, board->reg_shift);
 219 }
 220
 221 /*
 222  * Added for EKF Intel i960 serial boards
 223  */
 224 static int pci_inteli960ni_init(struct pci_dev *dev)
 225 {
 226         u32 oldval;
 227
 228         if (!(dev->subsystem_device & 0x1000))
 229                 return -ENODEV;
 230
 231         /* is firmware started? */
 232         pci_read_config_dword(dev, 0x44, &oldval);
 233         if (oldval == 0x00001000L) { /* RESET value */
 234                 dev_dbg(&dev->dev, "Local i960 firmware missing\n");
 235                 return -ENODEV;
 236         }
 237         return 0;
 238 }
 239
 240 /*
 241  * Some PCI serial cards using the PLX 9050 PCI interface chip require
 242  * that the card interrupt be explicitly enabled or disabled.  This
 243  * seems to be mainly needed on card using the PLX which also use I/O
 244  * mapped memory.
 245  */
 246 static int pci_plx9050_init(struct pci_dev *dev)
 247 {
 248         u8 irq_config;
 249         void __iomem *p;
 250
 251         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
 252                 moan_device("no memory in bar 0", dev);
 253                 return 0;
 254         }
 255
 256         irq_config = 0x41;
 257         if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
 258             dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
 259                 irq_config = 0x43;
 260
 261         if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
 262             (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
 263                 /*
 264                  * As the megawolf cards have the int pins active
 265                  * high, and have 2 UART chips, both ints must be
 266                  * enabled on the 9050. Also, the UARTS are set in
 267                  * 16450 mode by default, so we have to enable the
 268                  * 16C950 'enhanced' mode so that we can use the
 269                  * deep FIFOs
 270                  */
 271                 irq_config = 0x5b;
 272         /*
 273          * enable/disable interrupts
 274          */
 275         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 276         if (p == NULL)
 277                 return -ENOMEM;
 278         writel(irq_config, p + 0x4c);
 279
 280         /*
 281          * Read the register back to ensure that it took effect.
 282          */
 283         readl(p + 0x4c);
 284         iounmap(p);
 285
 286         return 0;
 287 }
 288
 289 static void pci_plx9050_exit(struct pci_dev *dev)
 290 {
 291         u8 __iomem *p;
 292
 293         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
 294                 return;
 295
 296         /*
 297          * disable interrupts
 298          */
 299         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 300         if (p != NULL) {
 301                 writel(0, p + 0x4c);
 302
 303                 /*
 304                  * Read the register back to ensure that it took effect.
 305                  */
 306                 readl(p + 0x4c);
 307                 iounmap(p);
 308         }
 309 }
 310
 311 #define NI8420_INT_ENABLE_REG   0x38
 312 #define NI8420_INT_ENABLE_BIT   0x2000
 313
 314 static void pci_ni8420_exit(struct pci_dev *dev)
 315 {
 316         void __iomem *p;
 317         unsigned int bar = 0;
 318
 319         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 320                 moan_device("no memory in bar", dev);
 321                 return;
 322         }
 323
 324         p = pci_ioremap_bar(dev, bar);
 325         if (p == NULL)
 326                 return;
 327
 328         /* Disable the CPU Interrupt */
 329         writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
 330                p + NI8420_INT_ENABLE_REG);
 331         iounmap(p);
 332 }
 333
 334
 335 /* MITE registers */
 336 #define MITE_IOWBSR1    0xc4
 337 #define MITE_IOWCR1     0xf4
 338 #define MITE_LCIMR1     0x08
 339 #define MITE_LCIMR2     0x10
 340
 341 #define MITE_LCIMR2_CLR_CPU_IE  (1 << 30)
 342
 343 static void pci_ni8430_exit(struct pci_dev *dev)
 344 {
 345         void __iomem *p;
 346         unsigned int bar = 0;
 347
 348         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 349                 moan_device("no memory in bar", dev);
 350                 return;
 351         }
 352
 353         p = pci_ioremap_bar(dev, bar);
 354         if (p == NULL)
 355                 return;
 356
 357         /* Disable the CPU Interrupt */
 358         writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
 359         iounmap(p);
 360 }
 361
 362 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
 363 static int
 364 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
 365                 struct uart_8250_port *port, int idx)
 366 {
 367         unsigned int bar, offset = board->first_offset;
 368
 369         bar = 0;
 370
 371         if (idx < 4) {
 372                 /* first four channels map to 0, 0x100, 0x200, 0x300 */
 373                 offset += idx * board->uart_offset;
 374         } else if (idx < 8) {
 375                 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
 376                 offset += idx * board->uart_offset + 0xC00;
 377         } else /* we have only 8 ports on PMC-OCTALPRO */
 378                 return 1;
 379
 380         return setup_port(priv, port, bar, offset, board->reg_shift);
 381 }
 382
 383 /*
 384 * This does initialization for PMC OCTALPRO cards:
 385 * maps the device memory, resets the UARTs (needed, bc
 386 * if the module is removed and inserted again, the card
 387 * is in the sleep mode) and enables global interrupt.
 388 */
 389
 390 /* global control register offset for SBS PMC-OctalPro */
 391 #define OCT_REG_CR_OFF          0x500
 392
 393 static int sbs_init(struct pci_dev *dev)
 394 {
 395         u8 __iomem *p;
 396
 397         p = pci_ioremap_bar(dev, 0);
 398
 399         if (p == NULL)
 400                 return -ENOMEM;
 401         /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
 402         writeb(0x10, p + OCT_REG_CR_OFF);
 403         udelay(50);
 404         writeb(0x0, p + OCT_REG_CR_OFF);
 405
 406         /* Set bit-2 (INTENABLE) of Control Register */
 407         writeb(0x4, p + OCT_REG_CR_OFF);
 408         iounmap(p);
 409
 410         return 0;
 411 }
 412
 413 /*
 414  * Disables the global interrupt of PMC-OctalPro
 415  */
 416
 417 static void sbs_exit(struct pci_dev *dev)
 418 {
 419         u8 __iomem *p;
 420
 421         p = pci_ioremap_bar(dev, 0);
 422         /* FIXME: What if resource_len < OCT_REG_CR_OFF */
 423         if (p != NULL)
 424                 writeb(0, p + OCT_REG_CR_OFF);
 425         iounmap(p);
 426 }
 427
 428 /*
 429  * SIIG serial cards have an PCI interface chip which also controls
 430  * the UART clocking frequency. Each UART can be clocked independently
 431  * (except cards equipped with 4 UARTs) and initial clocking settings
 432  * are stored in the EEPROM chip. It can cause problems because this
 433  * version of serial driver doesn't support differently clocked UART's
 434  * on single PCI card. To prevent this, initialization functions set
 435  * high frequency clocking for all UART's on given card. It is safe (I
 436  * hope) because it doesn't touch EEPROM settings to prevent conflicts
 437  * with other OSes (like M$ DOS).
 438  *
 439  *  SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
 440  *
 441  * There is two family of SIIG serial cards with different PCI
 442  * interface chip and different configuration methods:
 443  *     - 10x cards have control registers in IO and/or memory space;
 444  *     - 20x cards have control registers in standard PCI configuration space.
 445  *
 446  * Note: all 10x cards have PCI device ids 0x10..
 447  *       all 20x cards have PCI device ids 0x20..
 448  *
 449  * There are also Quartet Serial cards which use Oxford Semiconductor
 450  * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
 451  *
 452  * Note: some SIIG cards are probed by the parport_serial object.
 453  */
 454
 455 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
 456 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
 457
 458 static int pci_siig10x_init(struct pci_dev *dev)
 459 {
 460         u16 data;
 461         void __iomem *p;
 462
 463         switch (dev->device & 0xfff8) {
 464         case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
 465                 data = 0xffdf;
 466                 break;
 467         case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
 468                 data = 0xf7ff;
 469                 break;
 470         default:                        /* 1S1P, 4S */
 471                 data = 0xfffb;
 472                 break;
 473         }
 474
 475         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 476         if (p == NULL)
 477                 return -ENOMEM;
 478
 479         writew(readw(p + 0x28) & data, p + 0x28);
 480         readw(p + 0x28);
 481         iounmap(p);
 482         return 0;
 483 }
 484
 485 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
 486 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
 487
 488 static int pci_siig20x_init(struct pci_dev *dev)
 489 {
 490         u8 data;
 491
 492         /* Change clock frequency for the first UART. */
 493         pci_read_config_byte(dev, 0x6f, &data);
 494         pci_write_config_byte(dev, 0x6f, data & 0xef);
 495
 496         /* If this card has 2 UART, we have to do the same with second UART. */
 497         if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
 498             ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
 499                 pci_read_config_byte(dev, 0x73, &data);
 500                 pci_write_config_byte(dev, 0x73, data & 0xef);
 501         }
 502         return 0;
 503 }
 504
 505 static int pci_siig_init(struct pci_dev *dev)
 506 {
 507         unsigned int type = dev->device & 0xff00;
 508
 509         if (type == 0x1000)
 510                 return pci_siig10x_init(dev);
 511         else if (type == 0x2000)
 512                 return pci_siig20x_init(dev);
 513
 514         moan_device("Unknown SIIG card", dev);
 515         return -ENODEV;
 516 }
 517
 518 static int pci_siig_setup(struct serial_private *priv,
 519                           const struct pciserial_board *board,
 520                           struct uart_8250_port *port, int idx)
 521 {
 522         unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
 523
 524         if (idx > 3) {
 525                 bar = 4;
 526                 offset = (idx - 4) * 8;
 527         }
 528
 529         return setup_port(priv, port, bar, offset, 0);
 530 }
 531
 532 /*
 533  * Timedia has an explosion of boards, and to avoid the PCI table from
 534  * growing *huge*, we use this function to collapse some 70 entries
 535  * in the PCI table into one, for sanity's and compactness's sake.
 536  */
 537 static const unsigned short timedia_single_port[] = {
 538         0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
 539 };
 540
 541 static const unsigned short timedia_dual_port[] = {
 542         0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
 543         0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
 544         0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
 545         0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
 546         0xD079, 0
 547 };
 548
 549 static const unsigned short timedia_quad_port[] = {
 550         0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
 551         0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
 552         0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
 553         0xB157, 0
 554 };
 555
 556 static const unsigned short timedia_eight_port[] = {
 557         0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
 558         0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
 559 };
 560
 561 static const struct timedia_struct {
 562         int num;
 563         const unsigned short *ids;
 564 } timedia_data[] = {
 565         { 1, timedia_single_port },
 566         { 2, timedia_dual_port },
 567         { 4, timedia_quad_port },
 568         { 8, timedia_eight_port }
 569 };
 570
 571 /*
 572  * There are nearly 70 different Timedia/SUNIX PCI serial devices.  Instead of
 573  * listing them individually, this driver merely grabs them all with
 574  * PCI_ANY_ID.  Some of these devices, however, also feature a parallel port,
 575  * and should be left free to be claimed by parport_serial instead.
 576  */
 577 static int pci_timedia_probe(struct pci_dev *dev)
 578 {
 579         /*
 580          * Check the third digit of the subdevice ID
 581          * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
 582          */
 583         if ((dev->subsystem_device & 0x00f0) >= 0x70) {
 584                 dev_info(&dev->dev,
 585                         "ignoring Timedia subdevice %04x for parport_serial\n",
 586                         dev->subsystem_device);
 587                 return -ENODEV;
 588         }
 589
 590         return 0;
 591 }
 592
 593 static int pci_timedia_init(struct pci_dev *dev)
 594 {
 595         const unsigned short *ids;
 596         int i, j;
 597
 598         for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
 599                 ids = timedia_data[i].ids;
 600                 for (j = 0; ids[j]; j++)
 601                         if (dev->subsystem_device == ids[j])
 602                                 return timedia_data[i].num;
 603         }
 604         return 0;
 605 }
 606
 607 /*
 608  * Timedia/SUNIX uses a mixture of BARs and offsets
 609  * Ugh, this is ugly as all hell --- TYT
 610  */
 611 static int
 612 pci_timedia_setup(struct serial_private *priv,
 613                   const struct pciserial_board *board,
 614                   struct uart_8250_port *port, int idx)
 615 {
 616         unsigned int bar = 0, offset = board->first_offset;
 617
 618         switch (idx) {
 619         case 0:
 620                 bar = 0;
 621                 break;
 622         case 1:
 623                 offset = board->uart_offset;
 624                 bar = 0;
 625                 break;
 626         case 2:
 627                 bar = 1;
 628                 break;
 629         case 3:
 630                 offset = board->uart_offset;
 631                 /* FALLTHROUGH */
 632         case 4: /* BAR 2 */
 633         case 5: /* BAR 3 */
 634         case 6: /* BAR 4 */
 635         case 7: /* BAR 5 */
 636                 bar = idx - 2;
 637         }
 638
 639         return setup_port(priv, port, bar, offset, board->reg_shift);
 640 }
 641
 642 /*
 643  * Some Titan cards are also a little weird
 644  */
 645 static int
 646 titan_400l_800l_setup(struct serial_private *priv,
 647                       const struct pciserial_board *board,
 648                       struct uart_8250_port *port, int idx)
 649 {
 650         unsigned int bar, offset = board->first_offset;
 651
 652         switch (idx) {
 653         case 0:
 654                 bar = 1;
 655                 break;
 656         case 1:
 657                 bar = 2;
 658                 break;
 659         default:
 660                 bar = 4;
 661                 offset = (idx - 2) * board->uart_offset;
 662         }
 663
 664         return setup_port(priv, port, bar, offset, board->reg_shift);
 665 }
 666
 667 static int pci_xircom_init(struct pci_dev *dev)
 668 {
 669         msleep(100);
 670         return 0;
 671 }
 672
 673 static int pci_ni8420_init(struct pci_dev *dev)
 674 {
 675         void __iomem *p;
 676         unsigned int bar = 0;
 677
 678         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 679                 moan_device("no memory in bar", dev);
 680                 return 0;
 681         }
 682
 683         p = pci_ioremap_bar(dev, bar);
 684         if (p == NULL)
 685                 return -ENOMEM;
 686
 687         /* Enable CPU Interrupt */
 688         writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
 689                p + NI8420_INT_ENABLE_REG);
 690
 691         iounmap(p);
 692         return 0;
 693 }
 694
 695 #define MITE_IOWBSR1_WSIZE      0xa
 696 #define MITE_IOWBSR1_WIN_OFFSET 0x800
 697 #define MITE_IOWBSR1_WENAB      (1 << 7)
 698 #define MITE_LCIMR1_IO_IE_0     (1 << 24)
 699 #define MITE_LCIMR2_SET_CPU_IE  (1 << 31)
 700 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
 701
 702 static int pci_ni8430_init(struct pci_dev *dev)
 703 {
 704         void __iomem *p;
 705         struct pci_bus_region region;
 706         u32 device_window;
 707         unsigned int bar = 0;
 708
 709         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 710                 moan_device("no memory in bar", dev);
 711                 return 0;
 712         }
 713
 714         p = pci_ioremap_bar(dev, bar);
 715         if (p == NULL)
 716                 return -ENOMEM;
 717
 718         /*
 719          * Set device window address and size in BAR0, while acknowledging that
 720          * the resource structure may contain a translated address that differs
 721          * from the address the device responds to.
 722          */
 723         pcibios_resource_to_bus(dev->bus, &region, &dev->resource[bar]);
 724         device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
 725                         | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
 726         writel(device_window, p + MITE_IOWBSR1);
 727
 728         /* Set window access to go to RAMSEL IO address space */
 729         writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
 730                p + MITE_IOWCR1);
 731
 732         /* Enable IO Bus Interrupt 0 */
 733         writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
 734
 735         /* Enable CPU Interrupt */
 736         writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
 737
 738         iounmap(p);
 739         return 0;
 740 }
 741
 742 /* UART Port Control Register */
 743 #define NI8430_PORTCON  0x0f
 744 #define NI8430_PORTCON_TXVR_ENABLE      (1 << 3)
 745
 746 static int
 747 pci_ni8430_setup(struct serial_private *priv,
 748                  const struct pciserial_board *board,
 749                  struct uart_8250_port *port, int idx)
 750 {
 751         struct pci_dev *dev = priv->dev;
 752         void __iomem *p;
 753         unsigned int bar, offset = board->first_offset;
 754
 755         if (idx >= board->num_ports)
 756                 return 1;
 757
 758         bar = FL_GET_BASE(board->flags);
 759         offset += idx * board->uart_offset;
 760
 761         p = pci_ioremap_bar(dev, bar);
 762         if (!p)
 763                 return -ENOMEM;
 764
 765         /* enable the transceiver */
 766         writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
 767                p + offset + NI8430_PORTCON);
 768
 769         iounmap(p);
 770
 771         return setup_port(priv, port, bar, offset, board->reg_shift);
 772 }
 773
 774 static int pci_netmos_9900_setup(struct serial_private *priv,
 775                                 const struct pciserial_board *board,
 776                                 struct uart_8250_port *port, int idx)
 777 {
 778         unsigned int bar;
 779
 780         if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
 781             (priv->dev->subsystem_device & 0xff00) == 0x3000) {
 782                 /* netmos apparently orders BARs by datasheet layout, so serial
 783                  * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
 784                  */
 785                 bar = 3 * idx;
 786
 787                 return setup_port(priv, port, bar, 0, board->reg_shift);
 788         } else {
 789                 return pci_default_setup(priv, board, port, idx);
 790         }
 791 }
 792
 793 /* the 99xx series comes with a range of device IDs and a variety
 794  * of capabilities:
 795  *
 796  * 9900 has varying capabilities and can cascade to sub-controllers
 797  *   (cascading should be purely internal)
 798  * 9904 is hardwired with 4 serial ports
 799  * 9912 and 9922 are hardwired with 2 serial ports
 800  */
 801 static int pci_netmos_9900_numports(struct pci_dev *dev)
 802 {
 803         unsigned int c = dev->class;
 804         unsigned int pi;
 805         unsigned short sub_serports;
 806
 807         pi = (c & 0xff);
 808
 809         if (pi == 2) {
 810                 return 1;
 811         } else if ((pi == 0) &&
 812                            (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
 813                 /* two possibilities: 0x30ps encodes number of parallel and
 814                  * serial ports, or 0x1000 indicates *something*. This is not
 815                  * immediately obvious, since the 2s1p+4s configuration seems
 816                  * to offer all functionality on functions 0..2, while still
 817                  * advertising the same function 3 as the 4s+2s1p config.
 818                  */
 819                 sub_serports = dev->subsystem_device & 0xf;
 820                 if (sub_serports > 0) {
 821                         return sub_serports;
 822                 } else {
 823                         dev_err(&dev->dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
 824                         return 0;
 825                 }
 826         }
 827
 828         moan_device("unknown NetMos/Mostech program interface", dev);
 829         return 0;
 830 }
 831
 832 static int pci_netmos_init(struct pci_dev *dev)
 833 {
 834         /* subdevice 0x00PS means <P> parallel, <S> serial */
 835         unsigned int num_serial = dev->subsystem_device & 0xf;
 836
 837         if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
 838                 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
 839                 return 0;
 840
 841         if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
 842                         dev->subsystem_device == 0x0299)
 843                 return 0;
 844
 845         switch (dev->device) { /* FALLTHROUGH on all */
 846                 case PCI_DEVICE_ID_NETMOS_9904:
 847                 case PCI_DEVICE_ID_NETMOS_9912:
 848                 case PCI_DEVICE_ID_NETMOS_9922:
 849                 case PCI_DEVICE_ID_NETMOS_9900:
 850                         num_serial = pci_netmos_9900_numports(dev);
 851                         break;
 852
 853                 default:
 854                         if (num_serial == 0 ) {
 855                                 moan_device("unknown NetMos/Mostech device", dev);
 856                         }
 857         }
 858
 859         if (num_serial == 0)
 860                 return -ENODEV;
 861
 862         return num_serial;
 863 }
 864
 865 /*
 866  * These chips are available with optionally one parallel port and up to
 867  * two serial ports. Unfortunately they all have the same product id.
 868  *
 869  * Basic configuration is done over a region of 32 I/O ports. The base
 870  * ioport is called INTA or INTC, depending on docs/other drivers.
 871  *
 872  * The region of the 32 I/O ports is configured in POSIO0R...
 873  */
 874
 875 /* registers */
 876 #define ITE_887x_MISCR          0x9c
 877 #define ITE_887x_INTCBAR        0x78
 878 #define ITE_887x_UARTBAR        0x7c
 879 #define ITE_887x_PS0BAR         0x10
 880 #define ITE_887x_POSIO0         0x60
 881
 882 /* I/O space size */
 883 #define ITE_887x_IOSIZE         32
 884 /* I/O space size (bits 26-24; 8 bytes = 011b) */
 885 #define ITE_887x_POSIO_IOSIZE_8         (3 << 24)
 886 /* I/O space size (bits 26-24; 32 bytes = 101b) */
 887 #define ITE_887x_POSIO_IOSIZE_32        (5 << 24)
 888 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
 889 #define ITE_887x_POSIO_SPEED            (3 << 29)
 890 /* enable IO_Space bit */
 891 #define ITE_887x_POSIO_ENABLE           (1 << 31)
 892
 893 static int pci_ite887x_init(struct pci_dev *dev)
 894 {
 895         /* inta_addr are the configuration addresses of the ITE */
 896         static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
 897                                                         0x200, 0x280, 0 };
 898         int ret, i, type;
 899         struct resource *iobase = NULL;
 900         u32 miscr, uartbar, ioport;
 901
 902         /* search for the base-ioport */
 903         i = 0;
 904         while (inta_addr[i] && iobase == NULL) {
 905                 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
 906                                                                 "ite887x");
 907                 if (iobase != NULL) {
 908                         /* write POSIO0R - speed | size | ioport */
 909                         pci_write_config_dword(dev, ITE_887x_POSIO0,
 910                                 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
 911                                 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
 912                         /* write INTCBAR - ioport */
 913                         pci_write_config_dword(dev, ITE_887x_INTCBAR,
 914                                                                 inta_addr[i]);
 915                         ret = inb(inta_addr[i]);
 916                         if (ret != 0xff) {
 917                                 /* ioport connected */
 918                                 break;
 919                         }
 920                         release_region(iobase->start, ITE_887x_IOSIZE);
 921                         iobase = NULL;
 922                 }
 923                 i++;
 924         }
 925
 926         if (!inta_addr[i]) {
 927                 dev_err(&dev->dev, "ite887x: could not find iobase\n");
 928                 return -ENODEV;
 929         }
 930
 931         /* start of undocumented type checking (see parport_pc.c) */
 932         type = inb(iobase->start + 0x18) & 0x0f;
 933
 934         switch (type) {
 935         case 0x2:       /* ITE8871 (1P) */
 936         case 0xa:       /* ITE8875 (1P) */
 937                 ret = 0;
 938                 break;
 939         case 0xe:       /* ITE8872 (2S1P) */
 940                 ret = 2;
 941                 break;
 942         case 0x6:       /* ITE8873 (1S) */
 943                 ret = 1;
 944                 break;
 945         case 0x8:       /* ITE8874 (2S) */
 946                 ret = 2;
 947                 break;
 948         default:
 949                 moan_device("Unknown ITE887x", dev);
 950                 ret = -ENODEV;
 951         }
 952
 953         /* configure all serial ports */
 954         for (i = 0; i < ret; i++) {
 955                 /* read the I/O port from the device */
 956                 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
 957                                                                 &ioport);
 958                 ioport &= 0x0000FF00;   /* the actual base address */
 959                 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
 960                         ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
 961                         ITE_887x_POSIO_IOSIZE_8 | ioport);
 962
 963                 /* write the ioport to the UARTBAR */
 964                 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
 965                 uartbar &= ~(0xffff << (16 * i));       /* clear half the reg */
 966                 uartbar |= (ioport << (16 * i));        /* set the ioport */
 967                 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
 968
 969                 /* get current config */
 970                 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
 971                 /* disable interrupts (UARTx_Routing[3:0]) */
 972                 miscr &= ~(0xf << (12 - 4 * i));
 973                 /* activate the UART (UARTx_En) */
 974                 miscr |= 1 << (23 - i);
 975                 /* write new config with activated UART */
 976                 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
 977         }
 978
 979         if (ret <= 0) {
 980                 /* the device has no UARTs if we get here */
 981                 release_region(iobase->start, ITE_887x_IOSIZE);
 982         }
 983
 984         return ret;
 985 }
 986
 987 static void pci_ite887x_exit(struct pci_dev *dev)
 988 {
 989         u32 ioport;
 990         /* the ioport is bit 0-15 in POSIO0R */
 991         pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
 992         ioport &= 0xffff;
 993         release_region(ioport, ITE_887x_IOSIZE);
 994 }
 995
 996 /*
 997  * EndRun Technologies.
 998  * Determine the number of ports available on the device.
 999  */
1000 #define PCI_VENDOR_ID_ENDRUN                    0x7401
1001 #define PCI_DEVICE_ID_ENDRUN_1588       0xe100
1002
1003 static int pci_endrun_init(struct pci_dev *dev)
1004 {
1005         u8 __iomem *p;
1006         unsigned long deviceID;
1007         unsigned int  number_uarts = 0;
1008
1009         /* EndRun device is all 0xexxx */
1010         if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
1011                 (dev->device & 0xf000) != 0xe000)
1012                 return 0;
1013
1014         p = pci_iomap(dev, 0, 5);
1015         if (p == NULL)
1016                 return -ENOMEM;
1017
1018         deviceID = ioread32(p);
1019         /* EndRun device */
1020         if (deviceID == 0x07000200) {
1021                 number_uarts = ioread8(p + 4);
1022                 dev_dbg(&dev->dev,
1023                         "%d ports detected on EndRun PCI Express device\n",
1024                         number_uarts);
1025         }
1026         pci_iounmap(dev, p);
1027         return number_uarts;
1028 }
1029
1030 /*
1031  * Oxford Semiconductor Inc.
1032  * Check that device is part of the Tornado range of devices, then determine
1033  * the number of ports available on the device.
1034  */
1035 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1036 {
1037         u8 __iomem *p;
1038         unsigned long deviceID;
1039         unsigned int  number_uarts = 0;
1040
1041         /* OxSemi Tornado devices are all 0xCxxx */
1042         if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1043             (dev->device & 0xF000) != 0xC000)
1044                 return 0;
1045
1046         p = pci_iomap(dev, 0, 5);
1047         if (p == NULL)
1048                 return -ENOMEM;
1049
1050         deviceID = ioread32(p);
1051         /* Tornado device */
1052         if (deviceID == 0x07000200) {
1053                 number_uarts = ioread8(p + 4);
1054                 dev_dbg(&dev->dev,
1055                         "%d ports detected on Oxford PCI Express device\n",
1056                         number_uarts);
1057         }
1058         pci_iounmap(dev, p);
1059         return number_uarts;
1060 }
1061
1062 static int pci_asix_setup(struct serial_private *priv,
1063                   const struct pciserial_board *board,
1064                   struct uart_8250_port *port, int idx)
1065 {
1066         port->bugs |= UART_BUG_PARITY;
1067         return pci_default_setup(priv, board, port, idx);
1068 }
1069
1070 /* Quatech devices have their own extra interface features */
1071
1072 struct quatech_feature {
1073         u16 devid;
1074         bool amcc;
1075 };
1076
1077 #define QPCR_TEST_FOR1          0x3F
1078 #define QPCR_TEST_GET1          0x00
1079 #define QPCR_TEST_FOR2          0x40
1080 #define QPCR_TEST_GET2          0x40
1081 #define QPCR_TEST_FOR3          0x80
1082 #define QPCR_TEST_GET3          0x40
1083 #define QPCR_TEST_FOR4          0xC0
1084 #define QPCR_TEST_GET4          0x80
1085
1086 #define QOPR_CLOCK_X1           0x0000
1087 #define QOPR_CLOCK_X2           0x0001
1088 #define QOPR_CLOCK_X4           0x0002
1089 #define QOPR_CLOCK_X8           0x0003
1090 #define QOPR_CLOCK_RATE_MASK    0x0003
1091
1092
1093 static struct quatech_feature quatech_cards[] = {
1094         { PCI_DEVICE_ID_QUATECH_QSC100,   1 },
1095         { PCI_DEVICE_ID_QUATECH_DSC100,   1 },
1096         { PCI_DEVICE_ID_QUATECH_DSC100E,  0 },
1097         { PCI_DEVICE_ID_QUATECH_DSC200,   1 },
1098         { PCI_DEVICE_ID_QUATECH_DSC200E,  0 },
1099         { PCI_DEVICE_ID_QUATECH_ESC100D,  1 },
1100         { PCI_DEVICE_ID_QUATECH_ESC100M,  1 },
1101         { PCI_DEVICE_ID_QUATECH_QSCP100,  1 },
1102         { PCI_DEVICE_ID_QUATECH_DSCP100,  1 },
1103         { PCI_DEVICE_ID_QUATECH_QSCP200,  1 },
1104         { PCI_DEVICE_ID_QUATECH_DSCP200,  1 },
1105         { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1106         { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1107         { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1108         { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1109         { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1110         { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1111         { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1112         { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1113         { 0, }
1114 };
1115
1116 static int pci_quatech_amcc(u16 devid)
1117 {
1118         struct quatech_feature *qf = &quatech_cards[0];
1119         while (qf->devid) {
1120                 if (qf->devid == devid)
1121                         return qf->amcc;
1122                 qf++;
1123         }
1124         pr_err("quatech: unknown port type '0x%04X'.\n", devid);
1125         return 0;
1126 };
1127
1128 static int pci_quatech_rqopr(struct uart_8250_port *port)
1129 {
1130         unsigned long base = port->port.iobase;
1131         u8 LCR, val;
1132
1133         LCR = inb(base + UART_LCR);
1134         outb(0xBF, base + UART_LCR);
1135         val = inb(base + UART_SCR);
1136         outb(LCR, base + UART_LCR);
1137         return val;
1138 }
1139
1140 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1141 {
1142         unsigned long base = port->port.iobase;
1143         u8 LCR, val;
1144
1145         LCR = inb(base + UART_LCR);
1146         outb(0xBF, base + UART_LCR);
1147         val = inb(base + UART_SCR);
1148         outb(qopr, base + UART_SCR);
1149         outb(LCR, base + UART_LCR);
1150 }
1151
1152 static int pci_quatech_rqmcr(struct uart_8250_port *port)
1153 {
1154         unsigned long base = port->port.iobase;
1155         u8 LCR, val, qmcr;
1156
1157         LCR = inb(base + UART_LCR);
1158         outb(0xBF, base + UART_LCR);
1159         val = inb(base + UART_SCR);
1160         outb(val | 0x10, base + UART_SCR);
1161         qmcr = inb(base + UART_MCR);
1162         outb(val, base + UART_SCR);
1163         outb(LCR, base + UART_LCR);
1164
1165         return qmcr;
1166 }
1167
1168 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1169 {
1170         unsigned long base = port->port.iobase;
1171         u8 LCR, val;
1172
1173         LCR = inb(base + UART_LCR);
1174         outb(0xBF, base + UART_LCR);
1175         val = inb(base + UART_SCR);
1176         outb(val | 0x10, base + UART_SCR);
1177         outb(qmcr, base + UART_MCR);
1178         outb(val, base + UART_SCR);
1179         outb(LCR, base + UART_LCR);
1180 }
1181
1182 static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1183 {
1184         unsigned long base = port->port.iobase;
1185         u8 LCR, val;
1186
1187         LCR = inb(base + UART_LCR);
1188         outb(0xBF, base + UART_LCR);
1189         val = inb(base + UART_SCR);
1190         if (val & 0x20) {
1191                 outb(0x80, UART_LCR);
1192                 if (!(inb(UART_SCR) & 0x20)) {
1193                         outb(LCR, base + UART_LCR);
1194                         return 1;
1195                 }
1196         }
1197         return 0;
1198 }
1199
1200 static int pci_quatech_test(struct uart_8250_port *port)
1201 {
1202         u8 reg;
1203         u8 qopr = pci_quatech_rqopr(port);
1204         pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1205         reg = pci_quatech_rqopr(port) & 0xC0;
1206         if (reg != QPCR_TEST_GET1)
1207                 return -EINVAL;
1208         pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1209         reg = pci_quatech_rqopr(port) & 0xC0;
1210         if (reg != QPCR_TEST_GET2)
1211                 return -EINVAL;
1212         pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1213         reg = pci_quatech_rqopr(port) & 0xC0;
1214         if (reg != QPCR_TEST_GET3)
1215                 return -EINVAL;
1216         pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1217         reg = pci_quatech_rqopr(port) & 0xC0;
1218         if (reg != QPCR_TEST_GET4)
1219                 return -EINVAL;
1220
1221         pci_quatech_wqopr(port, qopr);
1222         return 0;
1223 }
1224
1225 static int pci_quatech_clock(struct uart_8250_port *port)
1226 {
1227         u8 qopr, reg, set;
1228         unsigned long clock;
1229
1230         if (pci_quatech_test(port) < 0)
1231                 return 1843200;
1232
1233         qopr = pci_quatech_rqopr(port);
1234
1235         pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1236         reg = pci_quatech_rqopr(port);
1237         if (reg & QOPR_CLOCK_X8) {
1238                 clock = 1843200;
1239                 goto out;
1240         }
1241         pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1242         reg = pci_quatech_rqopr(port);
1243         if (!(reg & QOPR_CLOCK_X8)) {
1244                 clock = 1843200;
1245                 goto out;
1246         }
1247         reg &= QOPR_CLOCK_X8;
1248         if (reg == QOPR_CLOCK_X2) {
1249                 clock =  3685400;
1250                 set = QOPR_CLOCK_X2;
1251         } else if (reg == QOPR_CLOCK_X4) {
1252                 clock = 7372800;
1253                 set = QOPR_CLOCK_X4;
1254         } else if (reg == QOPR_CLOCK_X8) {
1255                 clock = 14745600;
1256                 set = QOPR_CLOCK_X8;
1257         } else {
1258                 clock = 1843200;
1259                 set = QOPR_CLOCK_X1;
1260         }
1261         qopr &= ~QOPR_CLOCK_RATE_MASK;
1262         qopr |= set;
1263
1264 out:
1265         pci_quatech_wqopr(port, qopr);
1266         return clock;
1267 }
1268
1269 static int pci_quatech_rs422(struct uart_8250_port *port)
1270 {
1271         u8 qmcr;
1272         int rs422 = 0;
1273
1274         if (!pci_quatech_has_qmcr(port))
1275                 return 0;
1276         qmcr = pci_quatech_rqmcr(port);
1277         pci_quatech_wqmcr(port, 0xFF);
1278         if (pci_quatech_rqmcr(port))
1279                 rs422 = 1;
1280         pci_quatech_wqmcr(port, qmcr);
1281         return rs422;
1282 }
1283
1284 static int pci_quatech_init(struct pci_dev *dev)
1285 {
1286         if (pci_quatech_amcc(dev->device)) {
1287                 unsigned long base = pci_resource_start(dev, 0);
1288                 if (base) {
1289                         u32 tmp;
1290                         outl(inl(base + 0x38) | 0x00002000, base + 0x38);
1291                         tmp = inl(base + 0x3c);
1292                         outl(tmp | 0x01000000, base + 0x3c);
1293                         outl(tmp &= ~0x01000000, base + 0x3c);
1294                 }
1295         }
1296         return 0;
1297 }
1298
1299 static int pci_quatech_setup(struct serial_private *priv,
1300                   const struct pciserial_board *board,
1301                   struct uart_8250_port *port, int idx)
1302 {
1303         /* Needed by pci_quatech calls below */
1304         port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1305         /* Set up the clocking */
1306         port->port.uartclk = pci_quatech_clock(port);
1307         /* For now just warn about RS422 */
1308         if (pci_quatech_rs422(port))
1309                 pr_warn("quatech: software control of RS422 features not currently supported.\n");
1310         return pci_default_setup(priv, board, port, idx);
1311 }
1312
1313 static void pci_quatech_exit(struct pci_dev *dev)
1314 {
1315 }
1316
1317 static int pci_default_setup(struct serial_private *priv,
1318                   const struct pciserial_board *board,
1319                   struct uart_8250_port *port, int idx)
1320 {
1321         unsigned int bar, offset = board->first_offset, maxnr;
1322
1323         bar = FL_GET_BASE(board->flags);
1324         if (board->flags & FL_BASE_BARS)
1325                 bar += idx;
1326         else
1327                 offset += idx * board->uart_offset;
1328
1329         maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1330                 (board->reg_shift + 3);
1331
1332         if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1333                 return 1;
1334
1335         return setup_port(priv, port, bar, offset, board->reg_shift);
1336 }
1337
1338 static int pci_pericom_setup(struct serial_private *priv,
1339                   const struct pciserial_board *board,
1340                   struct uart_8250_port *port, int idx)
1341 {
1342         unsigned int bar, offset = board->first_offset, maxnr;
1343
1344         bar = FL_GET_BASE(board->flags);
1345         if (board->flags & FL_BASE_BARS)
1346                 bar += idx;
1347         else
1348                 offset += idx * board->uart_offset;
1349
1350         maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1351                 (board->reg_shift + 3);
1352
1353         if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1354                 return 1;
1355
1356         port->port.uartclk = 14745600;
1357
1358         return setup_port(priv, port, bar, offset, board->reg_shift);
1359 }
1360
1361 static int
1362 ce4100_serial_setup(struct serial_private *priv,
1363                   const struct pciserial_board *board,
1364                   struct uart_8250_port *port, int idx)
1365 {
1366         int ret;
1367
1368         ret = setup_port(priv, port, idx, 0, board->reg_shift);
1369         port->port.iotype = UPIO_MEM32;
1370         port->port.type = PORT_XSCALE;
1371         port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1372         port->port.regshift = 2;
1373
1374         return ret;
1375 }
1376
1377 #define PCI_DEVICE_ID_INTEL_BYT_UART1   0x0f0a
1378 #define PCI_DEVICE_ID_INTEL_BYT_UART2   0x0f0c
1379
1380 #define PCI_DEVICE_ID_INTEL_BSW_UART1   0x228a
1381 #define PCI_DEVICE_ID_INTEL_BSW_UART2   0x228c
1382
1383 #define BYT_PRV_CLK                     0x800
1384 #define BYT_PRV_CLK_EN                  (1 << 0)
1385 #define BYT_PRV_CLK_M_VAL_SHIFT         1
1386 #define BYT_PRV_CLK_N_VAL_SHIFT         16
1387 #define BYT_PRV_CLK_UPDATE              (1 << 31)
1388
1389 #define BYT_TX_OVF_INT                  0x820
1390 #define BYT_TX_OVF_INT_MASK             (1 << 1)
1391
1392 static void
1393 byt_set_termios(struct uart_port *p, struct ktermios *termios,
1394                 struct ktermios *old)
1395 {
1396         unsigned int baud = tty_termios_baud_rate(termios);
1397         unsigned long fref = 100000000, fuart = baud * 16;
1398         unsigned long w = BIT(15) - 1;
1399         unsigned long m, n;
1400         u32 reg;
1401
1402         /* Get Fuart closer to Fref */
1403         fuart *= rounddown_pow_of_two(fref / fuart);
1404
1405         /*
1406          * For baud rates 0.5M, 1M, 1.5M, 2M, 2.5M, 3M, 3.5M and 4M the
1407          * dividers must be adjusted.
1408          *
1409          * uartclk = (m / n) * 100 MHz, where m <= n
1410          */
1411         rational_best_approximation(fuart, fref, w, w, &m, &n);
1412         p->uartclk = fuart;
1413
1414         /* Reset the clock */
1415         reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT);
1416         writel(reg, p->membase + BYT_PRV_CLK);
1417         reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE;
1418         writel(reg, p->membase + BYT_PRV_CLK);
1419
1420         serial8250_do_set_termios(p, termios, old);
1421 }
1422
1423 static bool byt_dma_filter(struct dma_chan *chan, void *param)
1424 {
1425         struct dw_dma_slave *dws = param;
1426
1427         if (dws->dma_dev != chan->device->dev)
1428                 return false;
1429
1430         chan->private = dws;
1431         return true;
1432 }
1433
1434 static int
1435 byt_serial_setup(struct serial_private *priv,
1436                  const struct pciserial_board *board,
1437                  struct uart_8250_port *port, int idx)
1438 {
1439         struct pci_dev *pdev = priv->dev;
1440         struct device *dev = port->port.dev;
1441         struct uart_8250_dma *dma;
1442         struct dw_dma_slave *tx_param, *rx_param;
1443         struct pci_dev *dma_dev;
1444         int ret;
1445
1446         dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
1447         if (!dma)
1448                 return -ENOMEM;
1449
1450         tx_param = devm_kzalloc(dev, sizeof(*tx_param), GFP_KERNEL);
1451         if (!tx_param)
1452                 return -ENOMEM;
1453
1454         rx_param = devm_kzalloc(dev, sizeof(*rx_param), GFP_KERNEL);
1455         if (!rx_param)
1456                 return -ENOMEM;
1457
1458         switch (pdev->device) {
1459         case PCI_DEVICE_ID_INTEL_BYT_UART1:
1460         case PCI_DEVICE_ID_INTEL_BSW_UART1:
1461                 rx_param->src_id = 3;
1462                 tx_param->dst_id = 2;
1463                 break;
1464         case PCI_DEVICE_ID_INTEL_BYT_UART2:
1465         case PCI_DEVICE_ID_INTEL_BSW_UART2:
1466                 rx_param->src_id = 5;
1467                 tx_param->dst_id = 4;
1468                 break;
1469         default:
1470                 return -EINVAL;
1471         }
1472
1473         rx_param->src_master = 1;
1474         rx_param->dst_master = 0;
1475
1476         dma->rxconf.src_maxburst = 16;
1477
1478         tx_param->src_master = 1;
1479         tx_param->dst_master = 0;
1480
1481         dma->txconf.dst_maxburst = 16;
1482
1483         dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 0));
1484         rx_param->dma_dev = &dma_dev->dev;
1485         tx_param->dma_dev = &dma_dev->dev;
1486
1487         dma->fn = byt_dma_filter;
1488         dma->rx_param = rx_param;
1489         dma->tx_param = tx_param;
1490
1491         ret = pci_default_setup(priv, board, port, idx);
1492         port->port.iotype = UPIO_MEM;
1493         port->port.type = PORT_16550A;
1494         port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1495         port->port.set_termios = byt_set_termios;
1496         port->port.fifosize = 64;
1497         port->tx_loadsz = 64;
1498         port->dma = dma;
1499         port->capabilities = UART_CAP_FIFO | UART_CAP_AFE;
1500
1501         /* Disable Tx counter interrupts */
1502         writel(BYT_TX_OVF_INT_MASK, port->port.membase + BYT_TX_OVF_INT);
1503
1504         return ret;
1505 }
1506
1507 #define INTEL_MID_UART_PS               0x30
1508 #define INTEL_MID_UART_MUL              0x34
1509 #define INTEL_MID_UART_DIV              0x38
1510
1511 static void intel_mid_set_termios(struct uart_port *p,
1512                                   struct ktermios *termios,
1513                                   struct ktermios *old,
1514                                   unsigned long fref)
1515 {
1516         unsigned int baud = tty_termios_baud_rate(termios);
1517         unsigned short ps = 16;
1518         unsigned long fuart = baud * ps;
1519         unsigned long w = BIT(24) - 1;
1520         unsigned long mul, div;
1521
1522         if (fref < fuart) {
1523                 /* Find prescaler value that satisfies Fuart < Fref */
1524                 if (fref > baud)
1525                         ps = fref / baud;       /* baud rate too high */
1526                 else
1527                         ps = 1;                 /* PLL case */
1528                 fuart = baud * ps;
1529         } else {
1530                 /* Get Fuart closer to Fref */
1531                 fuart *= rounddown_pow_of_two(fref / fuart);
1532         }
1533
1534         rational_best_approximation(fuart, fref, w, w, &mul, &div);
1535         p->uartclk = fuart * 16 / ps;           /* core uses ps = 16 always */
1536
1537         writel(ps, p->membase + INTEL_MID_UART_PS);             /* set PS */
1538         writel(mul, p->membase + INTEL_MID_UART_MUL);           /* set MUL */
1539         writel(div, p->membase + INTEL_MID_UART_DIV);
1540
1541         serial8250_do_set_termios(p, termios, old);
1542 }
1543
1544 static void intel_mid_set_termios_38_4M(struct uart_port *p,
1545                                         struct ktermios *termios,
1546                                         struct ktermios *old)
1547 {
1548         intel_mid_set_termios(p, termios, old, 38400000);
1549 }
1550
1551 static void intel_mid_set_termios_50M(struct uart_port *p,
1552                                       struct ktermios *termios,
1553                                       struct ktermios *old)
1554 {
1555         /*
1556          * The uart clk is 50Mhz, and the baud rate come from:
1557          *      baud = 50M * MUL / (DIV * PS * DLAB)
1558          */
1559         intel_mid_set_termios(p, termios, old, 50000000);
1560 }
1561
1562 static bool intel_mid_dma_filter(struct dma_chan *chan, void *param)
1563 {
1564         struct hsu_dma_slave *s = param;
1565
1566         if (s->dma_dev != chan->device->dev || s->chan_id != chan->chan_id)
1567                 return false;
1568
1569         chan->private = s;
1570         return true;
1571 }
1572
1573 static int intel_mid_serial_setup(struct serial_private *priv,
1574                                   const struct pciserial_board *board,
1575                                   struct uart_8250_port *port, int idx,
1576                                   int index, struct pci_dev *dma_dev)
1577 {
1578         struct device *dev = port->port.dev;
1579         struct uart_8250_dma *dma;
1580         struct hsu_dma_slave *tx_param, *rx_param;
1581
1582         dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
1583         if (!dma)
1584                 return -ENOMEM;
1585
1586         tx_param = devm_kzalloc(dev, sizeof(*tx_param), GFP_KERNEL);
1587         if (!tx_param)
1588                 return -ENOMEM;
1589
1590         rx_param = devm_kzalloc(dev, sizeof(*rx_param), GFP_KERNEL);
1591         if (!rx_param)
1592                 return -ENOMEM;
1593
1594         rx_param->chan_id = index * 2 + 1;
1595         tx_param->chan_id = index * 2;
1596
1597         dma->rxconf.src_maxburst = 64;
1598         dma->txconf.dst_maxburst = 64;
1599
1600         rx_param->dma_dev = &dma_dev->dev;
1601         tx_param->dma_dev = &dma_dev->dev;
1602
1603         dma->fn = intel_mid_dma_filter;
1604         dma->rx_param = rx_param;
1605         dma->tx_param = tx_param;
1606
1607         port->port.type = PORT_16750;
1608         port->port.flags |= UPF_FIXED_PORT | UPF_FIXED_TYPE;
1609         port->dma = dma;
1610
1611         return pci_default_setup(priv, board, port, idx);
1612 }
1613
1614 #define PCI_DEVICE_ID_INTEL_PNW_UART1   0x081b
1615 #define PCI_DEVICE_ID_INTEL_PNW_UART2   0x081c
1616 #define PCI_DEVICE_ID_INTEL_PNW_UART3   0x081d
1617
1618 static int pnw_serial_setup(struct serial_private *priv,
1619                             const struct pciserial_board *board,
1620                             struct uart_8250_port *port, int idx)
1621 {
1622         struct pci_dev *pdev = priv->dev;
1623         struct pci_dev *dma_dev;
1624         int index;
1625
1626         switch (pdev->device) {
1627         case PCI_DEVICE_ID_INTEL_PNW_UART1:
1628                 index = 0;
1629                 break;
1630         case PCI_DEVICE_ID_INTEL_PNW_UART2:
1631                 index = 1;
1632                 break;
1633         case PCI_DEVICE_ID_INTEL_PNW_UART3:
1634                 index = 2;
1635                 break;
1636         default:
1637                 return -EINVAL;
1638         }
1639
1640         dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 3));
1641
1642         port->port.set_termios = intel_mid_set_termios_50M;
1643
1644         return intel_mid_serial_setup(priv, board, port, idx, index, dma_dev);
1645 }
1646
1647 #define PCI_DEVICE_ID_INTEL_TNG_UART    0x1191
1648
1649 static int tng_serial_setup(struct serial_private *priv,
1650                             const struct pciserial_board *board,
1651                             struct uart_8250_port *port, int idx)
1652 {
1653         struct pci_dev *pdev = priv->dev;
1654         struct pci_dev *dma_dev;
1655         int index = PCI_FUNC(pdev->devfn);
1656
1657         /* Currently no support for HSU port0 */
1658         if (index-- == 0)
1659                 return -ENODEV;
1660
1661         dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(5, 0));
1662
1663         port->port.set_termios = intel_mid_set_termios_38_4M;
1664
1665         return intel_mid_serial_setup(priv, board, port, idx, index, dma_dev);
1666 }
1667
1668 static int
1669 pci_omegapci_setup(struct serial_private *priv,
1670                       const struct pciserial_board *board,
1671                       struct uart_8250_port *port, int idx)
1672 {
1673         return setup_port(priv, port, 2, idx * 8, 0);
1674 }
1675
1676 static int
1677 pci_brcm_trumanage_setup(struct serial_private *priv,
1678                          const struct pciserial_board *board,
1679                          struct uart_8250_port *port, int idx)
1680 {
1681         int ret = pci_default_setup(priv, board, port, idx);
1682
1683         port->port.type = PORT_BRCM_TRUMANAGE;
1684         port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1685         return ret;
1686 }
1687
1688 static int pci_fintek_setup(struct serial_private *priv,
1689                             const struct pciserial_board *board,
1690                             struct uart_8250_port *port, int idx)
1691 {
1692         struct pci_dev *pdev = priv->dev;
1693         u8 config_base;
1694         u16 iobase;
1695
1696         config_base = 0x40 + 0x08 * idx;
1697
1698         /* Get the io address from configuration space */
1699         pci_read_config_word(pdev, config_base + 4, &iobase);
1700
1701         dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%x", __func__, idx, iobase);
1702
1703         port->port.iotype = UPIO_PORT;
1704         port->port.iobase = iobase;
1705
1706         return 0;
1707 }
1708
1709 static int pci_fintek_init(struct pci_dev *dev)
1710 {
1711         unsigned long iobase;
1712         u32 max_port, i;
1713         u32 bar_data[3];
1714         u8 config_base;
1715
1716         switch (dev->device) {
1717         case 0x1104: /* 4 ports */
1718         case 0x1108: /* 8 ports */
1719                 max_port = dev->device & 0xff;
1720                 break;
1721         case 0x1112: /* 12 ports */
1722                 max_port = 12;
1723                 break;
1724         default:
1725                 return -EINVAL;
1726         }
1727
1728         /* Get the io address dispatch from the BIOS */
1729         pci_read_config_dword(dev, 0x24, &bar_data[0]);
1730         pci_read_config_dword(dev, 0x20, &bar_data[1]);
1731         pci_read_config_dword(dev, 0x1c, &bar_data[2]);
1732
1733         for (i = 0; i < max_port; ++i) {
1734                 /* UART0 configuration offset start from 0x40 */
1735                 config_base = 0x40 + 0x08 * i;
1736
1737                 /* Calculate Real IO Port */
1738                 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8;
1739
1740                 /* Enable UART I/O port */
1741                 pci_write_config_byte(dev, config_base + 0x00, 0x01);
1742
1743                 /* Select 128-byte FIFO and 8x FIFO threshold */
1744                 pci_write_config_byte(dev, config_base + 0x01, 0x33);
1745
1746                 /* LSB UART */
1747                 pci_write_config_byte(dev, config_base + 0x04,
1748                                 (u8)(iobase & 0xff));
1749
1750                 /* MSB UART */
1751                 pci_write_config_byte(dev, config_base + 0x05,
1752                                 (u8)((iobase & 0xff00) >> 8));
1753
1754                 pci_write_config_byte(dev, config_base + 0x06, dev->irq);
1755         }
1756
1757         return max_port;
1758 }
1759
1760 static int skip_tx_en_setup(struct serial_private *priv,
1761                         const struct pciserial_board *board,
1762                         struct uart_8250_port *port, int idx)
1763 {
1764         port->port.flags |= UPF_NO_TXEN_TEST;
1765         dev_dbg(&priv->dev->dev,
1766                 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1767                 priv->dev->vendor, priv->dev->device,
1768                 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
1769
1770         return pci_default_setup(priv, board, port, idx);
1771 }
1772
1773 static void kt_handle_break(struct uart_port *p)
1774 {
1775         struct uart_8250_port *up = up_to_u8250p(p);
1776         /*
1777          * On receipt of a BI, serial device in Intel ME (Intel
1778          * management engine) needs to have its fifos cleared for sane
1779          * SOL (Serial Over Lan) output.
1780          */
1781         serial8250_clear_and_reinit_fifos(up);
1782 }
1783
1784 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1785 {
1786         struct uart_8250_port *up = up_to_u8250p(p);
1787         unsigned int val;
1788
1789         /*
1790          * When the Intel ME (management engine) gets reset its serial
1791          * port registers could return 0 momentarily.  Functions like
1792          * serial8250_console_write, read and save the IER, perform
1793          * some operation and then restore it.  In order to avoid
1794          * setting IER register inadvertently to 0, if the value read
1795          * is 0, double check with ier value in uart_8250_port and use
1796          * that instead.  up->ier should be the same value as what is
1797          * currently configured.
1798          */
1799         val = inb(p->iobase + offset);
1800         if (offset == UART_IER) {
1801                 if (val == 0)
1802                         val = up->ier;
1803         }
1804         return val;
1805 }
1806
1807 static int kt_serial_setup(struct serial_private *priv,
1808                            const struct pciserial_board *board,
1809                            struct uart_8250_port *port, int idx)
1810 {
1811         port->port.flags |= UPF_BUG_THRE;
1812         port->port.serial_in = kt_serial_in;
1813         port->port.handle_break = kt_handle_break;
1814         return skip_tx_en_setup(priv, board, port, idx);
1815 }
1816
1817 static int pci_eg20t_init(struct pci_dev *dev)
1818 {
1819 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1820         return -ENODEV;
1821 #else
1822         return 0;
1823 #endif
1824 }
1825
1826 static int
1827 pci_xr17c154_setup(struct serial_private *priv,
1828                   const struct pciserial_board *board,
1829                   struct uart_8250_port *port, int idx)
1830 {
1831         port->port.flags |= UPF_EXAR_EFR;
1832         return pci_default_setup(priv, board, port, idx);
1833 }
1834
1835 static int
1836 pci_xr17v35x_setup(struct serial_private *priv,
1837                   const struct pciserial_board *board,
1838                   struct uart_8250_port *port, int idx)
1839 {
1840         u8 __iomem *p;
1841
1842         p = pci_ioremap_bar(priv->dev, 0);
1843         if (p == NULL)
1844                 return -ENOMEM;
1845
1846         port->port.flags |= UPF_EXAR_EFR;
1847
1848         /*
1849          * Setup Multipurpose Input/Output pins.
1850          */
1851         if (idx == 0) {
1852                 writeb(0x00, p + 0x8f); /*MPIOINT[7:0]*/
1853                 writeb(0x00, p + 0x90); /*MPIOLVL[7:0]*/
1854                 writeb(0x00, p + 0x91); /*MPIO3T[7:0]*/
1855                 writeb(0x00, p + 0x92); /*MPIOINV[7:0]*/
1856                 writeb(0x00, p + 0x93); /*MPIOSEL[7:0]*/
1857                 writeb(0x00, p + 0x94); /*MPIOOD[7:0]*/
1858                 writeb(0x00, p + 0x95); /*MPIOINT[15:8]*/
1859                 writeb(0x00, p + 0x96); /*MPIOLVL[15:8]*/
1860                 writeb(0x00, p + 0x97); /*MPIO3T[15:8]*/
1861                 writeb(0x00, p + 0x98); /*MPIOINV[15:8]*/
1862                 writeb(0x00, p + 0x99); /*MPIOSEL[15:8]*/
1863                 writeb(0x00, p + 0x9a); /*MPIOOD[15:8]*/
1864         }
1865         writeb(0x00, p + UART_EXAR_8XMODE);
1866         writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1867         writeb(128, p + UART_EXAR_TXTRG);
1868         writeb(128, p + UART_EXAR_RXTRG);
1869         iounmap(p);
1870
1871         return pci_default_setup(priv, board, port, idx);
1872 }
1873
1874 #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
1875 #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
1876 #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
1877 #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
1878
1879 static int
1880 pci_fastcom335_setup(struct serial_private *priv,
1881                   const struct pciserial_board *board,
1882                   struct uart_8250_port *port, int idx)
1883 {
1884         u8 __iomem *p;
1885
1886         p = pci_ioremap_bar(priv->dev, 0);
1887         if (p == NULL)
1888                 return -ENOMEM;
1889
1890         port->port.flags |= UPF_EXAR_EFR;
1891
1892         /*
1893          * Setup Multipurpose Input/Output pins.
1894          */
1895         if (idx == 0) {
1896                 switch (priv->dev->device) {
1897                 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
1898                 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
1899                         writeb(0x78, p + 0x90); /* MPIOLVL[7:0] */
1900                         writeb(0x00, p + 0x92); /* MPIOINV[7:0] */
1901                         writeb(0x00, p + 0x93); /* MPIOSEL[7:0] */
1902                         break;
1903                 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
1904                 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
1905                         writeb(0x00, p + 0x90); /* MPIOLVL[7:0] */
1906                         writeb(0xc0, p + 0x92); /* MPIOINV[7:0] */
1907                         writeb(0xc0, p + 0x93); /* MPIOSEL[7:0] */
1908                         break;
1909                 }
1910                 writeb(0x00, p + 0x8f); /* MPIOINT[7:0] */
1911                 writeb(0x00, p + 0x91); /* MPIO3T[7:0] */
1912                 writeb(0x00, p + 0x94); /* MPIOOD[7:0] */
1913         }
1914         writeb(0x00, p + UART_EXAR_8XMODE);
1915         writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1916         writeb(32, p + UART_EXAR_TXTRG);
1917         writeb(32, p + UART_EXAR_RXTRG);
1918         iounmap(p);
1919
1920         return pci_default_setup(priv, board, port, idx);
1921 }
1922
1923 static int
1924 pci_wch_ch353_setup(struct serial_private *priv,
1925                     const struct pciserial_board *board,
1926                     struct uart_8250_port *port, int idx)
1927 {
1928         port->port.flags |= UPF_FIXED_TYPE;
1929         port->port.type = PORT_16550A;
1930         return pci_default_setup(priv, board, port, idx);
1931 }
1932
1933 static int
1934 pci_wch_ch38x_setup(struct serial_private *priv,
1935                     const struct pciserial_board *board,
1936                     struct uart_8250_port *port, int idx)
1937 {
1938         port->port.flags |= UPF_FIXED_TYPE;
1939         port->port.type = PORT_16850;
1940         return pci_default_setup(priv, board, port, idx);
1941 }
1942
1943 #define PCI_VENDOR_ID_SBSMODULARIO      0x124B
1944 #define PCI_SUBVENDOR_ID_SBSMODULARIO   0x124B
1945 #define PCI_DEVICE_ID_OCTPRO            0x0001
1946 #define PCI_SUBDEVICE_ID_OCTPRO232      0x0108
1947 #define PCI_SUBDEVICE_ID_OCTPRO422      0x0208
1948 #define PCI_SUBDEVICE_ID_POCTAL232      0x0308
1949 #define PCI_SUBDEVICE_ID_POCTAL422      0x0408
1950 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00   0x2500
1951 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30   0x2530
1952 #define PCI_VENDOR_ID_ADVANTECH         0x13fe
1953 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1954 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1955 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
1956 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
1957 #define PCI_DEVICE_ID_TITAN_200I        0x8028
1958 #define PCI_DEVICE_ID_TITAN_400I        0x8048
1959 #define PCI_DEVICE_ID_TITAN_800I        0x8088
1960 #define PCI_DEVICE_ID_TITAN_800EH       0xA007
1961 #define PCI_DEVICE_ID_TITAN_800EHB      0xA008
1962 #define PCI_DEVICE_ID_TITAN_400EH       0xA009
1963 #define PCI_DEVICE_ID_TITAN_100E        0xA010
1964 #define PCI_DEVICE_ID_TITAN_200E        0xA012
1965 #define PCI_DEVICE_ID_TITAN_400E        0xA013
1966 #define PCI_DEVICE_ID_TITAN_800E        0xA014
1967 #define PCI_DEVICE_ID_TITAN_200EI       0xA016
1968 #define PCI_DEVICE_ID_TITAN_200EISI     0xA017
1969 #define PCI_DEVICE_ID_TITAN_200V3       0xA306
1970 #define PCI_DEVICE_ID_TITAN_400V3       0xA310
1971 #define PCI_DEVICE_ID_TITAN_410V3       0xA312
1972 #define PCI_DEVICE_ID_TITAN_800V3       0xA314
1973 #define PCI_DEVICE_ID_TITAN_800V3B      0xA315
1974 #define PCI_DEVICE_ID_OXSEMI_16PCI958   0x9538
1975 #define PCIE_DEVICE_ID_NEO_2_OX_IBM     0x00F6
1976 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA  0xc001
1977 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1978 #define PCI_VENDOR_ID_WCH               0x4348
1979 #define PCI_DEVICE_ID_WCH_CH352_2S      0x3253
1980 #define PCI_DEVICE_ID_WCH_CH353_4S      0x3453
1981 #define PCI_DEVICE_ID_WCH_CH353_2S1PF   0x5046
1982 #define PCI_DEVICE_ID_WCH_CH353_1S1P    0x5053
1983 #define PCI_DEVICE_ID_WCH_CH353_2S1P    0x7053
1984 #define PCI_VENDOR_ID_AGESTAR           0x5372
1985 #define PCI_DEVICE_ID_AGESTAR_9375      0x6872
1986 #define PCI_VENDOR_ID_ASIX              0x9710
1987 #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
1988 #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
1989 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
1990 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
1991 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
1992 #define PCI_DEVICE_ID_INTEL_QRK_UART    0x0936
1993
1994 #define PCI_VENDOR_ID_SUNIX             0x1fd4
1995 #define PCI_DEVICE_ID_SUNIX_1999        0x1999
1996
1997 #define PCIE_VENDOR_ID_WCH              0x1c00
1998 #define PCIE_DEVICE_ID_WCH_CH382_2S1P   0x3250
1999 #define PCIE_DEVICE_ID_WCH_CH384_4S     0x3470
2000
2001 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
2002 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
2003 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
2004
2005 /*
2006  * Master list of serial port init/setup/exit quirks.
2007  * This does not describe the general nature of the port.
2008  * (ie, baud base, number and location of ports, etc)
2009  *
2010  * This list is ordered alphabetically by vendor then device.
2011  * Specific entries must come before more generic entries.
2012  */
2013 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
2014         /*
2015         * ADDI-DATA GmbH communication cards <info@addi-data.com>
2016         */
2017         {
2018                 .vendor         = PCI_VENDOR_ID_AMCC,
2019                 .device         = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
2020                 .subvendor      = PCI_ANY_ID,
2021                 .subdevice      = PCI_ANY_ID,
2022                 .setup          = addidata_apci7800_setup,
2023         },
2024         /*
2025          * AFAVLAB cards - these may be called via parport_serial
2026          *  It is not clear whether this applies to all products.
2027          */
2028         {
2029                 .vendor         = PCI_VENDOR_ID_AFAVLAB,
2030                 .device         = PCI_ANY_ID,
2031                 .subvendor      = PCI_ANY_ID,
2032                 .subdevice      = PCI_ANY_ID,
2033                 .setup          = afavlab_setup,
2034         },
2035         /*
2036          * HP Diva
2037          */
2038         {
2039                 .vendor         = PCI_VENDOR_ID_HP,
2040                 .device         = PCI_DEVICE_ID_HP_DIVA,
2041                 .subvendor      = PCI_ANY_ID,
2042                 .subdevice      = PCI_ANY_ID,
2043                 .init           = pci_hp_diva_init,
2044                 .setup          = pci_hp_diva_setup,
2045         },
2046         /*
2047          * Intel
2048          */
2049         {
2050                 .vendor         = PCI_VENDOR_ID_INTEL,
2051                 .device         = PCI_DEVICE_ID_INTEL_80960_RP,
2052                 .subvendor      = 0xe4bf,
2053                 .subdevice      = PCI_ANY_ID,
2054                 .init           = pci_inteli960ni_init,
2055                 .setup          = pci_default_setup,
2056         },
2057         {
2058                 .vendor         = PCI_VENDOR_ID_INTEL,
2059                 .device         = PCI_DEVICE_ID_INTEL_8257X_SOL,
2060                 .subvendor      = PCI_ANY_ID,
2061                 .subdevice      = PCI_ANY_ID,
2062                 .setup          = skip_tx_en_setup,
2063         },
2064         {
2065                 .vendor         = PCI_VENDOR_ID_INTEL,
2066                 .device         = PCI_DEVICE_ID_INTEL_82573L_SOL,
2067                 .subvendor      = PCI_ANY_ID,
2068                 .subdevice      = PCI_ANY_ID,
2069                 .setup          = skip_tx_en_setup,
2070         },
2071         {
2072                 .vendor         = PCI_VENDOR_ID_INTEL,
2073                 .device         = PCI_DEVICE_ID_INTEL_82573E_SOL,
2074                 .subvendor      = PCI_ANY_ID,
2075                 .subdevice      = PCI_ANY_ID,
2076                 .setup          = skip_tx_en_setup,
2077         },
2078         {
2079                 .vendor         = PCI_VENDOR_ID_INTEL,
2080                 .device         = PCI_DEVICE_ID_INTEL_CE4100_UART,
2081                 .subvendor      = PCI_ANY_ID,
2082                 .subdevice      = PCI_ANY_ID,
2083                 .setup          = ce4100_serial_setup,
2084         },
2085         {
2086                 .vendor         = PCI_VENDOR_ID_INTEL,
2087                 .device         = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
2088                 .subvendor      = PCI_ANY_ID,
2089                 .subdevice      = PCI_ANY_ID,
2090                 .setup          = kt_serial_setup,
2091         },
2092         {
2093                 .vendor         = PCI_VENDOR_ID_INTEL,
2094                 .device         = PCI_DEVICE_ID_INTEL_BYT_UART1,
2095                 .subvendor      = PCI_ANY_ID,
2096                 .subdevice      = PCI_ANY_ID,
2097                 .setup          = byt_serial_setup,
2098         },
2099         {
2100                 .vendor         = PCI_VENDOR_ID_INTEL,
2101                 .device         = PCI_DEVICE_ID_INTEL_BYT_UART2,
2102                 .subvendor      = PCI_ANY_ID,
2103                 .subdevice      = PCI_ANY_ID,
2104                 .setup          = byt_serial_setup,
2105         },
2106         {
2107                 .vendor         = PCI_VENDOR_ID_INTEL,
2108                 .device         = PCI_DEVICE_ID_INTEL_PNW_UART1,
2109                 .subvendor      = PCI_ANY_ID,
2110                 .subdevice      = PCI_ANY_ID,
2111                 .setup          = pnw_serial_setup,
2112         },
2113         {
2114                 .vendor         = PCI_VENDOR_ID_INTEL,
2115                 .device         = PCI_DEVICE_ID_INTEL_PNW_UART2,
2116                 .subvendor      = PCI_ANY_ID,
2117                 .subdevice      = PCI_ANY_ID,
2118                 .setup          = pnw_serial_setup,
2119         },
2120         {
2121                 .vendor         = PCI_VENDOR_ID_INTEL,
2122                 .device         = PCI_DEVICE_ID_INTEL_PNW_UART3,
2123                 .subvendor      = PCI_ANY_ID,
2124                 .subdevice      = PCI_ANY_ID,
2125                 .setup          = pnw_serial_setup,
2126         },
2127         {
2128                 .vendor         = PCI_VENDOR_ID_INTEL,
2129                 .device         = PCI_DEVICE_ID_INTEL_TNG_UART,
2130                 .subvendor      = PCI_ANY_ID,
2131                 .subdevice      = PCI_ANY_ID,
2132                 .setup          = tng_serial_setup,
2133         },
2134         {
2135                 .vendor         = PCI_VENDOR_ID_INTEL,
2136                 .device         = PCI_DEVICE_ID_INTEL_BSW_UART1,
2137                 .subvendor      = PCI_ANY_ID,
2138                 .subdevice      = PCI_ANY_ID,
2139                 .setup          = byt_serial_setup,
2140         },
2141         {
2142                 .vendor         = PCI_VENDOR_ID_INTEL,
2143                 .device         = PCI_DEVICE_ID_INTEL_BSW_UART2,
2144                 .subvendor      = PCI_ANY_ID,
2145                 .subdevice      = PCI_ANY_ID,
2146                 .setup          = byt_serial_setup,
2147         },
2148         /*
2149          * ITE
2150          */
2151         {
2152                 .vendor         = PCI_VENDOR_ID_ITE,
2153                 .device         = PCI_DEVICE_ID_ITE_8872,
2154                 .subvendor      = PCI_ANY_ID,
2155                 .subdevice      = PCI_ANY_ID,
2156                 .init           = pci_ite887x_init,
2157                 .setup          = pci_default_setup,
2158                 .exit           = pci_ite887x_exit,
2159         },
2160         /*
2161          * National Instruments
2162          */
2163         {
2164                 .vendor         = PCI_VENDOR_ID_NI,
2165                 .device         = PCI_DEVICE_ID_NI_PCI23216,
2166                 .subvendor      = PCI_ANY_ID,
2167                 .subdevice      = PCI_ANY_ID,
2168                 .init           = pci_ni8420_init,
2169                 .setup          = pci_default_setup,
2170                 .exit           = pci_ni8420_exit,
2171         },
2172         {
2173                 .vendor         = PCI_VENDOR_ID_NI,
2174                 .device         = PCI_DEVICE_ID_NI_PCI2328,
2175                 .subvendor      = PCI_ANY_ID,
2176                 .subdevice      = PCI_ANY_ID,
2177                 .init           = pci_ni8420_init,
2178                 .setup          = pci_default_setup,
2179                 .exit           = pci_ni8420_exit,
2180         },
2181         {
2182                 .vendor         = PCI_VENDOR_ID_NI,
2183                 .device         = PCI_DEVICE_ID_NI_PCI2324,
2184                 .subvendor      = PCI_ANY_ID,
2185                 .subdevice      = PCI_ANY_ID,
2186                 .init           = pci_ni8420_init,
2187                 .setup          = pci_default_setup,
2188                 .exit           = pci_ni8420_exit,
2189         },
2190         {
2191                 .vendor         = PCI_VENDOR_ID_NI,
2192                 .device         = PCI_DEVICE_ID_NI_PCI2322,
2193                 .subvendor      = PCI_ANY_ID,
2194                 .subdevice      = PCI_ANY_ID,
2195                 .init           = pci_ni8420_init,
2196                 .setup          = pci_default_setup,
2197                 .exit           = pci_ni8420_exit,
2198         },
2199         {
2200                 .vendor         = PCI_VENDOR_ID_NI,
2201                 .device         = PCI_DEVICE_ID_NI_PCI2324I,
2202                 .subvendor      = PCI_ANY_ID,
2203                 .subdevice      = PCI_ANY_ID,
2204                 .init           = pci_ni8420_init,
2205                 .setup          = pci_default_setup,
2206                 .exit           = pci_ni8420_exit,
2207         },
2208         {
2209                 .vendor         = PCI_VENDOR_ID_NI,
2210                 .device         = PCI_DEVICE_ID_NI_PCI2322I,
2211                 .subvendor      = PCI_ANY_ID,
2212                 .subdevice      = PCI_ANY_ID,
2213                 .init           = pci_ni8420_init,
2214                 .setup          = pci_default_setup,
2215                 .exit           = pci_ni8420_exit,
2216         },
2217         {
2218                 .vendor         = PCI_VENDOR_ID_NI,
2219                 .device         = PCI_DEVICE_ID_NI_PXI8420_23216,
2220                 .subvendor      = PCI_ANY_ID,
2221                 .subdevice      = PCI_ANY_ID,
2222                 .init           = pci_ni8420_init,
2223                 .setup          = pci_default_setup,
2224                 .exit           = pci_ni8420_exit,
2225         },
2226         {
2227                 .vendor         = PCI_VENDOR_ID_NI,
2228                 .device         = PCI_DEVICE_ID_NI_PXI8420_2328,
2229                 .subvendor      = PCI_ANY_ID,
2230                 .subdevice      = PCI_ANY_ID,
2231                 .init           = pci_ni8420_init,
2232                 .setup          = pci_default_setup,
2233                 .exit           = pci_ni8420_exit,
2234         },
2235         {
2236                 .vendor         = PCI_VENDOR_ID_NI,
2237                 .device         = PCI_DEVICE_ID_NI_PXI8420_2324,
2238                 .subvendor      = PCI_ANY_ID,
2239                 .subdevice      = PCI_ANY_ID,
2240                 .init           = pci_ni8420_init,
2241                 .setup          = pci_default_setup,
2242                 .exit           = pci_ni8420_exit,
2243         },
2244         {
2245                 .vendor         = PCI_VENDOR_ID_NI,
2246                 .device         = PCI_DEVICE_ID_NI_PXI8420_2322,
2247                 .subvendor      = PCI_ANY_ID,
2248                 .subdevice      = PCI_ANY_ID,
2249                 .init           = pci_ni8420_init,
2250                 .setup          = pci_default_setup,
2251                 .exit           = pci_ni8420_exit,
2252         },
2253         {
2254                 .vendor         = PCI_VENDOR_ID_NI,
2255                 .device         = PCI_DEVICE_ID_NI_PXI8422_2324,
2256                 .subvendor      = PCI_ANY_ID,
2257                 .subdevice      = PCI_ANY_ID,
2258                 .init           = pci_ni8420_init,
2259                 .setup          = pci_default_setup,
2260                 .exit           = pci_ni8420_exit,
2261         },
2262         {
2263                 .vendor         = PCI_VENDOR_ID_NI,
2264                 .device         = PCI_DEVICE_ID_NI_PXI8422_2322,
2265                 .subvendor      = PCI_ANY_ID,
2266                 .subdevice      = PCI_ANY_ID,
2267                 .init           = pci_ni8420_init,
2268                 .setup          = pci_default_setup,
2269                 .exit           = pci_ni8420_exit,
2270         },
2271         {
2272                 .vendor         = PCI_VENDOR_ID_NI,
2273                 .device         = PCI_ANY_ID,
2274                 .subvendor      = PCI_ANY_ID,
2275                 .subdevice      = PCI_ANY_ID,
2276                 .init           = pci_ni8430_init,
2277                 .setup          = pci_ni8430_setup,
2278                 .exit           = pci_ni8430_exit,
2279         },
2280         /* Quatech */
2281         {
2282                 .vendor         = PCI_VENDOR_ID_QUATECH,
2283                 .device         = PCI_ANY_ID,
2284                 .subvendor      = PCI_ANY_ID,
2285                 .subdevice      = PCI_ANY_ID,
2286                 .init           = pci_quatech_init,
2287                 .setup          = pci_quatech_setup,
2288                 .exit           = pci_quatech_exit,
2289         },
2290         /*
2291          * Panacom
2292          */
2293         {
2294                 .vendor         = PCI_VENDOR_ID_PANACOM,
2295                 .device         = PCI_DEVICE_ID_PANACOM_QUADMODEM,
2296                 .subvendor      = PCI_ANY_ID,
2297                 .subdevice      = PCI_ANY_ID,
2298                 .init           = pci_plx9050_init,
2299                 .setup          = pci_default_setup,
2300                 .exit           = pci_plx9050_exit,
2301         },
2302         {
2303                 .vendor         = PCI_VENDOR_ID_PANACOM,
2304                 .device         = PCI_DEVICE_ID_PANACOM_DUALMODEM,
2305                 .subvendor      = PCI_ANY_ID,
2306                 .subdevice      = PCI_ANY_ID,
2307                 .init           = pci_plx9050_init,
2308                 .setup          = pci_default_setup,
2309                 .exit           = pci_plx9050_exit,
2310         },
2311         /*
2312          * Pericom
2313          */
2314         {
2315                 .vendor         = 0x12d8,
2316                 .device         = 0x7952,
2317                 .subvendor      = PCI_ANY_ID,
2318                 .subdevice      = PCI_ANY_ID,
2319                 .setup          = pci_pericom_setup,
2320         },
2321         {
2322                 .vendor         = 0x12d8,
2323                 .device         = 0x7954,
2324                 .subvendor      = PCI_ANY_ID,
2325                 .subdevice      = PCI_ANY_ID,
2326                 .setup          = pci_pericom_setup,
2327         },
2328         {
2329                 .vendor         = 0x12d8,
2330                 .device         = 0x7958,
2331                 .subvendor      = PCI_ANY_ID,
2332                 .subdevice      = PCI_ANY_ID,
2333                 .setup          = pci_pericom_setup,
2334         },
2335
2336         /*
2337          * PLX
2338          */
2339         {
2340                 .vendor         = PCI_VENDOR_ID_PLX,
2341                 .device         = PCI_DEVICE_ID_PLX_9050,
2342                 .subvendor      = PCI_SUBVENDOR_ID_EXSYS,
2343                 .subdevice      = PCI_SUBDEVICE_ID_EXSYS_4055,
2344                 .init           = pci_plx9050_init,
2345                 .setup          = pci_default_setup,
2346                 .exit           = pci_plx9050_exit,
2347         },
2348         {
2349                 .vendor         = PCI_VENDOR_ID_PLX,
2350                 .device         = PCI_DEVICE_ID_PLX_9050,
2351                 .subvendor      = PCI_SUBVENDOR_ID_KEYSPAN,
2352                 .subdevice      = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2353                 .init           = pci_plx9050_init,
2354                 .setup          = pci_default_setup,
2355                 .exit           = pci_plx9050_exit,
2356         },
2357         {
2358                 .vendor         = PCI_VENDOR_ID_PLX,
2359                 .device         = PCI_DEVICE_ID_PLX_ROMULUS,
2360                 .subvendor      = PCI_VENDOR_ID_PLX,
2361                 .subdevice      = PCI_DEVICE_ID_PLX_ROMULUS,
2362                 .init           = pci_plx9050_init,
2363                 .setup          = pci_default_setup,
2364                 .exit           = pci_plx9050_exit,
2365         },
2366         /*
2367          * SBS Technologies, Inc., PMC-OCTALPRO 232
2368          */
2369         {
2370                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2371                 .device         = PCI_DEVICE_ID_OCTPRO,
2372                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2373                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO232,
2374                 .init           = sbs_init,
2375                 .setup          = sbs_setup,
2376                 .exit           = sbs_exit,
2377         },
2378         /*
2379          * SBS Technologies, Inc., PMC-OCTALPRO 422
2380          */
2381         {
2382                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2383                 .device         = PCI_DEVICE_ID_OCTPRO,
2384                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2385                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO422,
2386                 .init           = sbs_init,
2387                 .setup          = sbs_setup,
2388                 .exit           = sbs_exit,
2389         },
2390         /*
2391          * SBS Technologies, Inc., P-Octal 232
2392          */
2393         {
2394                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2395                 .device         = PCI_DEVICE_ID_OCTPRO,
2396                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2397                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL232,
2398                 .init           = sbs_init,
2399                 .setup          = sbs_setup,
2400                 .exit           = sbs_exit,
2401         },
2402         /*
2403          * SBS Technologies, Inc., P-Octal 422
2404          */
2405         {
2406                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2407                 .device         = PCI_DEVICE_ID_OCTPRO,
2408                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2409                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL422,
2410                 .init           = sbs_init,
2411                 .setup          = sbs_setup,
2412                 .exit           = sbs_exit,
2413         },
2414         /*
2415          * SIIG cards - these may be called via parport_serial
2416          */
2417         {
2418                 .vendor         = PCI_VENDOR_ID_SIIG,
2419                 .device         = PCI_ANY_ID,
2420                 .subvendor      = PCI_ANY_ID,
2421                 .subdevice      = PCI_ANY_ID,
2422                 .init           = pci_siig_init,
2423                 .setup          = pci_siig_setup,
2424         },
2425         /*
2426          * Titan cards
2427          */
2428         {
2429                 .vendor         = PCI_VENDOR_ID_TITAN,
2430                 .device         = PCI_DEVICE_ID_TITAN_400L,
2431                 .subvendor      = PCI_ANY_ID,
2432                 .subdevice      = PCI_ANY_ID,
2433                 .setup          = titan_400l_800l_setup,
2434         },
2435         {
2436                 .vendor         = PCI_VENDOR_ID_TITAN,
2437                 .device         = PCI_DEVICE_ID_TITAN_800L,
2438                 .subvendor      = PCI_ANY_ID,
2439                 .subdevice      = PCI_ANY_ID,
2440                 .setup          = titan_400l_800l_setup,
2441         },
2442         /*
2443          * Timedia cards
2444          */
2445         {
2446                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
2447                 .device         = PCI_DEVICE_ID_TIMEDIA_1889,
2448                 .subvendor      = PCI_VENDOR_ID_TIMEDIA,
2449                 .subdevice      = PCI_ANY_ID,
2450                 .probe          = pci_timedia_probe,
2451                 .init           = pci_timedia_init,
2452                 .setup          = pci_timedia_setup,
2453         },
2454         {
2455                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
2456                 .device         = PCI_ANY_ID,
2457                 .subvendor      = PCI_ANY_ID,
2458                 .subdevice      = PCI_ANY_ID,
2459                 .setup          = pci_timedia_setup,
2460         },
2461         /*
2462          * SUNIX (Timedia) cards
2463          * Do not "probe" for these cards as there is at least one combination
2464          * card that should be handled by parport_pc that doesn't match the
2465          * rule in pci_timedia_probe.
2466          * It is part number is MIO5079A but its subdevice ID is 0x0102.
2467          * There are some boards with part number SER5037AL that report
2468          * subdevice ID 0x0002.
2469          */
2470         {
2471                 .vendor         = PCI_VENDOR_ID_SUNIX,
2472                 .device         = PCI_DEVICE_ID_SUNIX_1999,
2473                 .subvendor      = PCI_VENDOR_ID_SUNIX,
2474                 .subdevice      = PCI_ANY_ID,
2475                 .init           = pci_timedia_init,
2476                 .setup          = pci_timedia_setup,
2477         },
2478         /*
2479          * Exar cards
2480          */
2481         {
2482                 .vendor = PCI_VENDOR_ID_EXAR,
2483                 .device = PCI_DEVICE_ID_EXAR_XR17C152,
2484                 .subvendor      = PCI_ANY_ID,
2485                 .subdevice      = PCI_ANY_ID,
2486                 .setup          = pci_xr17c154_setup,
2487         },
2488         {
2489                 .vendor = PCI_VENDOR_ID_EXAR,
2490                 .device = PCI_DEVICE_ID_EXAR_XR17C154,
2491                 .subvendor      = PCI_ANY_ID,
2492                 .subdevice      = PCI_ANY_ID,
2493                 .setup          = pci_xr17c154_setup,
2494         },
2495         {
2496                 .vendor = PCI_VENDOR_ID_EXAR,
2497                 .device = PCI_DEVICE_ID_EXAR_XR17C158,
2498                 .subvendor      = PCI_ANY_ID,
2499                 .subdevice      = PCI_ANY_ID,
2500                 .setup          = pci_xr17c154_setup,
2501         },
2502         {
2503                 .vendor = PCI_VENDOR_ID_EXAR,
2504                 .device = PCI_DEVICE_ID_EXAR_XR17V352,
2505                 .subvendor      = PCI_ANY_ID,
2506                 .subdevice      = PCI_ANY_ID,
2507                 .setup          = pci_xr17v35x_setup,
2508         },
2509         {
2510                 .vendor = PCI_VENDOR_ID_EXAR,
2511                 .device = PCI_DEVICE_ID_EXAR_XR17V354,
2512                 .subvendor      = PCI_ANY_ID,
2513                 .subdevice      = PCI_ANY_ID,
2514                 .setup          = pci_xr17v35x_setup,
2515         },
2516         {
2517                 .vendor = PCI_VENDOR_ID_EXAR,
2518                 .device = PCI_DEVICE_ID_EXAR_XR17V358,
2519                 .subvendor      = PCI_ANY_ID,
2520                 .subdevice      = PCI_ANY_ID,
2521                 .setup          = pci_xr17v35x_setup,
2522         },
2523         /*
2524          * Xircom cards
2525          */
2526         {
2527                 .vendor         = PCI_VENDOR_ID_XIRCOM,
2528                 .device         = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2529                 .subvendor      = PCI_ANY_ID,
2530                 .subdevice      = PCI_ANY_ID,
2531                 .init           = pci_xircom_init,
2532                 .setup          = pci_default_setup,
2533         },
2534         /*
2535          * Netmos cards - these may be called via parport_serial
2536          */
2537         {
2538                 .vendor         = PCI_VENDOR_ID_NETMOS,
2539                 .device         = PCI_ANY_ID,
2540                 .subvendor      = PCI_ANY_ID,
2541                 .subdevice      = PCI_ANY_ID,
2542                 .init           = pci_netmos_init,
2543                 .setup          = pci_netmos_9900_setup,
2544         },
2545         /*
2546          * EndRun Technologies
2547         */
2548         {
2549                 .vendor         = PCI_VENDOR_ID_ENDRUN,
2550                 .device         = PCI_ANY_ID,
2551                 .subvendor      = PCI_ANY_ID,
2552                 .subdevice      = PCI_ANY_ID,
2553                 .init           = pci_endrun_init,
2554                 .setup          = pci_default_setup,
2555         },
2556         /*
2557          * For Oxford Semiconductor Tornado based devices
2558          */
2559         {
2560                 .vendor         = PCI_VENDOR_ID_OXSEMI,
2561                 .device         = PCI_ANY_ID,
2562                 .subvendor      = PCI_ANY_ID,
2563                 .subdevice      = PCI_ANY_ID,
2564                 .init           = pci_oxsemi_tornado_init,
2565                 .setup          = pci_default_setup,
2566         },
2567         {
2568                 .vendor         = PCI_VENDOR_ID_MAINPINE,
2569                 .device         = PCI_ANY_ID,
2570                 .subvendor      = PCI_ANY_ID,
2571                 .subdevice      = PCI_ANY_ID,
2572                 .init           = pci_oxsemi_tornado_init,
2573                 .setup          = pci_default_setup,
2574         },
2575         {
2576                 .vendor         = PCI_VENDOR_ID_DIGI,
2577                 .device         = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2578                 .subvendor              = PCI_SUBVENDOR_ID_IBM,
2579                 .subdevice              = PCI_ANY_ID,
2580                 .init                   = pci_oxsemi_tornado_init,
2581                 .setup          = pci_default_setup,
2582         },
2583         {
2584                 .vendor         = PCI_VENDOR_ID_INTEL,
2585                 .device         = 0x8811,
2586                 .subvendor      = PCI_ANY_ID,
2587                 .subdevice      = PCI_ANY_ID,
2588                 .init           = pci_eg20t_init,
2589                 .setup          = pci_default_setup,
2590         },
2591         {
2592                 .vendor         = PCI_VENDOR_ID_INTEL,
2593                 .device         = 0x8812,
2594                 .subvendor      = PCI_ANY_ID,
2595                 .subdevice      = PCI_ANY_ID,
2596                 .init           = pci_eg20t_init,
2597                 .setup          = pci_default_setup,
2598         },
2599         {
2600                 .vendor         = PCI_VENDOR_ID_INTEL,
2601                 .device         = 0x8813,
2602                 .subvendor      = PCI_ANY_ID,
2603                 .subdevice      = PCI_ANY_ID,
2604                 .init           = pci_eg20t_init,
2605                 .setup          = pci_default_setup,
2606         },
2607         {
2608                 .vendor         = PCI_VENDOR_ID_INTEL,
2609                 .device         = 0x8814,
2610                 .subvendor      = PCI_ANY_ID,
2611                 .subdevice      = PCI_ANY_ID,
2612                 .init           = pci_eg20t_init,
2613                 .setup          = pci_default_setup,
2614         },
2615         {
2616                 .vendor         = 0x10DB,
2617                 .device         = 0x8027,
2618                 .subvendor      = PCI_ANY_ID,
2619                 .subdevice      = PCI_ANY_ID,
2620                 .init           = pci_eg20t_init,
2621                 .setup          = pci_default_setup,
2622         },
2623         {
2624                 .vendor         = 0x10DB,
2625                 .device         = 0x8028,
2626                 .subvendor      = PCI_ANY_ID,
2627                 .subdevice      = PCI_ANY_ID,
2628                 .init           = pci_eg20t_init,
2629                 .setup          = pci_default_setup,
2630         },
2631         {
2632                 .vendor         = 0x10DB,
2633                 .device         = 0x8029,
2634                 .subvendor      = PCI_ANY_ID,
2635                 .subdevice      = PCI_ANY_ID,
2636                 .init           = pci_eg20t_init,
2637                 .setup          = pci_default_setup,
2638         },
2639         {
2640                 .vendor         = 0x10DB,
2641                 .device         = 0x800C,
2642                 .subvendor      = PCI_ANY_ID,
2643                 .subdevice      = PCI_ANY_ID,
2644                 .init           = pci_eg20t_init,
2645                 .setup          = pci_default_setup,
2646         },
2647         {
2648                 .vendor         = 0x10DB,
2649                 .device         = 0x800D,
2650                 .subvendor      = PCI_ANY_ID,
2651                 .subdevice      = PCI_ANY_ID,
2652                 .init           = pci_eg20t_init,
2653                 .setup          = pci_default_setup,
2654         },
2655         /*
2656          * Cronyx Omega PCI (PLX-chip based)
2657          */
2658         {
2659                 .vendor         = PCI_VENDOR_ID_PLX,
2660                 .device         = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2661                 .subvendor      = PCI_ANY_ID,
2662                 .subdevice      = PCI_ANY_ID,
2663                 .setup          = pci_omegapci_setup,
2664         },
2665         /* WCH CH353 1S1P card (16550 clone) */
2666         {
2667                 .vendor         = PCI_VENDOR_ID_WCH,
2668                 .device         = PCI_DEVICE_ID_WCH_CH353_1S1P,
2669                 .subvendor      = PCI_ANY_ID,
2670                 .subdevice      = PCI_ANY_ID,
2671                 .setup          = pci_wch_ch353_setup,
2672         },
2673         /* WCH CH353 2S1P card (16550 clone) */
2674         {
2675                 .vendor         = PCI_VENDOR_ID_WCH,
2676                 .device         = PCI_DEVICE_ID_WCH_CH353_2S1P,
2677                 .subvendor      = PCI_ANY_ID,
2678                 .subdevice      = PCI_ANY_ID,
2679                 .setup          = pci_wch_ch353_setup,
2680         },
2681         /* WCH CH353 4S card (16550 clone) */
2682         {
2683                 .vendor         = PCI_VENDOR_ID_WCH,
2684                 .device         = PCI_DEVICE_ID_WCH_CH353_4S,
2685                 .subvendor      = PCI_ANY_ID,
2686                 .subdevice      = PCI_ANY_ID,
2687                 .setup          = pci_wch_ch353_setup,
2688         },
2689         /* WCH CH353 2S1PF card (16550 clone) */
2690         {
2691                 .vendor         = PCI_VENDOR_ID_WCH,
2692                 .device         = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2693                 .subvendor      = PCI_ANY_ID,
2694                 .subdevice      = PCI_ANY_ID,
2695                 .setup          = pci_wch_ch353_setup,
2696         },
2697         /* WCH CH352 2S card (16550 clone) */
2698         {
2699                 .vendor         = PCI_VENDOR_ID_WCH,
2700                 .device         = PCI_DEVICE_ID_WCH_CH352_2S,
2701                 .subvendor      = PCI_ANY_ID,
2702                 .subdevice      = PCI_ANY_ID,
2703                 .setup          = pci_wch_ch353_setup,
2704         },
2705         /* WCH CH382 2S1P card (16850 clone) */
2706         {
2707                 .vendor         = PCIE_VENDOR_ID_WCH,
2708                 .device         = PCIE_DEVICE_ID_WCH_CH382_2S1P,
2709                 .subvendor      = PCI_ANY_ID,
2710                 .subdevice      = PCI_ANY_ID,
2711                 .setup          = pci_wch_ch38x_setup,
2712         },
2713         /* WCH CH384 4S card (16850 clone) */
2714         {
2715                 .vendor         = PCIE_VENDOR_ID_WCH,
2716                 .device         = PCIE_DEVICE_ID_WCH_CH384_4S,
2717                 .subvendor      = PCI_ANY_ID,
2718                 .subdevice      = PCI_ANY_ID,
2719                 .setup          = pci_wch_ch38x_setup,
2720         },
2721         /*
2722          * ASIX devices with FIFO bug
2723          */
2724         {
2725                 .vendor         = PCI_VENDOR_ID_ASIX,
2726                 .device         = PCI_ANY_ID,
2727                 .subvendor      = PCI_ANY_ID,
2728                 .subdevice      = PCI_ANY_ID,
2729                 .setup          = pci_asix_setup,
2730         },
2731         /*
2732          * Commtech, Inc. Fastcom adapters
2733          *
2734          */
2735         {
2736                 .vendor = PCI_VENDOR_ID_COMMTECH,
2737                 .device = PCI_DEVICE_ID_COMMTECH_4222PCI335,
2738                 .subvendor      = PCI_ANY_ID,
2739                 .subdevice      = PCI_ANY_ID,
2740                 .setup          = pci_fastcom335_setup,
2741         },
2742         {
2743                 .vendor = PCI_VENDOR_ID_COMMTECH,
2744                 .device = PCI_DEVICE_ID_COMMTECH_4224PCI335,
2745                 .subvendor      = PCI_ANY_ID,
2746                 .subdevice      = PCI_ANY_ID,
2747                 .setup          = pci_fastcom335_setup,
2748         },
2749         {
2750                 .vendor = PCI_VENDOR_ID_COMMTECH,
2751                 .device = PCI_DEVICE_ID_COMMTECH_2324PCI335,
2752                 .subvendor      = PCI_ANY_ID,
2753                 .subdevice      = PCI_ANY_ID,
2754                 .setup          = pci_fastcom335_setup,
2755         },
2756         {
2757                 .vendor = PCI_VENDOR_ID_COMMTECH,
2758                 .device = PCI_DEVICE_ID_COMMTECH_2328PCI335,
2759                 .subvendor      = PCI_ANY_ID,
2760                 .subdevice      = PCI_ANY_ID,
2761                 .setup          = pci_fastcom335_setup,
2762         },
2763         {
2764                 .vendor = PCI_VENDOR_ID_COMMTECH,
2765                 .device = PCI_DEVICE_ID_COMMTECH_4222PCIE,
2766                 .subvendor      = PCI_ANY_ID,
2767                 .subdevice      = PCI_ANY_ID,
2768                 .setup          = pci_xr17v35x_setup,
2769         },
2770         {
2771                 .vendor = PCI_VENDOR_ID_COMMTECH,
2772                 .device = PCI_DEVICE_ID_COMMTECH_4224PCIE,
2773                 .subvendor      = PCI_ANY_ID,
2774                 .subdevice      = PCI_ANY_ID,
2775                 .setup          = pci_xr17v35x_setup,
2776         },
2777         {
2778                 .vendor = PCI_VENDOR_ID_COMMTECH,
2779                 .device = PCI_DEVICE_ID_COMMTECH_4228PCIE,
2780                 .subvendor      = PCI_ANY_ID,
2781                 .subdevice      = PCI_ANY_ID,
2782                 .setup          = pci_xr17v35x_setup,
2783         },
2784         /*
2785          * Broadcom TruManage (NetXtreme)
2786          */
2787         {
2788                 .vendor         = PCI_VENDOR_ID_BROADCOM,
2789                 .device         = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2790                 .subvendor      = PCI_ANY_ID,
2791                 .subdevice      = PCI_ANY_ID,
2792                 .setup          = pci_brcm_trumanage_setup,
2793         },
2794         {
2795                 .vendor         = 0x1c29,
2796                 .device         = 0x1104,
2797                 .subvendor      = PCI_ANY_ID,
2798                 .subdevice      = PCI_ANY_ID,
2799                 .setup          = pci_fintek_setup,
2800                 .init           = pci_fintek_init,
2801         },
2802         {
2803                 .vendor         = 0x1c29,
2804                 .device         = 0x1108,
2805                 .subvendor      = PCI_ANY_ID,
2806                 .subdevice      = PCI_ANY_ID,
2807                 .setup          = pci_fintek_setup,
2808                 .init           = pci_fintek_init,
2809         },
2810         {
2811                 .vendor         = 0x1c29,
2812                 .device         = 0x1112,
2813                 .subvendor      = PCI_ANY_ID,
2814                 .subdevice      = PCI_ANY_ID,
2815                 .setup          = pci_fintek_setup,
2816                 .init           = pci_fintek_init,
2817         },
2818
2819         /*
2820          * Default "match everything" terminator entry
2821          */
2822         {
2823                 .vendor         = PCI_ANY_ID,
2824                 .device         = PCI_ANY_ID,
2825                 .subvendor      = PCI_ANY_ID,
2826                 .subdevice      = PCI_ANY_ID,
2827                 .setup          = pci_default_setup,
2828         }
2829 };
2830
2831 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2832 {
2833         return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2834 }
2835
2836 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2837 {
2838         struct pci_serial_quirk *quirk;
2839
2840         for (quirk = pci_serial_quirks; ; quirk++)
2841                 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2842                     quirk_id_matches(quirk->device, dev->device) &&
2843                     quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2844                     quirk_id_matches(quirk->subdevice, dev->subsystem_device))
2845                         break;
2846         return quirk;
2847 }
2848
2849 static inline int get_pci_irq(struct pci_dev *dev,
2850                                 const struct pciserial_board *board)
2851 {
2852         if (board->flags & FL_NOIRQ)
2853                 return 0;
2854         else
2855                 return dev->irq;
2856 }
2857
2858 /*
2859  * This is the configuration table for all of the PCI serial boards
2860  * which we support.  It is directly indexed by the pci_board_num_t enum
2861  * value, which is encoded in the pci_device_id PCI probe table's
2862  * driver_data member.
2863  *
2864  * The makeup of these names are:
2865  *  pbn_bn{_bt}_n_baud{_offsetinhex}
2866  *
2867  *  bn          = PCI BAR number
2868  *  bt          = Index using PCI BARs
2869  *  n           = number of serial ports
2870  *  baud        = baud rate
2871  *  offsetinhex = offset for each sequential port (in hex)
2872  *
2873  * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
2874  *
2875  * Please note: in theory if n = 1, _bt infix should make no difference.
2876  * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2877  */
2878 enum pci_board_num_t {
2879         pbn_default = 0,
2880
2881         pbn_b0_1_115200,
2882         pbn_b0_2_115200,
2883         pbn_b0_4_115200,
2884         pbn_b0_5_115200,
2885         pbn_b0_8_115200,
2886
2887         pbn_b0_1_921600,
2888         pbn_b0_2_921600,
2889         pbn_b0_4_921600,
2890
2891         pbn_b0_2_1130000,
2892
2893         pbn_b0_4_1152000,
2894
2895         pbn_b0_2_1152000_200,
2896         pbn_b0_4_1152000_200,
2897         pbn_b0_8_1152000_200,
2898
2899         pbn_b0_2_1843200,
2900         pbn_b0_4_1843200,
2901
2902         pbn_b0_2_1843200_200,
2903         pbn_b0_4_1843200_200,
2904         pbn_b0_8_1843200_200,
2905
2906         pbn_b0_1_4000000,
2907
2908         pbn_b0_bt_1_115200,
2909         pbn_b0_bt_2_115200,
2910         pbn_b0_bt_4_115200,
2911         pbn_b0_bt_8_115200,
2912
2913         pbn_b0_bt_1_460800,
2914         pbn_b0_bt_2_460800,
2915         pbn_b0_bt_4_460800,
2916
2917         pbn_b0_bt_1_921600,
2918         pbn_b0_bt_2_921600,
2919         pbn_b0_bt_4_921600,
2920         pbn_b0_bt_8_921600,
2921
2922         pbn_b1_1_115200,
2923         pbn_b1_2_115200,
2924         pbn_b1_4_115200,
2925         pbn_b1_8_115200,
2926         pbn_b1_16_115200,
2927
2928         pbn_b1_1_921600,
2929         pbn_b1_2_921600,
2930         pbn_b1_4_921600,
2931         pbn_b1_8_921600,
2932
2933         pbn_b1_2_1250000,
2934
2935         pbn_b1_bt_1_115200,
2936         pbn_b1_bt_2_115200,
2937         pbn_b1_bt_4_115200,
2938
2939         pbn_b1_bt_2_921600,
2940
2941         pbn_b1_1_1382400,
2942         pbn_b1_2_1382400,
2943         pbn_b1_4_1382400,
2944         pbn_b1_8_1382400,
2945
2946         pbn_b2_1_115200,
2947         pbn_b2_2_115200,
2948         pbn_b2_4_115200,
2949         pbn_b2_8_115200,
2950
2951         pbn_b2_1_460800,
2952         pbn_b2_4_460800,
2953         pbn_b2_8_460800,
2954         pbn_b2_16_460800,
2955
2956         pbn_b2_1_921600,
2957         pbn_b2_4_921600,
2958         pbn_b2_8_921600,
2959
2960         pbn_b2_8_1152000,
2961
2962         pbn_b2_bt_1_115200,
2963         pbn_b2_bt_2_115200,
2964         pbn_b2_bt_4_115200,
2965
2966         pbn_b2_bt_2_921600,
2967         pbn_b2_bt_4_921600,
2968
2969         pbn_b3_2_115200,
2970         pbn_b3_4_115200,
2971         pbn_b3_8_115200,
2972
2973         pbn_b4_bt_2_921600,
2974         pbn_b4_bt_4_921600,
2975         pbn_b4_bt_8_921600,
2976
2977         /*
2978          * Board-specific versions.
2979          */
2980         pbn_panacom,
2981         pbn_panacom2,
2982         pbn_panacom4,
2983         pbn_plx_romulus,
2984         pbn_endrun_2_4000000,
2985         pbn_oxsemi,
2986         pbn_oxsemi_1_4000000,
2987         pbn_oxsemi_2_4000000,
2988         pbn_oxsemi_4_4000000,
2989         pbn_oxsemi_8_4000000,
2990         pbn_intel_i960,
2991         pbn_sgi_ioc3,
2992         pbn_computone_4,
2993         pbn_computone_6,
2994         pbn_computone_8,
2995         pbn_sbsxrsio,
2996         pbn_exar_XR17C152,
2997         pbn_exar_XR17C154,
2998         pbn_exar_XR17C158,
2999         pbn_exar_XR17V352,
3000         pbn_exar_XR17V354,
3001         pbn_exar_XR17V358,
3002         pbn_exar_ibm_saturn,
3003         pbn_pasemi_1682M,
3004         pbn_ni8430_2,
3005         pbn_ni8430_4,
3006         pbn_ni8430_8,
3007         pbn_ni8430_16,
3008         pbn_ADDIDATA_PCIe_1_3906250,
3009         pbn_ADDIDATA_PCIe_2_3906250,
3010         pbn_ADDIDATA_PCIe_4_3906250,
3011         pbn_ADDIDATA_PCIe_8_3906250,
3012         pbn_ce4100_1_115200,
3013         pbn_byt,
3014         pbn_pnw,
3015         pbn_tng,
3016         pbn_qrk,
3017         pbn_omegapci,
3018         pbn_NETMOS9900_2s_115200,
3019         pbn_brcm_trumanage,
3020         pbn_fintek_4,
3021         pbn_fintek_8,
3022         pbn_fintek_12,
3023         pbn_wch384_4,
3024 };
3025
3026 /*
3027  * uart_offset - the space between channels
3028  * reg_shift   - describes how the UART registers are mapped
3029  *               to PCI memory by the card.
3030  * For example IER register on SBS, Inc. PMC-OctPro is located at
3031  * offset 0x10 from the UART base, while UART_IER is defined as 1
3032  * in include/linux/serial_reg.h,
3033  * see first lines of serial_in() and serial_out() in 8250.c
3034 */
3035
3036 static struct pciserial_board pci_boards[] = {
3037         [pbn_default] = {
3038                 .flags          = FL_BASE0,
3039                 .num_ports      = 1,
3040                 .base_baud      = 115200,
3041                 .uart_offset    = 8,
3042         },
3043         [pbn_b0_1_115200] = {
3044                 .flags          = FL_BASE0,
3045                 .num_ports      = 1,
3046                 .base_baud      = 115200,
3047                 .uart_offset    = 8,
3048         },
3049         [pbn_b0_2_115200] = {
3050                 .flags          = FL_BASE0,
3051                 .num_ports      = 2,
3052                 .base_baud      = 115200,
3053                 .uart_offset    = 8,
3054         },
3055         [pbn_b0_4_115200] = {
3056                 .flags          = FL_BASE0,
3057                 .num_ports      = 4,
3058                 .base_baud      = 115200,
3059                 .uart_offset    = 8,
3060         },
3061         [pbn_b0_5_115200] = {
3062                 .flags          = FL_BASE0,
3063                 .num_ports      = 5,
3064                 .base_baud      = 115200,
3065                 .uart_offset    = 8,
3066         },
3067         [pbn_b0_8_115200] = {
3068                 .flags          = FL_BASE0,
3069                 .num_ports      = 8,
3070                 .base_baud      = 115200,
3071                 .uart_offset    = 8,
3072         },
3073         [pbn_b0_1_921600] = {
3074                 .flags          = FL_BASE0,
3075                 .num_ports      = 1,
3076                 .base_baud      = 921600,
3077                 .uart_offset    = 8,
3078         },
3079         [pbn_b0_2_921600] = {
3080                 .flags          = FL_BASE0,
3081                 .num_ports      = 2,
3082                 .base_baud      = 921600,
3083                 .uart_offset    = 8,
3084         },
3085         [pbn_b0_4_921600] = {
3086                 .flags          = FL_BASE0,
3087                 .num_ports      = 4,
3088                 .base_baud      = 921600,
3089                 .uart_offset    = 8,
3090         },
3091
3092         [pbn_b0_2_1130000] = {
3093                 .flags          = FL_BASE0,
3094                 .num_ports      = 2,
3095                 .base_baud      = 1130000,
3096                 .uart_offset    = 8,
3097         },
3098
3099         [pbn_b0_4_1152000] = {
3100                 .flags          = FL_BASE0,
3101                 .num_ports      = 4,
3102                 .base_baud      = 1152000,
3103                 .uart_offset    = 8,
3104         },
3105
3106         [pbn_b0_2_1152000_200] = {
3107                 .flags          = FL_BASE0,
3108                 .num_ports      = 2,
3109                 .base_baud      = 1152000,
3110                 .uart_offset    = 0x200,
3111         },
3112
3113         [pbn_b0_4_1152000_200] = {
3114                 .flags          = FL_BASE0,
3115                 .num_ports      = 4,
3116                 .base_baud      = 1152000,
3117                 .uart_offset    = 0x200,
3118         },
3119
3120         [pbn_b0_8_1152000_200] = {
3121                 .flags          = FL_BASE0,
3122                 .num_ports      = 8,
3123                 .base_baud      = 1152000,
3124                 .uart_offset    = 0x200,
3125         },
3126
3127         [pbn_b0_2_1843200] = {
3128                 .flags          = FL_BASE0,
3129                 .num_ports      = 2,
3130                 .base_baud      = 1843200,
3131                 .uart_offset    = 8,
3132         },
3133         [pbn_b0_4_1843200] = {
3134                 .flags          = FL_BASE0,
3135                 .num_ports      = 4,
3136                 .base_baud      = 1843200,
3137                 .uart_offset    = 8,
3138         },
3139
3140         [pbn_b0_2_1843200_200] = {
3141                 .flags          = FL_BASE0,
3142                 .num_ports      = 2,
3143                 .base_baud      = 1843200,
3144                 .uart_offset    = 0x200,
3145         },
3146         [pbn_b0_4_1843200_200] = {
3147                 .flags          = FL_BASE0,
3148                 .num_ports      = 4,
3149                 .base_baud      = 1843200,
3150                 .uart_offset    = 0x200,
3151         },
3152         [pbn_b0_8_1843200_200] = {
3153                 .flags          = FL_BASE0,
3154                 .num_ports      = 8,
3155                 .base_baud      = 1843200,
3156                 .uart_offset    = 0x200,
3157         },
3158         [pbn_b0_1_4000000] = {
3159                 .flags          = FL_BASE0,
3160                 .num_ports      = 1,
3161                 .base_baud      = 4000000,
3162                 .uart_offset    = 8,
3163         },
3164
3165         [pbn_b0_bt_1_115200] = {
3166                 .flags          = FL_BASE0|FL_BASE_BARS,
3167                 .num_ports      = 1,
3168                 .base_baud      = 115200,
3169                 .uart_offset    = 8,
3170         },
3171         [pbn_b0_bt_2_115200] = {
3172                 .flags          = FL_BASE0|FL_BASE_BARS,
3173                 .num_ports      = 2,
3174                 .base_baud      = 115200,
3175                 .uart_offset    = 8,
3176         },
3177         [pbn_b0_bt_4_115200] = {
3178                 .flags          = FL_BASE0|FL_BASE_BARS,
3179                 .num_ports      = 4,
3180                 .base_baud      = 115200,
3181                 .uart_offset    = 8,
3182         },
3183         [pbn_b0_bt_8_115200] = {
3184                 .flags          = FL_BASE0|FL_BASE_BARS,
3185                 .num_ports      = 8,
3186                 .base_baud      = 115200,
3187                 .uart_offset    = 8,
3188         },
3189
3190         [pbn_b0_bt_1_460800] = {
3191                 .flags          = FL_BASE0|FL_BASE_BARS,
3192                 .num_ports      = 1,
3193                 .base_baud      = 460800,
3194                 .uart_offset    = 8,
3195         },
3196         [pbn_b0_bt_2_460800] = {
3197                 .flags          = FL_BASE0|FL_BASE_BARS,
3198                 .num_ports      = 2,
3199                 .base_baud      = 460800,
3200                 .uart_offset    = 8,
3201         },
3202         [pbn_b0_bt_4_460800] = {
3203                 .flags          = FL_BASE0|FL_BASE_BARS,
3204                 .num_ports      = 4,
3205                 .base_baud      = 460800,
3206                 .uart_offset    = 8,
3207         },
3208
3209         [pbn_b0_bt_1_921600] = {
3210                 .flags          = FL_BASE0|FL_BASE_BARS,
3211                 .num_ports      = 1,
3212                 .base_baud      = 921600,
3213                 .uart_offset    = 8,
3214         },
3215         [pbn_b0_bt_2_921600] = {
3216                 .flags          = FL_BASE0|FL_BASE_BARS,
3217                 .num_ports      = 2,
3218                 .base_baud      = 921600,
3219                 .uart_offset    = 8,
3220         },
3221         [pbn_b0_bt_4_921600] = {
3222                 .flags          = FL_BASE0|FL_BASE_BARS,
3223                 .num_ports      = 4,
3224                 .base_baud      = 921600,
3225                 .uart_offset    = 8,
3226         },
3227         [pbn_b0_bt_8_921600] = {
3228                 .flags          = FL_BASE0|FL_BASE_BARS,
3229                 .num_ports      = 8,
3230                 .base_baud      = 921600,
3231                 .uart_offset    = 8,
3232         },
3233
3234         [pbn_b1_1_115200] = {
3235                 .flags          = FL_BASE1,
3236                 .num_ports      = 1,
3237                 .base_baud      = 115200,
3238                 .uart_offset    = 8,
3239         },
3240         [pbn_b1_2_115200] = {
3241                 .flags          = FL_BASE1,
3242                 .num_ports      = 2,
3243                 .base_baud      = 115200,
3244                 .uart_offset    = 8,
3245         },
3246         [pbn_b1_4_115200] = {
3247                 .flags          = FL_BASE1,
3248                 .num_ports      = 4,
3249                 .base_baud      = 115200,
3250                 .uart_offset    = 8,
3251         },
3252         [pbn_b1_8_115200] = {
3253                 .flags          = FL_BASE1,
3254                 .num_ports      = 8,
3255                 .base_baud      = 115200,
3256                 .uart_offset    = 8,
3257         },
3258         [pbn_b1_16_115200] = {
3259                 .flags          = FL_BASE1,
3260                 .num_ports      = 16,
3261                 .base_baud      = 115200,
3262                 .uart_offset    = 8,
3263         },
3264
3265         [pbn_b1_1_921600] = {
3266                 .flags          = FL_BASE1,
3267                 .num_ports      = 1,
3268                 .base_baud      = 921600,
3269                 .uart_offset    = 8,
3270         },
3271         [pbn_b1_2_921600] = {
3272                 .flags          = FL_BASE1,
3273                 .num_ports      = 2,
3274                 .base_baud      = 921600,
3275                 .uart_offset    = 8,
3276         },
3277         [pbn_b1_4_921600] = {
3278                 .flags          = FL_BASE1,
3279                 .num_ports      = 4,
3280                 .base_baud      = 921600,
3281                 .uart_offset    = 8,
3282         },
3283         [pbn_b1_8_921600] = {
3284                 .flags          = FL_BASE1,
3285                 .num_ports      = 8,
3286                 .base_baud      = 921600,
3287                 .uart_offset    = 8,
3288         },
3289         [pbn_b1_2_1250000] = {
3290                 .flags          = FL_BASE1,
3291                 .num_ports      = 2,
3292                 .base_baud      = 1250000,
3293                 .uart_offset    = 8,
3294         },
3295
3296         [pbn_b1_bt_1_115200] = {
3297                 .flags          = FL_BASE1|FL_BASE_BARS,
3298                 .num_ports      = 1,
3299                 .base_baud      = 115200,
3300                 .uart_offset    = 8,
3301         },
3302         [pbn_b1_bt_2_115200] = {
3303                 .flags          = FL_BASE1|FL_BASE_BARS,
3304                 .num_ports      = 2,
3305                 .base_baud      = 115200,
3306                 .uart_offset    = 8,
3307         },
3308         [pbn_b1_bt_4_115200] = {
3309                 .flags          = FL_BASE1|FL_BASE_BARS,
3310                 .num_ports      = 4,
3311                 .base_baud      = 115200,
3312                 .uart_offset    = 8,
3313         },
3314
3315         [pbn_b1_bt_2_921600] = {
3316                 .flags          = FL_BASE1|FL_BASE_BARS,
3317                 .num_ports      = 2,
3318                 .base_baud      = 921600,
3319                 .uart_offset    = 8,
3320         },
3321
3322         [pbn_b1_1_1382400] = {
3323                 .flags          = FL_BASE1,
3324                 .num_ports      = 1,
3325                 .base_baud      = 1382400,
3326                 .uart_offset    = 8,
3327         },
3328         [pbn_b1_2_1382400] = {
3329                 .flags          = FL_BASE1,
3330                 .num_ports      = 2,
3331                 .base_baud      = 1382400,
3332                 .uart_offset    = 8,
3333         },
3334         [pbn_b1_4_1382400] = {
3335                 .flags          = FL_BASE1,
3336                 .num_ports      = 4,
3337                 .base_baud      = 1382400,
3338                 .uart_offset    = 8,
3339         },
3340         [pbn_b1_8_1382400] = {
3341                 .flags          = FL_BASE1,
3342                 .num_ports      = 8,
3343                 .base_baud      = 1382400,
3344                 .uart_offset    = 8,
3345         },
3346
3347         [pbn_b2_1_115200] = {
3348                 .flags          = FL_BASE2,
3349                 .num_ports      = 1,
3350                 .base_baud      = 115200,
3351                 .uart_offset    = 8,
3352         },
3353         [pbn_b2_2_115200] = {
3354                 .flags          = FL_BASE2,
3355                 .num_ports      = 2,
3356                 .base_baud      = 115200,
3357                 .uart_offset    = 8,
3358         },
3359         [pbn_b2_4_115200] = {
3360                 .flags          = FL_BASE2,
3361                 .num_ports      = 4,
3362                 .base_baud      = 115200,
3363                 .uart_offset    = 8,
3364         },
3365         [pbn_b2_8_115200] = {
3366                 .flags          = FL_BASE2,
3367                 .num_ports      = 8,
3368                 .base_baud      = 115200,
3369                 .uart_offset    = 8,
3370         },
3371
3372         [pbn_b2_1_460800] = {
3373                 .flags          = FL_BASE2,
3374                 .num_ports      = 1,
3375                 .base_baud      = 460800,
3376                 .uart_offset    = 8,
3377         },
3378         [pbn_b2_4_460800] = {
3379                 .flags          = FL_BASE2,
3380                 .num_ports      = 4,
3381                 .base_baud      = 460800,
3382                 .uart_offset    = 8,
3383         },
3384         [pbn_b2_8_460800] = {
3385                 .flags          = FL_BASE2,
3386                 .num_ports      = 8,
3387                 .base_baud      = 460800,
3388                 .uart_offset    = 8,
3389         },
3390         [pbn_b2_16_460800] = {
3391                 .flags          = FL_BASE2,
3392                 .num_ports      = 16,
3393                 .base_baud      = 460800,
3394                 .uart_offset    = 8,
3395          },
3396
3397         [pbn_b2_1_921600] = {
3398                 .flags          = FL_BASE2,
3399                 .num_ports      = 1,
3400                 .base_baud      = 921600,
3401                 .uart_offset    = 8,
3402         },
3403         [pbn_b2_4_921600] = {
3404                 .flags          = FL_BASE2,
3405                 .num_ports      = 4,
3406                 .base_baud      = 921600,
3407                 .uart_offset    = 8,
3408         },
3409         [pbn_b2_8_921600] = {
3410                 .flags          = FL_BASE2,
3411                 .num_ports      = 8,
3412                 .base_baud      = 921600,
3413                 .uart_offset    = 8,
3414         },
3415
3416         [pbn_b2_8_1152000] = {
3417                 .flags          = FL_BASE2,
3418                 .num_ports      = 8,
3419                 .base_baud      = 1152000,
3420                 .uart_offset    = 8,
3421         },
3422
3423         [pbn_b2_bt_1_115200] = {
3424                 .flags          = FL_BASE2|FL_BASE_BARS,
3425                 .num_ports      = 1,
3426                 .base_baud      = 115200,
3427                 .uart_offset    = 8,
3428         },
3429         [pbn_b2_bt_2_115200] = {
3430                 .flags          = FL_BASE2|FL_BASE_BARS,
3431                 .num_ports      = 2,
3432                 .base_baud      = 115200,
3433                 .uart_offset    = 8,
3434         },
3435         [pbn_b2_bt_4_115200] = {
3436                 .flags          = FL_BASE2|FL_BASE_BARS,
3437                 .num_ports      = 4,
3438                 .base_baud      = 115200,
3439                 .uart_offset    = 8,
3440         },
3441
3442         [pbn_b2_bt_2_921600] = {
3443                 .flags          = FL_BASE2|FL_BASE_BARS,
3444                 .num_ports      = 2,
3445                 .base_baud      = 921600,
3446                 .uart_offset    = 8,
3447         },
3448         [pbn_b2_bt_4_921600] = {
3449                 .flags          = FL_BASE2|FL_BASE_BARS,
3450                 .num_ports      = 4,
3451                 .base_baud      = 921600,
3452                 .uart_offset    = 8,
3453         },
3454
3455         [pbn_b3_2_115200] = {
3456                 .flags          = FL_BASE3,
3457                 .num_ports      = 2,
3458                 .base_baud      = 115200,
3459                 .uart_offset    = 8,
3460         },
3461         [pbn_b3_4_115200] = {
3462                 .flags          = FL_BASE3,
3463                 .num_ports      = 4,
3464                 .base_baud      = 115200,
3465                 .uart_offset    = 8,
3466         },
3467         [pbn_b3_8_115200] = {
3468                 .flags          = FL_BASE3,
3469                 .num_ports      = 8,
3470                 .base_baud      = 115200,
3471                 .uart_offset    = 8,
3472         },
3473
3474         [pbn_b4_bt_2_921600] = {
3475                 .flags          = FL_BASE4,
3476                 .num_ports      = 2,
3477                 .base_baud      = 921600,
3478                 .uart_offset    = 8,
3479         },
3480         [pbn_b4_bt_4_921600] = {
3481                 .flags          = FL_BASE4,
3482                 .num_ports      = 4,
3483                 .base_baud      = 921600,
3484                 .uart_offset    = 8,
3485         },
3486         [pbn_b4_bt_8_921600] = {
3487                 .flags          = FL_BASE4,
3488                 .num_ports      = 8,
3489                 .base_baud      = 921600,
3490                 .uart_offset    = 8,
3491         },
3492
3493         /*
3494          * Entries following this are board-specific.
3495          */
3496
3497         /*
3498          * Panacom - IOMEM
3499          */
3500         [pbn_panacom] = {
3501                 .flags          = FL_BASE2,
3502                 .num_ports      = 2,
3503                 .base_baud      = 921600,
3504                 .uart_offset    = 0x400,
3505                 .reg_shift      = 7,
3506         },
3507         [pbn_panacom2] = {
3508                 .flags          = FL_BASE2|FL_BASE_BARS,
3509                 .num_ports      = 2,
3510                 .base_baud      = 921600,
3511                 .uart_offset    = 0x400,
3512                 .reg_shift      = 7,
3513         },
3514         [pbn_panacom4] = {
3515                 .flags          = FL_BASE2|FL_BASE_BARS,
3516                 .num_ports      = 4,
3517                 .base_baud      = 921600,
3518                 .uart_offset    = 0x400,
3519                 .reg_shift      = 7,
3520         },
3521
3522         /* I think this entry is broken - the first_offset looks wrong --rmk */
3523         [pbn_plx_romulus] = {
3524                 .flags          = FL_BASE2,
3525                 .num_ports      = 4,
3526                 .base_baud      = 921600,
3527                 .uart_offset    = 8 << 2,
3528                 .reg_shift      = 2,
3529                 .first_offset   = 0x03,
3530         },
3531
3532         /*
3533          * EndRun Technologies
3534         * Uses the size of PCI Base region 0 to
3535         * signal now many ports are available
3536         * 2 port 952 Uart support
3537         */
3538         [pbn_endrun_2_4000000] = {
3539                 .flags          = FL_BASE0,
3540                 .num_ports      = 2,
3541                 .base_baud      = 4000000,
3542                 .uart_offset    = 0x200,
3543                 .first_offset   = 0x1000,
3544         },
3545
3546         /*
3547          * This board uses the size of PCI Base region 0 to
3548          * signal now many ports are available
3549          */
3550         [pbn_oxsemi] = {
3551                 .flags          = FL_BASE0|FL_REGION_SZ_CAP,
3552                 .num_ports      = 32,
3553                 .base_baud      = 115200,
3554                 .uart_offset    = 8,
3555         },
3556         [pbn_oxsemi_1_4000000] = {
3557                 .flags          = FL_BASE0,
3558                 .num_ports      = 1,
3559                 .base_baud      = 4000000,
3560                 .uart_offset    = 0x200,
3561                 .first_offset   = 0x1000,
3562         },
3563         [pbn_oxsemi_2_4000000] = {
3564                 .flags          = FL_BASE0,
3565                 .num_ports      = 2,
3566                 .base_baud      = 4000000,
3567                 .uart_offset    = 0x200,
3568                 .first_offset   = 0x1000,
3569         },
3570         [pbn_oxsemi_4_4000000] = {
3571                 .flags          = FL_BASE0,
3572                 .num_ports      = 4,
3573                 .base_baud      = 4000000,
3574                 .uart_offset    = 0x200,
3575                 .first_offset   = 0x1000,
3576         },
3577         [pbn_oxsemi_8_4000000] = {
3578                 .flags          = FL_BASE0,
3579                 .num_ports      = 8,
3580                 .base_baud      = 4000000,
3581                 .uart_offset    = 0x200,
3582                 .first_offset   = 0x1000,
3583         },
3584
3585
3586         /*
3587          * EKF addition for i960 Boards form EKF with serial port.
3588          * Max 256 ports.
3589          */
3590         [pbn_intel_i960] = {
3591                 .flags          = FL_BASE0,
3592                 .num_ports      = 32,
3593                 .base_baud      = 921600,
3594                 .uart_offset    = 8 << 2,
3595                 .reg_shift      = 2,
3596                 .first_offset   = 0x10000,
3597         },
3598         [pbn_sgi_ioc3] = {
3599                 .flags          = FL_BASE0|FL_NOIRQ,
3600                 .num_ports      = 1,
3601                 .base_baud      = 458333,
3602                 .uart_offset    = 8,
3603                 .reg_shift      = 0,
3604                 .first_offset   = 0x20178,
3605         },
3606
3607         /*
3608          * Computone - uses IOMEM.
3609          */
3610         [pbn_computone_4] = {
3611                 .flags          = FL_BASE0,
3612                 .num_ports      = 4,
3613                 .base_baud      = 921600,
3614                 .uart_offset    = 0x40,
3615                 .reg_shift      = 2,
3616                 .first_offset   = 0x200,
3617         },
3618         [pbn_computone_6] = {
3619                 .flags          = FL_BASE0,
3620                 .num_ports      = 6,
3621                 .base_baud      = 921600,
3622                 .uart_offset    = 0x40,
3623                 .reg_shift      = 2,
3624                 .first_offset   = 0x200,
3625         },
3626         [pbn_computone_8] = {
3627                 .flags          = FL_BASE0,
3628                 .num_ports      = 8,
3629                 .base_baud      = 921600,
3630                 .uart_offset    = 0x40,
3631                 .reg_shift      = 2,
3632                 .first_offset   = 0x200,
3633         },
3634         [pbn_sbsxrsio] = {
3635                 .flags          = FL_BASE0,
3636                 .num_ports      = 8,
3637                 .base_baud      = 460800,
3638                 .uart_offset    = 256,
3639                 .reg_shift      = 4,
3640         },
3641         /*
3642          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3643          *  Only basic 16550A support.
3644          *  XR17C15[24] are not tested, but they should work.
3645          */
3646         [pbn_exar_XR17C152] = {
3647                 .flags          = FL_BASE0,
3648                 .num_ports      = 2,
3649                 .base_baud      = 921600,
3650                 .uart_offset    = 0x200,
3651         },
3652         [pbn_exar_XR17C154] = {
3653                 .flags          = FL_BASE0,
3654                 .num_ports      = 4,
3655                 .base_baud      = 921600,
3656                 .uart_offset    = 0x200,
3657         },
3658         [pbn_exar_XR17C158] = {
3659                 .flags          = FL_BASE0,
3660                 .num_ports      = 8,
3661                 .base_baud      = 921600,
3662                 .uart_offset    = 0x200,
3663         },
3664         [pbn_exar_XR17V352] = {
3665                 .flags          = FL_BASE0,
3666                 .num_ports      = 2,
3667                 .base_baud      = 7812500,
3668                 .uart_offset    = 0x400,
3669                 .reg_shift      = 0,
3670                 .first_offset   = 0,
3671         },
3672         [pbn_exar_XR17V354] = {
3673                 .flags          = FL_BASE0,
3674                 .num_ports      = 4,
3675                 .base_baud      = 7812500,
3676                 .uart_offset    = 0x400,
3677                 .reg_shift      = 0,
3678                 .first_offset   = 0,
3679         },
3680         [pbn_exar_XR17V358] = {
3681                 .flags          = FL_BASE0,
3682                 .num_ports      = 8,
3683                 .base_baud      = 7812500,
3684                 .uart_offset    = 0x400,
3685                 .reg_shift      = 0,
3686                 .first_offset   = 0,
3687         },
3688         [pbn_exar_ibm_saturn] = {
3689                 .flags          = FL_BASE0,
3690                 .num_ports      = 1,
3691                 .base_baud      = 921600,
3692                 .uart_offset    = 0x200,
3693         },
3694
3695         /*
3696          * PA Semi PWRficient PA6T-1682M on-chip UART
3697          */
3698         [pbn_pasemi_1682M] = {
3699                 .flags          = FL_BASE0,
3700                 .num_ports      = 1,
3701                 .base_baud      = 8333333,
3702         },
3703         /*
3704          * National Instruments 843x
3705          */
3706         [pbn_ni8430_16] = {
3707                 .flags          = FL_BASE0,
3708                 .num_ports      = 16,
3709                 .base_baud      = 3686400,
3710                 .uart_offset    = 0x10,
3711                 .first_offset   = 0x800,
3712         },
3713         [pbn_ni8430_8] = {
3714                 .flags          = FL_BASE0,
3715                 .num_ports      = 8,
3716                 .base_baud      = 3686400,
3717                 .uart_offset    = 0x10,
3718                 .first_offset   = 0x800,
3719         },
3720         [pbn_ni8430_4] = {
3721                 .flags          = FL_BASE0,
3722                 .num_ports      = 4,
3723                 .base_baud      = 3686400,
3724                 .uart_offset    = 0x10,
3725                 .first_offset   = 0x800,
3726         },
3727         [pbn_ni8430_2] = {
3728                 .flags          = FL_BASE0,
3729                 .num_ports      = 2,
3730                 .base_baud      = 3686400,
3731                 .uart_offset    = 0x10,
3732                 .first_offset   = 0x800,
3733         },
3734         /*
3735          * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3736          */
3737         [pbn_ADDIDATA_PCIe_1_3906250] = {
3738                 .flags          = FL_BASE0,
3739                 .num_ports      = 1,
3740                 .base_baud      = 3906250,
3741                 .uart_offset    = 0x200,
3742                 .first_offset   = 0x1000,
3743         },
3744         [pbn_ADDIDATA_PCIe_2_3906250] = {
3745                 .flags          = FL_BASE0,
3746                 .num_ports      = 2,
3747                 .base_baud      = 3906250,
3748                 .uart_offset    = 0x200,
3749                 .first_offset   = 0x1000,
3750         },
3751         [pbn_ADDIDATA_PCIe_4_3906250] = {
3752                 .flags          = FL_BASE0,
3753                 .num_ports      = 4,
3754                 .base_baud      = 3906250,
3755                 .uart_offset    = 0x200,
3756                 .first_offset   = 0x1000,
3757         },
3758         [pbn_ADDIDATA_PCIe_8_3906250] = {
3759                 .flags          = FL_BASE0,
3760                 .num_ports      = 8,
3761                 .base_baud      = 3906250,
3762                 .uart_offset    = 0x200,
3763                 .first_offset   = 0x1000,
3764         },
3765         [pbn_ce4100_1_115200] = {
3766                 .flags          = FL_BASE_BARS,
3767                 .num_ports      = 2,
3768                 .base_baud      = 921600,
3769                 .reg_shift      = 2,
3770         },
3771         /*
3772          * Intel BayTrail HSUART reference clock is 44.2368 MHz at power-on,
3773          * but is overridden by byt_set_termios.
3774          */
3775         [pbn_byt] = {
3776                 .flags          = FL_BASE0,
3777                 .num_ports      = 1,
3778                 .base_baud      = 2764800,
3779                 .uart_offset    = 0x80,
3780                 .reg_shift      = 2,
3781         },
3782         [pbn_pnw] = {
3783                 .flags          = FL_BASE0,
3784                 .num_ports      = 1,
3785                 .base_baud      = 115200,
3786         },
3787         [pbn_tng] = {
3788                 .flags          = FL_BASE0,
3789                 .num_ports      = 1,
3790                 .base_baud      = 1843200,
3791         },
3792         [pbn_qrk] = {
3793                 .flags          = FL_BASE0,
3794                 .num_ports      = 1,
3795                 .base_baud      = 2764800,
3796                 .reg_shift      = 2,
3797         },
3798         [pbn_omegapci] = {
3799                 .flags          = FL_BASE0,
3800                 .num_ports      = 8,
3801                 .base_baud      = 115200,
3802                 .uart_offset    = 0x200,
3803         },
3804         [pbn_NETMOS9900_2s_115200] = {
3805                 .flags          = FL_BASE0,
3806                 .num_ports      = 2,
3807                 .base_baud      = 115200,
3808         },
3809         [pbn_brcm_trumanage] = {
3810                 .flags          = FL_BASE0,
3811                 .num_ports      = 1,
3812                 .reg_shift      = 2,
3813                 .base_baud      = 115200,
3814         },
3815         [pbn_fintek_4] = {
3816                 .num_ports      = 4,
3817                 .uart_offset    = 8,
3818                 .base_baud      = 115200,
3819                 .first_offset   = 0x40,
3820         },
3821         [pbn_fintek_8] = {
3822                 .num_ports      = 8,
3823                 .uart_offset    = 8,
3824                 .base_baud      = 115200,
3825                 .first_offset   = 0x40,
3826         },
3827         [pbn_fintek_12] = {
3828                 .num_ports      = 12,
3829                 .uart_offset    = 8,
3830                 .base_baud      = 115200,
3831                 .first_offset   = 0x40,
3832         },
3833
3834         [pbn_wch384_4] = {
3835                 .flags          = FL_BASE0,
3836                 .num_ports      = 4,
3837                 .base_baud      = 115200,
3838                 .uart_offset    = 8,
3839                 .first_offset   = 0xC0,
3840         },
3841 };
3842
3843 static const struct pci_device_id blacklist[] = {
3844         /* softmodems */
3845         { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3846         { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3847         { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3848
3849         /* multi-io cards handled by parport_serial */
3850         { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
3851         { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */
3852         { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */
3853         { PCI_DEVICE(0x1c00, 0x3470), }, /* WCH CH384 4S */
3854 };
3855
3856 /*
3857  * Given a complete unknown PCI device, try to use some heuristics to
3858  * guess what the configuration might be, based on the pitiful PCI
3859  * serial specs.  Returns 0 on success, 1 on failure.
3860  */
3861 static int
3862 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
3863 {
3864         const struct pci_device_id *bldev;
3865         int num_iomem, num_port, first_port = -1, i;
3866
3867         /*
3868          * If it is not a communications device or the programming
3869          * interface is greater than 6, give up.
3870          *
3871          * (Should we try to make guesses for multiport serial devices
3872          * later?)
3873          */
3874         if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3875              ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3876             (dev->class & 0xff) > 6)
3877                 return -ENODEV;
3878
3879         /*
3880          * Do not access blacklisted devices that are known not to
3881          * feature serial ports or are handled by other modules.
3882          */
3883         for (bldev = blacklist;
3884              bldev < blacklist + ARRAY_SIZE(blacklist);
3885              bldev++) {
3886                 if (dev->vendor == bldev->vendor &&
3887                     dev->device == bldev->device)
3888                         return -ENODEV;
3889         }
3890
3891         num_iomem = num_port = 0;
3892         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3893                 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3894                         num_port++;
3895                         if (first_port == -1)
3896                                 first_port = i;
3897                 }
3898                 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
3899                         num_iomem++;
3900         }
3901
3902         /*
3903          * If there is 1 or 0 iomem regions, and exactly one port,
3904          * use it.  We guess the number of ports based on the IO
3905          * region size.
3906          */
3907         if (num_iomem <= 1 && num_port == 1) {
3908                 board->flags = first_port;
3909                 board->num_ports = pci_resource_len(dev, first_port) / 8;
3910                 return 0;
3911         }
3912
3913         /*
3914          * Now guess if we've got a board which indexes by BARs.
3915          * Each IO BAR should be 8 bytes, and they should follow
3916          * consecutively.
3917          */
3918         first_port = -1;
3919         num_port = 0;
3920         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3921                 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3922                     pci_resource_len(dev, i) == 8 &&
3923                     (first_port == -1 || (first_port + num_port) == i)) {
3924                         num_port++;
3925                         if (first_port == -1)
3926                                 first_port = i;
3927                 }
3928         }
3929
3930         if (num_port > 1) {
3931                 board->flags = first_port | FL_BASE_BARS;
3932                 board->num_ports = num_port;
3933                 return 0;
3934         }
3935
3936         return -ENODEV;
3937 }
3938
3939 static inline int
3940 serial_pci_matches(const struct pciserial_board *board,
3941                    const struct pciserial_board *guessed)
3942 {
3943         return
3944             board->num_ports == guessed->num_ports &&
3945             board->base_baud == guessed->base_baud &&
3946             board->uart_offset == guessed->uart_offset &&
3947             board->reg_shift == guessed->reg_shift &&
3948             board->first_offset == guessed->first_offset;
3949 }
3950
3951 struct serial_private *
3952 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
3953 {
3954         struct uart_8250_port uart;
3955         struct serial_private *priv;
3956         struct pci_serial_quirk *quirk;
3957         int rc, nr_ports, i;
3958
3959         nr_ports = board->num_ports;
3960
3961         /*
3962          * Find an init and setup quirks.
3963          */
3964         quirk = find_quirk(dev);
3965
3966         /*
3967          * Run the new-style initialization function.
3968          * The initialization function returns:
3969          *  <0  - error
3970          *   0  - use board->num_ports
3971          *  >0  - number of ports
3972          */
3973         if (quirk->init) {
3974                 rc = quirk->init(dev);
3975                 if (rc < 0) {
3976                         priv = ERR_PTR(rc);
3977                         goto err_out;
3978                 }
3979                 if (rc)
3980                         nr_ports = rc;
3981         }
3982
3983         priv = kzalloc(sizeof(struct serial_private) +
3984                        sizeof(unsigned int) * nr_ports,
3985                        GFP_KERNEL);
3986         if (!priv) {
3987                 priv = ERR_PTR(-ENOMEM);
3988                 goto err_deinit;
3989         }
3990
3991         priv->dev = dev;
3992         priv->quirk = quirk;
3993
3994         memset(&uart, 0, sizeof(uart));
3995         uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
3996         uart.port.uartclk = board->base_baud * 16;
3997         uart.port.irq = get_pci_irq(dev, board);
3998         uart.port.dev = &dev->dev;
3999
4000         for (i = 0; i < nr_ports; i++) {
4001                 if (quirk->setup(priv, board, &uart, i))
4002                         break;
4003
4004                 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
4005                         uart.port.iobase, uart.port.irq, uart.port.iotype);
4006
4007                 priv->line[i] = serial8250_register_8250_port(&uart);
4008                 if (priv->line[i] < 0) {
4009                         dev_err(&dev->dev,
4010                                 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
4011                                 uart.port.iobase, uart.port.irq,
4012                                 uart.port.iotype, priv->line[i]);
4013                         break;
4014                 }
4015         }
4016         priv->nr = i;
4017         return priv;
4018
4019 err_deinit:
4020         if (quirk->exit)
4021                 quirk->exit(dev);
4022 err_out:
4023         return priv;
4024 }
4025 EXPORT_SYMBOL_GPL(pciserial_init_ports);
4026
4027 void pciserial_remove_ports(struct serial_private *priv)
4028 {
4029         struct pci_serial_quirk *quirk;
4030         int i;
4031
4032         for (i = 0; i < priv->nr; i++)
4033                 serial8250_unregister_port(priv->line[i]);
4034
4035         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
4036                 if (priv->remapped_bar[i])
4037                         iounmap(priv->remapped_bar[i]);
4038                 priv->remapped_bar[i] = NULL;
4039         }
4040
4041         /*
4042          * Find the exit quirks.
4043          */
4044         quirk = find_quirk(priv->dev);
4045         if (quirk->exit)
4046                 quirk->exit(priv->dev);
4047
4048         kfree(priv);
4049 }
4050 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
4051
4052 void pciserial_suspend_ports(struct serial_private *priv)
4053 {
4054         int i;
4055
4056         for (i = 0; i < priv->nr; i++)
4057                 if (priv->line[i] >= 0)
4058                         serial8250_suspend_port(priv->line[i]);
4059
4060         /*
4061          * Ensure that every init quirk is properly torn down
4062          */
4063         if (priv->quirk->exit)
4064                 priv->quirk->exit(priv->dev);
4065 }
4066 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
4067
4068 void pciserial_resume_ports(struct serial_private *priv)
4069 {
4070         int i;
4071
4072         /*
4073          * Ensure that the board is correctly configured.
4074          */
4075         if (priv->quirk->init)
4076                 priv->quirk->init(priv->dev);
4077
4078         for (i = 0; i < priv->nr; i++)
4079                 if (priv->line[i] >= 0)
4080                         serial8250_resume_port(priv->line[i]);
4081 }
4082 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
4083
4084 /*
4085  * Probe one serial board.  Unfortunately, there is no rhyme nor reason
4086  * to the arrangement of serial ports on a PCI card.
4087  */
4088 static int
4089 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
4090 {
4091         struct pci_serial_quirk *quirk;
4092         struct serial_private *priv;
4093         const struct pciserial_board *board;
4094         struct pciserial_board tmp;
4095         int rc;
4096
4097         quirk = find_quirk(dev);
4098         if (quirk->probe) {
4099                 rc = quirk->probe(dev);
4100                 if (rc)
4101                         return rc;
4102         }
4103
4104         if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
4105                 dev_err(&dev->dev, "invalid driver_data: %ld\n",
4106                         ent->driver_data);
4107                 return -EINVAL;
4108         }
4109
4110         board = &pci_boards[ent->driver_data];
4111
4112         rc = pci_enable_device(dev);
4113         pci_save_state(dev);
4114         if (rc)
4115                 return rc;
4116
4117         if (ent->driver_data == pbn_default) {
4118                 /*
4119                  * Use a copy of the pci_board entry for this;
4120                  * avoid changing entries in the table.
4121                  */
4122                 memcpy(&tmp, board, sizeof(struct pciserial_board));
4123                 board = &tmp;
4124
4125                 /*
4126                  * We matched one of our class entries.  Try to
4127                  * determine the parameters of this board.
4128                  */
4129                 rc = serial_pci_guess_board(dev, &tmp);
4130                 if (rc)
4131                         goto disable;
4132         } else {
4133                 /*
4134                  * We matched an explicit entry.  If we are able to
4135                  * detect this boards settings with our heuristic,
4136                  * then we no longer need this entry.
4137                  */
4138                 memcpy(&tmp, &pci_boards[pbn_default],
4139                        sizeof(struct pciserial_board));
4140                 rc = serial_pci_guess_board(dev, &tmp);
4141                 if (rc == 0 && serial_pci_matches(board, &tmp))
4142                         moan_device("Redundant entry in serial pci_table.",
4143                                     dev);
4144         }
4145
4146         priv = pciserial_init_ports(dev, board);
4147         if (!IS_ERR(priv)) {
4148                 pci_set_drvdata(dev, priv);
4149                 return 0;
4150         }
4151
4152         rc = PTR_ERR(priv);
4153
4154  disable:
4155         pci_disable_device(dev);
4156         return rc;
4157 }
4158
4159 static void pciserial_remove_one(struct pci_dev *dev)
4160 {
4161         struct serial_private *priv = pci_get_drvdata(dev);
4162
4163         pciserial_remove_ports(priv);
4164
4165         pci_disable_device(dev);
4166 }
4167
4168 #ifdef CONFIG_PM_SLEEP
4169 static int pciserial_suspend_one(struct device *dev)
4170 {
4171         struct pci_dev *pdev = to_pci_dev(dev);
4172         struct serial_private *priv = pci_get_drvdata(pdev);
4173
4174         if (priv)
4175                 pciserial_suspend_ports(priv);
4176
4177         return 0;
4178 }
4179
4180 static int pciserial_resume_one(struct device *dev)
4181 {
4182         struct pci_dev *pdev = to_pci_dev(dev);
4183         struct serial_private *priv = pci_get_drvdata(pdev);
4184         int err;
4185
4186         if (priv) {
4187                 /*
4188                  * The device may have been disabled.  Re-enable it.
4189                  */
4190                 err = pci_enable_device(pdev);
4191                 /* FIXME: We cannot simply error out here */
4192                 if (err)
4193                         dev_err(dev, "Unable to re-enable ports, trying to continue.\n");
4194                 pciserial_resume_ports(priv);
4195         }
4196         return 0;
4197 }
4198 #endif
4199
4200 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one,
4201                          pciserial_resume_one);
4202
4203 static struct pci_device_id serial_pci_tbl[] = {
4204         /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
4205         {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
4206                 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
4207                 pbn_b2_8_921600 },
4208         /* Advantech also use 0x3618 and 0xf618 */
4209         {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
4210                 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4211                 pbn_b0_4_921600 },
4212         {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
4213                 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4214                 pbn_b0_4_921600 },
4215         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4216                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4217                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4218                 pbn_b1_8_1382400 },
4219         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4220                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4221                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4222                 pbn_b1_4_1382400 },
4223         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4224                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4225                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4226                 pbn_b1_2_1382400 },
4227         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4228                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4229                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4230                 pbn_b1_8_1382400 },
4231         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4232                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4233                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4234                 pbn_b1_4_1382400 },
4235         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4236                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4237                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4238                 pbn_b1_2_1382400 },
4239         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4240                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4241                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
4242                 pbn_b1_8_921600 },
4243         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4244                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4245                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
4246                 pbn_b1_8_921600 },
4247         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4248                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4249                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
4250                 pbn_b1_4_921600 },
4251         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4252                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4253                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
4254                 pbn_b1_4_921600 },
4255         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4256                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4257                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
4258                 pbn_b1_2_921600 },
4259         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4260                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4261                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
4262                 pbn_b1_8_921600 },
4263         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4264                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4265                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
4266                 pbn_b1_8_921600 },
4267         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4268                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4269                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
4270                 pbn_b1_4_921600 },
4271         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4272                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4273                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
4274                 pbn_b1_2_1250000 },
4275         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4276                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4277                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
4278                 pbn_b0_2_1843200 },
4279         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4280                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4281                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
4282                 pbn_b0_4_1843200 },
4283         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4284                 PCI_VENDOR_ID_AFAVLAB,
4285                 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
4286                 pbn_b0_4_1152000 },
4287         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4288                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4289                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
4290                 pbn_b0_2_1843200_200 },
4291         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4292                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4293                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
4294                 pbn_b0_4_1843200_200 },
4295         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4296                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4297                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
4298                 pbn_b0_8_1843200_200 },
4299         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4300                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4301                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
4302                 pbn_b0_2_1843200_200 },
4303         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4304                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4305                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
4306                 pbn_b0_4_1843200_200 },
4307         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4308                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4309                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
4310                 pbn_b0_8_1843200_200 },
4311         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4312                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4313                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
4314                 pbn_b0_2_1843200_200 },
4315         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4316                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4317                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
4318                 pbn_b0_4_1843200_200 },
4319         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4320                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4321                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
4322                 pbn_b0_8_1843200_200 },
4323         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4324                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4325                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
4326                 pbn_b0_2_1843200_200 },
4327         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4328                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4329                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
4330                 pbn_b0_4_1843200_200 },
4331         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4332                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4333                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
4334                 pbn_b0_8_1843200_200 },
4335         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4336                 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
4337                 0, 0, pbn_exar_ibm_saturn },
4338
4339         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
4340                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4341                 pbn_b2_bt_1_115200 },
4342         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
4343                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4344                 pbn_b2_bt_2_115200 },
4345         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
4346                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4347                 pbn_b2_bt_4_115200 },
4348         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
4349                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4350                 pbn_b2_bt_2_115200 },
4351         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
4352                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4353                 pbn_b2_bt_4_115200 },
4354         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
4355                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4356                 pbn_b2_8_115200 },
4357         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
4358                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4359                 pbn_b2_8_460800 },
4360         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
4361                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4362                 pbn_b2_8_115200 },
4363
4364         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
4365                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4366                 pbn_b2_bt_2_115200 },
4367         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
4368                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4369                 pbn_b2_bt_2_921600 },
4370         /*
4371          * VScom SPCOM800, from sl@s.pl
4372          */
4373         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
4374                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4375                 pbn_b2_8_921600 },
4376         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
4377                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4378                 pbn_b2_4_921600 },
4379         /* Unknown card - subdevice 0x1584 */
4380         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4381                 PCI_VENDOR_ID_PLX,
4382                 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
4383                 pbn_b2_4_115200 },
4384         /* Unknown card - subdevice 0x1588 */
4385         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4386                 PCI_VENDOR_ID_PLX,
4387                 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4388                 pbn_b2_8_115200 },
4389         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4390                 PCI_SUBVENDOR_ID_KEYSPAN,
4391                 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4392                 pbn_panacom },
4393         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
4394                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4395                 pbn_panacom4 },
4396         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
4397                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4398                 pbn_panacom2 },
4399         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4400                 PCI_VENDOR_ID_ESDGMBH,
4401                 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4402                 pbn_b2_4_115200 },
4403         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4404                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4405                 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
4406                 pbn_b2_4_460800 },
4407         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4408                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4409                 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
4410                 pbn_b2_8_460800 },
4411         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4412                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4413                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
4414                 pbn_b2_16_460800 },
4415         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4416                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4417                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
4418                 pbn_b2_16_460800 },
4419         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4420                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4421                 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
4422                 pbn_b2_4_460800 },
4423         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4424                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4425                 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
4426                 pbn_b2_8_460800 },
4427         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4428                 PCI_SUBVENDOR_ID_EXSYS,
4429                 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
4430                 pbn_b2_4_115200 },
4431         /*
4432          * Megawolf Romulus PCI Serial Card, from Mike Hudson
4433          * (Exoray@isys.ca)
4434          */
4435         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4436                 0x10b5, 0x106a, 0, 0,
4437                 pbn_plx_romulus },
4438         /*
4439         * EndRun Technologies. PCI express device range.
4440         *    EndRun PTP/1588 has 2 Native UARTs.
4441         */
4442         {       PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
4443                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4444                 pbn_endrun_2_4000000 },
4445         /*
4446          * Quatech cards. These actually have configurable clocks but for
4447          * now we just use the default.
4448          *
4449          * 100 series are RS232, 200 series RS422,
4450          */
4451         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4452                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4453                 pbn_b1_4_115200 },
4454         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4455                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4456                 pbn_b1_2_115200 },
4457         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4458                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4459                 pbn_b2_2_115200 },
4460         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4461                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4462                 pbn_b1_2_115200 },
4463         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4464                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4465                 pbn_b2_2_115200 },
4466         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4467                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4468                 pbn_b1_4_115200 },
4469         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4470                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4471                 pbn_b1_8_115200 },
4472         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4473                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4474                 pbn_b1_8_115200 },
4475         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4476                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4477                 pbn_b1_4_115200 },
4478         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4479                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4480                 pbn_b1_2_115200 },
4481         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4482                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4483                 pbn_b1_4_115200 },
4484         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4485                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4486                 pbn_b1_2_115200 },
4487         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4488                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4489                 pbn_b2_4_115200 },
4490         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4491                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4492                 pbn_b2_2_115200 },
4493         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4494                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4495                 pbn_b2_1_115200 },
4496         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4497                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4498                 pbn_b2_4_115200 },
4499         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4500                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4501                 pbn_b2_2_115200 },
4502         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4503                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4504                 pbn_b2_1_115200 },
4505         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4506                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4507                 pbn_b0_8_115200 },
4508
4509         {       PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
4510                 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4511                 0, 0,
4512                 pbn_b0_4_921600 },
4513         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4514                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4515                 0, 0,
4516                 pbn_b0_4_1152000 },
4517         {       PCI_VENDOR_ID_OXSEMI, 0x9505,
4518                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4519                 pbn_b0_bt_2_921600 },
4520
4521                 /*
4522                  * The below card is a little controversial since it is the
4523                  * subject of a PCI vendor/device ID clash.  (See
4524                  * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4525                  * For now just used the hex ID 0x950a.
4526                  */
4527         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
4528                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4529                 0, 0, pbn_b0_2_115200 },
4530         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
4531                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4532                 0, 0, pbn_b0_2_115200 },
4533         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
4534                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4535                 pbn_b0_2_1130000 },
4536         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4537                 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4538                 pbn_b0_1_921600 },
4539         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4540                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4541                 pbn_b0_4_115200 },
4542         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4543                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4544                 pbn_b0_bt_2_921600 },
4545         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4546                 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
4547                 pbn_b2_8_1152000 },
4548
4549         /*
4550          * Oxford Semiconductor Inc. Tornado PCI express device range.
4551          */
4552         {       PCI_VENDOR_ID_OXSEMI, 0xc101,    /* OXPCIe952 1 Legacy UART */
4553                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4554                 pbn_b0_1_4000000 },
4555         {       PCI_VENDOR_ID_OXSEMI, 0xc105,    /* OXPCIe952 1 Legacy UART */
4556                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4557                 pbn_b0_1_4000000 },
4558         {       PCI_VENDOR_ID_OXSEMI, 0xc11b,    /* OXPCIe952 1 Native UART */
4559                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4560                 pbn_oxsemi_1_4000000 },
4561         {       PCI_VENDOR_ID_OXSEMI, 0xc11f,    /* OXPCIe952 1 Native UART */
4562                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4563                 pbn_oxsemi_1_4000000 },
4564         {       PCI_VENDOR_ID_OXSEMI, 0xc120,    /* OXPCIe952 1 Legacy UART */
4565                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4566                 pbn_b0_1_4000000 },
4567         {       PCI_VENDOR_ID_OXSEMI, 0xc124,    /* OXPCIe952 1 Legacy UART */
4568                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4569                 pbn_b0_1_4000000 },
4570         {       PCI_VENDOR_ID_OXSEMI, 0xc138,    /* OXPCIe952 1 Native UART */
4571                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4572                 pbn_oxsemi_1_4000000 },
4573         {       PCI_VENDOR_ID_OXSEMI, 0xc13d,    /* OXPCIe952 1 Native UART */
4574                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4575                 pbn_oxsemi_1_4000000 },
4576         {       PCI_VENDOR_ID_OXSEMI, 0xc140,    /* OXPCIe952 1 Legacy UART */
4577                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4578                 pbn_b0_1_4000000 },
4579         {       PCI_VENDOR_ID_OXSEMI, 0xc141,    /* OXPCIe952 1 Legacy UART */
4580                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4581                 pbn_b0_1_4000000 },
4582         {       PCI_VENDOR_ID_OXSEMI, 0xc144,    /* OXPCIe952 1 Legacy UART */
4583                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4584                 pbn_b0_1_4000000 },
4585         {       PCI_VENDOR_ID_OXSEMI, 0xc145,    /* OXPCIe952 1 Legacy UART */
4586                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4587                 pbn_b0_1_4000000 },
4588         {       PCI_VENDOR_ID_OXSEMI, 0xc158,    /* OXPCIe952 2 Native UART */
4589                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4590                 pbn_oxsemi_2_4000000 },
4591         {       PCI_VENDOR_ID_OXSEMI, 0xc15d,    /* OXPCIe952 2 Native UART */
4592                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4593                 pbn_oxsemi_2_4000000 },
4594         {       PCI_VENDOR_ID_OXSEMI, 0xc208,    /* OXPCIe954 4 Native UART */
4595                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4596                 pbn_oxsemi_4_4000000 },
4597         {       PCI_VENDOR_ID_OXSEMI, 0xc20d,    /* OXPCIe954 4 Native UART */
4598                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4599                 pbn_oxsemi_4_4000000 },
4600         {       PCI_VENDOR_ID_OXSEMI, 0xc308,    /* OXPCIe958 8 Native UART */
4601                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4602                 pbn_oxsemi_8_4000000 },
4603         {       PCI_VENDOR_ID_OXSEMI, 0xc30d,    /* OXPCIe958 8 Native UART */
4604                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4605                 pbn_oxsemi_8_4000000 },
4606         {       PCI_VENDOR_ID_OXSEMI, 0xc40b,    /* OXPCIe200 1 Native UART */
4607                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4608                 pbn_oxsemi_1_4000000 },
4609         {       PCI_VENDOR_ID_OXSEMI, 0xc40f,    /* OXPCIe200 1 Native UART */
4610                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4611                 pbn_oxsemi_1_4000000 },
4612         {       PCI_VENDOR_ID_OXSEMI, 0xc41b,    /* OXPCIe200 1 Native UART */
4613                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4614                 pbn_oxsemi_1_4000000 },
4615         {       PCI_VENDOR_ID_OXSEMI, 0xc41f,    /* OXPCIe200 1 Native UART */
4616                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4617                 pbn_oxsemi_1_4000000 },
4618         {       PCI_VENDOR_ID_OXSEMI, 0xc42b,    /* OXPCIe200 1 Native UART */
4619                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4620                 pbn_oxsemi_1_4000000 },
4621         {       PCI_VENDOR_ID_OXSEMI, 0xc42f,    /* OXPCIe200 1 Native UART */
4622                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4623                 pbn_oxsemi_1_4000000 },
4624         {       PCI_VENDOR_ID_OXSEMI, 0xc43b,    /* OXPCIe200 1 Native UART */
4625                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4626                 pbn_oxsemi_1_4000000 },
4627         {       PCI_VENDOR_ID_OXSEMI, 0xc43f,    /* OXPCIe200 1 Native UART */
4628                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4629                 pbn_oxsemi_1_4000000 },
4630         {       PCI_VENDOR_ID_OXSEMI, 0xc44b,    /* OXPCIe200 1 Native UART */
4631                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4632                 pbn_oxsemi_1_4000000 },
4633         {       PCI_VENDOR_ID_OXSEMI, 0xc44f,    /* OXPCIe200 1 Native UART */
4634                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4635                 pbn_oxsemi_1_4000000 },
4636         {       PCI_VENDOR_ID_OXSEMI, 0xc45b,    /* OXPCIe200 1 Native UART */
4637                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4638                 pbn_oxsemi_1_4000000 },
4639         {       PCI_VENDOR_ID_OXSEMI, 0xc45f,    /* OXPCIe200 1 Native UART */
4640                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4641                 pbn_oxsemi_1_4000000 },
4642         {       PCI_VENDOR_ID_OXSEMI, 0xc46b,    /* OXPCIe200 1 Native UART */
4643                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4644                 pbn_oxsemi_1_4000000 },
4645         {       PCI_VENDOR_ID_OXSEMI, 0xc46f,    /* OXPCIe200 1 Native UART */
4646                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4647                 pbn_oxsemi_1_4000000 },
4648         {       PCI_VENDOR_ID_OXSEMI, 0xc47b,    /* OXPCIe200 1 Native UART */
4649                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4650                 pbn_oxsemi_1_4000000 },
4651         {       PCI_VENDOR_ID_OXSEMI, 0xc47f,    /* OXPCIe200 1 Native UART */
4652                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4653                 pbn_oxsemi_1_4000000 },
4654         {       PCI_VENDOR_ID_OXSEMI, 0xc48b,    /* OXPCIe200 1 Native UART */
4655                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4656                 pbn_oxsemi_1_4000000 },
4657         {       PCI_VENDOR_ID_OXSEMI, 0xc48f,    /* OXPCIe200 1 Native UART */
4658                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4659                 pbn_oxsemi_1_4000000 },
4660         {       PCI_VENDOR_ID_OXSEMI, 0xc49b,    /* OXPCIe200 1 Native UART */
4661                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4662                 pbn_oxsemi_1_4000000 },
4663         {       PCI_VENDOR_ID_OXSEMI, 0xc49f,    /* OXPCIe200 1 Native UART */
4664                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4665                 pbn_oxsemi_1_4000000 },
4666         {       PCI_VENDOR_ID_OXSEMI, 0xc4ab,    /* OXPCIe200 1 Native UART */
4667                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4668                 pbn_oxsemi_1_4000000 },
4669         {       PCI_VENDOR_ID_OXSEMI, 0xc4af,    /* OXPCIe200 1 Native UART */
4670                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4671                 pbn_oxsemi_1_4000000 },
4672         {       PCI_VENDOR_ID_OXSEMI, 0xc4bb,    /* OXPCIe200 1 Native UART */
4673                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4674                 pbn_oxsemi_1_4000000 },
4675         {       PCI_VENDOR_ID_OXSEMI, 0xc4bf,    /* OXPCIe200 1 Native UART */
4676                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4677                 pbn_oxsemi_1_4000000 },
4678         {       PCI_VENDOR_ID_OXSEMI, 0xc4cb,    /* OXPCIe200 1 Native UART */
4679                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4680                 pbn_oxsemi_1_4000000 },
4681         {       PCI_VENDOR_ID_OXSEMI, 0xc4cf,    /* OXPCIe200 1 Native UART */
4682                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4683                 pbn_oxsemi_1_4000000 },
4684         /*
4685          * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4686          */
4687         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4688                 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4689                 pbn_oxsemi_1_4000000 },
4690         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4691                 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4692                 pbn_oxsemi_2_4000000 },
4693         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4694                 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4695                 pbn_oxsemi_4_4000000 },
4696         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4697                 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4698                 pbn_oxsemi_8_4000000 },
4699
4700         /*
4701          * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4702          */
4703         {       PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4704                 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4705                 pbn_oxsemi_2_4000000 },
4706
4707         /*
4708          * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4709          * from skokodyn@yahoo.com
4710          */
4711         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4712                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4713                 pbn_sbsxrsio },
4714         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4715                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4716                 pbn_sbsxrsio },
4717         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4718                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4719                 pbn_sbsxrsio },
4720         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4721                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4722                 pbn_sbsxrsio },
4723
4724         /*
4725          * Digitan DS560-558, from jimd@esoft.com
4726          */
4727         {       PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
4728                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4729                 pbn_b1_1_115200 },
4730
4731         /*
4732          * Titan Electronic cards
4733          *  The 400L and 800L have a custom setup quirk.
4734          */
4735         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
4736                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4737                 pbn_b0_1_921600 },
4738         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
4739                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4740                 pbn_b0_2_921600 },
4741         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
4742                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4743                 pbn_b0_4_921600 },
4744         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
4745                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4746                 pbn_b0_4_921600 },
4747         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4748                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4749                 pbn_b1_1_921600 },
4750         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4751                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4752                 pbn_b1_bt_2_921600 },
4753         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4754                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4755                 pbn_b0_bt_4_921600 },
4756         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4757                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4758                 pbn_b0_bt_8_921600 },
4759         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4760                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4761                 pbn_b4_bt_2_921600 },
4762         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4763                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4764                 pbn_b4_bt_4_921600 },
4765         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4766                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4767                 pbn_b4_bt_8_921600 },
4768         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4769                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4770                 pbn_b0_4_921600 },
4771         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4772                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4773                 pbn_b0_4_921600 },
4774         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4775                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4776                 pbn_b0_4_921600 },
4777         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4778                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4779                 pbn_oxsemi_1_4000000 },
4780         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4781                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4782                 pbn_oxsemi_2_4000000 },
4783         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4784                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4785                 pbn_oxsemi_4_4000000 },
4786         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4787                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4788                 pbn_oxsemi_8_4000000 },
4789         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4790                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4791                 pbn_oxsemi_2_4000000 },
4792         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4793                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4794                 pbn_oxsemi_2_4000000 },
4795         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4796                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4797                 pbn_b0_bt_2_921600 },
4798         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4799                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4800                 pbn_b0_4_921600 },
4801         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4802                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4803                 pbn_b0_4_921600 },
4804         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4805                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4806                 pbn_b0_4_921600 },
4807         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4808                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4809                 pbn_b0_4_921600 },
4810
4811         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4812                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4813                 pbn_b2_1_460800 },
4814         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4815                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4816                 pbn_b2_1_460800 },
4817         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4818                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4819                 pbn_b2_1_460800 },
4820         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4821                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4822                 pbn_b2_bt_2_921600 },
4823         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4824                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4825                 pbn_b2_bt_2_921600 },
4826         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4827                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4828                 pbn_b2_bt_2_921600 },
4829         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4830                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4831                 pbn_b2_bt_4_921600 },
4832         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4833                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4834                 pbn_b2_bt_4_921600 },
4835         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4836                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4837                 pbn_b2_bt_4_921600 },
4838         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4839                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4840                 pbn_b0_1_921600 },
4841         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4842                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4843                 pbn_b0_1_921600 },
4844         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4845                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4846                 pbn_b0_1_921600 },
4847         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4848                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4849                 pbn_b0_bt_2_921600 },
4850         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4851                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4852                 pbn_b0_bt_2_921600 },
4853         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4854                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4855                 pbn_b0_bt_2_921600 },
4856         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4857                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4858                 pbn_b0_bt_4_921600 },
4859         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4860                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4861                 pbn_b0_bt_4_921600 },
4862         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4863                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4864                 pbn_b0_bt_4_921600 },
4865         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4866                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4867                 pbn_b0_bt_8_921600 },
4868         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4869                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4870                 pbn_b0_bt_8_921600 },
4871         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4872                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4873                 pbn_b0_bt_8_921600 },
4874
4875         /*
4876          * Computone devices submitted by Doug McNash dmcnash@computone.com
4877          */
4878         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4879                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4880                 0, 0, pbn_computone_4 },
4881         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4882                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4883                 0, 0, pbn_computone_8 },
4884         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4885                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4886                 0, 0, pbn_computone_6 },
4887
4888         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4889                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4890                 pbn_oxsemi },
4891         {       PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4892                 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4893                 pbn_b0_bt_1_921600 },
4894
4895         /*
4896          * SUNIX (TIMEDIA)
4897          */
4898         {       PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4899                 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4900                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00,
4901                 pbn_b0_bt_1_921600 },
4902
4903         {       PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4904                 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4905                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4906                 pbn_b0_bt_1_921600 },
4907
4908         /*
4909          * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
4910          */
4911         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
4912                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4913                 pbn_b0_bt_8_115200 },
4914         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
4915                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4916                 pbn_b0_bt_8_115200 },
4917
4918         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
4919                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4920                 pbn_b0_bt_2_115200 },
4921         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
4922                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4923                 pbn_b0_bt_2_115200 },
4924         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
4925                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4926                 pbn_b0_bt_2_115200 },
4927         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
4928                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4929                 pbn_b0_bt_2_115200 },
4930         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
4931                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4932                 pbn_b0_bt_2_115200 },
4933         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
4934                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4935                 pbn_b0_bt_4_460800 },
4936         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
4937                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4938                 pbn_b0_bt_4_460800 },
4939         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
4940                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4941                 pbn_b0_bt_2_460800 },
4942         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
4943                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4944                 pbn_b0_bt_2_460800 },
4945         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
4946                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4947                 pbn_b0_bt_2_460800 },
4948         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
4949                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4950                 pbn_b0_bt_1_115200 },
4951         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
4952                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4953                 pbn_b0_bt_1_460800 },
4954
4955         /*
4956          * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
4957          * Cards are identified by their subsystem vendor IDs, which
4958          * (in hex) match the model number.
4959          *
4960          * Note that JC140x are RS422/485 cards which require ox950
4961          * ACR = 0x10, and as such are not currently fully supported.
4962          */
4963         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4964                 0x1204, 0x0004, 0, 0,
4965                 pbn_b0_4_921600 },
4966         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4967                 0x1208, 0x0004, 0, 0,
4968                 pbn_b0_4_921600 },
4969 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4970                 0x1402, 0x0002, 0, 0,
4971                 pbn_b0_2_921600 }, */
4972 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4973                 0x1404, 0x0004, 0, 0,
4974                 pbn_b0_4_921600 }, */
4975         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
4976                 0x1208, 0x0004, 0, 0,
4977                 pbn_b0_4_921600 },
4978
4979         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4980                 0x1204, 0x0004, 0, 0,
4981                 pbn_b0_4_921600 },
4982         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4983                 0x1208, 0x0004, 0, 0,
4984                 pbn_b0_4_921600 },
4985         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
4986                 0x1208, 0x0004, 0, 0,
4987                 pbn_b0_4_921600 },
4988         /*
4989          * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
4990          */
4991         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
4992                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4993                 pbn_b1_1_1382400 },
4994
4995         /*
4996          * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
4997          */
4998         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
4999                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5000                 pbn_b1_1_1382400 },
5001
5002         /*
5003          * RAStel 2 port modem, gerg@moreton.com.au
5004          */
5005         {       PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
5006                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5007                 pbn_b2_bt_2_115200 },
5008
5009         /*
5010          * EKF addition for i960 Boards form EKF with serial port
5011          */
5012         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
5013                 0xE4BF, PCI_ANY_ID, 0, 0,
5014                 pbn_intel_i960 },
5015
5016         /*
5017          * Xircom Cardbus/Ethernet combos
5018          */
5019         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
5020                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5021                 pbn_b0_1_115200 },
5022         /*
5023          * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
5024          */
5025         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
5026                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5027                 pbn_b0_1_115200 },
5028
5029         /*
5030          * Untested PCI modems, sent in from various folks...
5031          */
5032
5033         /*
5034          * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
5035          */
5036         {       PCI_VENDOR_ID_ROCKWELL, 0x1004,
5037                 0x1048, 0x1500, 0, 0,
5038                 pbn_b1_1_115200 },
5039
5040         {       PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
5041                 0xFF00, 0, 0, 0,
5042                 pbn_sgi_ioc3 },
5043
5044         /*
5045          * HP Diva card
5046          */
5047         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5048                 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
5049                 pbn_b1_1_115200 },
5050         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5051                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5052                 pbn_b0_5_115200 },
5053         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
5054                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5055                 pbn_b2_1_115200 },
5056
5057         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
5058                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5059                 pbn_b3_2_115200 },
5060         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
5061                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5062                 pbn_b3_4_115200 },
5063         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
5064                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5065                 pbn_b3_8_115200 },
5066
5067         /*
5068          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
5069          */
5070         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
5071                 PCI_ANY_ID, PCI_ANY_ID,
5072                 0,
5073                 0, pbn_exar_XR17C152 },
5074         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
5075                 PCI_ANY_ID, PCI_ANY_ID,
5076                 0,
5077                 0, pbn_exar_XR17C154 },
5078         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
5079                 PCI_ANY_ID, PCI_ANY_ID,
5080                 0,
5081                 0, pbn_exar_XR17C158 },
5082         /*
5083          * Exar Corp. XR17V35[248] Dual/Quad/Octal PCIe UARTs
5084          */
5085         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V352,
5086                 PCI_ANY_ID, PCI_ANY_ID,
5087                 0,
5088                 0, pbn_exar_XR17V352 },
5089         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V354,
5090                 PCI_ANY_ID, PCI_ANY_ID,
5091                 0,
5092                 0, pbn_exar_XR17V354 },
5093         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V358,
5094                 PCI_ANY_ID, PCI_ANY_ID,
5095                 0,
5096                 0, pbn_exar_XR17V358 },
5097
5098         /*
5099          * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
5100          */
5101         {       PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
5102                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5103                 pbn_b0_1_115200 },
5104         /*
5105          * ITE
5106          */
5107         {       PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
5108                 PCI_ANY_ID, PCI_ANY_ID,
5109                 0, 0,
5110                 pbn_b1_bt_1_115200 },
5111
5112         /*
5113          * IntaShield IS-200
5114          */
5115         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
5116                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,   /* 135a.0811 */
5117                 pbn_b2_2_115200 },
5118         /*
5119          * IntaShield IS-400
5120          */
5121         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
5122                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,    /* 135a.0dc0 */
5123                 pbn_b2_4_115200 },
5124         /*
5125          * Perle PCI-RAS cards
5126          */
5127         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5128                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
5129                 0, 0, pbn_b2_4_921600 },
5130         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5131                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
5132                 0, 0, pbn_b2_8_921600 },
5133
5134         /*
5135          * Mainpine series cards: Fairly standard layout but fools
5136          * parts of the autodetect in some cases and uses otherwise
5137          * unmatched communications subclasses in the PCI Express case
5138          */
5139
5140         {       /* RockForceDUO */
5141                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5142                 PCI_VENDOR_ID_MAINPINE, 0x0200,
5143                 0, 0, pbn_b0_2_115200 },
5144         {       /* RockForceQUATRO */
5145                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5146                 PCI_VENDOR_ID_MAINPINE, 0x0300,
5147                 0, 0, pbn_b0_4_115200 },
5148         {       /* RockForceDUO+ */
5149                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5150                 PCI_VENDOR_ID_MAINPINE, 0x0400,
5151                 0, 0, pbn_b0_2_115200 },
5152         {       /* RockForceQUATRO+ */
5153                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5154                 PCI_VENDOR_ID_MAINPINE, 0x0500,
5155                 0, 0, pbn_b0_4_115200 },
5156         {       /* RockForce+ */
5157                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5158                 PCI_VENDOR_ID_MAINPINE, 0x0600,
5159                 0, 0, pbn_b0_2_115200 },
5160         {       /* RockForce+ */
5161                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5162                 PCI_VENDOR_ID_MAINPINE, 0x0700,
5163                 0, 0, pbn_b0_4_115200 },
5164         {       /* RockForceOCTO+ */
5165                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5166                 PCI_VENDOR_ID_MAINPINE, 0x0800,
5167                 0, 0, pbn_b0_8_115200 },
5168         {       /* RockForceDUO+ */
5169                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5170                 PCI_VENDOR_ID_MAINPINE, 0x0C00,
5171                 0, 0, pbn_b0_2_115200 },
5172         {       /* RockForceQUARTRO+ */
5173                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5174                 PCI_VENDOR_ID_MAINPINE, 0x0D00,
5175                 0, 0, pbn_b0_4_115200 },
5176         {       /* RockForceOCTO+ */
5177                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5178                 PCI_VENDOR_ID_MAINPINE, 0x1D00,
5179                 0, 0, pbn_b0_8_115200 },
5180         {       /* RockForceD1 */
5181                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5182                 PCI_VENDOR_ID_MAINPINE, 0x2000,
5183                 0, 0, pbn_b0_1_115200 },
5184         {       /* RockForceF1 */
5185                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5186                 PCI_VENDOR_ID_MAINPINE, 0x2100,
5187                 0, 0, pbn_b0_1_115200 },
5188         {       /* RockForceD2 */
5189                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5190                 PCI_VENDOR_ID_MAINPINE, 0x2200,
5191                 0, 0, pbn_b0_2_115200 },
5192         {       /* RockForceF2 */
5193                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5194                 PCI_VENDOR_ID_MAINPINE, 0x2300,
5195                 0, 0, pbn_b0_2_115200 },
5196         {       /* RockForceD4 */
5197                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5198                 PCI_VENDOR_ID_MAINPINE, 0x2400,
5199                 0, 0, pbn_b0_4_115200 },
5200         {       /* RockForceF4 */
5201                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5202                 PCI_VENDOR_ID_MAINPINE, 0x2500,
5203                 0, 0, pbn_b0_4_115200 },
5204         {       /* RockForceD8 */
5205                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5206                 PCI_VENDOR_ID_MAINPINE, 0x2600,
5207                 0, 0, pbn_b0_8_115200 },
5208         {       /* RockForceF8 */
5209                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5210                 PCI_VENDOR_ID_MAINPINE, 0x2700,
5211                 0, 0, pbn_b0_8_115200 },
5212         {       /* IQ Express D1 */
5213                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5214                 PCI_VENDOR_ID_MAINPINE, 0x3000,
5215                 0, 0, pbn_b0_1_115200 },
5216         {       /* IQ Express F1 */
5217                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5218                 PCI_VENDOR_ID_MAINPINE, 0x3100,
5219                 0, 0, pbn_b0_1_115200 },
5220         {       /* IQ Express D2 */
5221                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5222                 PCI_VENDOR_ID_MAINPINE, 0x3200,
5223                 0, 0, pbn_b0_2_115200 },
5224         {       /* IQ Express F2 */
5225                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5226                 PCI_VENDOR_ID_MAINPINE, 0x3300,
5227                 0, 0, pbn_b0_2_115200 },
5228         {       /* IQ Express D4 */
5229                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5230                 PCI_VENDOR_ID_MAINPINE, 0x3400,
5231                 0, 0, pbn_b0_4_115200 },
5232         {       /* IQ Express F4 */
5233                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5234                 PCI_VENDOR_ID_MAINPINE, 0x3500,
5235                 0, 0, pbn_b0_4_115200 },
5236         {       /* IQ Express D8 */
5237                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5238                 PCI_VENDOR_ID_MAINPINE, 0x3C00,
5239                 0, 0, pbn_b0_8_115200 },
5240         {       /* IQ Express F8 */
5241                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5242                 PCI_VENDOR_ID_MAINPINE, 0x3D00,
5243                 0, 0, pbn_b0_8_115200 },
5244
5245
5246         /*
5247          * PA Semi PA6T-1682M on-chip UART
5248          */
5249         {       PCI_VENDOR_ID_PASEMI, 0xa004,
5250                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5251                 pbn_pasemi_1682M },
5252
5253         /*
5254          * National Instruments
5255          */
5256         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
5257                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5258                 pbn_b1_16_115200 },
5259         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
5260                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5261                 pbn_b1_8_115200 },
5262         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
5263                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5264                 pbn_b1_bt_4_115200 },
5265         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
5266                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5267                 pbn_b1_bt_2_115200 },
5268         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
5269                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5270                 pbn_b1_bt_4_115200 },
5271         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
5272                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5273                 pbn_b1_bt_2_115200 },
5274         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
5275                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5276                 pbn_b1_16_115200 },
5277         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
5278                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5279                 pbn_b1_8_115200 },
5280         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
5281                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5282                 pbn_b1_bt_4_115200 },
5283         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
5284                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5285                 pbn_b1_bt_2_115200 },
5286         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
5287                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5288                 pbn_b1_bt_4_115200 },
5289         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
5290                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5291                 pbn_b1_bt_2_115200 },
5292         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
5293                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5294                 pbn_ni8430_2 },
5295         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
5296                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5297                 pbn_ni8430_2 },
5298         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
5299                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5300                 pbn_ni8430_4 },
5301         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
5302                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5303                 pbn_ni8430_4 },
5304         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
5305                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5306                 pbn_ni8430_8 },
5307         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
5308                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5309                 pbn_ni8430_8 },
5310         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
5311                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5312                 pbn_ni8430_16 },
5313         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
5314                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5315                 pbn_ni8430_16 },
5316         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
5317                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5318                 pbn_ni8430_2 },
5319         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
5320                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5321                 pbn_ni8430_2 },
5322         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
5323                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5324                 pbn_ni8430_4 },
5325         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
5326                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5327                 pbn_ni8430_4 },
5328
5329         /*
5330         * ADDI-DATA GmbH communication cards <info@addi-data.com>
5331         */
5332         {       PCI_VENDOR_ID_ADDIDATA,
5333                 PCI_DEVICE_ID_ADDIDATA_APCI7500,
5334                 PCI_ANY_ID,
5335                 PCI_ANY_ID,
5336                 0,
5337                 0,
5338                 pbn_b0_4_115200 },
5339
5340         {       PCI_VENDOR_ID_ADDIDATA,
5341                 PCI_DEVICE_ID_ADDIDATA_APCI7420,
5342                 PCI_ANY_ID,
5343                 PCI_ANY_ID,
5344                 0,
5345                 0,
5346                 pbn_b0_2_115200 },
5347
5348         {       PCI_VENDOR_ID_ADDIDATA,
5349                 PCI_DEVICE_ID_ADDIDATA_APCI7300,
5350                 PCI_ANY_ID,
5351                 PCI_ANY_ID,
5352                 0,
5353                 0,
5354                 pbn_b0_1_115200 },
5355
5356         {       PCI_VENDOR_ID_AMCC,
5357                 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
5358                 PCI_ANY_ID,
5359                 PCI_ANY_ID,
5360                 0,
5361                 0,
5362                 pbn_b1_8_115200 },
5363
5364         {       PCI_VENDOR_ID_ADDIDATA,
5365                 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
5366                 PCI_ANY_ID,
5367                 PCI_ANY_ID,
5368                 0,
5369                 0,
5370                 pbn_b0_4_115200 },
5371
5372         {       PCI_VENDOR_ID_ADDIDATA,
5373                 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5374                 PCI_ANY_ID,
5375                 PCI_ANY_ID,
5376                 0,
5377                 0,
5378                 pbn_b0_2_115200 },
5379
5380         {       PCI_VENDOR_ID_ADDIDATA,
5381                 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5382                 PCI_ANY_ID,
5383                 PCI_ANY_ID,
5384                 0,
5385                 0,
5386                 pbn_b0_1_115200 },
5387
5388         {       PCI_VENDOR_ID_ADDIDATA,
5389                 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
5390                 PCI_ANY_ID,
5391                 PCI_ANY_ID,
5392                 0,
5393                 0,
5394                 pbn_b0_4_115200 },
5395
5396         {       PCI_VENDOR_ID_ADDIDATA,
5397                 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
5398                 PCI_ANY_ID,
5399                 PCI_ANY_ID,
5400                 0,
5401                 0,
5402                 pbn_b0_2_115200 },
5403
5404         {       PCI_VENDOR_ID_ADDIDATA,
5405                 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
5406                 PCI_ANY_ID,
5407                 PCI_ANY_ID,
5408                 0,
5409                 0,
5410                 pbn_b0_1_115200 },
5411
5412         {       PCI_VENDOR_ID_ADDIDATA,
5413                 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5414                 PCI_ANY_ID,
5415                 PCI_ANY_ID,
5416                 0,
5417                 0,
5418                 pbn_b0_8_115200 },
5419
5420         {       PCI_VENDOR_ID_ADDIDATA,
5421                 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5422                 PCI_ANY_ID,
5423                 PCI_ANY_ID,
5424                 0,
5425                 0,
5426                 pbn_ADDIDATA_PCIe_4_3906250 },
5427
5428         {       PCI_VENDOR_ID_ADDIDATA,
5429                 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5430                 PCI_ANY_ID,
5431                 PCI_ANY_ID,
5432                 0,
5433                 0,
5434                 pbn_ADDIDATA_PCIe_2_3906250 },
5435
5436         {       PCI_VENDOR_ID_ADDIDATA,
5437                 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5438                 PCI_ANY_ID,
5439                 PCI_ANY_ID,
5440                 0,
5441                 0,
5442                 pbn_ADDIDATA_PCIe_1_3906250 },
5443
5444         {       PCI_VENDOR_ID_ADDIDATA,
5445                 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5446                 PCI_ANY_ID,
5447                 PCI_ANY_ID,
5448                 0,
5449                 0,
5450                 pbn_ADDIDATA_PCIe_8_3906250 },
5451
5452         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5453                 PCI_VENDOR_ID_IBM, 0x0299,
5454                 0, 0, pbn_b0_bt_2_115200 },
5455
5456         /*
5457          * other NetMos 9835 devices are most likely handled by the
5458          * parport_serial driver, check drivers/parport/parport_serial.c
5459          * before adding them here.
5460          */
5461
5462         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5463                 0xA000, 0x1000,
5464                 0, 0, pbn_b0_1_115200 },
5465
5466         /* the 9901 is a rebranded 9912 */
5467         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5468                 0xA000, 0x1000,
5469                 0, 0, pbn_b0_1_115200 },
5470
5471         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5472                 0xA000, 0x1000,
5473                 0, 0, pbn_b0_1_115200 },
5474
5475         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5476                 0xA000, 0x1000,
5477                 0, 0, pbn_b0_1_115200 },
5478
5479         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5480                 0xA000, 0x1000,
5481                 0, 0, pbn_b0_1_115200 },
5482
5483         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5484                 0xA000, 0x3002,
5485                 0, 0, pbn_NETMOS9900_2s_115200 },
5486
5487         /*
5488          * Best Connectivity and Rosewill PCI Multi I/O cards
5489          */
5490
5491         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5492                 0xA000, 0x1000,
5493                 0, 0, pbn_b0_1_115200 },
5494
5495         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5496                 0xA000, 0x3002,
5497                 0, 0, pbn_b0_bt_2_115200 },
5498
5499         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5500                 0xA000, 0x3004,
5501                 0, 0, pbn_b0_bt_4_115200 },
5502         /* Intel CE4100 */
5503         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
5504                 PCI_ANY_ID,  PCI_ANY_ID, 0, 0,
5505                 pbn_ce4100_1_115200 },
5506         /* Intel BayTrail */
5507         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART1,
5508                 PCI_ANY_ID,  PCI_ANY_ID,
5509                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5510                 pbn_byt },
5511         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART2,
5512                 PCI_ANY_ID,  PCI_ANY_ID,
5513                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5514                 pbn_byt },
5515         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART1,
5516                 PCI_ANY_ID,  PCI_ANY_ID,
5517                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5518                 pbn_byt },
5519         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART2,
5520                 PCI_ANY_ID,  PCI_ANY_ID,
5521                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5522                 pbn_byt },
5523
5524         /*
5525          * Intel Penwell
5526          */
5527         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PNW_UART1,
5528                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5529                 pbn_pnw},
5530         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PNW_UART2,
5531                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5532                 pbn_pnw},
5533         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PNW_UART3,
5534                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5535                 pbn_pnw},
5536
5537         /*
5538          * Intel Tangier
5539          */
5540         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TNG_UART,
5541                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5542                 pbn_tng},
5543
5544         /*
5545          * Intel Quark x1000
5546          */
5547         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_UART,
5548                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5549                 pbn_qrk },
5550         /*
5551          * Cronyx Omega PCI
5552          */
5553         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
5554                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5555                 pbn_omegapci },
5556
5557         /*
5558          * Broadcom TruManage
5559          */
5560         {       PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
5561                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5562                 pbn_brcm_trumanage },
5563
5564         /*
5565          * AgeStar as-prs2-009
5566          */
5567         {       PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
5568                 PCI_ANY_ID, PCI_ANY_ID,
5569                 0, 0, pbn_b0_bt_2_115200 },
5570
5571         /*
5572          * WCH CH353 series devices: The 2S1P is handled by parport_serial
5573          * so not listed here.
5574          */
5575         {       PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
5576                 PCI_ANY_ID, PCI_ANY_ID,
5577                 0, 0, pbn_b0_bt_4_115200 },
5578
5579         {       PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
5580                 PCI_ANY_ID, PCI_ANY_ID,
5581                 0, 0, pbn_b0_bt_2_115200 },
5582
5583         {       PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S,
5584                 PCI_ANY_ID, PCI_ANY_ID,
5585                 0, 0, pbn_wch384_4 },
5586
5587         /*
5588          * Commtech, Inc. Fastcom adapters
5589          */
5590         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCI335,
5591                 PCI_ANY_ID, PCI_ANY_ID,
5592                 0,
5593                 0, pbn_b0_2_1152000_200 },
5594         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCI335,
5595                 PCI_ANY_ID, PCI_ANY_ID,
5596                 0,
5597                 0, pbn_b0_4_1152000_200 },
5598         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2324PCI335,
5599                 PCI_ANY_ID, PCI_ANY_ID,
5600                 0,
5601                 0, pbn_b0_4_1152000_200 },
5602         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2328PCI335,
5603                 PCI_ANY_ID, PCI_ANY_ID,
5604                 0,
5605                 0, pbn_b0_8_1152000_200 },
5606         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCIE,
5607                 PCI_ANY_ID, PCI_ANY_ID,
5608                 0,
5609                 0, pbn_exar_XR17V352 },
5610         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCIE,
5611                 PCI_ANY_ID, PCI_ANY_ID,
5612                 0,
5613                 0, pbn_exar_XR17V354 },
5614         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4228PCIE,
5615                 PCI_ANY_ID, PCI_ANY_ID,
5616                 0,
5617                 0, pbn_exar_XR17V358 },
5618
5619         /* Fintek PCI serial cards */
5620         { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
5621         { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
5622         { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
5623
5624         /*
5625          * These entries match devices with class COMMUNICATION_SERIAL,
5626          * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
5627          */
5628         {       PCI_ANY_ID, PCI_ANY_ID,
5629                 PCI_ANY_ID, PCI_ANY_ID,
5630                 PCI_CLASS_COMMUNICATION_SERIAL << 8,
5631                 0xffff00, pbn_default },
5632         {       PCI_ANY_ID, PCI_ANY_ID,
5633                 PCI_ANY_ID, PCI_ANY_ID,
5634                 PCI_CLASS_COMMUNICATION_MODEM << 8,
5635                 0xffff00, pbn_default },
5636         {       PCI_ANY_ID, PCI_ANY_ID,
5637                 PCI_ANY_ID, PCI_ANY_ID,
5638                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
5639                 0xffff00, pbn_default },
5640         { 0, }
5641 };
5642
5643 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
5644                                                 pci_channel_state_t state)
5645 {
5646         struct serial_private *priv = pci_get_drvdata(dev);
5647
5648         if (state == pci_channel_io_perm_failure)
5649                 return PCI_ERS_RESULT_DISCONNECT;
5650
5651         if (priv)
5652                 pciserial_suspend_ports(priv);
5653
5654         pci_disable_device(dev);
5655
5656         return PCI_ERS_RESULT_NEED_RESET;
5657 }
5658
5659 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
5660 {
5661         int rc;
5662
5663         rc = pci_enable_device(dev);
5664
5665         if (rc)
5666                 return PCI_ERS_RESULT_DISCONNECT;
5667
5668         pci_restore_state(dev);
5669         pci_save_state(dev);
5670
5671         return PCI_ERS_RESULT_RECOVERED;
5672 }
5673
5674 static void serial8250_io_resume(struct pci_dev *dev)
5675 {
5676         struct serial_private *priv = pci_get_drvdata(dev);
5677
5678         if (priv)
5679                 pciserial_resume_ports(priv);
5680 }
5681
5682 static const struct pci_error_handlers serial8250_err_handler = {
5683         .error_detected = serial8250_io_error_detected,
5684         .slot_reset = serial8250_io_slot_reset,
5685         .resume = serial8250_io_resume,
5686 };
5687
5688 static struct pci_driver serial_pci_driver = {
5689         .name           = "serial",
5690         .probe          = pciserial_init_one,
5691         .remove         = pciserial_remove_one,
5692         .driver         = {
5693                 .pm     = &pciserial_pm_ops,
5694         },
5695         .id_table       = serial_pci_tbl,
5696         .err_handler    = &serial8250_err_handler,
5697 };
5698
5699 module_pci_driver(serial_pci_driver);
5700
5701 MODULE_LICENSE("GPL");
5702 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
5703 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);