drivers/spi/spi-ti-qspi.c

   1 /*
   2  * TI QSPI driver
   3  *
   4  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
   5  * Author: Sourav Poddar <sourav.poddar@ti.com>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GPLv2.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/module.h>
  20 #include <linux/device.h>
  21 #include <linux/delay.h>
  22 #include <linux/dma-mapping.h>
  23 #include <linux/dmaengine.h>
  24 #include <linux/omap-dma.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/err.h>
  27 #include <linux/clk.h>
  28 #include <linux/io.h>
  29 #include <linux/slab.h>
  30 #include <linux/pm_runtime.h>
  31 #include <linux/of.h>
  32 #include <linux/of_device.h>
  33 #include <linux/pinctrl/consumer.h>
  34 #include <linux/mfd/syscon.h>
  35 #include <linux/regmap.h>
  36 #include <linux/sizes.h>
  37
  38 #include <linux/spi/spi.h>
  39 #include <linux/spi/spi-mem.h>
  40
  41 struct ti_qspi_regs {
  42         u32 clkctrl;
  43 };
  44
  45 struct ti_qspi {
  46         struct completion       transfer_complete;
  47
  48         /* list synchronization */
  49         struct mutex            list_lock;
  50
  51         struct spi_master       *master;
  52         void __iomem            *base;
  53         void __iomem            *mmap_base;
  54         size_t                  mmap_size;
  55         struct regmap           *ctrl_base;
  56         unsigned int            ctrl_reg;
  57         struct clk              *fclk;
  58         struct device           *dev;
  59
  60         struct ti_qspi_regs     ctx_reg;
  61
  62         dma_addr_t              mmap_phys_base;
  63         dma_addr_t              rx_bb_dma_addr;
  64         void                    *rx_bb_addr;
  65         struct dma_chan         *rx_chan;
  66
  67         u32 spi_max_frequency;
  68         u32 cmd;
  69         u32 dc;
  70
  71         bool mmap_enabled;
  72 };
  73
  74 #define QSPI_PID                        (0x0)
  75 #define QSPI_SYSCONFIG                  (0x10)
  76 #define QSPI_SPI_CLOCK_CNTRL_REG        (0x40)
  77 #define QSPI_SPI_DC_REG                 (0x44)
  78 #define QSPI_SPI_CMD_REG                (0x48)
  79 #define QSPI_SPI_STATUS_REG             (0x4c)
  80 #define QSPI_SPI_DATA_REG               (0x50)
  81 #define QSPI_SPI_SETUP_REG(n)           ((0x54 + 4 * n))
  82 #define QSPI_SPI_SWITCH_REG             (0x64)
  83 #define QSPI_SPI_DATA_REG_1             (0x68)
  84 #define QSPI_SPI_DATA_REG_2             (0x6c)
  85 #define QSPI_SPI_DATA_REG_3             (0x70)
  86
  87 #define QSPI_COMPLETION_TIMEOUT         msecs_to_jiffies(2000)
  88
  89 #define QSPI_FCLK                       192000000
  90
  91 /* Clock Control */
  92 #define QSPI_CLK_EN                     (1 << 31)
  93 #define QSPI_CLK_DIV_MAX                0xffff
  94
  95 /* Command */
  96 #define QSPI_EN_CS(n)                   (n << 28)
  97 #define QSPI_WLEN(n)                    ((n - 1) << 19)
  98 #define QSPI_3_PIN                      (1 << 18)
  99 #define QSPI_RD_SNGL                    (1 << 16)
 100 #define QSPI_WR_SNGL                    (2 << 16)
 101 #define QSPI_RD_DUAL                    (3 << 16)
 102 #define QSPI_RD_QUAD                    (7 << 16)
 103 #define QSPI_INVAL                      (4 << 16)
 104 #define QSPI_FLEN(n)                    ((n - 1) << 0)
 105 #define QSPI_WLEN_MAX_BITS              128
 106 #define QSPI_WLEN_MAX_BYTES             16
 107 #define QSPI_WLEN_MASK                  QSPI_WLEN(QSPI_WLEN_MAX_BITS)
 108
 109 /* STATUS REGISTER */
 110 #define BUSY                            0x01
 111 #define WC                              0x02
 112
 113 /* Device Control */
 114 #define QSPI_DD(m, n)                   (m << (3 + n * 8))
 115 #define QSPI_CKPHA(n)                   (1 << (2 + n * 8))
 116 #define QSPI_CSPOL(n)                   (1 << (1 + n * 8))
 117 #define QSPI_CKPOL(n)                   (1 << (n * 8))
 118
 119 #define QSPI_FRAME                      4096
 120
 121 #define QSPI_AUTOSUSPEND_TIMEOUT         2000
 122
 123 #define MEM_CS_EN(n)                    ((n + 1) << 8)
 124 #define MEM_CS_MASK                     (7 << 8)
 125
 126 #define MM_SWITCH                       0x1
 127
 128 #define QSPI_SETUP_RD_NORMAL            (0x0 << 12)
 129 #define QSPI_SETUP_RD_DUAL              (0x1 << 12)
 130 #define QSPI_SETUP_RD_QUAD              (0x3 << 12)
 131 #define QSPI_SETUP_ADDR_SHIFT           8
 132 #define QSPI_SETUP_DUMMY_SHIFT          10
 133
 134 #define QSPI_DMA_BUFFER_SIZE            SZ_64K
 135
 136 static inline unsigned long ti_qspi_read(struct ti_qspi *qspi,
 137                 unsigned long reg)
 138 {
 139         return readl(qspi->base + reg);
 140 }
 141
 142 static inline void ti_qspi_write(struct ti_qspi *qspi,
 143                 unsigned long val, unsigned long reg)
 144 {
 145         writel(val, qspi->base + reg);
 146 }
 147
 148 static int ti_qspi_setup(struct spi_device *spi)
 149 {
 150         struct ti_qspi  *qspi = spi_master_get_devdata(spi->master);
 151         struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
 152         int clk_div = 0, ret;
 153         u32 clk_ctrl_reg, clk_rate, clk_mask;
 154
 155         if (spi->master->busy) {
 156                 dev_dbg(qspi->dev, "master busy doing other transfers\n");
 157                 return -EBUSY;
 158         }
 159
 160         if (!qspi->spi_max_frequency) {
 161                 dev_err(qspi->dev, "spi max frequency not defined\n");
 162                 return -EINVAL;
 163         }
 164
 165         clk_rate = clk_get_rate(qspi->fclk);
 166
 167         clk_div = DIV_ROUND_UP(clk_rate, qspi->spi_max_frequency) - 1;
 168
 169         if (clk_div < 0) {
 170                 dev_dbg(qspi->dev, "clock divider < 0, using /1 divider\n");
 171                 return -EINVAL;
 172         }
 173
 174         if (clk_div > QSPI_CLK_DIV_MAX) {
 175                 dev_dbg(qspi->dev, "clock divider >%d , using /%d divider\n",
 176                                 QSPI_CLK_DIV_MAX, QSPI_CLK_DIV_MAX + 1);
 177                 return -EINVAL;
 178         }
 179
 180         dev_dbg(qspi->dev, "hz: %d, clock divider %d\n",
 181                         qspi->spi_max_frequency, clk_div);
 182
 183         ret = pm_runtime_get_sync(qspi->dev);
 184         if (ret < 0) {
 185                 dev_err(qspi->dev, "pm_runtime_get_sync() failed\n");
 186                 return ret;
 187         }
 188
 189         clk_ctrl_reg = ti_qspi_read(qspi, QSPI_SPI_CLOCK_CNTRL_REG);
 190
 191         clk_ctrl_reg &= ~QSPI_CLK_EN;
 192
 193         /* disable SCLK */
 194         ti_qspi_write(qspi, clk_ctrl_reg, QSPI_SPI_CLOCK_CNTRL_REG);
 195
 196         /* enable SCLK */
 197         clk_mask = QSPI_CLK_EN | clk_div;
 198         ti_qspi_write(qspi, clk_mask, QSPI_SPI_CLOCK_CNTRL_REG);
 199         ctx_reg->clkctrl = clk_mask;
 200
 201         pm_runtime_mark_last_busy(qspi->dev);
 202         ret = pm_runtime_put_autosuspend(qspi->dev);
 203         if (ret < 0) {
 204                 dev_err(qspi->dev, "pm_runtime_put_autosuspend() failed\n");
 205                 return ret;
 206         }
 207
 208         return 0;
 209 }
 210
 211 static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
 212 {
 213         struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
 214
 215         ti_qspi_write(qspi, ctx_reg->clkctrl, QSPI_SPI_CLOCK_CNTRL_REG);
 216 }
 217
 218 static inline u32 qspi_is_busy(struct ti_qspi *qspi)
 219 {
 220         u32 stat;
 221         unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT;
 222
 223         stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
 224         while ((stat & BUSY) && time_after(timeout, jiffies)) {
 225                 cpu_relax();
 226                 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
 227         }
 228
 229         WARN(stat & BUSY, "qspi busy\n");
 230         return stat & BUSY;
 231 }
 232
 233 static inline int ti_qspi_poll_wc(struct ti_qspi *qspi)
 234 {
 235         u32 stat;
 236         unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT;
 237
 238         do {
 239                 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
 240                 if (stat & WC)
 241                         return 0;
 242                 cpu_relax();
 243         } while (time_after(timeout, jiffies));
 244
 245         stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
 246         if (stat & WC)
 247                 return 0;
 248         return  -ETIMEDOUT;
 249 }
 250
 251 static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t,
 252                           int count)
 253 {
 254         int wlen, xfer_len;
 255         unsigned int cmd;
 256         const u8 *txbuf;
 257         u32 data;
 258
 259         txbuf = t->tx_buf;
 260         cmd = qspi->cmd | QSPI_WR_SNGL;
 261         wlen = t->bits_per_word >> 3;   /* in bytes */
 262         xfer_len = wlen;
 263
 264         while (count) {
 265                 if (qspi_is_busy(qspi))
 266                         return -EBUSY;
 267
 268                 switch (wlen) {
 269                 case 1:
 270                         dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %02x\n",
 271                                         cmd, qspi->dc, *txbuf);
 272                         if (count >= QSPI_WLEN_MAX_BYTES) {
 273                                 u32 *txp = (u32 *)txbuf;
 274
 275                                 data = cpu_to_be32(*txp++);
 276                                 writel(data, qspi->base +
 277                                        QSPI_SPI_DATA_REG_3);
 278                                 data = cpu_to_be32(*txp++);
 279                                 writel(data, qspi->base +
 280                                        QSPI_SPI_DATA_REG_2);
 281                                 data = cpu_to_be32(*txp++);
 282                                 writel(data, qspi->base +
 283                                        QSPI_SPI_DATA_REG_1);
 284                                 data = cpu_to_be32(*txp++);
 285                                 writel(data, qspi->base +
 286                                        QSPI_SPI_DATA_REG);
 287                                 xfer_len = QSPI_WLEN_MAX_BYTES;
 288                                 cmd |= QSPI_WLEN(QSPI_WLEN_MAX_BITS);
 289                         } else {
 290                                 writeb(*txbuf, qspi->base + QSPI_SPI_DATA_REG);
 291                                 cmd = qspi->cmd | QSPI_WR_SNGL;
 292                                 xfer_len = wlen;
 293                                 cmd |= QSPI_WLEN(wlen);
 294                         }
 295                         break;
 296                 case 2:
 297                         dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %04x\n",
 298                                         cmd, qspi->dc, *txbuf);
 299                         writew(*((u16 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
 300                         break;
 301                 case 4:
 302                         dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %08x\n",
 303                                         cmd, qspi->dc, *txbuf);
 304                         writel(*((u32 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
 305                         break;
 306                 }
 307
 308                 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
 309                 if (ti_qspi_poll_wc(qspi)) {
 310                         dev_err(qspi->dev, "write timed out\n");
 311                         return -ETIMEDOUT;
 312                 }
 313                 txbuf += xfer_len;
 314                 count -= xfer_len;
 315         }
 316
 317         return 0;
 318 }
 319
 320 static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t,
 321                          int count)
 322 {
 323         int wlen;
 324         unsigned int cmd;
 325         u8 *rxbuf;
 326
 327         rxbuf = t->rx_buf;
 328         cmd = qspi->cmd;
 329         switch (t->rx_nbits) {
 330         case SPI_NBITS_DUAL:
 331                 cmd |= QSPI_RD_DUAL;
 332                 break;
 333         case SPI_NBITS_QUAD:
 334                 cmd |= QSPI_RD_QUAD;
 335                 break;
 336         default:
 337                 cmd |= QSPI_RD_SNGL;
 338                 break;
 339         }
 340         wlen = t->bits_per_word >> 3;   /* in bytes */
 341
 342         while (count) {
 343                 dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", cmd, qspi->dc);
 344                 if (qspi_is_busy(qspi))
 345                         return -EBUSY;
 346
 347                 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
 348                 if (ti_qspi_poll_wc(qspi)) {
 349                         dev_err(qspi->dev, "read timed out\n");
 350                         return -ETIMEDOUT;
 351                 }
 352                 switch (wlen) {
 353                 case 1:
 354                         *rxbuf = readb(qspi->base + QSPI_SPI_DATA_REG);
 355                         break;
 356                 case 2:
 357                         *((u16 *)rxbuf) = readw(qspi->base + QSPI_SPI_DATA_REG);
 358                         break;
 359                 case 4:
 360                         *((u32 *)rxbuf) = readl(qspi->base + QSPI_SPI_DATA_REG);
 361                         break;
 362                 }
 363                 rxbuf += wlen;
 364                 count -= wlen;
 365         }
 366
 367         return 0;
 368 }
 369
 370 static int qspi_transfer_msg(struct ti_qspi *qspi, struct spi_transfer *t,
 371                              int count)
 372 {
 373         int ret;
 374
 375         if (t->tx_buf) {
 376                 ret = qspi_write_msg(qspi, t, count);
 377                 if (ret) {
 378                         dev_dbg(qspi->dev, "Error while writing\n");
 379                         return ret;
 380                 }
 381         }
 382
 383         if (t->rx_buf) {
 384                 ret = qspi_read_msg(qspi, t, count);
 385                 if (ret) {
 386                         dev_dbg(qspi->dev, "Error while reading\n");
 387                         return ret;
 388                 }
 389         }
 390
 391         return 0;
 392 }
 393
 394 static void ti_qspi_dma_callback(void *param)
 395 {
 396         struct ti_qspi *qspi = param;
 397
 398         complete(&qspi->transfer_complete);
 399 }
 400
 401 static int ti_qspi_dma_xfer(struct ti_qspi *qspi, dma_addr_t dma_dst,
 402                             dma_addr_t dma_src, size_t len)
 403 {
 404         struct dma_chan *chan = qspi->rx_chan;
 405         dma_cookie_t cookie;
 406         enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
 407         struct dma_async_tx_descriptor *tx;
 408         int ret;
 409
 410         tx = dmaengine_prep_dma_memcpy(chan, dma_dst, dma_src, len, flags);
 411         if (!tx) {
 412                 dev_err(qspi->dev, "device_prep_dma_memcpy error\n");
 413                 return -EIO;
 414         }
 415
 416         tx->callback = ti_qspi_dma_callback;
 417         tx->callback_param = qspi;
 418         cookie = tx->tx_submit(tx);
 419         reinit_completion(&qspi->transfer_complete);
 420
 421         ret = dma_submit_error(cookie);
 422         if (ret) {
 423                 dev_err(qspi->dev, "dma_submit_error %d\n", cookie);
 424                 return -EIO;
 425         }
 426
 427         dma_async_issue_pending(chan);
 428         ret = wait_for_completion_timeout(&qspi->transfer_complete,
 429                                           msecs_to_jiffies(len));
 430         if (ret <= 0) {
 431                 dmaengine_terminate_sync(chan);
 432                 dev_err(qspi->dev, "DMA wait_for_completion_timeout\n");
 433                 return -ETIMEDOUT;
 434         }
 435
 436         return 0;
 437 }
 438
 439 static int ti_qspi_dma_bounce_buffer(struct ti_qspi *qspi, loff_t offs,
 440                                      void *to, size_t readsize)
 441 {
 442         dma_addr_t dma_src = qspi->mmap_phys_base + offs;
 443         int ret = 0;
 444
 445         /*
 446          * Use bounce buffer as FS like jffs2, ubifs may pass
 447          * buffers that does not belong to kernel lowmem region.
 448          */
 449         while (readsize != 0) {
 450                 size_t xfer_len = min_t(size_t, QSPI_DMA_BUFFER_SIZE,
 451                                         readsize);
 452
 453                 ret = ti_qspi_dma_xfer(qspi, qspi->rx_bb_dma_addr,
 454                                        dma_src, xfer_len);
 455                 if (ret != 0)
 456                         return ret;
 457                 memcpy(to, qspi->rx_bb_addr, xfer_len);
 458                 readsize -= xfer_len;
 459                 dma_src += xfer_len;
 460                 to += xfer_len;
 461         }
 462
 463         return ret;
 464 }
 465
 466 static int ti_qspi_dma_xfer_sg(struct ti_qspi *qspi, struct sg_table rx_sg,
 467                                loff_t from)
 468 {
 469         struct scatterlist *sg;
 470         dma_addr_t dma_src = qspi->mmap_phys_base + from;
 471         dma_addr_t dma_dst;
 472         int i, len, ret;
 473
 474         for_each_sg(rx_sg.sgl, sg, rx_sg.nents, i) {
 475                 dma_dst = sg_dma_address(sg);
 476                 len = sg_dma_len(sg);
 477                 ret = ti_qspi_dma_xfer(qspi, dma_dst, dma_src, len);
 478                 if (ret)
 479                         return ret;
 480                 dma_src += len;
 481         }
 482
 483         return 0;
 484 }
 485
 486 static void ti_qspi_enable_memory_map(struct spi_device *spi)
 487 {
 488         struct ti_qspi  *qspi = spi_master_get_devdata(spi->master);
 489
 490         ti_qspi_write(qspi, MM_SWITCH, QSPI_SPI_SWITCH_REG);
 491         if (qspi->ctrl_base) {
 492                 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,
 493                                    MEM_CS_MASK,
 494                                    MEM_CS_EN(spi->chip_select));
 495         }
 496         qspi->mmap_enabled = true;
 497 }
 498
 499 static void ti_qspi_disable_memory_map(struct spi_device *spi)
 500 {
 501         struct ti_qspi  *qspi = spi_master_get_devdata(spi->master);
 502
 503         ti_qspi_write(qspi, 0, QSPI_SPI_SWITCH_REG);
 504         if (qspi->ctrl_base)
 505                 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,
 506                                    MEM_CS_MASK, 0);
 507         qspi->mmap_enabled = false;
 508 }
 509
 510 static void ti_qspi_setup_mmap_read(struct spi_device *spi, u8 opcode,
 511                                     u8 data_nbits, u8 addr_width,
 512                                     u8 dummy_bytes)
 513 {
 514         struct ti_qspi  *qspi = spi_master_get_devdata(spi->master);
 515         u32 memval = opcode;
 516
 517         switch (data_nbits) {
 518         case SPI_NBITS_QUAD:
 519                 memval |= QSPI_SETUP_RD_QUAD;
 520                 break;
 521         case SPI_NBITS_DUAL:
 522                 memval |= QSPI_SETUP_RD_DUAL;
 523                 break;
 524         default:
 525                 memval |= QSPI_SETUP_RD_NORMAL;
 526                 break;
 527         }
 528         memval |= ((addr_width - 1) << QSPI_SETUP_ADDR_SHIFT |
 529                    dummy_bytes << QSPI_SETUP_DUMMY_SHIFT);
 530         ti_qspi_write(qspi, memval,
 531                       QSPI_SPI_SETUP_REG(spi->chip_select));
 532 }
 533
 534 static int ti_qspi_exec_mem_op(struct spi_mem *mem,
 535                                const struct spi_mem_op *op)
 536 {
 537         struct ti_qspi *qspi = spi_master_get_devdata(mem->spi->master);
 538         u32 from = 0;
 539         int ret = 0;
 540
 541         /* Only optimize read path. */
 542         if (!op->data.nbytes || op->data.dir != SPI_MEM_DATA_IN ||
 543             !op->addr.nbytes || op->addr.nbytes > 4)
 544                 return -ENOTSUPP;
 545
 546         /* Address exceeds MMIO window size, fall back to regular mode. */
 547         from = op->addr.val;
 548         if (from + op->data.nbytes > qspi->mmap_size)
 549                 return -ENOTSUPP;
 550
 551         mutex_lock(&qspi->list_lock);
 552
 553         if (!qspi->mmap_enabled)
 554                 ti_qspi_enable_memory_map(mem->spi);
 555         ti_qspi_setup_mmap_read(mem->spi, op->cmd.opcode, op->data.buswidth,
 556                                 op->addr.nbytes, op->dummy.nbytes);
 557
 558         if (qspi->rx_chan) {
 559                 struct sg_table sgt;
 560
 561                 if (virt_addr_valid(op->data.buf.in) &&
 562                     !spi_controller_dma_map_mem_op_data(mem->spi->master, op,
 563                                                         &sgt)) {
 564                         ret = ti_qspi_dma_xfer_sg(qspi, sgt, from);
 565                         spi_controller_dma_unmap_mem_op_data(mem->spi->master,
 566                                                              op, &sgt);
 567                 } else {
 568                         ret = ti_qspi_dma_bounce_buffer(qspi, from,
 569                                                         op->data.buf.in,
 570                                                         op->data.nbytes);
 571                 }
 572         } else {
 573                 memcpy_fromio(op->data.buf.in, qspi->mmap_base + from,
 574                               op->data.nbytes);
 575         }
 576
 577         mutex_unlock(&qspi->list_lock);
 578
 579         return ret;
 580 }
 581
 582 static const struct spi_controller_mem_ops ti_qspi_mem_ops = {
 583         .exec_op = ti_qspi_exec_mem_op,
 584 };
 585
 586 static int ti_qspi_start_transfer_one(struct spi_master *master,
 587                 struct spi_message *m)
 588 {
 589         struct ti_qspi *qspi = spi_master_get_devdata(master);
 590         struct spi_device *spi = m->spi;
 591         struct spi_transfer *t;
 592         int status = 0, ret;
 593         unsigned int frame_len_words, transfer_len_words;
 594         int wlen;
 595
 596         /* setup device control reg */
 597         qspi->dc = 0;
 598
 599         if (spi->mode & SPI_CPHA)
 600                 qspi->dc |= QSPI_CKPHA(spi->chip_select);
 601         if (spi->mode & SPI_CPOL)
 602                 qspi->dc |= QSPI_CKPOL(spi->chip_select);
 603         if (spi->mode & SPI_CS_HIGH)
 604                 qspi->dc |= QSPI_CSPOL(spi->chip_select);
 605
 606         frame_len_words = 0;
 607         list_for_each_entry(t, &m->transfers, transfer_list)
 608                 frame_len_words += t->len / (t->bits_per_word >> 3);
 609         frame_len_words = min_t(unsigned int, frame_len_words, QSPI_FRAME);
 610
 611         /* setup command reg */
 612         qspi->cmd = 0;
 613         qspi->cmd |= QSPI_EN_CS(spi->chip_select);
 614         qspi->cmd |= QSPI_FLEN(frame_len_words);
 615
 616         ti_qspi_write(qspi, qspi->dc, QSPI_SPI_DC_REG);
 617
 618         mutex_lock(&qspi->list_lock);
 619
 620         if (qspi->mmap_enabled)
 621                 ti_qspi_disable_memory_map(spi);
 622
 623         list_for_each_entry(t, &m->transfers, transfer_list) {
 624                 qspi->cmd = ((qspi->cmd & ~QSPI_WLEN_MASK) |
 625                              QSPI_WLEN(t->bits_per_word));
 626
 627                 wlen = t->bits_per_word >> 3;
 628                 transfer_len_words = min(t->len / wlen, frame_len_words);
 629
 630                 ret = qspi_transfer_msg(qspi, t, transfer_len_words * wlen);
 631                 if (ret) {
 632                         dev_dbg(qspi->dev, "transfer message failed\n");
 633                         mutex_unlock(&qspi->list_lock);
 634                         return -EINVAL;
 635                 }
 636
 637                 m->actual_length += transfer_len_words * wlen;
 638                 frame_len_words -= transfer_len_words;
 639                 if (frame_len_words == 0)
 640                         break;
 641         }
 642
 643         mutex_unlock(&qspi->list_lock);
 644
 645         ti_qspi_write(qspi, qspi->cmd | QSPI_INVAL, QSPI_SPI_CMD_REG);
 646         m->status = status;
 647         spi_finalize_current_message(master);
 648
 649         return status;
 650 }
 651
 652 static int ti_qspi_runtime_resume(struct device *dev)
 653 {
 654         struct ti_qspi      *qspi;
 655
 656         qspi = dev_get_drvdata(dev);
 657         ti_qspi_restore_ctx(qspi);
 658
 659         return 0;
 660 }
 661
 662 static const struct of_device_id ti_qspi_match[] = {
 663         {.compatible = "ti,dra7xxx-qspi" },
 664         {.compatible = "ti,am4372-qspi" },
 665         {},
 666 };
 667 MODULE_DEVICE_TABLE(of, ti_qspi_match);
 668
 669 static int ti_qspi_probe(struct platform_device *pdev)
 670 {
 671         struct  ti_qspi *qspi;
 672         struct spi_master *master;
 673         struct resource         *r, *res_mmap;
 674         struct device_node *np = pdev->dev.of_node;
 675         u32 max_freq;
 676         int ret = 0, num_cs, irq;
 677         dma_cap_mask_t mask;
 678
 679         master = spi_alloc_master(&pdev->dev, sizeof(*qspi));
 680         if (!master)
 681                 return -ENOMEM;
 682
 683         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD;
 684
 685         master->flags = SPI_MASTER_HALF_DUPLEX;
 686         master->setup = ti_qspi_setup;
 687         master->auto_runtime_pm = true;
 688         master->transfer_one_message = ti_qspi_start_transfer_one;
 689         master->dev.of_node = pdev->dev.of_node;
 690         master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
 691                                      SPI_BPW_MASK(8);
 692         master->mem_ops = &ti_qspi_mem_ops;
 693
 694         if (!of_property_read_u32(np, "num-cs", &num_cs))
 695                 master->num_chipselect = num_cs;
 696
 697         qspi = spi_master_get_devdata(master);
 698         qspi->master = master;
 699         qspi->dev = &pdev->dev;
 700         platform_set_drvdata(pdev, qspi);
 701
 702         r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base");
 703         if (r == NULL) {
 704                 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 705                 if (r == NULL) {
 706                         dev_err(&pdev->dev, "missing platform data\n");
 707                         ret = -ENODEV;
 708                         goto free_master;
 709                 }
 710         }
 711
 712         res_mmap = platform_get_resource_byname(pdev,
 713                         IORESOURCE_MEM, "qspi_mmap");
 714         if (res_mmap == NULL) {
 715                 res_mmap = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 716                 if (res_mmap == NULL) {
 717                         dev_err(&pdev->dev,
 718                                 "memory mapped resource not required\n");
 719                 }
 720         }
 721
 722         if (res_mmap)
 723                 qspi->mmap_size = resource_size(res_mmap);
 724
 725         irq = platform_get_irq(pdev, 0);
 726         if (irq < 0) {
 727                 dev_err(&pdev->dev, "no irq resource?\n");
 728                 ret = irq;
 729                 goto free_master;
 730         }
 731
 732         mutex_init(&qspi->list_lock);
 733
 734         qspi->base = devm_ioremap_resource(&pdev->dev, r);
 735         if (IS_ERR(qspi->base)) {
 736                 ret = PTR_ERR(qspi->base);
 737                 goto free_master;
 738         }
 739
 740
 741         if (of_property_read_bool(np, "syscon-chipselects")) {
 742                 qspi->ctrl_base =
 743                 syscon_regmap_lookup_by_phandle(np,
 744                                                 "syscon-chipselects");
 745                 if (IS_ERR(qspi->ctrl_base)) {
 746                         ret = PTR_ERR(qspi->ctrl_base);
 747                         goto free_master;
 748                 }
 749                 ret = of_property_read_u32_index(np,
 750                                                  "syscon-chipselects",
 751                                                  1, &qspi->ctrl_reg);
 752                 if (ret) {
 753                         dev_err(&pdev->dev,
 754                                 "couldn't get ctrl_mod reg index\n");
 755                         goto free_master;
 756                 }
 757         }
 758
 759         qspi->fclk = devm_clk_get(&pdev->dev, "fck");
 760         if (IS_ERR(qspi->fclk)) {
 761                 ret = PTR_ERR(qspi->fclk);
 762                 dev_err(&pdev->dev, "could not get clk: %d\n", ret);
 763         }
 764
 765         pm_runtime_use_autosuspend(&pdev->dev);
 766         pm_runtime_set_autosuspend_delay(&pdev->dev, QSPI_AUTOSUSPEND_TIMEOUT);
 767         pm_runtime_enable(&pdev->dev);
 768
 769         if (!of_property_read_u32(np, "spi-max-frequency", &max_freq))
 770                 qspi->spi_max_frequency = max_freq;
 771
 772         dma_cap_zero(mask);
 773         dma_cap_set(DMA_MEMCPY, mask);
 774
 775         qspi->rx_chan = dma_request_chan_by_mask(&mask);
 776         if (IS_ERR(qspi->rx_chan)) {
 777                 dev_err(qspi->dev,
 778                         "No Rx DMA available, trying mmap mode\n");
 779                 qspi->rx_chan = NULL;
 780                 ret = 0;
 781                 goto no_dma;
 782         }
 783         qspi->rx_bb_addr = dma_alloc_coherent(qspi->dev,
 784                                               QSPI_DMA_BUFFER_SIZE,
 785                                               &qspi->rx_bb_dma_addr,
 786                                               GFP_KERNEL | GFP_DMA);
 787         if (!qspi->rx_bb_addr) {
 788                 dev_err(qspi->dev,
 789                         "dma_alloc_coherent failed, using PIO mode\n");
 790                 dma_release_channel(qspi->rx_chan);
 791                 goto no_dma;
 792         }
 793         master->dma_rx = qspi->rx_chan;
 794         init_completion(&qspi->transfer_complete);
 795         if (res_mmap)
 796                 qspi->mmap_phys_base = (dma_addr_t)res_mmap->start;
 797
 798 no_dma:
 799         if (!qspi->rx_chan && res_mmap) {
 800                 qspi->mmap_base = devm_ioremap_resource(&pdev->dev, res_mmap);
 801                 if (IS_ERR(qspi->mmap_base)) {
 802                         dev_info(&pdev->dev,
 803                                  "mmap failed with error %ld using PIO mode\n",
 804                                  PTR_ERR(qspi->mmap_base));
 805                         qspi->mmap_base = NULL;
 806                         master->mem_ops = NULL;
 807                 }
 808         }
 809         qspi->mmap_enabled = false;
 810
 811         ret = devm_spi_register_master(&pdev->dev, master);
 812         if (!ret)
 813                 return 0;
 814
 815         pm_runtime_disable(&pdev->dev);
 816 free_master:
 817         spi_master_put(master);
 818         return ret;
 819 }
 820
 821 static int ti_qspi_remove(struct platform_device *pdev)
 822 {
 823         struct ti_qspi *qspi = platform_get_drvdata(pdev);
 824         int rc;
 825
 826         rc = spi_master_suspend(qspi->master);
 827         if (rc)
 828                 return rc;
 829
 830         pm_runtime_put_sync(&pdev->dev);
 831         pm_runtime_disable(&pdev->dev);
 832
 833         if (qspi->rx_bb_addr)
 834                 dma_free_coherent(qspi->dev, QSPI_DMA_BUFFER_SIZE,
 835                                   qspi->rx_bb_addr,
 836                                   qspi->rx_bb_dma_addr);
 837         if (qspi->rx_chan)
 838                 dma_release_channel(qspi->rx_chan);
 839
 840         return 0;
 841 }
 842
 843 static const struct dev_pm_ops ti_qspi_pm_ops = {
 844         .runtime_resume = ti_qspi_runtime_resume,
 845 };
 846
 847 static struct platform_driver ti_qspi_driver = {
 848         .probe  = ti_qspi_probe,
 849         .remove = ti_qspi_remove,
 850         .driver = {
 851                 .name   = "ti-qspi",
 852                 .pm =   &ti_qspi_pm_ops,
 853                 .of_match_table = ti_qspi_match,
 854         }
 855 };
 856
 857 module_platform_driver(ti_qspi_driver);
 858
 859 MODULE_AUTHOR("Sourav Poddar <sourav.poddar@ti.com>");
 860 MODULE_LICENSE("GPL v2");
 861 MODULE_DESCRIPTION("TI QSPI controller driver");
 862 MODULE_ALIAS("platform:ti-qspi");