2 * Copyright (C) 2005 - 2009 ServerEngines
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
10 * Written by: Jayamohan Kallickal (jayamohank@serverengines.com)
12 * Contact Information:
13 * linux-drivers@serverengines.com
16 * 209 N. Fair Oaks Ave
21 #ifndef _BEISCSI_MAIN_
22 #define _BEISCSI_MAIN_
25 #include <linux/kernel.h>
26 #include <linux/pci.h>
28 #include <linux/blk-iopoll.h>
29 #include <scsi/scsi.h>
30 #include <scsi/scsi_cmnd.h>
31 #include <scsi/scsi_device.h>
32 #include <scsi/scsi_host.h>
33 #include <scsi/iscsi_proto.h>
34 #include <scsi/libiscsi.h>
35 #include <scsi/scsi_transport_iscsi.h>
41 #define DRV_NAME "be2iscsi"
42 #define BUILD_STR "2.0.527.0"
44 #define BE_NAME "ServerEngines BladeEngine2" \
45 "Linux iSCSI Driver version" BUILD_STR
46 #define DRV_DESC BE_NAME " " "Driver"
48 #define BE_VENDOR_ID 0x19A2
49 #define BE_DEVICE_ID1 0x212
50 #define OC_DEVICE_ID1 0x702
51 #define OC_DEVICE_ID2 0x703
53 #define BE2_MAX_SESSIONS 64
54 #define BE2_CMDS_PER_CXN 128
55 #define BE2_LOGOUTS BE2_MAX_SESSIONS
57 #define BE2_NOPOUT_REQ 16
58 #define BE2_ASYNCPDUS BE2_MAX_SESSIONS
59 #define BE2_MAX_ICDS 2048
61 #define BE2_DEFPDU_HDR_SZ 64
62 #define BE2_DEFPDU_DATA_SZ 8192
63 #define BE2_IO_DEPTH \
64 (BE2_MAX_ICDS / 2 - (BE2_LOGOUTS + BE2_TMFS + BE2_NOPOUT_REQ))
66 #define BEISCSI_SGLIST_ELEMENTS BE2_SGE
68 #define BEISCSI_MAX_CMNDS 1024 /* Max IO's per Ctrlr sht->can_queue */
69 #define BEISCSI_CMD_PER_LUN 128 /* scsi_host->cmd_per_lun */
70 #define BEISCSI_MAX_SECTORS 2048 /* scsi_host->max_sectors */
72 #define BEISCSI_MAX_CMD_LEN 16 /* scsi_host->max_cmd_len */
73 #define BEISCSI_NUM_MAX_LUN 256 /* scsi_host->max_lun */
74 #define BEISCSI_NUM_DEVICES_SUPPORTED 0x01
75 #define BEISCSI_MAX_FRAGS_INIT 192
76 #define BE_NUM_MSIX_ENTRIES 1
77 #define MPU_EP_SEMAPHORE 0xac
79 #define BE_SENSE_INFO_SIZE 258
80 #define BE_ISCSI_PDU_HEADER_SIZE 64
81 #define BE_MIN_MEM_SIZE 16384
83 #define IIOC_SCSI_DATA 0x05 /* Write Operation */
85 #define DBG_LVL 0x00000001
86 #define DBG_LVL_1 0x00000001
87 #define DBG_LVL_2 0x00000002
88 #define DBG_LVL_3 0x00000004
89 #define DBG_LVL_4 0x00000008
90 #define DBG_LVL_5 0x00000010
91 #define DBG_LVL_6 0x00000020
92 #define DBG_LVL_7 0x00000040
93 #define DBG_LVL_8 0x00000080
95 #define SE_DEBUG(debug_mask, fmt, args...) \
97 if (debug_mask & DBG_LVL) { \
98 printk(KERN_ERR "(%s():%d):", __func__, __LINE__);\
99 printk(fmt, ##args); \
104 * hardware needs the async PDU buffers to be posted in multiples of 8
105 * So have atleast 8 of them by default
108 #define HWI_GET_ASYNC_PDU_CTX(phwi) (phwi->phwi_ctxt->pasync_ctx)
110 /********* Memory BAR register ************/
111 #define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET 0xfc
113 * Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt
114 * Disable" may still globally block interrupts in addition to individual
115 * interrupt masks; a mechanism for the device driver to block all interrupts
116 * atomically without having to arbitrate for the PCI Interrupt Disable bit
119 #define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK (1 << 29) /* bit 29 */
121 /********* ISR0 Register offset **********/
122 #define CEV_ISR0_OFFSET 0xC18
123 #define CEV_ISR_SIZE 4
126 * Macros for reading/writing a protection domain or CSR registers
130 #define DB_TXULP0_OFFSET 0x40
131 #define DB_RXULP0_OFFSET 0xA0
132 /********* Event Q door bell *************/
133 #define DB_EQ_OFFSET DB_CQ_OFFSET
134 #define DB_EQ_RING_ID_MASK 0x1FF /* bits 0 - 8 */
135 /* Clear the interrupt for this eq */
136 #define DB_EQ_CLR_SHIFT (9) /* bit 9 */
138 #define DB_EQ_EVNT_SHIFT (10) /* bit 10 */
139 /* Number of event entries processed */
140 #define DB_EQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
142 #define DB_EQ_REARM_SHIFT (29) /* bit 29 */
144 /********* Compl Q door bell *************/
145 #define DB_CQ_OFFSET 0x120
146 #define DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
147 /* Number of event entries processed */
148 #define DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
150 #define DB_CQ_REARM_SHIFT (29) /* bit 29 */
152 #define GET_HWI_CONTROLLER_WS(pc) (pc->phwi_ctrlr)
153 #define HWI_GET_DEF_BUFQ_ID(pc) (((struct hwi_controller *)\
154 (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_data.id)
155 #define HWI_GET_DEF_HDRQ_ID(pc) (((struct hwi_controller *)\
156 (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_hdr.id)
158 #define PAGES_REQUIRED(x) \
159 ((x < PAGE_SIZE) ? 1 : ((x + PAGE_SIZE - 1) / PAGE_SIZE))
162 HWI_MEM_ADDN_CONTEXT,
167 HWI_MEM_SGLH, /* 5 */
169 HWI_MEM_ASYNC_HEADER_BUF,
170 HWI_MEM_ASYNC_DATA_BUF,
171 HWI_MEM_ASYNC_HEADER_RING,
172 HWI_MEM_ASYNC_DATA_RING, /* 10 */
173 HWI_MEM_ASYNC_HEADER_HANDLE,
174 HWI_MEM_ASYNC_DATA_HANDLE,
175 HWI_MEM_ASYNC_PDU_CONTEXT,
176 ISCSI_MEM_GLOBAL_HEADER,
180 struct be_bus_address32 {
181 unsigned int address_lo;
182 unsigned int address_hi;
185 struct be_bus_address64 {
186 unsigned long long address;
189 struct be_bus_address {
191 struct be_bus_address32 a32;
192 struct be_bus_address64 a64;
197 struct be_bus_address bus_address; /* Bus address of location */
198 void *virtual_address; /* virtual address to the location */
199 unsigned int size; /* Size required by memory block */
202 struct be_mem_descriptor {
203 unsigned int index; /* Index of this memory parameter */
204 unsigned int category; /* type indicates cached/non-cached */
205 unsigned int num_elements; /* number of elements in this
208 unsigned int alignment_mask; /* Alignment mask for this block */
209 unsigned int size_in_bytes; /* Size required by memory block */
210 struct mem_array *mem_array;
214 unsigned int sgl_index;
215 struct iscsi_sge *pfrag;
218 struct hba_parameters {
219 unsigned int ios_per_ctrl;
220 unsigned int cxns_per_ctrl;
221 unsigned int asyncpdus_per_ctrl;
222 unsigned int icds_per_ctrl;
223 unsigned int num_sge_per_io;
224 unsigned int defpdu_hdr_sz;
225 unsigned int defpdu_data_sz;
226 unsigned int num_cq_entries;
227 unsigned int num_eq_entries;
228 unsigned int wrbs_per_cxn;
229 unsigned int crashmode;
230 unsigned int hba_num;
232 unsigned int mgmt_ws_sz;
233 unsigned int hwi_ws_sz;
238 unsigned int dbg_flags;
239 unsigned int num_cxn;
241 unsigned int eq_timer;
243 * These are calculated from other params. They're here
246 unsigned int num_mcc_pages;
247 unsigned int num_mcc_cq_pages;
248 unsigned int num_cq_pages;
249 unsigned int num_eq_pages;
251 unsigned int num_async_pdu_buf_pages;
252 unsigned int num_async_pdu_buf_sgl_pages;
253 unsigned int num_async_pdu_buf_cq_pages;
255 unsigned int num_async_pdu_hdr_pages;
256 unsigned int num_async_pdu_hdr_sgl_pages;
257 unsigned int num_async_pdu_hdr_cq_pages;
259 unsigned int num_sge;
263 struct hba_parameters params;
264 struct hwi_controller *phwi_ctrlr;
265 unsigned int mem_req[SE_MEM_MAX];
266 /* PCI BAR mapped addresses */
267 u8 __iomem *csr_va; /* CSR */
268 u8 __iomem *db_va; /* Door Bell */
269 u8 __iomem *pci_va; /* PCI Config */
270 struct be_bus_address csr_pa; /* CSR */
271 struct be_bus_address db_pa; /* CSR */
272 struct be_bus_address pci_pa; /* CSR */
273 /* PCI representation of our HBA */
274 struct pci_dev *pcidev;
276 unsigned short asic_revision;
277 struct blk_iopoll iopoll;
278 struct be_mem_descriptor *init_mem;
280 unsigned short io_sgl_alloc_index;
281 unsigned short io_sgl_free_index;
282 unsigned short io_sgl_hndl_avbl;
283 struct sgl_handle **io_sgl_hndl_base;
285 unsigned short eh_sgl_alloc_index;
286 unsigned short eh_sgl_free_index;
287 unsigned short eh_sgl_hndl_avbl;
288 struct sgl_handle **eh_sgl_hndl_base;
289 spinlock_t io_sgl_lock;
290 spinlock_t mgmt_sgl_lock;
293 unsigned short avlbl_cids;
294 unsigned short cid_alloc;
295 unsigned short cid_free;
296 struct beiscsi_conn *conn_table[BE2_MAX_SESSIONS * 2];
297 struct list_head hba_queue;
298 unsigned short *cid_array;
299 struct iscsi_endpoint **ep_array;
300 struct Scsi_Host *shost;
303 * group together since they are used most frequently
304 * for cid to cri conversion
306 unsigned int iscsi_cid_start;
307 unsigned int phys_port;
309 unsigned int isr_offset;
310 unsigned int iscsi_icd_start;
311 unsigned int iscsi_cid_count;
312 unsigned int iscsi_icd_count;
313 unsigned int pci_function;
315 unsigned short cid_alloc;
316 unsigned short cid_free;
317 unsigned short avlbl_cids;
321 u8 mac_address[ETH_ALEN];
322 unsigned short todo_cq;
323 unsigned short todo_mcc_cq;
325 struct workqueue_struct *wq; /* The actuak work queue */
326 struct work_struct work_cqs; /* The work being queued */
327 struct be_ctrl_info ctrl;
331 * struct beiscsi_conn - iscsi connection structure
333 struct beiscsi_conn {
334 struct iscsi_conn *conn;
335 struct beiscsi_hba *phba;
337 u32 beiscsi_conn_cid;
338 struct beiscsi_endpoint *ep;
339 unsigned short login_in_progress;
340 struct sgl_handle *plogin_sgl_handle;
343 /* This structure is used by the chip */
344 struct pdu_data_out {
348 * Pseudo amap definition in which each bit of the actual structure is defined
349 * as a byte: used to calculate offset/shift/mask of each field
351 struct amap_pdu_data_out {
352 u8 opcode[6]; /* opcode */
353 u8 rsvd0[2]; /* should be 0 */
355 u8 final_bit; /* F bit */
357 u8 ahs_length[8]; /* no AHS */
359 u8 data_len_lo[16]; /* DataSegmentLength */
361 u8 itt[32]; /* ITT; initiator task tag */
362 u8 ttt[32]; /* TTT; valid for R2T or 0xffffffff */
367 u8 buffer_offset[32];
372 struct iscsi_cmd iscsi_hdr;
373 unsigned char pad1[16];
374 struct pdu_data_out iscsi_data_pdu;
375 unsigned char pad2[BE_SENSE_INFO_SIZE -
376 sizeof(struct pdu_data_out)];
379 struct beiscsi_io_task {
380 struct wrb_handle *pwrb_handle;
381 struct sgl_handle *psgl_handle;
382 struct beiscsi_conn *conn;
383 struct scsi_cmnd *scsi_cmnd;
387 unsigned short header_len;
389 unsigned int alloc_size;
390 struct be_cmd_bhs *cmd_bhs;
391 struct be_bus_address bhs_pa;
392 unsigned short bhs_len;
395 struct be_nonio_bhs {
396 struct iscsi_hdr iscsi_hdr;
397 unsigned char pad1[16];
398 struct pdu_data_out iscsi_data_pdu;
399 unsigned char pad2[BE_SENSE_INFO_SIZE -
400 sizeof(struct pdu_data_out)];
403 struct be_status_bhs {
404 struct iscsi_cmd iscsi_hdr;
405 unsigned char pad1[16];
407 * The plus 2 below is to hold the sense info length that gets
410 unsigned char sense_info[BE_SENSE_INFO_SIZE];
418 * Pseudo amap definition in which each bit of the actual structure is defined
419 * as a byte: used to calculate offset/shift/mask of each field
421 struct amap_iscsi_sge {
424 u8 sge_offset[22]; /* DWORD 2 */
425 u8 rsvd0[9]; /* DWORD 2 */
426 u8 last_sge; /* DWORD 2 */
427 u8 len[17]; /* DWORD 3 */
428 u8 rsvd1[15]; /* DWORD 3 */
431 struct beiscsi_offload_params {
435 #define OFFLD_PARAMS_ERL 0x00000003
436 #define OFFLD_PARAMS_DDE 0x00000004
437 #define OFFLD_PARAMS_HDE 0x00000008
438 #define OFFLD_PARAMS_IR2T 0x00000010
439 #define OFFLD_PARAMS_IMD 0x00000020
442 * Pseudo amap definition in which each bit of the actual structure is defined
443 * as a byte: used to calculate offset/shift/mask of each field
445 struct amap_beiscsi_offload_params {
446 u8 max_burst_length[32];
447 u8 max_send_data_segment_length[32];
448 u8 first_burst_length[32];
458 /* void hwi_complete_drvr_msgs(struct beiscsi_conn *beiscsi_conn,
459 struct beiscsi_hba *phba, struct sol_cqe *psol);*/
461 struct async_pdu_handle {
462 struct list_head link;
463 struct be_bus_address pa;
465 unsigned int consumed;
467 unsigned char is_header;
469 unsigned long buffer_len;
472 struct hwi_async_entry {
474 unsigned char hdr_received;
475 unsigned char hdr_len;
476 unsigned short bytes_received;
477 unsigned int bytes_needed;
478 struct list_head list;
481 struct list_head header_busy_list;
482 struct list_head data_busy_list;
485 #define BE_MIN_ASYNC_ENTRIES 128
487 struct hwi_async_pdu_context {
489 struct be_bus_address pa_base;
492 struct async_pdu_handle *handle_base;
494 unsigned int host_write_ptr;
495 unsigned int ep_read_ptr;
496 unsigned int writables;
498 unsigned int free_entries;
499 unsigned int busy_entries;
500 unsigned int buffer_size;
501 unsigned int num_entries;
503 struct list_head free_list;
507 struct be_bus_address pa_base;
510 struct async_pdu_handle *handle_base;
512 unsigned int host_write_ptr;
513 unsigned int ep_read_ptr;
514 unsigned int writables;
516 unsigned int free_entries;
517 unsigned int busy_entries;
518 unsigned int buffer_size;
519 struct list_head free_list;
520 unsigned int num_entries;
524 * This is a varying size list! Do not add anything
527 struct hwi_async_entry async_entry[BE_MIN_ASYNC_ENTRIES];
530 #define PDUCQE_CODE_MASK 0x0000003F
531 #define PDUCQE_DPL_MASK 0xFFFF0000
532 #define PDUCQE_INDEX_MASK 0x0000FFFF
534 struct i_t_dpdu_cqe {
539 * Pseudo amap definition in which each bit of the actual structure is defined
540 * as a byte: used to calculate offset/shift/mask of each field
542 struct amap_i_t_dpdu_cqe {
555 #define CQE_VALID_MASK 0x80000000
556 #define CQE_CODE_MASK 0x0000003F
557 #define CQE_CID_MASK 0x0000FFC0
559 #define EQE_VALID_MASK 0x00000001
560 #define EQE_MAJORCODE_MASK 0x0000000E
561 #define EQE_RESID_MASK 0xFFFF0000
568 * Pseudo amap definition in which each bit of the actual structure is defined
569 * as a byte: used to calculate offset/shift/mask of each field
571 struct amap_eq_entry {
572 u8 valid; /* DWORD 0 */
573 u8 major_code[3]; /* DWORD 0 */
574 u8 minor_code[12]; /* DWORD 0 */
575 u8 resource_id[16]; /* DWORD 0 */
584 * Pseudo amap definition in which each bit of the actual structure is defined
585 * as a byte: used to calculate offset/shift/mask of each field
596 void beiscsi_process_eq(struct beiscsi_hba *phba);
603 #define WRB_TYPE_MASK 0xF0000000
606 * Pseudo amap definition in which each bit of the actual structure is defined
607 * as a byte: used to calculate offset/shift/mask of each field
609 struct amap_iscsi_wrb {
610 u8 lun[14]; /* DWORD 0 */
612 u8 invld; /* DWORD 0 */
613 u8 wrb_idx[8]; /* DWORD 0 */
614 u8 dsp; /* DWORD 0 */
615 u8 dmsg; /* DWORD 0 */
616 u8 undr_run; /* DWORD 0 */
617 u8 over_run; /* DWORD 0 */
618 u8 type[4]; /* DWORD 0 */
619 u8 ptr2nextwrb[8]; /* DWORD 1 */
620 u8 r2t_exp_dtl[24]; /* DWORD 1 */
621 u8 sgl_icd_idx[12]; /* DWORD 2 */
622 u8 rsvd0[20]; /* DWORD 2 */
623 u8 exp_data_sn[32]; /* DWORD 3 */
624 u8 iscsi_bhs_addr_hi[32]; /* DWORD 4 */
625 u8 iscsi_bhs_addr_lo[32]; /* DWORD 5 */
626 u8 cmdsn_itt[32]; /* DWORD 6 */
627 u8 dif_ref_tag[32]; /* DWORD 7 */
628 u8 sge0_addr_hi[32]; /* DWORD 8 */
629 u8 sge0_addr_lo[32]; /* DWORD 9 */
630 u8 sge0_offset[22]; /* DWORD 10 */
631 u8 pbs; /* DWORD 10 */
632 u8 dif_mode[2]; /* DWORD 10 */
633 u8 rsvd1[6]; /* DWORD 10 */
634 u8 sge0_last; /* DWORD 10 */
635 u8 sge0_len[17]; /* DWORD 11 */
636 u8 dif_meta_tag[14]; /* DWORD 11 */
637 u8 sge0_in_ddr; /* DWORD 11 */
638 u8 sge1_addr_hi[32]; /* DWORD 12 */
639 u8 sge1_addr_lo[32]; /* DWORD 13 */
640 u8 sge1_r2t_offset[22]; /* DWORD 14 */
641 u8 rsvd2[9]; /* DWORD 14 */
642 u8 sge1_last; /* DWORD 14 */
643 u8 sge1_len[17]; /* DWORD 15 */
644 u8 ref_sgl_icd_idx[12]; /* DWORD 15 */
645 u8 rsvd3[2]; /* DWORD 15 */
646 u8 sge1_in_ddr; /* DWORD 15 */
650 struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid,
653 free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle);
660 * Pseudo amap definition in which each bit of the actual structure is defined
661 * as a byte: used to calculate offset/shift/mask of each field
663 struct amap_pdu_nop_out {
664 u8 opcode[6]; /* opcode 0x00 */
665 u8 i_bit; /* I Bit */
666 u8 x_bit; /* reserved; should be 0 */
667 u8 fp_bit_filler1[7];
668 u8 f_bit; /* always 1 */
670 u8 ahs_length[8]; /* no AHS */
672 u8 data_len_lo[16]; /* DataSegmentLength */
674 u8 itt[32]; /* initiator id for ping or 0xffffffff */
675 u8 ttt[32]; /* target id for ping or 0xffffffff */
681 #define PDUBASE_OPCODE_MASK 0x0000003F
682 #define PDUBASE_DATALENHI_MASK 0x0000FF00
683 #define PDUBASE_DATALENLO_MASK 0xFFFF0000
690 * Pseudo amap definition in which each bit of the actual structure is defined
691 * as a byte: used to calculate offset/shift/mask of each field
693 struct amap_pdu_base {
695 u8 i_bit; /* immediate bit */
696 u8 x_bit; /* reserved, always 0 */
697 u8 reserved1[24]; /* opcode-specific fields */
698 u8 ahs_length[8]; /* length units is 4 byte words */
700 u8 data_len_lo[16]; /* DatasegmentLength */
701 u8 lun[64]; /* lun or opcode-specific fields */
702 u8 itt[32]; /* initiator task tag */
706 struct iscsi_target_context_update_wrb {
711 * Pseudo amap definition in which each bit of the actual structure is defined
712 * as a byte: used to calculate offset/shift/mask of each field
714 struct amap_iscsi_target_context_update_wrb {
715 u8 lun[14]; /* DWORD 0 */
717 u8 invld; /* DWORD 0 */
718 u8 wrb_idx[8]; /* DWORD 0 */
719 u8 dsp; /* DWORD 0 */
720 u8 dmsg; /* DWORD 0 */
721 u8 undr_run; /* DWORD 0 */
722 u8 over_run; /* DWORD 0 */
723 u8 type[4]; /* DWORD 0 */
724 u8 ptr2nextwrb[8]; /* DWORD 1 */
725 u8 max_burst_length[19]; /* DWORD 1 */
726 u8 rsvd0[5]; /* DWORD 1 */
727 u8 rsvd1[15]; /* DWORD 2 */
728 u8 max_send_data_segment_length[17]; /* DWORD 2 */
729 u8 first_burst_length[14]; /* DWORD 3 */
730 u8 rsvd2[2]; /* DWORD 3 */
731 u8 tx_wrbindex_drv_msg[8]; /* DWORD 3 */
732 u8 rsvd3[5]; /* DWORD 3 */
733 u8 session_state[3]; /* DWORD 3 */
734 u8 rsvd4[16]; /* DWORD 4 */
735 u8 tx_jumbo; /* DWORD 4 */
736 u8 hde; /* DWORD 4 */
737 u8 dde; /* DWORD 4 */
738 u8 erl[2]; /* DWORD 4 */
739 u8 domain_id[5]; /* DWORD 4 */
740 u8 mode; /* DWORD 4 */
741 u8 imd; /* DWORD 4 */
742 u8 ir2t; /* DWORD 4 */
743 u8 notpredblq[2]; /* DWORD 4 */
744 u8 compltonack; /* DWORD 4 */
745 u8 stat_sn[32]; /* DWORD 5 */
746 u8 pad_buffer_addr_hi[32]; /* DWORD 6 */
747 u8 pad_buffer_addr_lo[32]; /* DWORD 7 */
748 u8 pad_addr_hi[32]; /* DWORD 8 */
749 u8 pad_addr_lo[32]; /* DWORD 9 */
750 u8 rsvd5[32]; /* DWORD 10 */
751 u8 rsvd6[32]; /* DWORD 11 */
752 u8 rsvd7[32]; /* DWORD 12 */
753 u8 rsvd8[32]; /* DWORD 13 */
754 u8 rsvd9[32]; /* DWORD 14 */
755 u8 rsvd10[32]; /* DWORD 15 */
760 u32 pages; /* queue size in pages */
761 u32 id; /* queue id assigned by beklib */
762 u32 num; /* number of elements in queue */
763 u32 cidx; /* consumer index */
764 u32 pidx; /* producer index -- not used by most rings */
765 u32 item_size; /* size in bytes of one object */
767 void *va; /* The virtual address of the ring. This
768 * should be last to allow 32 & 64 bit debugger
769 * extensions to work.
773 struct hwi_wrb_context {
774 struct list_head wrb_handle_list;
775 struct list_head wrb_handle_drvr_list;
776 struct wrb_handle **pwrb_handle_base;
777 struct wrb_handle **pwrb_handle_basestd;
778 struct iscsi_wrb *plast_wrb;
779 unsigned short alloc_index;
780 unsigned short free_index;
781 unsigned short wrb_handles_available;
785 struct hwi_controller {
786 struct list_head io_sgl_list;
787 struct list_head eh_sgl_list;
788 struct sgl_handle *psgl_handle_base;
789 unsigned int wrb_mem_index;
791 struct hwi_wrb_context wrb_context[BE2_MAX_SESSIONS * 2];
792 struct mcc_wrb *pmcc_wrb_base;
793 struct be_ring default_pdu_hdr;
794 struct be_ring default_pdu_data;
795 struct hwi_context_memory *phwi_ctxt;
796 unsigned short cq_errors[CXN_KILLED_CMND_DATA_NOT_ON_SAME_CONN];
806 HWH_TYPE_INVALID = 0xFFFFFFFF
810 enum hwh_type_enum type;
811 unsigned short wrb_index;
812 unsigned short nxt_wrb_index;
814 struct iscsi_task *pio_handle;
815 struct iscsi_wrb *pwrb;
818 struct hwi_context_memory {
819 struct be_eq_obj be_eq;
820 struct be_queue_info be_cq;
821 struct be_queue_info be_mcc_cq;
822 struct be_queue_info be_mcc;
824 struct be_queue_info be_def_hdrq;
825 struct be_queue_info be_def_dataq;
827 struct be_queue_info be_wrbq[BE2_MAX_SESSIONS];
828 struct be_mcc_wrb_context *pbe_mcc_context;
830 struct hwi_async_pdu_context *pasync_ctx;