1 // SPDX-License-Identifier: GPL-2.0
3 * PCI Bus Services, see include/linux/pci.h for further explanation.
5 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
8 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
11 #include <linux/acpi.h>
12 #include <linux/kernel.h>
13 #include <linux/delay.h>
14 #include <linux/dmi.h>
15 #include <linux/init.h>
17 #include <linux/of_pci.h>
18 #include <linux/pci.h>
20 #include <linux/slab.h>
21 #include <linux/module.h>
22 #include <linux/spinlock.h>
23 #include <linux/string.h>
24 #include <linux/log2.h>
25 #include <linux/pci-aspm.h>
26 #include <linux/pm_wakeup.h>
27 #include <linux/interrupt.h>
28 #include <linux/device.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/pci_hotplug.h>
31 #include <linux/vmalloc.h>
32 #include <linux/pci-ats.h>
33 #include <asm/setup.h>
35 #include <linux/aer.h>
38 const char *pci_power_names[] = {
39 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
41 EXPORT_SYMBOL_GPL(pci_power_names);
43 int isa_dma_bridge_buggy;
44 EXPORT_SYMBOL(isa_dma_bridge_buggy);
47 EXPORT_SYMBOL(pci_pci_problems);
49 unsigned int pci_pm_d3_delay;
51 static void pci_pme_list_scan(struct work_struct *work);
53 static LIST_HEAD(pci_pme_list);
54 static DEFINE_MUTEX(pci_pme_list_mutex);
55 static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
57 struct pci_pme_device {
58 struct list_head list;
62 #define PME_TIMEOUT 1000 /* How long between PME checks */
64 static void pci_dev_d3_sleep(struct pci_dev *dev)
66 unsigned int delay = dev->d3_delay;
68 if (delay < pci_pm_d3_delay)
69 delay = pci_pm_d3_delay;
75 #ifdef CONFIG_PCI_DOMAINS
76 int pci_domains_supported = 1;
79 #define DEFAULT_CARDBUS_IO_SIZE (256)
80 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
81 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
82 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
83 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
85 #define DEFAULT_HOTPLUG_IO_SIZE (256)
86 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
87 /* pci=hpmemsize=nnM,hpiosize=nn can override this */
88 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
89 unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
91 #define DEFAULT_HOTPLUG_BUS_SIZE 1
92 unsigned long pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
94 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_DEFAULT;
97 * The default CLS is used if arch didn't set CLS explicitly and not
98 * all pci devices agree on the same value. Arch can override either
99 * the dfl or actual value as it sees fit. Don't forget this is
100 * measured in 32-bit words, not bytes.
102 u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2;
103 u8 pci_cache_line_size;
106 * If we set up a device for bus mastering, we need to check the latency
107 * timer as certain BIOSes forget to set it properly.
109 unsigned int pcibios_max_latency = 255;
111 /* If set, the PCIe ARI capability will not be used. */
112 static bool pcie_ari_disabled;
114 /* Disable bridge_d3 for all PCIe ports */
115 static bool pci_bridge_d3_disable;
116 /* Force bridge_d3 for all PCIe ports */
117 static bool pci_bridge_d3_force;
119 static int __init pcie_port_pm_setup(char *str)
121 if (!strcmp(str, "off"))
122 pci_bridge_d3_disable = true;
123 else if (!strcmp(str, "force"))
124 pci_bridge_d3_force = true;
127 __setup("pcie_port_pm=", pcie_port_pm_setup);
129 /* Time to wait after a reset for device to become responsive */
130 #define PCIE_RESET_READY_POLL_MS 60000
133 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
134 * @bus: pointer to PCI bus structure to search
136 * Given a PCI bus, returns the highest PCI bus number present in the set
137 * including the given PCI bus and its list of child PCI buses.
139 unsigned char pci_bus_max_busnr(struct pci_bus *bus)
142 unsigned char max, n;
144 max = bus->busn_res.end;
145 list_for_each_entry(tmp, &bus->children, node) {
146 n = pci_bus_max_busnr(tmp);
152 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
154 #ifdef CONFIG_HAS_IOMEM
155 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
157 struct resource *res = &pdev->resource[bar];
160 * Make sure the BAR is actually a memory resource, not an IO resource
162 if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) {
163 pci_warn(pdev, "can't ioremap BAR %d: %pR\n", bar, res);
166 return ioremap_nocache(res->start, resource_size(res));
168 EXPORT_SYMBOL_GPL(pci_ioremap_bar);
170 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar)
173 * Make sure the BAR is actually a memory resource, not an IO resource
175 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
179 return ioremap_wc(pci_resource_start(pdev, bar),
180 pci_resource_len(pdev, bar));
182 EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar);
186 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
187 u8 pos, int cap, int *ttl)
192 pci_bus_read_config_byte(bus, devfn, pos, &pos);
198 pci_bus_read_config_word(bus, devfn, pos, &ent);
210 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
213 int ttl = PCI_FIND_CAP_TTL;
215 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
218 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
220 return __pci_find_next_cap(dev->bus, dev->devfn,
221 pos + PCI_CAP_LIST_NEXT, cap);
223 EXPORT_SYMBOL_GPL(pci_find_next_capability);
225 static int __pci_bus_find_cap_start(struct pci_bus *bus,
226 unsigned int devfn, u8 hdr_type)
230 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
231 if (!(status & PCI_STATUS_CAP_LIST))
235 case PCI_HEADER_TYPE_NORMAL:
236 case PCI_HEADER_TYPE_BRIDGE:
237 return PCI_CAPABILITY_LIST;
238 case PCI_HEADER_TYPE_CARDBUS:
239 return PCI_CB_CAPABILITY_LIST;
246 * pci_find_capability - query for devices' capabilities
247 * @dev: PCI device to query
248 * @cap: capability code
250 * Tell if a device supports a given PCI capability.
251 * Returns the address of the requested capability structure within the
252 * device's PCI configuration space or 0 in case the device does not
253 * support it. Possible values for @cap:
255 * %PCI_CAP_ID_PM Power Management
256 * %PCI_CAP_ID_AGP Accelerated Graphics Port
257 * %PCI_CAP_ID_VPD Vital Product Data
258 * %PCI_CAP_ID_SLOTID Slot Identification
259 * %PCI_CAP_ID_MSI Message Signalled Interrupts
260 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
261 * %PCI_CAP_ID_PCIX PCI-X
262 * %PCI_CAP_ID_EXP PCI Express
264 int pci_find_capability(struct pci_dev *dev, int cap)
268 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
270 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
274 EXPORT_SYMBOL(pci_find_capability);
277 * pci_bus_find_capability - query for devices' capabilities
278 * @bus: the PCI bus to query
279 * @devfn: PCI device to query
280 * @cap: capability code
282 * Like pci_find_capability() but works for pci devices that do not have a
283 * pci_dev structure set up yet.
285 * Returns the address of the requested capability structure within the
286 * device's PCI configuration space or 0 in case the device does not
289 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
294 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
296 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
298 pos = __pci_find_next_cap(bus, devfn, pos, cap);
302 EXPORT_SYMBOL(pci_bus_find_capability);
305 * pci_find_next_ext_capability - Find an extended capability
306 * @dev: PCI device to query
307 * @start: address at which to start looking (0 to start at beginning of list)
308 * @cap: capability code
310 * Returns the address of the next matching extended capability structure
311 * within the device's PCI configuration space or 0 if the device does
312 * not support it. Some capabilities can occur several times, e.g., the
313 * vendor-specific capability, and this provides a way to find them all.
315 int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap)
319 int pos = PCI_CFG_SPACE_SIZE;
321 /* minimum 8 bytes per capability */
322 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
324 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
330 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
334 * If we have no capabilities, this is indicated by cap ID,
335 * cap version and next pointer all being 0.
341 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
344 pos = PCI_EXT_CAP_NEXT(header);
345 if (pos < PCI_CFG_SPACE_SIZE)
348 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
354 EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
357 * pci_find_ext_capability - Find an extended capability
358 * @dev: PCI device to query
359 * @cap: capability code
361 * Returns the address of the requested extended capability structure
362 * within the device's PCI configuration space or 0 if the device does
363 * not support it. Possible values for @cap:
365 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
366 * %PCI_EXT_CAP_ID_VC Virtual Channel
367 * %PCI_EXT_CAP_ID_DSN Device Serial Number
368 * %PCI_EXT_CAP_ID_PWR Power Budgeting
370 int pci_find_ext_capability(struct pci_dev *dev, int cap)
372 return pci_find_next_ext_capability(dev, 0, cap);
374 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
376 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
378 int rc, ttl = PCI_FIND_CAP_TTL;
381 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
382 mask = HT_3BIT_CAP_MASK;
384 mask = HT_5BIT_CAP_MASK;
386 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
387 PCI_CAP_ID_HT, &ttl);
389 rc = pci_read_config_byte(dev, pos + 3, &cap);
390 if (rc != PCIBIOS_SUCCESSFUL)
393 if ((cap & mask) == ht_cap)
396 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
397 pos + PCI_CAP_LIST_NEXT,
398 PCI_CAP_ID_HT, &ttl);
404 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
405 * @dev: PCI device to query
406 * @pos: Position from which to continue searching
407 * @ht_cap: Hypertransport capability code
409 * To be used in conjunction with pci_find_ht_capability() to search for
410 * all capabilities matching @ht_cap. @pos should always be a value returned
411 * from pci_find_ht_capability().
413 * NB. To be 100% safe against broken PCI devices, the caller should take
414 * steps to avoid an infinite loop.
416 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
418 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
420 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
423 * pci_find_ht_capability - query a device's Hypertransport capabilities
424 * @dev: PCI device to query
425 * @ht_cap: Hypertransport capability code
427 * Tell if a device supports a given Hypertransport capability.
428 * Returns an address within the device's PCI configuration space
429 * or 0 in case the device does not support the request capability.
430 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
431 * which has a Hypertransport capability matching @ht_cap.
433 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
437 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
439 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
443 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
446 * pci_find_parent_resource - return resource region of parent bus of given region
447 * @dev: PCI device structure contains resources to be searched
448 * @res: child resource record for which parent is sought
450 * For given resource region of given device, return the resource
451 * region of parent bus the given region is contained in.
453 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
454 struct resource *res)
456 const struct pci_bus *bus = dev->bus;
460 pci_bus_for_each_resource(bus, r, i) {
463 if (resource_contains(r, res)) {
466 * If the window is prefetchable but the BAR is
467 * not, the allocator made a mistake.
469 if (r->flags & IORESOURCE_PREFETCH &&
470 !(res->flags & IORESOURCE_PREFETCH))
474 * If we're below a transparent bridge, there may
475 * be both a positively-decoded aperture and a
476 * subtractively-decoded region that contain the BAR.
477 * We want the positively-decoded one, so this depends
478 * on pci_bus_for_each_resource() giving us those
486 EXPORT_SYMBOL(pci_find_parent_resource);
489 * pci_find_resource - Return matching PCI device resource
490 * @dev: PCI device to query
491 * @res: Resource to look for
493 * Goes over standard PCI resources (BARs) and checks if the given resource
494 * is partially or fully contained in any of them. In that case the
495 * matching resource is returned, %NULL otherwise.
497 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res)
501 for (i = 0; i < PCI_ROM_RESOURCE; i++) {
502 struct resource *r = &dev->resource[i];
504 if (r->start && resource_contains(r, res))
510 EXPORT_SYMBOL(pci_find_resource);
513 * pci_find_pcie_root_port - return PCIe Root Port
514 * @dev: PCI device to query
516 * Traverse up the parent chain and return the PCIe Root Port PCI Device
517 * for a given PCI Device.
519 struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev)
521 struct pci_dev *bridge, *highest_pcie_bridge = dev;
523 bridge = pci_upstream_bridge(dev);
524 while (bridge && pci_is_pcie(bridge)) {
525 highest_pcie_bridge = bridge;
526 bridge = pci_upstream_bridge(bridge);
529 if (pci_pcie_type(highest_pcie_bridge) != PCI_EXP_TYPE_ROOT_PORT)
532 return highest_pcie_bridge;
534 EXPORT_SYMBOL(pci_find_pcie_root_port);
537 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
538 * @dev: the PCI device to operate on
539 * @pos: config space offset of status word
540 * @mask: mask of bit(s) to care about in status word
542 * Return 1 when mask bit(s) in status word clear, 0 otherwise.
544 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask)
548 /* Wait for Transaction Pending bit clean */
549 for (i = 0; i < 4; i++) {
552 msleep((1 << (i - 1)) * 100);
554 pci_read_config_word(dev, pos, &status);
555 if (!(status & mask))
563 * pci_restore_bars - restore a device's BAR values (e.g. after wake-up)
564 * @dev: PCI device to have its BARs restored
566 * Restore the BAR values for a given device, so as to make it
567 * accessible by its driver.
569 static void pci_restore_bars(struct pci_dev *dev)
573 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
574 pci_update_resource(dev, i);
577 static const struct pci_platform_pm_ops *pci_platform_pm;
579 int pci_set_platform_pm(const struct pci_platform_pm_ops *ops)
581 if (!ops->is_manageable || !ops->set_state || !ops->get_state ||
582 !ops->choose_state || !ops->set_wakeup || !ops->need_resume)
584 pci_platform_pm = ops;
588 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
590 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
593 static inline int platform_pci_set_power_state(struct pci_dev *dev,
596 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
599 static inline pci_power_t platform_pci_get_power_state(struct pci_dev *dev)
601 return pci_platform_pm ? pci_platform_pm->get_state(dev) : PCI_UNKNOWN;
604 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
606 return pci_platform_pm ?
607 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
610 static inline int platform_pci_set_wakeup(struct pci_dev *dev, bool enable)
612 return pci_platform_pm ?
613 pci_platform_pm->set_wakeup(dev, enable) : -ENODEV;
616 static inline bool platform_pci_need_resume(struct pci_dev *dev)
618 return pci_platform_pm ? pci_platform_pm->need_resume(dev) : false;
622 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
624 * @dev: PCI device to handle.
625 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
628 * -EINVAL if the requested state is invalid.
629 * -EIO if device does not support PCI PM or its PM capabilities register has a
630 * wrong version, or device doesn't support the requested state.
631 * 0 if device already is in the requested state.
632 * 0 if device's power state has been successfully changed.
634 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
637 bool need_restore = false;
639 /* Check if we're already there */
640 if (dev->current_state == state)
646 if (state < PCI_D0 || state > PCI_D3hot)
649 /* Validate current state:
650 * Can enter D0 from any state, but if we can only go deeper
651 * to sleep if we're already in a low power state
653 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
654 && dev->current_state > state) {
655 pci_err(dev, "invalid power transition (from state %d to %d)\n",
656 dev->current_state, state);
660 /* check if this device supports the desired state */
661 if ((state == PCI_D1 && !dev->d1_support)
662 || (state == PCI_D2 && !dev->d2_support))
665 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
667 /* If we're (effectively) in D3, force entire word to 0.
668 * This doesn't affect PME_Status, disables PME_En, and
669 * sets PowerState to 0.
671 switch (dev->current_state) {
675 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
680 case PCI_UNKNOWN: /* Boot-up */
681 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
682 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
684 /* Fall-through: force to D0 */
690 /* enter specified state */
691 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
693 /* Mandatory power management transition delays */
694 /* see PCI PM 1.1 5.6.1 table 18 */
695 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
696 pci_dev_d3_sleep(dev);
697 else if (state == PCI_D2 || dev->current_state == PCI_D2)
698 udelay(PCI_PM_D2_DELAY);
700 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
701 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
702 if (dev->current_state != state && printk_ratelimit())
703 pci_info(dev, "Refused to change power state, currently in D%d\n",
707 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
708 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
709 * from D3hot to D0 _may_ perform an internal reset, thereby
710 * going to "D0 Uninitialized" rather than "D0 Initialized".
711 * For example, at least some versions of the 3c905B and the
712 * 3c556B exhibit this behaviour.
714 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
715 * devices in a D3hot state at boot. Consequently, we need to
716 * restore at least the BARs so that the device will be
717 * accessible to its driver.
720 pci_restore_bars(dev);
723 pcie_aspm_pm_state_change(dev->bus->self);
729 * pci_update_current_state - Read power state of given device and cache it
730 * @dev: PCI device to handle.
731 * @state: State to cache in case the device doesn't have the PM capability
733 * The power state is read from the PMCSR register, which however is
734 * inaccessible in D3cold. The platform firmware is therefore queried first
735 * to detect accessibility of the register. In case the platform firmware
736 * reports an incorrect state or the device isn't power manageable by the
737 * platform at all, we try to detect D3cold by testing accessibility of the
738 * vendor ID in config space.
740 void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
742 if (platform_pci_get_power_state(dev) == PCI_D3cold ||
743 !pci_device_is_present(dev)) {
744 dev->current_state = PCI_D3cold;
745 } else if (dev->pm_cap) {
748 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
749 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
751 dev->current_state = state;
756 * pci_power_up - Put the given device into D0 forcibly
757 * @dev: PCI device to power up
759 void pci_power_up(struct pci_dev *dev)
761 if (platform_pci_power_manageable(dev))
762 platform_pci_set_power_state(dev, PCI_D0);
764 pci_raw_set_power_state(dev, PCI_D0);
765 pci_update_current_state(dev, PCI_D0);
769 * pci_platform_power_transition - Use platform to change device power state
770 * @dev: PCI device to handle.
771 * @state: State to put the device into.
773 static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
777 if (platform_pci_power_manageable(dev)) {
778 error = platform_pci_set_power_state(dev, state);
780 pci_update_current_state(dev, state);
784 if (error && !dev->pm_cap) /* Fall back to PCI_D0 */
785 dev->current_state = PCI_D0;
791 * pci_wakeup - Wake up a PCI device
792 * @pci_dev: Device to handle.
793 * @ign: ignored parameter
795 static int pci_wakeup(struct pci_dev *pci_dev, void *ign)
797 pci_wakeup_event(pci_dev);
798 pm_request_resume(&pci_dev->dev);
803 * pci_wakeup_bus - Walk given bus and wake up devices on it
804 * @bus: Top bus of the subtree to walk.
806 static void pci_wakeup_bus(struct pci_bus *bus)
809 pci_walk_bus(bus, pci_wakeup, NULL);
813 * __pci_start_power_transition - Start power transition of a PCI device
814 * @dev: PCI device to handle.
815 * @state: State to put the device into.
817 static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
819 if (state == PCI_D0) {
820 pci_platform_power_transition(dev, PCI_D0);
822 * Mandatory power management transition delays, see
823 * PCI Express Base Specification Revision 2.0 Section
824 * 6.6.1: Conventional Reset. Do not delay for
825 * devices powered on/off by corresponding bridge,
826 * because have already delayed for the bridge.
828 if (dev->runtime_d3cold) {
829 if (dev->d3cold_delay)
830 msleep(dev->d3cold_delay);
832 * When powering on a bridge from D3cold, the
833 * whole hierarchy may be powered on into
834 * D0uninitialized state, resume them to give
835 * them a chance to suspend again
837 pci_wakeup_bus(dev->subordinate);
843 * __pci_dev_set_current_state - Set current state of a PCI device
844 * @dev: Device to handle
845 * @data: pointer to state to be set
847 static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
849 pci_power_t state = *(pci_power_t *)data;
851 dev->current_state = state;
856 * __pci_bus_set_current_state - Walk given bus and set current state of devices
857 * @bus: Top bus of the subtree to walk.
858 * @state: state to be set
860 static void __pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
863 pci_walk_bus(bus, __pci_dev_set_current_state, &state);
867 * __pci_complete_power_transition - Complete power transition of a PCI device
868 * @dev: PCI device to handle.
869 * @state: State to put the device into.
871 * This function should not be called directly by device drivers.
873 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
879 ret = pci_platform_power_transition(dev, state);
880 /* Power off the bridge may power off the whole hierarchy */
881 if (!ret && state == PCI_D3cold)
882 __pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
885 EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
888 * pci_set_power_state - Set the power state of a PCI device
889 * @dev: PCI device to handle.
890 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
892 * Transition a device to a new power state, using the platform firmware and/or
893 * the device's PCI PM registers.
896 * -EINVAL if the requested state is invalid.
897 * -EIO if device does not support PCI PM or its PM capabilities register has a
898 * wrong version, or device doesn't support the requested state.
899 * 0 if the transition is to D1 or D2 but D1 and D2 are not supported.
900 * 0 if device already is in the requested state.
901 * 0 if the transition is to D3 but D3 is not supported.
902 * 0 if device's power state has been successfully changed.
904 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
908 /* bound the state we're entering */
909 if (state > PCI_D3cold)
911 else if (state < PCI_D0)
913 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
915 * If the device or the parent bridge do not support PCI PM,
916 * ignore the request if we're doing anything other than putting
917 * it into D0 (which would only happen on boot).
921 /* Check if we're already there */
922 if (dev->current_state == state)
925 __pci_start_power_transition(dev, state);
927 /* This device is quirked not to be put into D3, so
928 don't put it in D3 */
929 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
933 * To put device in D3cold, we put device into D3hot in native
934 * way, then put device into D3cold with platform ops
936 error = pci_raw_set_power_state(dev, state > PCI_D3hot ?
939 if (!__pci_complete_power_transition(dev, state))
944 EXPORT_SYMBOL(pci_set_power_state);
947 * pci_choose_state - Choose the power state of a PCI device
948 * @dev: PCI device to be suspended
949 * @state: target sleep state for the whole system. This is the value
950 * that is passed to suspend() function.
952 * Returns PCI power state suitable for given device and given system
956 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
963 ret = platform_pci_choose_state(dev);
964 if (ret != PCI_POWER_ERROR)
967 switch (state.event) {
970 case PM_EVENT_FREEZE:
971 case PM_EVENT_PRETHAW:
972 /* REVISIT both freeze and pre-thaw "should" use D0 */
973 case PM_EVENT_SUSPEND:
974 case PM_EVENT_HIBERNATE:
977 pci_info(dev, "unrecognized suspend event %d\n",
983 EXPORT_SYMBOL(pci_choose_state);
985 #define PCI_EXP_SAVE_REGS 7
987 static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev,
988 u16 cap, bool extended)
990 struct pci_cap_saved_state *tmp;
992 hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) {
993 if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap)
999 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap)
1001 return _pci_find_saved_cap(dev, cap, false);
1004 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap)
1006 return _pci_find_saved_cap(dev, cap, true);
1009 static int pci_save_pcie_state(struct pci_dev *dev)
1012 struct pci_cap_saved_state *save_state;
1015 if (!pci_is_pcie(dev))
1018 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1020 pci_err(dev, "buffer not found in %s\n", __func__);
1024 cap = (u16 *)&save_state->cap.data[0];
1025 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
1026 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
1027 pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
1028 pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]);
1029 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
1030 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
1031 pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
1036 static void pci_restore_pcie_state(struct pci_dev *dev)
1039 struct pci_cap_saved_state *save_state;
1042 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1046 cap = (u16 *)&save_state->cap.data[0];
1047 pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
1048 pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
1049 pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
1050 pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
1051 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
1052 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
1053 pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
1057 static int pci_save_pcix_state(struct pci_dev *dev)
1060 struct pci_cap_saved_state *save_state;
1062 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1066 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1068 pci_err(dev, "buffer not found in %s\n", __func__);
1072 pci_read_config_word(dev, pos + PCI_X_CMD,
1073 (u16 *)save_state->cap.data);
1078 static void pci_restore_pcix_state(struct pci_dev *dev)
1081 struct pci_cap_saved_state *save_state;
1084 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1085 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1086 if (!save_state || !pos)
1088 cap = (u16 *)&save_state->cap.data[0];
1090 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
1095 * pci_save_state - save the PCI configuration space of a device before suspending
1096 * @dev: - PCI device that we're dealing with
1098 int pci_save_state(struct pci_dev *dev)
1101 /* XXX: 100% dword access ok here? */
1102 for (i = 0; i < 16; i++)
1103 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
1104 dev->state_saved = true;
1106 i = pci_save_pcie_state(dev);
1110 i = pci_save_pcix_state(dev);
1114 return pci_save_vc_state(dev);
1116 EXPORT_SYMBOL(pci_save_state);
1118 static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
1119 u32 saved_val, int retry)
1123 pci_read_config_dword(pdev, offset, &val);
1124 if (val == saved_val)
1128 pci_dbg(pdev, "restoring config space at offset %#x (was %#x, writing %#x)\n",
1129 offset, val, saved_val);
1130 pci_write_config_dword(pdev, offset, saved_val);
1134 pci_read_config_dword(pdev, offset, &val);
1135 if (val == saved_val)
1142 static void pci_restore_config_space_range(struct pci_dev *pdev,
1143 int start, int end, int retry)
1147 for (index = end; index >= start; index--)
1148 pci_restore_config_dword(pdev, 4 * index,
1149 pdev->saved_config_space[index],
1153 static void pci_restore_config_space(struct pci_dev *pdev)
1155 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
1156 pci_restore_config_space_range(pdev, 10, 15, 0);
1157 /* Restore BARs before the command register. */
1158 pci_restore_config_space_range(pdev, 4, 9, 10);
1159 pci_restore_config_space_range(pdev, 0, 3, 0);
1161 pci_restore_config_space_range(pdev, 0, 15, 0);
1166 * pci_restore_state - Restore the saved state of a PCI device
1167 * @dev: - PCI device that we're dealing with
1169 void pci_restore_state(struct pci_dev *dev)
1171 if (!dev->state_saved)
1174 /* PCI Express register must be restored first */
1175 pci_restore_pcie_state(dev);
1176 pci_restore_pasid_state(dev);
1177 pci_restore_pri_state(dev);
1178 pci_restore_ats_state(dev);
1179 pci_restore_vc_state(dev);
1181 pci_cleanup_aer_error_status_regs(dev);
1183 pci_restore_config_space(dev);
1185 pci_restore_pcix_state(dev);
1186 pci_restore_msi_state(dev);
1188 /* Restore ACS and IOV configuration state */
1189 pci_enable_acs(dev);
1190 pci_restore_iov_state(dev);
1192 dev->state_saved = false;
1194 EXPORT_SYMBOL(pci_restore_state);
1196 struct pci_saved_state {
1197 u32 config_space[16];
1198 struct pci_cap_saved_data cap[0];
1202 * pci_store_saved_state - Allocate and return an opaque struct containing
1203 * the device saved state.
1204 * @dev: PCI device that we're dealing with
1206 * Return NULL if no state or error.
1208 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
1210 struct pci_saved_state *state;
1211 struct pci_cap_saved_state *tmp;
1212 struct pci_cap_saved_data *cap;
1215 if (!dev->state_saved)
1218 size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1220 hlist_for_each_entry(tmp, &dev->saved_cap_space, next)
1221 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1223 state = kzalloc(size, GFP_KERNEL);
1227 memcpy(state->config_space, dev->saved_config_space,
1228 sizeof(state->config_space));
1231 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) {
1232 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1233 memcpy(cap, &tmp->cap, len);
1234 cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1236 /* Empty cap_save terminates list */
1240 EXPORT_SYMBOL_GPL(pci_store_saved_state);
1243 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1244 * @dev: PCI device that we're dealing with
1245 * @state: Saved state returned from pci_store_saved_state()
1247 int pci_load_saved_state(struct pci_dev *dev,
1248 struct pci_saved_state *state)
1250 struct pci_cap_saved_data *cap;
1252 dev->state_saved = false;
1257 memcpy(dev->saved_config_space, state->config_space,
1258 sizeof(state->config_space));
1262 struct pci_cap_saved_state *tmp;
1264 tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended);
1265 if (!tmp || tmp->cap.size != cap->size)
1268 memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1269 cap = (struct pci_cap_saved_data *)((u8 *)cap +
1270 sizeof(struct pci_cap_saved_data) + cap->size);
1273 dev->state_saved = true;
1276 EXPORT_SYMBOL_GPL(pci_load_saved_state);
1279 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1280 * and free the memory allocated for it.
1281 * @dev: PCI device that we're dealing with
1282 * @state: Pointer to saved state returned from pci_store_saved_state()
1284 int pci_load_and_free_saved_state(struct pci_dev *dev,
1285 struct pci_saved_state **state)
1287 int ret = pci_load_saved_state(dev, *state);
1292 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
1294 int __weak pcibios_enable_device(struct pci_dev *dev, int bars)
1296 return pci_enable_resources(dev, bars);
1299 static int do_pci_enable_device(struct pci_dev *dev, int bars)
1302 struct pci_dev *bridge;
1306 err = pci_set_power_state(dev, PCI_D0);
1307 if (err < 0 && err != -EIO)
1310 bridge = pci_upstream_bridge(dev);
1312 pcie_aspm_powersave_config_link(bridge);
1314 err = pcibios_enable_device(dev, bars);
1317 pci_fixup_device(pci_fixup_enable, dev);
1319 if (dev->msi_enabled || dev->msix_enabled)
1322 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1324 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1325 if (cmd & PCI_COMMAND_INTX_DISABLE)
1326 pci_write_config_word(dev, PCI_COMMAND,
1327 cmd & ~PCI_COMMAND_INTX_DISABLE);
1334 * pci_reenable_device - Resume abandoned device
1335 * @dev: PCI device to be resumed
1337 * Note this function is a backend of pci_default_resume and is not supposed
1338 * to be called by normal code, write proper resume handler and use it instead.
1340 int pci_reenable_device(struct pci_dev *dev)
1342 if (pci_is_enabled(dev))
1343 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1346 EXPORT_SYMBOL(pci_reenable_device);
1348 static void pci_enable_bridge(struct pci_dev *dev)
1350 struct pci_dev *bridge;
1353 bridge = pci_upstream_bridge(dev);
1355 pci_enable_bridge(bridge);
1357 if (pci_is_enabled(dev)) {
1358 if (!dev->is_busmaster)
1359 pci_set_master(dev);
1363 retval = pci_enable_device(dev);
1365 pci_err(dev, "Error enabling bridge (%d), continuing\n",
1367 pci_set_master(dev);
1370 static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags)
1372 struct pci_dev *bridge;
1377 * Power state could be unknown at this point, either due to a fresh
1378 * boot or a device removal call. So get the current power state
1379 * so that things like MSI message writing will behave as expected
1380 * (e.g. if the device really is in D0 at enable time).
1384 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1385 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1388 if (atomic_inc_return(&dev->enable_cnt) > 1)
1389 return 0; /* already enabled */
1391 bridge = pci_upstream_bridge(dev);
1393 pci_enable_bridge(bridge);
1395 /* only skip sriov related */
1396 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
1397 if (dev->resource[i].flags & flags)
1399 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
1400 if (dev->resource[i].flags & flags)
1403 err = do_pci_enable_device(dev, bars);
1405 atomic_dec(&dev->enable_cnt);
1410 * pci_enable_device_io - Initialize a device for use with IO space
1411 * @dev: PCI device to be initialized
1413 * Initialize device before it's used by a driver. Ask low-level code
1414 * to enable I/O resources. Wake up the device if it was suspended.
1415 * Beware, this function can fail.
1417 int pci_enable_device_io(struct pci_dev *dev)
1419 return pci_enable_device_flags(dev, IORESOURCE_IO);
1421 EXPORT_SYMBOL(pci_enable_device_io);
1424 * pci_enable_device_mem - Initialize a device for use with Memory space
1425 * @dev: PCI device to be initialized
1427 * Initialize device before it's used by a driver. Ask low-level code
1428 * to enable Memory resources. Wake up the device if it was suspended.
1429 * Beware, this function can fail.
1431 int pci_enable_device_mem(struct pci_dev *dev)
1433 return pci_enable_device_flags(dev, IORESOURCE_MEM);
1435 EXPORT_SYMBOL(pci_enable_device_mem);
1438 * pci_enable_device - Initialize device before it's used by a driver.
1439 * @dev: PCI device to be initialized
1441 * Initialize device before it's used by a driver. Ask low-level code
1442 * to enable I/O and memory. Wake up the device if it was suspended.
1443 * Beware, this function can fail.
1445 * Note we don't actually enable the device many times if we call
1446 * this function repeatedly (we just increment the count).
1448 int pci_enable_device(struct pci_dev *dev)
1450 return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
1452 EXPORT_SYMBOL(pci_enable_device);
1455 * Managed PCI resources. This manages device on/off, intx/msi/msix
1456 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1457 * there's no need to track it separately. pci_devres is initialized
1458 * when a device is enabled using managed PCI device enable interface.
1461 unsigned int enabled:1;
1462 unsigned int pinned:1;
1463 unsigned int orig_intx:1;
1464 unsigned int restore_intx:1;
1469 static void pcim_release(struct device *gendev, void *res)
1471 struct pci_dev *dev = to_pci_dev(gendev);
1472 struct pci_devres *this = res;
1475 if (dev->msi_enabled)
1476 pci_disable_msi(dev);
1477 if (dev->msix_enabled)
1478 pci_disable_msix(dev);
1480 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1481 if (this->region_mask & (1 << i))
1482 pci_release_region(dev, i);
1487 if (this->restore_intx)
1488 pci_intx(dev, this->orig_intx);
1490 if (this->enabled && !this->pinned)
1491 pci_disable_device(dev);
1494 static struct pci_devres *get_pci_dr(struct pci_dev *pdev)
1496 struct pci_devres *dr, *new_dr;
1498 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1502 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1505 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1508 static struct pci_devres *find_pci_dr(struct pci_dev *pdev)
1510 if (pci_is_managed(pdev))
1511 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1516 * pcim_enable_device - Managed pci_enable_device()
1517 * @pdev: PCI device to be initialized
1519 * Managed pci_enable_device().
1521 int pcim_enable_device(struct pci_dev *pdev)
1523 struct pci_devres *dr;
1526 dr = get_pci_dr(pdev);
1532 rc = pci_enable_device(pdev);
1534 pdev->is_managed = 1;
1539 EXPORT_SYMBOL(pcim_enable_device);
1542 * pcim_pin_device - Pin managed PCI device
1543 * @pdev: PCI device to pin
1545 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1546 * driver detach. @pdev must have been enabled with
1547 * pcim_enable_device().
1549 void pcim_pin_device(struct pci_dev *pdev)
1551 struct pci_devres *dr;
1553 dr = find_pci_dr(pdev);
1554 WARN_ON(!dr || !dr->enabled);
1558 EXPORT_SYMBOL(pcim_pin_device);
1561 * pcibios_add_device - provide arch specific hooks when adding device dev
1562 * @dev: the PCI device being added
1564 * Permits the platform to provide architecture specific functionality when
1565 * devices are added. This is the default implementation. Architecture
1566 * implementations can override this.
1568 int __weak pcibios_add_device(struct pci_dev *dev)
1574 * pcibios_release_device - provide arch specific hooks when releasing device dev
1575 * @dev: the PCI device being released
1577 * Permits the platform to provide architecture specific functionality when
1578 * devices are released. This is the default implementation. Architecture
1579 * implementations can override this.
1581 void __weak pcibios_release_device(struct pci_dev *dev) {}
1584 * pcibios_disable_device - disable arch specific PCI resources for device dev
1585 * @dev: the PCI device to disable
1587 * Disables architecture specific PCI resources for the device. This
1588 * is the default implementation. Architecture implementations can
1591 void __weak pcibios_disable_device(struct pci_dev *dev) {}
1594 * pcibios_penalize_isa_irq - penalize an ISA IRQ
1595 * @irq: ISA IRQ to penalize
1596 * @active: IRQ active or not
1598 * Permits the platform to provide architecture-specific functionality when
1599 * penalizing ISA IRQs. This is the default implementation. Architecture
1600 * implementations can override this.
1602 void __weak pcibios_penalize_isa_irq(int irq, int active) {}
1604 static void do_pci_disable_device(struct pci_dev *dev)
1608 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1609 if (pci_command & PCI_COMMAND_MASTER) {
1610 pci_command &= ~PCI_COMMAND_MASTER;
1611 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1614 pcibios_disable_device(dev);
1618 * pci_disable_enabled_device - Disable device without updating enable_cnt
1619 * @dev: PCI device to disable
1621 * NOTE: This function is a backend of PCI power management routines and is
1622 * not supposed to be called drivers.
1624 void pci_disable_enabled_device(struct pci_dev *dev)
1626 if (pci_is_enabled(dev))
1627 do_pci_disable_device(dev);
1631 * pci_disable_device - Disable PCI device after use
1632 * @dev: PCI device to be disabled
1634 * Signal to the system that the PCI device is not in use by the system
1635 * anymore. This only involves disabling PCI bus-mastering, if active.
1637 * Note we don't actually disable the device until all callers of
1638 * pci_enable_device() have called pci_disable_device().
1640 void pci_disable_device(struct pci_dev *dev)
1642 struct pci_devres *dr;
1644 dr = find_pci_dr(dev);
1648 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0,
1649 "disabling already-disabled device");
1651 if (atomic_dec_return(&dev->enable_cnt) != 0)
1654 do_pci_disable_device(dev);
1656 dev->is_busmaster = 0;
1658 EXPORT_SYMBOL(pci_disable_device);
1661 * pcibios_set_pcie_reset_state - set reset state for device dev
1662 * @dev: the PCIe device reset
1663 * @state: Reset state to enter into
1666 * Sets the PCIe reset state for the device. This is the default
1667 * implementation. Architecture implementations can override this.
1669 int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
1670 enum pcie_reset_state state)
1676 * pci_set_pcie_reset_state - set reset state for device dev
1677 * @dev: the PCIe device reset
1678 * @state: Reset state to enter into
1681 * Sets the PCI reset state for the device.
1683 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1685 return pcibios_set_pcie_reset_state(dev, state);
1687 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
1690 * pci_check_pme_status - Check if given device has generated PME.
1691 * @dev: Device to check.
1693 * Check the PME status of the device and if set, clear it and clear PME enable
1694 * (if set). Return 'true' if PME status and PME enable were both set or
1695 * 'false' otherwise.
1697 bool pci_check_pme_status(struct pci_dev *dev)
1706 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
1707 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
1708 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
1711 /* Clear PME status. */
1712 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1713 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
1714 /* Disable PME to avoid interrupt flood. */
1715 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1719 pci_write_config_word(dev, pmcsr_pos, pmcsr);
1725 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1726 * @dev: Device to handle.
1727 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
1729 * Check if @dev has generated PME and queue a resume request for it in that
1732 static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
1734 if (pme_poll_reset && dev->pme_poll)
1735 dev->pme_poll = false;
1737 if (pci_check_pme_status(dev)) {
1738 pci_wakeup_event(dev);
1739 pm_request_resume(&dev->dev);
1745 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1746 * @bus: Top bus of the subtree to walk.
1748 void pci_pme_wakeup_bus(struct pci_bus *bus)
1751 pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
1756 * pci_pme_capable - check the capability of PCI device to generate PME#
1757 * @dev: PCI device to handle.
1758 * @state: PCI state from which device will issue PME#.
1760 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
1765 return !!(dev->pme_support & (1 << state));
1767 EXPORT_SYMBOL(pci_pme_capable);
1769 static void pci_pme_list_scan(struct work_struct *work)
1771 struct pci_pme_device *pme_dev, *n;
1773 mutex_lock(&pci_pme_list_mutex);
1774 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
1775 if (pme_dev->dev->pme_poll) {
1776 struct pci_dev *bridge;
1778 bridge = pme_dev->dev->bus->self;
1780 * If bridge is in low power state, the
1781 * configuration space of subordinate devices
1782 * may be not accessible
1784 if (bridge && bridge->current_state != PCI_D0)
1786 pci_pme_wakeup(pme_dev->dev, NULL);
1788 list_del(&pme_dev->list);
1792 if (!list_empty(&pci_pme_list))
1793 queue_delayed_work(system_freezable_wq, &pci_pme_work,
1794 msecs_to_jiffies(PME_TIMEOUT));
1795 mutex_unlock(&pci_pme_list_mutex);
1798 static void __pci_pme_active(struct pci_dev *dev, bool enable)
1802 if (!dev->pme_support)
1805 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1806 /* Clear PME_Status by writing 1 to it and enable PME# */
1807 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1809 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1811 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1815 * pci_pme_restore - Restore PME configuration after config space restore.
1816 * @dev: PCI device to update.
1818 void pci_pme_restore(struct pci_dev *dev)
1822 if (!dev->pme_support)
1825 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1826 if (dev->wakeup_prepared) {
1827 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
1828 pmcsr &= ~PCI_PM_CTRL_PME_STATUS;
1830 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1831 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1833 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1837 * pci_pme_active - enable or disable PCI device's PME# function
1838 * @dev: PCI device to handle.
1839 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1841 * The caller must verify that the device is capable of generating PME# before
1842 * calling this function with @enable equal to 'true'.
1844 void pci_pme_active(struct pci_dev *dev, bool enable)
1846 __pci_pme_active(dev, enable);
1849 * PCI (as opposed to PCIe) PME requires that the device have
1850 * its PME# line hooked up correctly. Not all hardware vendors
1851 * do this, so the PME never gets delivered and the device
1852 * remains asleep. The easiest way around this is to
1853 * periodically walk the list of suspended devices and check
1854 * whether any have their PME flag set. The assumption is that
1855 * we'll wake up often enough anyway that this won't be a huge
1856 * hit, and the power savings from the devices will still be a
1859 * Although PCIe uses in-band PME message instead of PME# line
1860 * to report PME, PME does not work for some PCIe devices in
1861 * reality. For example, there are devices that set their PME
1862 * status bits, but don't really bother to send a PME message;
1863 * there are PCI Express Root Ports that don't bother to
1864 * trigger interrupts when they receive PME messages from the
1865 * devices below. So PME poll is used for PCIe devices too.
1868 if (dev->pme_poll) {
1869 struct pci_pme_device *pme_dev;
1871 pme_dev = kmalloc(sizeof(struct pci_pme_device),
1874 pci_warn(dev, "can't enable PME#\n");
1878 mutex_lock(&pci_pme_list_mutex);
1879 list_add(&pme_dev->list, &pci_pme_list);
1880 if (list_is_singular(&pci_pme_list))
1881 queue_delayed_work(system_freezable_wq,
1883 msecs_to_jiffies(PME_TIMEOUT));
1884 mutex_unlock(&pci_pme_list_mutex);
1886 mutex_lock(&pci_pme_list_mutex);
1887 list_for_each_entry(pme_dev, &pci_pme_list, list) {
1888 if (pme_dev->dev == dev) {
1889 list_del(&pme_dev->list);
1894 mutex_unlock(&pci_pme_list_mutex);
1898 pci_dbg(dev, "PME# %s\n", enable ? "enabled" : "disabled");
1900 EXPORT_SYMBOL(pci_pme_active);
1903 * pci_enable_wake - enable PCI device as wakeup event source
1904 * @dev: PCI device affected
1905 * @state: PCI state from which device will issue wakeup events
1906 * @enable: True to enable event generation; false to disable
1908 * This enables the device as a wakeup event source, or disables it.
1909 * When such events involves platform-specific hooks, those hooks are
1910 * called automatically by this routine.
1912 * Devices with legacy power management (no standard PCI PM capabilities)
1913 * always require such platform hooks.
1916 * 0 is returned on success
1917 * -EINVAL is returned if device is not supposed to wake up the system
1918 * Error code depending on the platform is returned if both the platform and
1919 * the native mechanism fail to enable the generation of wake-up events
1921 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable)
1926 * Bridges can only signal wakeup on behalf of subordinate devices,
1927 * but that is set up elsewhere, so skip them.
1929 if (pci_has_subordinate(dev))
1932 /* Don't do the same thing twice in a row for one device. */
1933 if (!!enable == !!dev->wakeup_prepared)
1937 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1938 * Anderson we should be doing PME# wake enable followed by ACPI wake
1939 * enable. To disable wake-up we call the platform first, for symmetry.
1945 if (pci_pme_capable(dev, state))
1946 pci_pme_active(dev, true);
1949 error = platform_pci_set_wakeup(dev, true);
1953 dev->wakeup_prepared = true;
1955 platform_pci_set_wakeup(dev, false);
1956 pci_pme_active(dev, false);
1957 dev->wakeup_prepared = false;
1962 EXPORT_SYMBOL(pci_enable_wake);
1965 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1966 * @dev: PCI device to prepare
1967 * @enable: True to enable wake-up event generation; false to disable
1969 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1970 * and this function allows them to set that up cleanly - pci_enable_wake()
1971 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1972 * ordering constraints.
1974 * This function only returns error code if the device is not capable of
1975 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1976 * enable wake-up power for it.
1978 int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1980 return pci_pme_capable(dev, PCI_D3cold) ?
1981 pci_enable_wake(dev, PCI_D3cold, enable) :
1982 pci_enable_wake(dev, PCI_D3hot, enable);
1984 EXPORT_SYMBOL(pci_wake_from_d3);
1987 * pci_target_state - find an appropriate low power state for a given PCI dev
1989 * @wakeup: Whether or not wakeup functionality will be enabled for the device.
1991 * Use underlying platform code to find a supported low power state for @dev.
1992 * If the platform can't manage @dev, return the deepest state from which it
1993 * can generate wake events, based on any available PME info.
1995 static pci_power_t pci_target_state(struct pci_dev *dev, bool wakeup)
1997 pci_power_t target_state = PCI_D3hot;
1999 if (platform_pci_power_manageable(dev)) {
2001 * Call the platform to choose the target state of the device
2002 * and enable wake-up from this state if supported.
2004 pci_power_t state = platform_pci_choose_state(dev);
2007 case PCI_POWER_ERROR:
2012 if (pci_no_d1d2(dev))
2015 target_state = state;
2018 return target_state;
2022 target_state = PCI_D0;
2025 * If the device is in D3cold even though it's not power-manageable by
2026 * the platform, it may have been powered down by non-standard means.
2027 * Best to let it slumber.
2029 if (dev->current_state == PCI_D3cold)
2030 target_state = PCI_D3cold;
2034 * Find the deepest state from which the device can generate
2035 * wake-up events, make it the target state and enable device
2038 if (dev->pme_support) {
2040 && !(dev->pme_support & (1 << target_state)))
2045 return target_state;
2049 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
2050 * @dev: Device to handle.
2052 * Choose the power state appropriate for the device depending on whether
2053 * it can wake up the system and/or is power manageable by the platform
2054 * (PCI_D3hot is the default) and put the device into that state.
2056 int pci_prepare_to_sleep(struct pci_dev *dev)
2058 bool wakeup = device_may_wakeup(&dev->dev);
2059 pci_power_t target_state = pci_target_state(dev, wakeup);
2062 if (target_state == PCI_POWER_ERROR)
2065 pci_enable_wake(dev, target_state, wakeup);
2067 error = pci_set_power_state(dev, target_state);
2070 pci_enable_wake(dev, target_state, false);
2074 EXPORT_SYMBOL(pci_prepare_to_sleep);
2077 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
2078 * @dev: Device to handle.
2080 * Disable device's system wake-up capability and put it into D0.
2082 int pci_back_from_sleep(struct pci_dev *dev)
2084 pci_enable_wake(dev, PCI_D0, false);
2085 return pci_set_power_state(dev, PCI_D0);
2087 EXPORT_SYMBOL(pci_back_from_sleep);
2090 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
2091 * @dev: PCI device being suspended.
2093 * Prepare @dev to generate wake-up events at run time and put it into a low
2096 int pci_finish_runtime_suspend(struct pci_dev *dev)
2098 pci_power_t target_state;
2101 target_state = pci_target_state(dev, device_can_wakeup(&dev->dev));
2102 if (target_state == PCI_POWER_ERROR)
2105 dev->runtime_d3cold = target_state == PCI_D3cold;
2107 pci_enable_wake(dev, target_state, pci_dev_run_wake(dev));
2109 error = pci_set_power_state(dev, target_state);
2112 pci_enable_wake(dev, target_state, false);
2113 dev->runtime_d3cold = false;
2120 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
2121 * @dev: Device to check.
2123 * Return true if the device itself is capable of generating wake-up events
2124 * (through the platform or using the native PCIe PME) or if the device supports
2125 * PME and one of its upstream bridges can generate wake-up events.
2127 bool pci_dev_run_wake(struct pci_dev *dev)
2129 struct pci_bus *bus = dev->bus;
2131 if (device_can_wakeup(&dev->dev))
2134 if (!dev->pme_support)
2137 /* PME-capable in principle, but not from the target power state */
2138 if (!pci_pme_capable(dev, pci_target_state(dev, false)))
2141 while (bus->parent) {
2142 struct pci_dev *bridge = bus->self;
2144 if (device_can_wakeup(&bridge->dev))
2150 /* We have reached the root bus. */
2152 return device_can_wakeup(bus->bridge);
2156 EXPORT_SYMBOL_GPL(pci_dev_run_wake);
2159 * pci_dev_keep_suspended - Check if the device can stay in the suspended state.
2160 * @pci_dev: Device to check.
2162 * Return 'true' if the device is runtime-suspended, it doesn't have to be
2163 * reconfigured due to wakeup settings difference between system and runtime
2164 * suspend and the current power state of it is suitable for the upcoming
2165 * (system) transition.
2167 * If the device is not configured for system wakeup, disable PME for it before
2168 * returning 'true' to prevent it from waking up the system unnecessarily.
2170 bool pci_dev_keep_suspended(struct pci_dev *pci_dev)
2172 struct device *dev = &pci_dev->dev;
2173 bool wakeup = device_may_wakeup(dev);
2175 if (!pm_runtime_suspended(dev)
2176 || pci_target_state(pci_dev, wakeup) != pci_dev->current_state
2177 || platform_pci_need_resume(pci_dev))
2181 * At this point the device is good to go unless it's been configured
2182 * to generate PME at the runtime suspend time, but it is not supposed
2183 * to wake up the system. In that case, simply disable PME for it
2184 * (it will have to be re-enabled on exit from system resume).
2186 * If the device's power state is D3cold and the platform check above
2187 * hasn't triggered, the device's configuration is suitable and we don't
2188 * need to manipulate it at all.
2190 spin_lock_irq(&dev->power.lock);
2192 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold &&
2194 __pci_pme_active(pci_dev, false);
2196 spin_unlock_irq(&dev->power.lock);
2201 * pci_dev_complete_resume - Finalize resume from system sleep for a device.
2202 * @pci_dev: Device to handle.
2204 * If the device is runtime suspended and wakeup-capable, enable PME for it as
2205 * it might have been disabled during the prepare phase of system suspend if
2206 * the device was not configured for system wakeup.
2208 void pci_dev_complete_resume(struct pci_dev *pci_dev)
2210 struct device *dev = &pci_dev->dev;
2212 if (!pci_dev_run_wake(pci_dev))
2215 spin_lock_irq(&dev->power.lock);
2217 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold)
2218 __pci_pme_active(pci_dev, true);
2220 spin_unlock_irq(&dev->power.lock);
2223 void pci_config_pm_runtime_get(struct pci_dev *pdev)
2225 struct device *dev = &pdev->dev;
2226 struct device *parent = dev->parent;
2229 pm_runtime_get_sync(parent);
2230 pm_runtime_get_noresume(dev);
2232 * pdev->current_state is set to PCI_D3cold during suspending,
2233 * so wait until suspending completes
2235 pm_runtime_barrier(dev);
2237 * Only need to resume devices in D3cold, because config
2238 * registers are still accessible for devices suspended but
2241 if (pdev->current_state == PCI_D3cold)
2242 pm_runtime_resume(dev);
2245 void pci_config_pm_runtime_put(struct pci_dev *pdev)
2247 struct device *dev = &pdev->dev;
2248 struct device *parent = dev->parent;
2250 pm_runtime_put(dev);
2252 pm_runtime_put_sync(parent);
2256 * pci_bridge_d3_possible - Is it possible to put the bridge into D3
2257 * @bridge: Bridge to check
2259 * This function checks if it is possible to move the bridge to D3.
2260 * Currently we only allow D3 for recent enough PCIe ports.
2262 bool pci_bridge_d3_possible(struct pci_dev *bridge)
2266 if (!pci_is_pcie(bridge))
2269 switch (pci_pcie_type(bridge)) {
2270 case PCI_EXP_TYPE_ROOT_PORT:
2271 case PCI_EXP_TYPE_UPSTREAM:
2272 case PCI_EXP_TYPE_DOWNSTREAM:
2273 if (pci_bridge_d3_disable)
2277 * Hotplug interrupts cannot be delivered if the link is down,
2278 * so parents of a hotplug port must stay awake. In addition,
2279 * hotplug ports handled by firmware in System Management Mode
2280 * may not be put into D3 by the OS (Thunderbolt on non-Macs).
2281 * For simplicity, disallow in general for now.
2283 if (bridge->is_hotplug_bridge)
2286 if (pci_bridge_d3_force)
2290 * It should be safe to put PCIe ports from 2015 or newer
2293 if (dmi_get_date(DMI_BIOS_DATE, &year, NULL, NULL) &&
2303 static int pci_dev_check_d3cold(struct pci_dev *dev, void *data)
2305 bool *d3cold_ok = data;
2307 if (/* The device needs to be allowed to go D3cold ... */
2308 dev->no_d3cold || !dev->d3cold_allowed ||
2310 /* ... and if it is wakeup capable to do so from D3cold. */
2311 (device_may_wakeup(&dev->dev) &&
2312 !pci_pme_capable(dev, PCI_D3cold)) ||
2314 /* If it is a bridge it must be allowed to go to D3. */
2315 !pci_power_manageable(dev))
2323 * pci_bridge_d3_update - Update bridge D3 capabilities
2324 * @dev: PCI device which is changed
2326 * Update upstream bridge PM capabilities accordingly depending on if the
2327 * device PM configuration was changed or the device is being removed. The
2328 * change is also propagated upstream.
2330 void pci_bridge_d3_update(struct pci_dev *dev)
2332 bool remove = !device_is_registered(&dev->dev);
2333 struct pci_dev *bridge;
2334 bool d3cold_ok = true;
2336 bridge = pci_upstream_bridge(dev);
2337 if (!bridge || !pci_bridge_d3_possible(bridge))
2341 * If D3 is currently allowed for the bridge, removing one of its
2342 * children won't change that.
2344 if (remove && bridge->bridge_d3)
2348 * If D3 is currently allowed for the bridge and a child is added or
2349 * changed, disallowance of D3 can only be caused by that child, so
2350 * we only need to check that single device, not any of its siblings.
2352 * If D3 is currently not allowed for the bridge, checking the device
2353 * first may allow us to skip checking its siblings.
2356 pci_dev_check_d3cold(dev, &d3cold_ok);
2359 * If D3 is currently not allowed for the bridge, this may be caused
2360 * either by the device being changed/removed or any of its siblings,
2361 * so we need to go through all children to find out if one of them
2362 * continues to block D3.
2364 if (d3cold_ok && !bridge->bridge_d3)
2365 pci_walk_bus(bridge->subordinate, pci_dev_check_d3cold,
2368 if (bridge->bridge_d3 != d3cold_ok) {
2369 bridge->bridge_d3 = d3cold_ok;
2370 /* Propagate change to upstream bridges */
2371 pci_bridge_d3_update(bridge);
2376 * pci_d3cold_enable - Enable D3cold for device
2377 * @dev: PCI device to handle
2379 * This function can be used in drivers to enable D3cold from the device
2380 * they handle. It also updates upstream PCI bridge PM capabilities
2383 void pci_d3cold_enable(struct pci_dev *dev)
2385 if (dev->no_d3cold) {
2386 dev->no_d3cold = false;
2387 pci_bridge_d3_update(dev);
2390 EXPORT_SYMBOL_GPL(pci_d3cold_enable);
2393 * pci_d3cold_disable - Disable D3cold for device
2394 * @dev: PCI device to handle
2396 * This function can be used in drivers to disable D3cold from the device
2397 * they handle. It also updates upstream PCI bridge PM capabilities
2400 void pci_d3cold_disable(struct pci_dev *dev)
2402 if (!dev->no_d3cold) {
2403 dev->no_d3cold = true;
2404 pci_bridge_d3_update(dev);
2407 EXPORT_SYMBOL_GPL(pci_d3cold_disable);
2410 * pci_pm_init - Initialize PM functions of given PCI device
2411 * @dev: PCI device to handle.
2413 void pci_pm_init(struct pci_dev *dev)
2418 pm_runtime_forbid(&dev->dev);
2419 pm_runtime_set_active(&dev->dev);
2420 pm_runtime_enable(&dev->dev);
2421 device_enable_async_suspend(&dev->dev);
2422 dev->wakeup_prepared = false;
2425 dev->pme_support = 0;
2427 /* find PCI PM capability in list */
2428 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
2431 /* Check device's ability to generate PME# */
2432 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
2434 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
2435 pci_err(dev, "unsupported PM cap regs version (%u)\n",
2436 pmc & PCI_PM_CAP_VER_MASK);
2441 dev->d3_delay = PCI_PM_D3_WAIT;
2442 dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
2443 dev->bridge_d3 = pci_bridge_d3_possible(dev);
2444 dev->d3cold_allowed = true;
2446 dev->d1_support = false;
2447 dev->d2_support = false;
2448 if (!pci_no_d1d2(dev)) {
2449 if (pmc & PCI_PM_CAP_D1)
2450 dev->d1_support = true;
2451 if (pmc & PCI_PM_CAP_D2)
2452 dev->d2_support = true;
2454 if (dev->d1_support || dev->d2_support)
2455 pci_printk(KERN_DEBUG, dev, "supports%s%s\n",
2456 dev->d1_support ? " D1" : "",
2457 dev->d2_support ? " D2" : "");
2460 pmc &= PCI_PM_CAP_PME_MASK;
2462 pci_printk(KERN_DEBUG, dev, "PME# supported from%s%s%s%s%s\n",
2463 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
2464 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
2465 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
2466 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
2467 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
2468 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
2469 dev->pme_poll = true;
2471 * Make device's PM flags reflect the wake-up capability, but
2472 * let the user space enable it to wake up the system as needed.
2474 device_set_wakeup_capable(&dev->dev, true);
2475 /* Disable the PME# generation functionality */
2476 pci_pme_active(dev, false);
2480 static unsigned long pci_ea_flags(struct pci_dev *dev, u8 prop)
2482 unsigned long flags = IORESOURCE_PCI_FIXED | IORESOURCE_PCI_EA_BEI;
2486 case PCI_EA_P_VF_MEM:
2487 flags |= IORESOURCE_MEM;
2489 case PCI_EA_P_MEM_PREFETCH:
2490 case PCI_EA_P_VF_MEM_PREFETCH:
2491 flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
2494 flags |= IORESOURCE_IO;
2503 static struct resource *pci_ea_get_resource(struct pci_dev *dev, u8 bei,
2506 if (bei <= PCI_EA_BEI_BAR5 && prop <= PCI_EA_P_IO)
2507 return &dev->resource[bei];
2508 #ifdef CONFIG_PCI_IOV
2509 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5 &&
2510 (prop == PCI_EA_P_VF_MEM || prop == PCI_EA_P_VF_MEM_PREFETCH))
2511 return &dev->resource[PCI_IOV_RESOURCES +
2512 bei - PCI_EA_BEI_VF_BAR0];
2514 else if (bei == PCI_EA_BEI_ROM)
2515 return &dev->resource[PCI_ROM_RESOURCE];
2520 /* Read an Enhanced Allocation (EA) entry */
2521 static int pci_ea_read(struct pci_dev *dev, int offset)
2523 struct resource *res;
2524 int ent_size, ent_offset = offset;
2525 resource_size_t start, end;
2526 unsigned long flags;
2527 u32 dw0, bei, base, max_offset;
2529 bool support_64 = (sizeof(resource_size_t) >= 8);
2531 pci_read_config_dword(dev, ent_offset, &dw0);
2534 /* Entry size field indicates DWORDs after 1st */
2535 ent_size = ((dw0 & PCI_EA_ES) + 1) << 2;
2537 if (!(dw0 & PCI_EA_ENABLE)) /* Entry not enabled */
2540 bei = (dw0 & PCI_EA_BEI) >> 4;
2541 prop = (dw0 & PCI_EA_PP) >> 8;
2544 * If the Property is in the reserved range, try the Secondary
2547 if (prop > PCI_EA_P_BRIDGE_IO && prop < PCI_EA_P_MEM_RESERVED)
2548 prop = (dw0 & PCI_EA_SP) >> 16;
2549 if (prop > PCI_EA_P_BRIDGE_IO)
2552 res = pci_ea_get_resource(dev, bei, prop);
2554 pci_err(dev, "Unsupported EA entry BEI: %u\n", bei);
2558 flags = pci_ea_flags(dev, prop);
2560 pci_err(dev, "Unsupported EA properties: %#x\n", prop);
2565 pci_read_config_dword(dev, ent_offset, &base);
2566 start = (base & PCI_EA_FIELD_MASK);
2569 /* Read MaxOffset */
2570 pci_read_config_dword(dev, ent_offset, &max_offset);
2573 /* Read Base MSBs (if 64-bit entry) */
2574 if (base & PCI_EA_IS_64) {
2577 pci_read_config_dword(dev, ent_offset, &base_upper);
2580 flags |= IORESOURCE_MEM_64;
2582 /* entry starts above 32-bit boundary, can't use */
2583 if (!support_64 && base_upper)
2587 start |= ((u64)base_upper << 32);
2590 end = start + (max_offset | 0x03);
2592 /* Read MaxOffset MSBs (if 64-bit entry) */
2593 if (max_offset & PCI_EA_IS_64) {
2594 u32 max_offset_upper;
2596 pci_read_config_dword(dev, ent_offset, &max_offset_upper);
2599 flags |= IORESOURCE_MEM_64;
2601 /* entry too big, can't use */
2602 if (!support_64 && max_offset_upper)
2606 end += ((u64)max_offset_upper << 32);
2610 pci_err(dev, "EA Entry crosses address boundary\n");
2614 if (ent_size != ent_offset - offset) {
2615 pci_err(dev, "EA Entry Size (%d) does not match length read (%d)\n",
2616 ent_size, ent_offset - offset);
2620 res->name = pci_name(dev);
2625 if (bei <= PCI_EA_BEI_BAR5)
2626 pci_printk(KERN_DEBUG, dev, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
2628 else if (bei == PCI_EA_BEI_ROM)
2629 pci_printk(KERN_DEBUG, dev, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n",
2631 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5)
2632 pci_printk(KERN_DEBUG, dev, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
2633 bei - PCI_EA_BEI_VF_BAR0, res, prop);
2635 pci_printk(KERN_DEBUG, dev, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n",
2639 return offset + ent_size;
2642 /* Enhanced Allocation Initialization */
2643 void pci_ea_init(struct pci_dev *dev)
2650 /* find PCI EA capability in list */
2651 ea = pci_find_capability(dev, PCI_CAP_ID_EA);
2655 /* determine the number of entries */
2656 pci_bus_read_config_byte(dev->bus, dev->devfn, ea + PCI_EA_NUM_ENT,
2658 num_ent &= PCI_EA_NUM_ENT_MASK;
2660 offset = ea + PCI_EA_FIRST_ENT;
2662 /* Skip DWORD 2 for type 1 functions */
2663 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
2666 /* parse each EA entry */
2667 for (i = 0; i < num_ent; ++i)
2668 offset = pci_ea_read(dev, offset);
2671 static void pci_add_saved_cap(struct pci_dev *pci_dev,
2672 struct pci_cap_saved_state *new_cap)
2674 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
2678 * _pci_add_cap_save_buffer - allocate buffer for saving given
2679 * capability registers
2680 * @dev: the PCI device
2681 * @cap: the capability to allocate the buffer for
2682 * @extended: Standard or Extended capability ID
2683 * @size: requested size of the buffer
2685 static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap,
2686 bool extended, unsigned int size)
2689 struct pci_cap_saved_state *save_state;
2692 pos = pci_find_ext_capability(dev, cap);
2694 pos = pci_find_capability(dev, cap);
2699 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
2703 save_state->cap.cap_nr = cap;
2704 save_state->cap.cap_extended = extended;
2705 save_state->cap.size = size;
2706 pci_add_saved_cap(dev, save_state);
2711 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size)
2713 return _pci_add_cap_save_buffer(dev, cap, false, size);
2716 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size)
2718 return _pci_add_cap_save_buffer(dev, cap, true, size);
2722 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
2723 * @dev: the PCI device
2725 void pci_allocate_cap_save_buffers(struct pci_dev *dev)
2729 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
2730 PCI_EXP_SAVE_REGS * sizeof(u16));
2732 pci_err(dev, "unable to preallocate PCI Express save buffer\n");
2734 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
2736 pci_err(dev, "unable to preallocate PCI-X save buffer\n");
2738 pci_allocate_vc_save_buffers(dev);
2741 void pci_free_cap_save_buffers(struct pci_dev *dev)
2743 struct pci_cap_saved_state *tmp;
2744 struct hlist_node *n;
2746 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next)
2751 * pci_configure_ari - enable or disable ARI forwarding
2752 * @dev: the PCI device
2754 * If @dev and its upstream bridge both support ARI, enable ARI in the
2755 * bridge. Otherwise, disable ARI in the bridge.
2757 void pci_configure_ari(struct pci_dev *dev)
2760 struct pci_dev *bridge;
2762 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
2765 bridge = dev->bus->self;
2769 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
2770 if (!(cap & PCI_EXP_DEVCAP2_ARI))
2773 if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) {
2774 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
2775 PCI_EXP_DEVCTL2_ARI);
2776 bridge->ari_enabled = 1;
2778 pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2,
2779 PCI_EXP_DEVCTL2_ARI);
2780 bridge->ari_enabled = 0;
2784 static int pci_acs_enable;
2787 * pci_request_acs - ask for ACS to be enabled if supported
2789 void pci_request_acs(void)
2795 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilites
2796 * @dev: the PCI device
2798 static void pci_std_enable_acs(struct pci_dev *dev)
2804 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
2808 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
2809 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
2811 /* Source Validation */
2812 ctrl |= (cap & PCI_ACS_SV);
2814 /* P2P Request Redirect */
2815 ctrl |= (cap & PCI_ACS_RR);
2817 /* P2P Completion Redirect */
2818 ctrl |= (cap & PCI_ACS_CR);
2820 /* Upstream Forwarding */
2821 ctrl |= (cap & PCI_ACS_UF);
2823 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
2827 * pci_enable_acs - enable ACS if hardware support it
2828 * @dev: the PCI device
2830 void pci_enable_acs(struct pci_dev *dev)
2832 if (!pci_acs_enable)
2835 if (!pci_dev_specific_enable_acs(dev))
2838 pci_std_enable_acs(dev);
2841 static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags)
2846 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS);
2851 * Except for egress control, capabilities are either required
2852 * or only required if controllable. Features missing from the
2853 * capability field can therefore be assumed as hard-wired enabled.
2855 pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap);
2856 acs_flags &= (cap | PCI_ACS_EC);
2858 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
2859 return (ctrl & acs_flags) == acs_flags;
2863 * pci_acs_enabled - test ACS against required flags for a given device
2864 * @pdev: device to test
2865 * @acs_flags: required PCI ACS flags
2867 * Return true if the device supports the provided flags. Automatically
2868 * filters out flags that are not implemented on multifunction devices.
2870 * Note that this interface checks the effective ACS capabilities of the
2871 * device rather than the actual capabilities. For instance, most single
2872 * function endpoints are not required to support ACS because they have no
2873 * opportunity for peer-to-peer access. We therefore return 'true'
2874 * regardless of whether the device exposes an ACS capability. This makes
2875 * it much easier for callers of this function to ignore the actual type
2876 * or topology of the device when testing ACS support.
2878 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
2882 ret = pci_dev_specific_acs_enabled(pdev, acs_flags);
2887 * Conventional PCI and PCI-X devices never support ACS, either
2888 * effectively or actually. The shared bus topology implies that
2889 * any device on the bus can receive or snoop DMA.
2891 if (!pci_is_pcie(pdev))
2894 switch (pci_pcie_type(pdev)) {
2896 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec,
2897 * but since their primary interface is PCI/X, we conservatively
2898 * handle them as we would a non-PCIe device.
2900 case PCI_EXP_TYPE_PCIE_BRIDGE:
2902 * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never
2903 * applicable... must never implement an ACS Extended Capability...".
2904 * This seems arbitrary, but we take a conservative interpretation
2905 * of this statement.
2907 case PCI_EXP_TYPE_PCI_BRIDGE:
2908 case PCI_EXP_TYPE_RC_EC:
2911 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should
2912 * implement ACS in order to indicate their peer-to-peer capabilities,
2913 * regardless of whether they are single- or multi-function devices.
2915 case PCI_EXP_TYPE_DOWNSTREAM:
2916 case PCI_EXP_TYPE_ROOT_PORT:
2917 return pci_acs_flags_enabled(pdev, acs_flags);
2919 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be
2920 * implemented by the remaining PCIe types to indicate peer-to-peer
2921 * capabilities, but only when they are part of a multifunction
2922 * device. The footnote for section 6.12 indicates the specific
2923 * PCIe types included here.
2925 case PCI_EXP_TYPE_ENDPOINT:
2926 case PCI_EXP_TYPE_UPSTREAM:
2927 case PCI_EXP_TYPE_LEG_END:
2928 case PCI_EXP_TYPE_RC_END:
2929 if (!pdev->multifunction)
2932 return pci_acs_flags_enabled(pdev, acs_flags);
2936 * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable
2937 * to single function devices with the exception of downstream ports.
2943 * pci_acs_path_enable - test ACS flags from start to end in a hierarchy
2944 * @start: starting downstream device
2945 * @end: ending upstream device or NULL to search to the root bus
2946 * @acs_flags: required flags
2948 * Walk up a device tree from start to end testing PCI ACS support. If
2949 * any step along the way does not support the required flags, return false.
2951 bool pci_acs_path_enabled(struct pci_dev *start,
2952 struct pci_dev *end, u16 acs_flags)
2954 struct pci_dev *pdev, *parent = start;
2959 if (!pci_acs_enabled(pdev, acs_flags))
2962 if (pci_is_root_bus(pdev->bus))
2963 return (end == NULL);
2965 parent = pdev->bus->self;
2966 } while (pdev != end);
2972 * pci_rebar_find_pos - find position of resize ctrl reg for BAR
2976 * Helper to find the position of the ctrl register for a BAR.
2977 * Returns -ENOTSUPP if resizable BARs are not supported at all.
2978 * Returns -ENOENT if no ctrl register for the BAR could be found.
2980 static int pci_rebar_find_pos(struct pci_dev *pdev, int bar)
2982 unsigned int pos, nbars, i;
2985 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR);
2989 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
2990 nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >>
2991 PCI_REBAR_CTRL_NBAR_SHIFT;
2993 for (i = 0; i < nbars; i++, pos += 8) {
2996 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
2997 bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX;
3006 * pci_rebar_get_possible_sizes - get possible sizes for BAR
3008 * @bar: BAR to query
3010 * Get the possible sizes of a resizable BAR as bitmask defined in the spec
3011 * (bit 0=1MB, bit 19=512GB). Returns 0 if BAR isn't resizable.
3013 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar)
3018 pos = pci_rebar_find_pos(pdev, bar);
3022 pci_read_config_dword(pdev, pos + PCI_REBAR_CAP, &cap);
3023 return (cap & PCI_REBAR_CAP_SIZES) >> 4;
3027 * pci_rebar_get_current_size - get the current size of a BAR
3029 * @bar: BAR to set size to
3031 * Read the size of a BAR from the resizable BAR config.
3032 * Returns size if found or negative error code.
3034 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar)
3039 pos = pci_rebar_find_pos(pdev, bar);
3043 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3044 return (ctrl & PCI_REBAR_CTRL_BAR_SIZE) >> 8;
3048 * pci_rebar_set_size - set a new size for a BAR
3050 * @bar: BAR to set size to
3051 * @size: new size as defined in the spec (0=1MB, 19=512GB)
3053 * Set the new size of a BAR as defined in the spec.
3054 * Returns zero if resizing was successful, error code otherwise.
3056 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size)
3061 pos = pci_rebar_find_pos(pdev, bar);
3065 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3066 ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
3068 pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
3073 * pci_enable_atomic_ops_to_root - enable AtomicOp requests to root port
3074 * @dev: the PCI device
3075 * @cap_mask: mask of desired AtomicOp sizes, including one or more of:
3076 * PCI_EXP_DEVCAP2_ATOMIC_COMP32
3077 * PCI_EXP_DEVCAP2_ATOMIC_COMP64
3078 * PCI_EXP_DEVCAP2_ATOMIC_COMP128
3080 * Return 0 if all upstream bridges support AtomicOp routing, egress
3081 * blocking is disabled on all upstream ports, and the root port supports
3082 * the requested completion capabilities (32-bit, 64-bit and/or 128-bit
3083 * AtomicOp completion), or negative otherwise.
3085 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask)
3087 struct pci_bus *bus = dev->bus;
3088 struct pci_dev *bridge;
3091 if (!pci_is_pcie(dev))
3095 * Per PCIe r4.0, sec 6.15, endpoints and root ports may be
3096 * AtomicOp requesters. For now, we only support endpoints as
3097 * requesters and root ports as completers. No endpoints as
3098 * completers, and no peer-to-peer.
3101 switch (pci_pcie_type(dev)) {
3102 case PCI_EXP_TYPE_ENDPOINT:
3103 case PCI_EXP_TYPE_LEG_END:
3104 case PCI_EXP_TYPE_RC_END:
3110 while (bus->parent) {
3113 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
3115 switch (pci_pcie_type(bridge)) {
3116 /* Ensure switch ports support AtomicOp routing */
3117 case PCI_EXP_TYPE_UPSTREAM:
3118 case PCI_EXP_TYPE_DOWNSTREAM:
3119 if (!(cap & PCI_EXP_DEVCAP2_ATOMIC_ROUTE))
3123 /* Ensure root port supports all the sizes we care about */
3124 case PCI_EXP_TYPE_ROOT_PORT:
3125 if ((cap & cap_mask) != cap_mask)
3130 /* Ensure upstream ports don't block AtomicOps on egress */
3131 if (!bridge->has_secondary_link) {
3132 pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2,
3134 if (ctl2 & PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK)
3141 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
3142 PCI_EXP_DEVCTL2_ATOMIC_REQ);
3145 EXPORT_SYMBOL(pci_enable_atomic_ops_to_root);
3148 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
3149 * @dev: the PCI device
3150 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
3152 * Perform INTx swizzling for a device behind one level of bridge. This is
3153 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
3154 * behind bridges on add-in cards. For devices with ARI enabled, the slot
3155 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
3156 * the PCI Express Base Specification, Revision 2.1)
3158 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
3162 if (pci_ari_enabled(dev->bus))
3165 slot = PCI_SLOT(dev->devfn);
3167 return (((pin - 1) + slot) % 4) + 1;
3170 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
3178 while (!pci_is_root_bus(dev->bus)) {
3179 pin = pci_swizzle_interrupt_pin(dev, pin);
3180 dev = dev->bus->self;
3187 * pci_common_swizzle - swizzle INTx all the way to root bridge
3188 * @dev: the PCI device
3189 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
3191 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
3192 * bridges all the way up to a PCI root bus.
3194 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
3198 while (!pci_is_root_bus(dev->bus)) {
3199 pin = pci_swizzle_interrupt_pin(dev, pin);
3200 dev = dev->bus->self;
3203 return PCI_SLOT(dev->devfn);
3205 EXPORT_SYMBOL_GPL(pci_common_swizzle);
3208 * pci_release_region - Release a PCI bar
3209 * @pdev: PCI device whose resources were previously reserved by pci_request_region
3210 * @bar: BAR to release
3212 * Releases the PCI I/O and memory resources previously reserved by a
3213 * successful call to pci_request_region. Call this function only
3214 * after all use of the PCI regions has ceased.
3216 void pci_release_region(struct pci_dev *pdev, int bar)
3218 struct pci_devres *dr;
3220 if (pci_resource_len(pdev, bar) == 0)
3222 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
3223 release_region(pci_resource_start(pdev, bar),
3224 pci_resource_len(pdev, bar));
3225 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
3226 release_mem_region(pci_resource_start(pdev, bar),
3227 pci_resource_len(pdev, bar));
3229 dr = find_pci_dr(pdev);
3231 dr->region_mask &= ~(1 << bar);
3233 EXPORT_SYMBOL(pci_release_region);
3236 * __pci_request_region - Reserved PCI I/O and memory resource
3237 * @pdev: PCI device whose resources are to be reserved
3238 * @bar: BAR to be reserved
3239 * @res_name: Name to be associated with resource.
3240 * @exclusive: whether the region access is exclusive or not
3242 * Mark the PCI region associated with PCI device @pdev BR @bar as
3243 * being reserved by owner @res_name. Do not access any
3244 * address inside the PCI regions unless this call returns
3247 * If @exclusive is set, then the region is marked so that userspace
3248 * is explicitly not allowed to map the resource via /dev/mem or
3249 * sysfs MMIO access.
3251 * Returns 0 on success, or %EBUSY on error. A warning
3252 * message is also printed on failure.
3254 static int __pci_request_region(struct pci_dev *pdev, int bar,
3255 const char *res_name, int exclusive)
3257 struct pci_devres *dr;
3259 if (pci_resource_len(pdev, bar) == 0)
3262 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
3263 if (!request_region(pci_resource_start(pdev, bar),
3264 pci_resource_len(pdev, bar), res_name))
3266 } else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
3267 if (!__request_mem_region(pci_resource_start(pdev, bar),
3268 pci_resource_len(pdev, bar), res_name,
3273 dr = find_pci_dr(pdev);
3275 dr->region_mask |= 1 << bar;
3280 pci_warn(pdev, "BAR %d: can't reserve %pR\n", bar,
3281 &pdev->resource[bar]);
3286 * pci_request_region - Reserve PCI I/O and memory resource
3287 * @pdev: PCI device whose resources are to be reserved
3288 * @bar: BAR to be reserved
3289 * @res_name: Name to be associated with resource
3291 * Mark the PCI region associated with PCI device @pdev BAR @bar as
3292 * being reserved by owner @res_name. Do not access any
3293 * address inside the PCI regions unless this call returns
3296 * Returns 0 on success, or %EBUSY on error. A warning
3297 * message is also printed on failure.
3299 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
3301 return __pci_request_region(pdev, bar, res_name, 0);
3303 EXPORT_SYMBOL(pci_request_region);
3306 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
3307 * @pdev: PCI device whose resources are to be reserved
3308 * @bar: BAR to be reserved
3309 * @res_name: Name to be associated with resource.
3311 * Mark the PCI region associated with PCI device @pdev BR @bar as
3312 * being reserved by owner @res_name. Do not access any
3313 * address inside the PCI regions unless this call returns
3316 * Returns 0 on success, or %EBUSY on error. A warning
3317 * message is also printed on failure.
3319 * The key difference that _exclusive makes it that userspace is
3320 * explicitly not allowed to map the resource via /dev/mem or
3323 int pci_request_region_exclusive(struct pci_dev *pdev, int bar,
3324 const char *res_name)
3326 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
3328 EXPORT_SYMBOL(pci_request_region_exclusive);
3331 * pci_release_selected_regions - Release selected PCI I/O and memory resources
3332 * @pdev: PCI device whose resources were previously reserved
3333 * @bars: Bitmask of BARs to be released
3335 * Release selected PCI I/O and memory resources previously reserved.
3336 * Call this function only after all use of the PCI regions has ceased.
3338 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
3342 for (i = 0; i < 6; i++)
3343 if (bars & (1 << i))
3344 pci_release_region(pdev, i);
3346 EXPORT_SYMBOL(pci_release_selected_regions);
3348 static int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
3349 const char *res_name, int excl)
3353 for (i = 0; i < 6; i++)
3354 if (bars & (1 << i))
3355 if (__pci_request_region(pdev, i, res_name, excl))
3361 if (bars & (1 << i))
3362 pci_release_region(pdev, i);
3369 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
3370 * @pdev: PCI device whose resources are to be reserved
3371 * @bars: Bitmask of BARs to be requested
3372 * @res_name: Name to be associated with resource
3374 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
3375 const char *res_name)
3377 return __pci_request_selected_regions(pdev, bars, res_name, 0);
3379 EXPORT_SYMBOL(pci_request_selected_regions);
3381 int pci_request_selected_regions_exclusive(struct pci_dev *pdev, int bars,
3382 const char *res_name)
3384 return __pci_request_selected_regions(pdev, bars, res_name,
3385 IORESOURCE_EXCLUSIVE);
3387 EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
3390 * pci_release_regions - Release reserved PCI I/O and memory resources
3391 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
3393 * Releases all PCI I/O and memory resources previously reserved by a
3394 * successful call to pci_request_regions. Call this function only
3395 * after all use of the PCI regions has ceased.
3398 void pci_release_regions(struct pci_dev *pdev)
3400 pci_release_selected_regions(pdev, (1 << 6) - 1);
3402 EXPORT_SYMBOL(pci_release_regions);
3405 * pci_request_regions - Reserved PCI I/O and memory resources
3406 * @pdev: PCI device whose resources are to be reserved
3407 * @res_name: Name to be associated with resource.
3409 * Mark all PCI regions associated with PCI device @pdev as
3410 * being reserved by owner @res_name. Do not access any
3411 * address inside the PCI regions unless this call returns
3414 * Returns 0 on success, or %EBUSY on error. A warning
3415 * message is also printed on failure.
3417 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
3419 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
3421 EXPORT_SYMBOL(pci_request_regions);
3424 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
3425 * @pdev: PCI device whose resources are to be reserved
3426 * @res_name: Name to be associated with resource.
3428 * Mark all PCI regions associated with PCI device @pdev as
3429 * being reserved by owner @res_name. Do not access any
3430 * address inside the PCI regions unless this call returns
3433 * pci_request_regions_exclusive() will mark the region so that
3434 * /dev/mem and the sysfs MMIO access will not be allowed.
3436 * Returns 0 on success, or %EBUSY on error. A warning
3437 * message is also printed on failure.
3439 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
3441 return pci_request_selected_regions_exclusive(pdev,
3442 ((1 << 6) - 1), res_name);
3444 EXPORT_SYMBOL(pci_request_regions_exclusive);
3448 struct list_head list;
3450 resource_size_t size;
3453 static LIST_HEAD(io_range_list);
3454 static DEFINE_SPINLOCK(io_range_lock);
3458 * Record the PCI IO range (expressed as CPU physical address + size).
3459 * Return a negative value if an error has occured, zero otherwise
3461 int __weak pci_register_io_range(phys_addr_t addr, resource_size_t size)
3466 struct io_range *range;
3467 resource_size_t allocated_size = 0;
3469 /* check if the range hasn't been previously recorded */
3470 spin_lock(&io_range_lock);
3471 list_for_each_entry(range, &io_range_list, list) {
3472 if (addr >= range->start && addr + size <= range->start + size) {
3473 /* range already registered, bail out */
3476 allocated_size += range->size;
3479 /* range not registed yet, check for available space */
3480 if (allocated_size + size - 1 > IO_SPACE_LIMIT) {
3481 /* if it's too big check if 64K space can be reserved */
3482 if (allocated_size + SZ_64K - 1 > IO_SPACE_LIMIT) {
3488 pr_warn("Requested IO range too big, new size set to 64K\n");
3491 /* add the range to the list */
3492 range = kzalloc(sizeof(*range), GFP_ATOMIC);
3498 range->start = addr;
3501 list_add_tail(&range->list, &io_range_list);
3504 spin_unlock(&io_range_lock);
3510 phys_addr_t pci_pio_to_address(unsigned long pio)
3512 phys_addr_t address = (phys_addr_t)OF_BAD_ADDR;
3515 struct io_range *range;
3516 resource_size_t allocated_size = 0;
3518 if (pio > IO_SPACE_LIMIT)
3521 spin_lock(&io_range_lock);
3522 list_for_each_entry(range, &io_range_list, list) {
3523 if (pio >= allocated_size && pio < allocated_size + range->size) {
3524 address = range->start + pio - allocated_size;
3527 allocated_size += range->size;
3529 spin_unlock(&io_range_lock);
3535 unsigned long __weak pci_address_to_pio(phys_addr_t address)
3538 struct io_range *res;
3539 resource_size_t offset = 0;
3540 unsigned long addr = -1;
3542 spin_lock(&io_range_lock);
3543 list_for_each_entry(res, &io_range_list, list) {
3544 if (address >= res->start && address < res->start + res->size) {
3545 addr = address - res->start + offset;
3548 offset += res->size;
3550 spin_unlock(&io_range_lock);
3554 if (address > IO_SPACE_LIMIT)
3555 return (unsigned long)-1;
3557 return (unsigned long) address;
3562 * pci_remap_iospace - Remap the memory mapped I/O space
3563 * @res: Resource describing the I/O space
3564 * @phys_addr: physical address of range to be mapped
3566 * Remap the memory mapped I/O space described by the @res
3567 * and the CPU physical address @phys_addr into virtual address space.
3568 * Only architectures that have memory mapped IO functions defined
3569 * (and the PCI_IOBASE value defined) should call this function.
3571 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr)
3573 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
3574 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
3576 if (!(res->flags & IORESOURCE_IO))
3579 if (res->end > IO_SPACE_LIMIT)
3582 return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr,
3583 pgprot_device(PAGE_KERNEL));
3585 /* this architecture does not have memory mapped I/O space,
3586 so this function should never be called */
3587 WARN_ONCE(1, "This architecture does not support memory mapped I/O\n");
3591 EXPORT_SYMBOL(pci_remap_iospace);
3594 * pci_unmap_iospace - Unmap the memory mapped I/O space
3595 * @res: resource to be unmapped
3597 * Unmap the CPU virtual address @res from virtual address space.
3598 * Only architectures that have memory mapped IO functions defined
3599 * (and the PCI_IOBASE value defined) should call this function.
3601 void pci_unmap_iospace(struct resource *res)
3603 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
3604 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
3606 unmap_kernel_range(vaddr, resource_size(res));
3609 EXPORT_SYMBOL(pci_unmap_iospace);
3612 * devm_pci_remap_cfgspace - Managed pci_remap_cfgspace()
3613 * @dev: Generic device to remap IO address for
3614 * @offset: Resource address to map
3615 * @size: Size of map
3617 * Managed pci_remap_cfgspace(). Map is automatically unmapped on driver
3620 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
3621 resource_size_t offset,
3622 resource_size_t size)
3624 void __iomem **ptr, *addr;
3626 ptr = devres_alloc(devm_ioremap_release, sizeof(*ptr), GFP_KERNEL);
3630 addr = pci_remap_cfgspace(offset, size);
3633 devres_add(dev, ptr);
3639 EXPORT_SYMBOL(devm_pci_remap_cfgspace);
3642 * devm_pci_remap_cfg_resource - check, request region and ioremap cfg resource
3643 * @dev: generic device to handle the resource for
3644 * @res: configuration space resource to be handled
3646 * Checks that a resource is a valid memory region, requests the memory
3647 * region and ioremaps with pci_remap_cfgspace() API that ensures the
3648 * proper PCI configuration space memory attributes are guaranteed.
3650 * All operations are managed and will be undone on driver detach.
3652 * Returns a pointer to the remapped memory or an ERR_PTR() encoded error code
3653 * on failure. Usage example::
3655 * res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3656 * base = devm_pci_remap_cfg_resource(&pdev->dev, res);
3658 * return PTR_ERR(base);
3660 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
3661 struct resource *res)
3663 resource_size_t size;
3665 void __iomem *dest_ptr;
3669 if (!res || resource_type(res) != IORESOURCE_MEM) {
3670 dev_err(dev, "invalid resource\n");
3671 return IOMEM_ERR_PTR(-EINVAL);
3674 size = resource_size(res);
3675 name = res->name ?: dev_name(dev);
3677 if (!devm_request_mem_region(dev, res->start, size, name)) {
3678 dev_err(dev, "can't request region for resource %pR\n", res);
3679 return IOMEM_ERR_PTR(-EBUSY);
3682 dest_ptr = devm_pci_remap_cfgspace(dev, res->start, size);
3684 dev_err(dev, "ioremap failed for resource %pR\n", res);
3685 devm_release_mem_region(dev, res->start, size);
3686 dest_ptr = IOMEM_ERR_PTR(-ENOMEM);
3691 EXPORT_SYMBOL(devm_pci_remap_cfg_resource);
3693 static void __pci_set_master(struct pci_dev *dev, bool enable)
3697 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
3699 cmd = old_cmd | PCI_COMMAND_MASTER;
3701 cmd = old_cmd & ~PCI_COMMAND_MASTER;
3702 if (cmd != old_cmd) {
3703 pci_dbg(dev, "%s bus mastering\n",
3704 enable ? "enabling" : "disabling");
3705 pci_write_config_word(dev, PCI_COMMAND, cmd);
3707 dev->is_busmaster = enable;
3711 * pcibios_setup - process "pci=" kernel boot arguments
3712 * @str: string used to pass in "pci=" kernel boot arguments
3714 * Process kernel boot arguments. This is the default implementation.
3715 * Architecture specific implementations can override this as necessary.
3717 char * __weak __init pcibios_setup(char *str)
3723 * pcibios_set_master - enable PCI bus-mastering for device dev
3724 * @dev: the PCI device to enable
3726 * Enables PCI bus-mastering for the device. This is the default
3727 * implementation. Architecture specific implementations can override
3728 * this if necessary.
3730 void __weak pcibios_set_master(struct pci_dev *dev)
3734 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
3735 if (pci_is_pcie(dev))
3738 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
3740 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
3741 else if (lat > pcibios_max_latency)
3742 lat = pcibios_max_latency;
3746 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
3750 * pci_set_master - enables bus-mastering for device dev
3751 * @dev: the PCI device to enable
3753 * Enables bus-mastering on the device and calls pcibios_set_master()
3754 * to do the needed arch specific settings.
3756 void pci_set_master(struct pci_dev *dev)
3758 __pci_set_master(dev, true);
3759 pcibios_set_master(dev);
3761 EXPORT_SYMBOL(pci_set_master);
3764 * pci_clear_master - disables bus-mastering for device dev
3765 * @dev: the PCI device to disable
3767 void pci_clear_master(struct pci_dev *dev)
3769 __pci_set_master(dev, false);
3771 EXPORT_SYMBOL(pci_clear_master);
3774 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
3775 * @dev: the PCI device for which MWI is to be enabled
3777 * Helper function for pci_set_mwi.
3778 * Originally copied from drivers/net/acenic.c.
3779 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
3781 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3783 int pci_set_cacheline_size(struct pci_dev *dev)
3787 if (!pci_cache_line_size)
3790 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
3791 equal to or multiple of the right value. */
3792 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
3793 if (cacheline_size >= pci_cache_line_size &&
3794 (cacheline_size % pci_cache_line_size) == 0)
3797 /* Write the correct value. */
3798 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
3800 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
3801 if (cacheline_size == pci_cache_line_size)
3804 pci_printk(KERN_DEBUG, dev, "cache line size of %d is not supported\n",
3805 pci_cache_line_size << 2);
3809 EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
3812 * pci_set_mwi - enables memory-write-invalidate PCI transaction
3813 * @dev: the PCI device for which MWI is enabled
3815 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
3817 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3819 int pci_set_mwi(struct pci_dev *dev)
3821 #ifdef PCI_DISABLE_MWI
3827 rc = pci_set_cacheline_size(dev);
3831 pci_read_config_word(dev, PCI_COMMAND, &cmd);
3832 if (!(cmd & PCI_COMMAND_INVALIDATE)) {
3833 pci_dbg(dev, "enabling Mem-Wr-Inval\n");
3834 cmd |= PCI_COMMAND_INVALIDATE;
3835 pci_write_config_word(dev, PCI_COMMAND, cmd);
3840 EXPORT_SYMBOL(pci_set_mwi);
3843 * pcim_set_mwi - a device-managed pci_set_mwi()
3844 * @dev: the PCI device for which MWI is enabled
3846 * Managed pci_set_mwi().
3848 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3850 int pcim_set_mwi(struct pci_dev *dev)
3852 struct pci_devres *dr;
3854 dr = find_pci_dr(dev);
3859 return pci_set_mwi(dev);
3861 EXPORT_SYMBOL(pcim_set_mwi);
3864 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
3865 * @dev: the PCI device for which MWI is enabled
3867 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
3868 * Callers are not required to check the return value.
3870 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3872 int pci_try_set_mwi(struct pci_dev *dev)
3874 #ifdef PCI_DISABLE_MWI
3877 return pci_set_mwi(dev);
3880 EXPORT_SYMBOL(pci_try_set_mwi);
3883 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
3884 * @dev: the PCI device to disable
3886 * Disables PCI Memory-Write-Invalidate transaction on the device
3888 void pci_clear_mwi(struct pci_dev *dev)
3890 #ifndef PCI_DISABLE_MWI
3893 pci_read_config_word(dev, PCI_COMMAND, &cmd);
3894 if (cmd & PCI_COMMAND_INVALIDATE) {
3895 cmd &= ~PCI_COMMAND_INVALIDATE;
3896 pci_write_config_word(dev, PCI_COMMAND, cmd);
3900 EXPORT_SYMBOL(pci_clear_mwi);
3903 * pci_intx - enables/disables PCI INTx for device dev
3904 * @pdev: the PCI device to operate on
3905 * @enable: boolean: whether to enable or disable PCI INTx
3907 * Enables/disables PCI INTx for device dev
3909 void pci_intx(struct pci_dev *pdev, int enable)
3911 u16 pci_command, new;
3913 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
3916 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
3918 new = pci_command | PCI_COMMAND_INTX_DISABLE;
3920 if (new != pci_command) {
3921 struct pci_devres *dr;
3923 pci_write_config_word(pdev, PCI_COMMAND, new);
3925 dr = find_pci_dr(pdev);
3926 if (dr && !dr->restore_intx) {
3927 dr->restore_intx = 1;
3928 dr->orig_intx = !enable;
3932 EXPORT_SYMBOL_GPL(pci_intx);
3934 static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
3936 struct pci_bus *bus = dev->bus;
3937 bool mask_updated = true;
3938 u32 cmd_status_dword;
3939 u16 origcmd, newcmd;
3940 unsigned long flags;
3944 * We do a single dword read to retrieve both command and status.
3945 * Document assumptions that make this possible.
3947 BUILD_BUG_ON(PCI_COMMAND % 4);
3948 BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
3950 raw_spin_lock_irqsave(&pci_lock, flags);
3952 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
3954 irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
3957 * Check interrupt status register to see whether our device
3958 * triggered the interrupt (when masking) or the next IRQ is
3959 * already pending (when unmasking).
3961 if (mask != irq_pending) {
3962 mask_updated = false;
3966 origcmd = cmd_status_dword;
3967 newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
3969 newcmd |= PCI_COMMAND_INTX_DISABLE;
3970 if (newcmd != origcmd)
3971 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
3974 raw_spin_unlock_irqrestore(&pci_lock, flags);
3976 return mask_updated;
3980 * pci_check_and_mask_intx - mask INTx on pending interrupt
3981 * @dev: the PCI device to operate on
3983 * Check if the device dev has its INTx line asserted, mask it and
3984 * return true in that case. False is returned if no interrupt was
3987 bool pci_check_and_mask_intx(struct pci_dev *dev)
3989 return pci_check_and_set_intx_mask(dev, true);
3991 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
3994 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
3995 * @dev: the PCI device to operate on
3997 * Check if the device dev has its INTx line asserted, unmask it if not
3998 * and return true. False is returned and the mask remains active if
3999 * there was still an interrupt pending.
4001 bool pci_check_and_unmask_intx(struct pci_dev *dev)
4003 return pci_check_and_set_intx_mask(dev, false);
4005 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
4008 * pci_wait_for_pending_transaction - waits for pending transaction
4009 * @dev: the PCI device to operate on
4011 * Return 0 if transaction is pending 1 otherwise.
4013 int pci_wait_for_pending_transaction(struct pci_dev *dev)
4015 if (!pci_is_pcie(dev))
4018 return pci_wait_for_pending(dev, pci_pcie_cap(dev) + PCI_EXP_DEVSTA,
4019 PCI_EXP_DEVSTA_TRPND);
4021 EXPORT_SYMBOL(pci_wait_for_pending_transaction);
4023 static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout)
4029 * After reset, the device should not silently discard config
4030 * requests, but it may still indicate that it needs more time by
4031 * responding to them with CRS completions. The Root Port will
4032 * generally synthesize ~0 data to complete the read (except when
4033 * CRS SV is enabled and the read was for the Vendor ID; in that
4034 * case it synthesizes 0x0001 data).
4036 * Wait for the device to return a non-CRS completion. Read the
4037 * Command register instead of Vendor ID so we don't have to
4038 * contend with the CRS SV value.
4040 pci_read_config_dword(dev, PCI_COMMAND, &id);
4042 if (delay > timeout) {
4043 pci_warn(dev, "not ready %dms after %s; giving up\n",
4044 delay - 1, reset_type);
4049 pci_info(dev, "not ready %dms after %s; waiting\n",
4050 delay - 1, reset_type);
4054 pci_read_config_dword(dev, PCI_COMMAND, &id);
4058 pci_info(dev, "ready %dms after %s\n", delay - 1,
4065 * pcie_has_flr - check if a device supports function level resets
4066 * @dev: device to check
4068 * Returns true if the device advertises support for PCIe function level
4071 static bool pcie_has_flr(struct pci_dev *dev)
4075 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
4078 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
4079 return cap & PCI_EXP_DEVCAP_FLR;
4083 * pcie_flr - initiate a PCIe function level reset
4084 * @dev: device to reset
4086 * Initiate a function level reset on @dev. The caller should ensure the
4087 * device supports FLR before calling this function, e.g. by using the
4088 * pcie_has_flr() helper.
4090 int pcie_flr(struct pci_dev *dev)
4092 if (!pci_wait_for_pending_transaction(dev))
4093 pci_err(dev, "timed out waiting for pending transaction; performing function level reset anyway\n");
4095 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
4098 * Per PCIe r4.0, sec 6.6.2, a device must complete an FLR within
4099 * 100ms, but may silently discard requests while the FLR is in
4100 * progress. Wait 100ms before trying to access the device.
4104 return pci_dev_wait(dev, "FLR", PCIE_RESET_READY_POLL_MS);
4106 EXPORT_SYMBOL_GPL(pcie_flr);
4108 static int pci_af_flr(struct pci_dev *dev, int probe)
4113 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
4117 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
4120 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
4121 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
4128 * Wait for Transaction Pending bit to clear. A word-aligned test
4129 * is used, so we use the conrol offset rather than status and shift
4130 * the test bit to match.
4132 if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL,
4133 PCI_AF_STATUS_TP << 8))
4134 pci_err(dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n");
4136 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
4139 * Per Advanced Capabilities for Conventional PCI ECN, 13 April 2006,
4140 * updated 27 July 2006; a device must complete an FLR within
4141 * 100ms, but may silently discard requests while the FLR is in
4142 * progress. Wait 100ms before trying to access the device.
4146 return pci_dev_wait(dev, "AF_FLR", PCIE_RESET_READY_POLL_MS);
4150 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
4151 * @dev: Device to reset.
4152 * @probe: If set, only check if the device can be reset this way.
4154 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
4155 * unset, it will be reinitialized internally when going from PCI_D3hot to
4156 * PCI_D0. If that's the case and the device is not in a low-power state
4157 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
4159 * NOTE: This causes the caller to sleep for twice the device power transition
4160 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
4161 * by default (i.e. unless the @dev's d3_delay field has a different value).
4162 * Moreover, only devices in D0 can be reset by this function.
4164 static int pci_pm_reset(struct pci_dev *dev, int probe)
4168 if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET)
4171 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
4172 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
4178 if (dev->current_state != PCI_D0)
4181 csr &= ~PCI_PM_CTRL_STATE_MASK;
4183 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
4184 pci_dev_d3_sleep(dev);
4186 csr &= ~PCI_PM_CTRL_STATE_MASK;
4188 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
4189 pci_dev_d3_sleep(dev);
4191 return pci_dev_wait(dev, "PM D3->D0", PCIE_RESET_READY_POLL_MS);
4194 void pci_reset_secondary_bus(struct pci_dev *dev)
4198 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
4199 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
4200 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
4202 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
4203 * this to 2ms to ensure that we meet the minimum requirement.
4207 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
4208 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
4211 * Trhfa for conventional PCI is 2^25 clock cycles.
4212 * Assuming a minimum 33MHz clock this results in a 1s
4213 * delay before we can consider subordinate devices to
4214 * be re-initialized. PCIe has some ways to shorten this,
4215 * but we don't make use of them yet.
4220 void __weak pcibios_reset_secondary_bus(struct pci_dev *dev)
4222 pci_reset_secondary_bus(dev);
4226 * pci_reset_bridge_secondary_bus - Reset the secondary bus on a PCI bridge.
4227 * @dev: Bridge device
4229 * Use the bridge control register to assert reset on the secondary bus.
4230 * Devices on the secondary bus are left in power-on state.
4232 void pci_reset_bridge_secondary_bus(struct pci_dev *dev)
4234 pcibios_reset_secondary_bus(dev);
4236 EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus);
4238 static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
4240 struct pci_dev *pdev;
4242 if (pci_is_root_bus(dev->bus) || dev->subordinate ||
4243 !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
4246 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
4253 pci_reset_bridge_secondary_bus(dev->bus->self);
4258 static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe)
4262 if (!hotplug || !try_module_get(hotplug->ops->owner))
4265 if (hotplug->ops->reset_slot)
4266 rc = hotplug->ops->reset_slot(hotplug, probe);
4268 module_put(hotplug->ops->owner);
4273 static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe)
4275 struct pci_dev *pdev;
4277 if (dev->subordinate || !dev->slot ||
4278 dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
4281 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
4282 if (pdev != dev && pdev->slot == dev->slot)
4285 return pci_reset_hotplug_slot(dev->slot->hotplug, probe);
4288 static void pci_dev_lock(struct pci_dev *dev)
4290 pci_cfg_access_lock(dev);
4291 /* block PM suspend, driver probe, etc. */
4292 device_lock(&dev->dev);
4295 /* Return 1 on successful lock, 0 on contention */
4296 static int pci_dev_trylock(struct pci_dev *dev)
4298 if (pci_cfg_access_trylock(dev)) {
4299 if (device_trylock(&dev->dev))
4301 pci_cfg_access_unlock(dev);
4307 static void pci_dev_unlock(struct pci_dev *dev)
4309 device_unlock(&dev->dev);
4310 pci_cfg_access_unlock(dev);
4313 static void pci_dev_save_and_disable(struct pci_dev *dev)
4315 const struct pci_error_handlers *err_handler =
4316 dev->driver ? dev->driver->err_handler : NULL;
4319 * dev->driver->err_handler->reset_prepare() is protected against
4320 * races with ->remove() by the device lock, which must be held by
4323 if (err_handler && err_handler->reset_prepare)
4324 err_handler->reset_prepare(dev);
4327 * Wake-up device prior to save. PM registers default to D0 after
4328 * reset and a simple register restore doesn't reliably return
4329 * to a non-D0 state anyway.
4331 pci_set_power_state(dev, PCI_D0);
4333 pci_save_state(dev);
4335 * Disable the device by clearing the Command register, except for
4336 * INTx-disable which is set. This not only disables MMIO and I/O port
4337 * BARs, but also prevents the device from being Bus Master, preventing
4338 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3
4339 * compliant devices, INTx-disable prevents legacy interrupts.
4341 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
4344 static void pci_dev_restore(struct pci_dev *dev)
4346 const struct pci_error_handlers *err_handler =
4347 dev->driver ? dev->driver->err_handler : NULL;
4349 pci_restore_state(dev);
4352 * dev->driver->err_handler->reset_done() is protected against
4353 * races with ->remove() by the device lock, which must be held by
4356 if (err_handler && err_handler->reset_done)
4357 err_handler->reset_done(dev);
4361 * __pci_reset_function_locked - reset a PCI device function while holding
4362 * the @dev mutex lock.
4363 * @dev: PCI device to reset
4365 * Some devices allow an individual function to be reset without affecting
4366 * other functions in the same device. The PCI device must be responsive
4367 * to PCI config space in order to use this function.
4369 * The device function is presumed to be unused and the caller is holding
4370 * the device mutex lock when this function is called.
4371 * Resetting the device will make the contents of PCI configuration space
4372 * random, so any caller of this must be prepared to reinitialise the
4373 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
4376 * Returns 0 if the device function was successfully reset or negative if the
4377 * device doesn't support resetting a single function.
4379 int __pci_reset_function_locked(struct pci_dev *dev)
4386 * A reset method returns -ENOTTY if it doesn't support this device
4387 * and we should try the next method.
4389 * If it returns 0 (success), we're finished. If it returns any
4390 * other error, we're also finished: this indicates that further
4391 * reset mechanisms might be broken on the device.
4393 rc = pci_dev_specific_reset(dev, 0);
4396 if (pcie_has_flr(dev)) {
4401 rc = pci_af_flr(dev, 0);
4404 rc = pci_pm_reset(dev, 0);
4407 rc = pci_dev_reset_slot_function(dev, 0);
4410 return pci_parent_bus_reset(dev, 0);
4412 EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
4415 * pci_probe_reset_function - check whether the device can be safely reset
4416 * @dev: PCI device to reset
4418 * Some devices allow an individual function to be reset without affecting
4419 * other functions in the same device. The PCI device must be responsive
4420 * to PCI config space in order to use this function.
4422 * Returns 0 if the device function can be reset or negative if the
4423 * device doesn't support resetting a single function.
4425 int pci_probe_reset_function(struct pci_dev *dev)
4431 rc = pci_dev_specific_reset(dev, 1);
4434 if (pcie_has_flr(dev))
4436 rc = pci_af_flr(dev, 1);
4439 rc = pci_pm_reset(dev, 1);
4442 rc = pci_dev_reset_slot_function(dev, 1);
4446 return pci_parent_bus_reset(dev, 1);
4450 * pci_reset_function - quiesce and reset a PCI device function
4451 * @dev: PCI device to reset
4453 * Some devices allow an individual function to be reset without affecting
4454 * other functions in the same device. The PCI device must be responsive
4455 * to PCI config space in order to use this function.
4457 * This function does not just reset the PCI portion of a device, but
4458 * clears all the state associated with the device. This function differs
4459 * from __pci_reset_function_locked() in that it saves and restores device state
4460 * over the reset and takes the PCI device lock.
4462 * Returns 0 if the device function was successfully reset or negative if the
4463 * device doesn't support resetting a single function.
4465 int pci_reset_function(struct pci_dev *dev)
4473 pci_dev_save_and_disable(dev);
4475 rc = __pci_reset_function_locked(dev);
4477 pci_dev_restore(dev);
4478 pci_dev_unlock(dev);
4482 EXPORT_SYMBOL_GPL(pci_reset_function);
4485 * pci_reset_function_locked - quiesce and reset a PCI device function
4486 * @dev: PCI device to reset
4488 * Some devices allow an individual function to be reset without affecting
4489 * other functions in the same device. The PCI device must be responsive
4490 * to PCI config space in order to use this function.
4492 * This function does not just reset the PCI portion of a device, but
4493 * clears all the state associated with the device. This function differs
4494 * from __pci_reset_function_locked() in that it saves and restores device state
4495 * over the reset. It also differs from pci_reset_function() in that it
4496 * requires the PCI device lock to be held.
4498 * Returns 0 if the device function was successfully reset or negative if the
4499 * device doesn't support resetting a single function.
4501 int pci_reset_function_locked(struct pci_dev *dev)
4508 pci_dev_save_and_disable(dev);
4510 rc = __pci_reset_function_locked(dev);
4512 pci_dev_restore(dev);
4516 EXPORT_SYMBOL_GPL(pci_reset_function_locked);
4519 * pci_try_reset_function - quiesce and reset a PCI device function
4520 * @dev: PCI device to reset
4522 * Same as above, except return -EAGAIN if unable to lock device.
4524 int pci_try_reset_function(struct pci_dev *dev)
4531 if (!pci_dev_trylock(dev))
4534 pci_dev_save_and_disable(dev);
4535 rc = __pci_reset_function_locked(dev);
4536 pci_dev_restore(dev);
4537 pci_dev_unlock(dev);
4541 EXPORT_SYMBOL_GPL(pci_try_reset_function);
4543 /* Do any devices on or below this bus prevent a bus reset? */
4544 static bool pci_bus_resetable(struct pci_bus *bus)
4546 struct pci_dev *dev;
4549 if (bus->self && (bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))
4552 list_for_each_entry(dev, &bus->devices, bus_list) {
4553 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
4554 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
4561 /* Lock devices from the top of the tree down */
4562 static void pci_bus_lock(struct pci_bus *bus)
4564 struct pci_dev *dev;
4566 list_for_each_entry(dev, &bus->devices, bus_list) {
4568 if (dev->subordinate)
4569 pci_bus_lock(dev->subordinate);
4573 /* Unlock devices from the bottom of the tree up */
4574 static void pci_bus_unlock(struct pci_bus *bus)
4576 struct pci_dev *dev;
4578 list_for_each_entry(dev, &bus->devices, bus_list) {
4579 if (dev->subordinate)
4580 pci_bus_unlock(dev->subordinate);
4581 pci_dev_unlock(dev);
4585 /* Return 1 on successful lock, 0 on contention */
4586 static int pci_bus_trylock(struct pci_bus *bus)
4588 struct pci_dev *dev;
4590 list_for_each_entry(dev, &bus->devices, bus_list) {
4591 if (!pci_dev_trylock(dev))
4593 if (dev->subordinate) {
4594 if (!pci_bus_trylock(dev->subordinate)) {
4595 pci_dev_unlock(dev);
4603 list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) {
4604 if (dev->subordinate)
4605 pci_bus_unlock(dev->subordinate);
4606 pci_dev_unlock(dev);
4611 /* Do any devices on or below this slot prevent a bus reset? */
4612 static bool pci_slot_resetable(struct pci_slot *slot)
4614 struct pci_dev *dev;
4616 if (slot->bus->self &&
4617 (slot->bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))
4620 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4621 if (!dev->slot || dev->slot != slot)
4623 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
4624 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
4631 /* Lock devices from the top of the tree down */
4632 static void pci_slot_lock(struct pci_slot *slot)
4634 struct pci_dev *dev;
4636 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4637 if (!dev->slot || dev->slot != slot)
4640 if (dev->subordinate)
4641 pci_bus_lock(dev->subordinate);
4645 /* Unlock devices from the bottom of the tree up */
4646 static void pci_slot_unlock(struct pci_slot *slot)
4648 struct pci_dev *dev;
4650 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4651 if (!dev->slot || dev->slot != slot)
4653 if (dev->subordinate)
4654 pci_bus_unlock(dev->subordinate);
4655 pci_dev_unlock(dev);
4659 /* Return 1 on successful lock, 0 on contention */
4660 static int pci_slot_trylock(struct pci_slot *slot)
4662 struct pci_dev *dev;
4664 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4665 if (!dev->slot || dev->slot != slot)
4667 if (!pci_dev_trylock(dev))
4669 if (dev->subordinate) {
4670 if (!pci_bus_trylock(dev->subordinate)) {
4671 pci_dev_unlock(dev);
4679 list_for_each_entry_continue_reverse(dev,
4680 &slot->bus->devices, bus_list) {
4681 if (!dev->slot || dev->slot != slot)
4683 if (dev->subordinate)
4684 pci_bus_unlock(dev->subordinate);
4685 pci_dev_unlock(dev);
4690 /* Save and disable devices from the top of the tree down */
4691 static void pci_bus_save_and_disable(struct pci_bus *bus)
4693 struct pci_dev *dev;
4695 list_for_each_entry(dev, &bus->devices, bus_list) {
4697 pci_dev_save_and_disable(dev);
4698 pci_dev_unlock(dev);
4699 if (dev->subordinate)
4700 pci_bus_save_and_disable(dev->subordinate);
4705 * Restore devices from top of the tree down - parent bridges need to be
4706 * restored before we can get to subordinate devices.
4708 static void pci_bus_restore(struct pci_bus *bus)
4710 struct pci_dev *dev;
4712 list_for_each_entry(dev, &bus->devices, bus_list) {
4714 pci_dev_restore(dev);
4715 pci_dev_unlock(dev);
4716 if (dev->subordinate)
4717 pci_bus_restore(dev->subordinate);
4721 /* Save and disable devices from the top of the tree down */
4722 static void pci_slot_save_and_disable(struct pci_slot *slot)
4724 struct pci_dev *dev;
4726 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4727 if (!dev->slot || dev->slot != slot)
4729 pci_dev_save_and_disable(dev);
4730 if (dev->subordinate)
4731 pci_bus_save_and_disable(dev->subordinate);
4736 * Restore devices from top of the tree down - parent bridges need to be
4737 * restored before we can get to subordinate devices.
4739 static void pci_slot_restore(struct pci_slot *slot)
4741 struct pci_dev *dev;
4743 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4744 if (!dev->slot || dev->slot != slot)
4747 pci_dev_restore(dev);
4748 pci_dev_unlock(dev);
4749 if (dev->subordinate)
4750 pci_bus_restore(dev->subordinate);
4754 static int pci_slot_reset(struct pci_slot *slot, int probe)
4758 if (!slot || !pci_slot_resetable(slot))
4762 pci_slot_lock(slot);
4766 rc = pci_reset_hotplug_slot(slot->hotplug, probe);
4769 pci_slot_unlock(slot);
4775 * pci_probe_reset_slot - probe whether a PCI slot can be reset
4776 * @slot: PCI slot to probe
4778 * Return 0 if slot can be reset, negative if a slot reset is not supported.
4780 int pci_probe_reset_slot(struct pci_slot *slot)
4782 return pci_slot_reset(slot, 1);
4784 EXPORT_SYMBOL_GPL(pci_probe_reset_slot);
4787 * pci_reset_slot - reset a PCI slot
4788 * @slot: PCI slot to reset
4790 * A PCI bus may host multiple slots, each slot may support a reset mechanism
4791 * independent of other slots. For instance, some slots may support slot power
4792 * control. In the case of a 1:1 bus to slot architecture, this function may
4793 * wrap the bus reset to avoid spurious slot related events such as hotplug.
4794 * Generally a slot reset should be attempted before a bus reset. All of the
4795 * function of the slot and any subordinate buses behind the slot are reset
4796 * through this function. PCI config space of all devices in the slot and
4797 * behind the slot is saved before and restored after reset.
4799 * Return 0 on success, non-zero on error.
4801 int pci_reset_slot(struct pci_slot *slot)
4805 rc = pci_slot_reset(slot, 1);
4809 pci_slot_save_and_disable(slot);
4811 rc = pci_slot_reset(slot, 0);
4813 pci_slot_restore(slot);
4817 EXPORT_SYMBOL_GPL(pci_reset_slot);
4820 * pci_try_reset_slot - Try to reset a PCI slot
4821 * @slot: PCI slot to reset
4823 * Same as above except return -EAGAIN if the slot cannot be locked
4825 int pci_try_reset_slot(struct pci_slot *slot)
4829 rc = pci_slot_reset(slot, 1);
4833 pci_slot_save_and_disable(slot);
4835 if (pci_slot_trylock(slot)) {
4837 rc = pci_reset_hotplug_slot(slot->hotplug, 0);
4838 pci_slot_unlock(slot);
4842 pci_slot_restore(slot);
4846 EXPORT_SYMBOL_GPL(pci_try_reset_slot);
4848 static int pci_bus_reset(struct pci_bus *bus, int probe)
4850 if (!bus->self || !pci_bus_resetable(bus))
4860 pci_reset_bridge_secondary_bus(bus->self);
4862 pci_bus_unlock(bus);
4868 * pci_probe_reset_bus - probe whether a PCI bus can be reset
4869 * @bus: PCI bus to probe
4871 * Return 0 if bus can be reset, negative if a bus reset is not supported.
4873 int pci_probe_reset_bus(struct pci_bus *bus)
4875 return pci_bus_reset(bus, 1);
4877 EXPORT_SYMBOL_GPL(pci_probe_reset_bus);
4880 * pci_reset_bus - reset a PCI bus
4881 * @bus: top level PCI bus to reset
4883 * Do a bus reset on the given bus and any subordinate buses, saving
4884 * and restoring state of all devices.
4886 * Return 0 on success, non-zero on error.
4888 int pci_reset_bus(struct pci_bus *bus)
4892 rc = pci_bus_reset(bus, 1);
4896 pci_bus_save_and_disable(bus);
4898 rc = pci_bus_reset(bus, 0);
4900 pci_bus_restore(bus);
4904 EXPORT_SYMBOL_GPL(pci_reset_bus);
4907 * pci_try_reset_bus - Try to reset a PCI bus
4908 * @bus: top level PCI bus to reset
4910 * Same as above except return -EAGAIN if the bus cannot be locked
4912 int pci_try_reset_bus(struct pci_bus *bus)
4916 rc = pci_bus_reset(bus, 1);
4920 pci_bus_save_and_disable(bus);
4922 if (pci_bus_trylock(bus)) {
4924 pci_reset_bridge_secondary_bus(bus->self);
4925 pci_bus_unlock(bus);
4929 pci_bus_restore(bus);
4933 EXPORT_SYMBOL_GPL(pci_try_reset_bus);
4936 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
4937 * @dev: PCI device to query
4939 * Returns mmrbc: maximum designed memory read count in bytes
4940 * or appropriate error value.
4942 int pcix_get_max_mmrbc(struct pci_dev *dev)
4947 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
4951 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
4954 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
4956 EXPORT_SYMBOL(pcix_get_max_mmrbc);
4959 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
4960 * @dev: PCI device to query
4962 * Returns mmrbc: maximum memory read count in bytes
4963 * or appropriate error value.
4965 int pcix_get_mmrbc(struct pci_dev *dev)
4970 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
4974 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
4977 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
4979 EXPORT_SYMBOL(pcix_get_mmrbc);
4982 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
4983 * @dev: PCI device to query
4984 * @mmrbc: maximum memory read count in bytes
4985 * valid values are 512, 1024, 2048, 4096
4987 * If possible sets maximum memory read byte count, some bridges have erratas
4988 * that prevent this.
4990 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
4996 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
4999 v = ffs(mmrbc) - 10;
5001 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
5005 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
5008 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
5011 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
5014 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
5016 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
5019 cmd &= ~PCI_X_CMD_MAX_READ;
5021 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
5026 EXPORT_SYMBOL(pcix_set_mmrbc);
5029 * pcie_get_readrq - get PCI Express read request size
5030 * @dev: PCI device to query
5032 * Returns maximum memory read request in bytes
5033 * or appropriate error value.
5035 int pcie_get_readrq(struct pci_dev *dev)
5039 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
5041 return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
5043 EXPORT_SYMBOL(pcie_get_readrq);
5046 * pcie_set_readrq - set PCI Express maximum memory read request
5047 * @dev: PCI device to query
5048 * @rq: maximum memory read count in bytes
5049 * valid values are 128, 256, 512, 1024, 2048, 4096
5051 * If possible sets maximum memory read request in bytes
5053 int pcie_set_readrq(struct pci_dev *dev, int rq)
5057 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
5061 * If using the "performance" PCIe config, we clamp the
5062 * read rq size to the max packet size to prevent the
5063 * host bridge generating requests larger than we can
5066 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
5067 int mps = pcie_get_mps(dev);
5073 v = (ffs(rq) - 8) << 12;
5075 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
5076 PCI_EXP_DEVCTL_READRQ, v);
5078 EXPORT_SYMBOL(pcie_set_readrq);
5081 * pcie_get_mps - get PCI Express maximum payload size
5082 * @dev: PCI device to query
5084 * Returns maximum payload size in bytes
5086 int pcie_get_mps(struct pci_dev *dev)
5090 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
5092 return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
5094 EXPORT_SYMBOL(pcie_get_mps);
5097 * pcie_set_mps - set PCI Express maximum payload size
5098 * @dev: PCI device to query
5099 * @mps: maximum payload size in bytes
5100 * valid values are 128, 256, 512, 1024, 2048, 4096
5102 * If possible sets maximum payload size
5104 int pcie_set_mps(struct pci_dev *dev, int mps)
5108 if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
5112 if (v > dev->pcie_mpss)
5116 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
5117 PCI_EXP_DEVCTL_PAYLOAD, v);
5119 EXPORT_SYMBOL(pcie_set_mps);
5122 * pcie_get_minimum_link - determine minimum link settings of a PCI device
5123 * @dev: PCI device to query
5124 * @speed: storage for minimum speed
5125 * @width: storage for minimum width
5127 * This function will walk up the PCI device chain and determine the minimum
5128 * link width and speed of the device.
5130 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
5131 enum pcie_link_width *width)
5135 *speed = PCI_SPEED_UNKNOWN;
5136 *width = PCIE_LNK_WIDTH_UNKNOWN;
5140 enum pci_bus_speed next_speed;
5141 enum pcie_link_width next_width;
5143 ret = pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
5147 next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS];
5148 next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >>
5149 PCI_EXP_LNKSTA_NLW_SHIFT;
5151 if (next_speed < *speed)
5152 *speed = next_speed;
5154 if (next_width < *width)
5155 *width = next_width;
5157 dev = dev->bus->self;
5162 EXPORT_SYMBOL(pcie_get_minimum_link);
5165 * pci_select_bars - Make BAR mask from the type of resource
5166 * @dev: the PCI device for which BAR mask is made
5167 * @flags: resource type mask to be selected
5169 * This helper routine makes bar mask from the type of resource.
5171 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
5174 for (i = 0; i < PCI_NUM_RESOURCES; i++)
5175 if (pci_resource_flags(dev, i) & flags)
5179 EXPORT_SYMBOL(pci_select_bars);
5181 /* Some architectures require additional programming to enable VGA */
5182 static arch_set_vga_state_t arch_set_vga_state;
5184 void __init pci_register_set_vga_state(arch_set_vga_state_t func)
5186 arch_set_vga_state = func; /* NULL disables */
5189 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
5190 unsigned int command_bits, u32 flags)
5192 if (arch_set_vga_state)
5193 return arch_set_vga_state(dev, decode, command_bits,
5199 * pci_set_vga_state - set VGA decode state on device and parents if requested
5200 * @dev: the PCI device
5201 * @decode: true = enable decoding, false = disable decoding
5202 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
5203 * @flags: traverse ancestors and change bridges
5204 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
5206 int pci_set_vga_state(struct pci_dev *dev, bool decode,
5207 unsigned int command_bits, u32 flags)
5209 struct pci_bus *bus;
5210 struct pci_dev *bridge;
5214 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
5216 /* ARCH specific VGA enables */
5217 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
5221 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
5222 pci_read_config_word(dev, PCI_COMMAND, &cmd);
5224 cmd |= command_bits;
5226 cmd &= ~command_bits;
5227 pci_write_config_word(dev, PCI_COMMAND, cmd);
5230 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
5237 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
5240 cmd |= PCI_BRIDGE_CTL_VGA;
5242 cmd &= ~PCI_BRIDGE_CTL_VGA;
5243 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
5252 * pci_add_dma_alias - Add a DMA devfn alias for a device
5253 * @dev: the PCI device for which alias is added
5254 * @devfn: alias slot and function
5256 * This helper encodes 8-bit devfn as bit number in dma_alias_mask.
5257 * It should be called early, preferably as PCI fixup header quirk.
5259 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn)
5261 if (!dev->dma_alias_mask)
5262 dev->dma_alias_mask = kcalloc(BITS_TO_LONGS(U8_MAX),
5263 sizeof(long), GFP_KERNEL);
5264 if (!dev->dma_alias_mask) {
5265 pci_warn(dev, "Unable to allocate DMA alias mask\n");
5269 set_bit(devfn, dev->dma_alias_mask);
5270 pci_info(dev, "Enabling fixed DMA alias to %02x.%d\n",
5271 PCI_SLOT(devfn), PCI_FUNC(devfn));
5274 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2)
5276 return (dev1->dma_alias_mask &&
5277 test_bit(dev2->devfn, dev1->dma_alias_mask)) ||
5278 (dev2->dma_alias_mask &&
5279 test_bit(dev1->devfn, dev2->dma_alias_mask));
5282 bool pci_device_is_present(struct pci_dev *pdev)
5286 if (pci_dev_is_disconnected(pdev))
5288 return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0);
5290 EXPORT_SYMBOL_GPL(pci_device_is_present);
5292 void pci_ignore_hotplug(struct pci_dev *dev)
5294 struct pci_dev *bridge = dev->bus->self;
5296 dev->ignore_hotplug = 1;
5297 /* Propagate the "ignore hotplug" setting to the parent bridge. */
5299 bridge->ignore_hotplug = 1;
5301 EXPORT_SYMBOL_GPL(pci_ignore_hotplug);
5303 resource_size_t __weak pcibios_default_alignment(void)
5308 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
5309 static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
5310 static DEFINE_SPINLOCK(resource_alignment_lock);
5313 * pci_specified_resource_alignment - get resource alignment specified by user.
5314 * @dev: the PCI device to get
5315 * @resize: whether or not to change resources' size when reassigning alignment
5317 * RETURNS: Resource alignment if it is specified.
5318 * Zero if it is not specified.
5320 static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev,
5323 int seg, bus, slot, func, align_order, count;
5324 unsigned short vendor, device, subsystem_vendor, subsystem_device;
5325 resource_size_t align = pcibios_default_alignment();
5328 spin_lock(&resource_alignment_lock);
5329 p = resource_alignment_param;
5332 if (pci_has_flag(PCI_PROBE_ONLY)) {
5334 pr_info_once("PCI: Ignoring requested alignments (PCI_PROBE_ONLY)\n");
5340 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
5346 if (strncmp(p, "pci:", 4) == 0) {
5347 /* PCI vendor/device (subvendor/subdevice) ids are specified */
5349 if (sscanf(p, "%hx:%hx:%hx:%hx%n",
5350 &vendor, &device, &subsystem_vendor, &subsystem_device, &count) != 4) {
5351 if (sscanf(p, "%hx:%hx%n", &vendor, &device, &count) != 2) {
5352 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: pci:%s\n",
5356 subsystem_vendor = subsystem_device = 0;
5359 if ((!vendor || (vendor == dev->vendor)) &&
5360 (!device || (device == dev->device)) &&
5361 (!subsystem_vendor || (subsystem_vendor == dev->subsystem_vendor)) &&
5362 (!subsystem_device || (subsystem_device == dev->subsystem_device))) {
5364 if (align_order == -1)
5367 align = 1 << align_order;
5373 if (sscanf(p, "%x:%x:%x.%x%n",
5374 &seg, &bus, &slot, &func, &count) != 4) {
5376 if (sscanf(p, "%x:%x.%x%n",
5377 &bus, &slot, &func, &count) != 3) {
5378 /* Invalid format */
5379 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
5385 if (seg == pci_domain_nr(dev->bus) &&
5386 bus == dev->bus->number &&
5387 slot == PCI_SLOT(dev->devfn) &&
5388 func == PCI_FUNC(dev->devfn)) {
5390 if (align_order == -1)
5393 align = 1 << align_order;
5398 if (*p != ';' && *p != ',') {
5399 /* End of param or invalid format */
5405 spin_unlock(&resource_alignment_lock);
5409 static void pci_request_resource_alignment(struct pci_dev *dev, int bar,
5410 resource_size_t align, bool resize)
5412 struct resource *r = &dev->resource[bar];
5413 resource_size_t size;
5415 if (!(r->flags & IORESOURCE_MEM))
5418 if (r->flags & IORESOURCE_PCI_FIXED) {
5419 pci_info(dev, "BAR%d %pR: ignoring requested alignment %#llx\n",
5420 bar, r, (unsigned long long)align);
5424 size = resource_size(r);
5429 * Increase the alignment of the resource. There are two ways we
5432 * 1) Increase the size of the resource. BARs are aligned on their
5433 * size, so when we reallocate space for this resource, we'll
5434 * allocate it with the larger alignment. This also prevents
5435 * assignment of any other BARs inside the alignment region, so
5436 * if we're requesting page alignment, this means no other BARs
5437 * will share the page.
5439 * The disadvantage is that this makes the resource larger than
5440 * the hardware BAR, which may break drivers that compute things
5441 * based on the resource size, e.g., to find registers at a
5442 * fixed offset before the end of the BAR.
5444 * 2) Retain the resource size, but use IORESOURCE_STARTALIGN and
5445 * set r->start to the desired alignment. By itself this
5446 * doesn't prevent other BARs being put inside the alignment
5447 * region, but if we realign *every* resource of every device in
5448 * the system, none of them will share an alignment region.
5450 * When the user has requested alignment for only some devices via
5451 * the "pci=resource_alignment" argument, "resize" is true and we
5452 * use the first method. Otherwise we assume we're aligning all
5453 * devices and we use the second.
5456 pci_info(dev, "BAR%d %pR: requesting alignment to %#llx\n",
5457 bar, r, (unsigned long long)align);
5463 r->flags &= ~IORESOURCE_SIZEALIGN;
5464 r->flags |= IORESOURCE_STARTALIGN;
5466 r->end = r->start + size - 1;
5468 r->flags |= IORESOURCE_UNSET;
5472 * This function disables memory decoding and releases memory resources
5473 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
5474 * It also rounds up size to specified alignment.
5475 * Later on, the kernel will assign page-aligned memory resource back
5478 void pci_reassigndev_resource_alignment(struct pci_dev *dev)
5482 resource_size_t align;
5484 bool resize = false;
5487 * VF BARs are read-only zero according to SR-IOV spec r1.1, sec
5488 * 3.4.1.11. Their resources are allocated from the space
5489 * described by the VF BARx register in the PF's SR-IOV capability.
5490 * We can't influence their alignment here.
5495 /* check if specified PCI is target device to reassign */
5496 align = pci_specified_resource_alignment(dev, &resize);
5500 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
5501 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
5502 pci_warn(dev, "Can't reassign resources to host bridge\n");
5506 pci_info(dev, "Disabling memory decoding and releasing memory resources\n");
5507 pci_read_config_word(dev, PCI_COMMAND, &command);
5508 command &= ~PCI_COMMAND_MEMORY;
5509 pci_write_config_word(dev, PCI_COMMAND, command);
5511 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
5512 pci_request_resource_alignment(dev, i, align, resize);
5515 * Need to disable bridge's resource window,
5516 * to enable the kernel to reassign new resource
5519 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
5520 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
5521 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
5522 r = &dev->resource[i];
5523 if (!(r->flags & IORESOURCE_MEM))
5525 r->flags |= IORESOURCE_UNSET;
5526 r->end = resource_size(r) - 1;
5529 pci_disable_bridge_window(dev);
5533 static ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
5535 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
5536 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
5537 spin_lock(&resource_alignment_lock);
5538 strncpy(resource_alignment_param, buf, count);
5539 resource_alignment_param[count] = '\0';
5540 spin_unlock(&resource_alignment_lock);
5544 static ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
5547 spin_lock(&resource_alignment_lock);
5548 count = snprintf(buf, size, "%s", resource_alignment_param);
5549 spin_unlock(&resource_alignment_lock);
5553 static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
5555 return pci_get_resource_alignment_param(buf, PAGE_SIZE);
5558 static ssize_t pci_resource_alignment_store(struct bus_type *bus,
5559 const char *buf, size_t count)
5561 return pci_set_resource_alignment_param(buf, count);
5564 static BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
5565 pci_resource_alignment_store);
5567 static int __init pci_resource_alignment_sysfs_init(void)
5569 return bus_create_file(&pci_bus_type,
5570 &bus_attr_resource_alignment);
5572 late_initcall(pci_resource_alignment_sysfs_init);
5574 static void pci_no_domains(void)
5576 #ifdef CONFIG_PCI_DOMAINS
5577 pci_domains_supported = 0;
5581 #ifdef CONFIG_PCI_DOMAINS
5582 static atomic_t __domain_nr = ATOMIC_INIT(-1);
5584 int pci_get_new_domain_nr(void)
5586 return atomic_inc_return(&__domain_nr);
5589 #ifdef CONFIG_PCI_DOMAINS_GENERIC
5590 static int of_pci_bus_find_domain_nr(struct device *parent)
5592 static int use_dt_domains = -1;
5596 domain = of_get_pci_domain_nr(parent->of_node);
5598 * Check DT domain and use_dt_domains values.
5600 * If DT domain property is valid (domain >= 0) and
5601 * use_dt_domains != 0, the DT assignment is valid since this means
5602 * we have not previously allocated a domain number by using
5603 * pci_get_new_domain_nr(); we should also update use_dt_domains to
5604 * 1, to indicate that we have just assigned a domain number from
5607 * If DT domain property value is not valid (ie domain < 0), and we
5608 * have not previously assigned a domain number from DT
5609 * (use_dt_domains != 1) we should assign a domain number by
5612 * pci_get_new_domain_nr()
5614 * API and update the use_dt_domains value to keep track of method we
5615 * are using to assign domain numbers (use_dt_domains = 0).
5617 * All other combinations imply we have a platform that is trying
5618 * to mix domain numbers obtained from DT and pci_get_new_domain_nr(),
5619 * which is a recipe for domain mishandling and it is prevented by
5620 * invalidating the domain value (domain = -1) and printing a
5621 * corresponding error.
5623 if (domain >= 0 && use_dt_domains) {
5625 } else if (domain < 0 && use_dt_domains != 1) {
5627 domain = pci_get_new_domain_nr();
5629 dev_err(parent, "Node %pOF has inconsistent \"linux,pci-domain\" property in DT\n",
5637 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent)
5639 return acpi_disabled ? of_pci_bus_find_domain_nr(parent) :
5640 acpi_pci_bus_find_domain_nr(bus);
5646 * pci_ext_cfg_avail - can we access extended PCI config space?
5648 * Returns 1 if we can access PCI extended config space (offsets
5649 * greater than 0xff). This is the default implementation. Architecture
5650 * implementations can override this.
5652 int __weak pci_ext_cfg_avail(void)
5657 void __weak pci_fixup_cardbus(struct pci_bus *bus)
5660 EXPORT_SYMBOL(pci_fixup_cardbus);
5662 static int __init pci_setup(char *str)
5665 char *k = strchr(str, ',');
5668 if (*str && (str = pcibios_setup(str)) && *str) {
5669 if (!strcmp(str, "nomsi")) {
5671 } else if (!strcmp(str, "noaer")) {
5673 } else if (!strncmp(str, "realloc=", 8)) {
5674 pci_realloc_get_opt(str + 8);
5675 } else if (!strncmp(str, "realloc", 7)) {
5676 pci_realloc_get_opt("on");
5677 } else if (!strcmp(str, "nodomains")) {
5679 } else if (!strncmp(str, "noari", 5)) {
5680 pcie_ari_disabled = true;
5681 } else if (!strncmp(str, "cbiosize=", 9)) {
5682 pci_cardbus_io_size = memparse(str + 9, &str);
5683 } else if (!strncmp(str, "cbmemsize=", 10)) {
5684 pci_cardbus_mem_size = memparse(str + 10, &str);
5685 } else if (!strncmp(str, "resource_alignment=", 19)) {
5686 pci_set_resource_alignment_param(str + 19,
5688 } else if (!strncmp(str, "ecrc=", 5)) {
5689 pcie_ecrc_get_policy(str + 5);
5690 } else if (!strncmp(str, "hpiosize=", 9)) {
5691 pci_hotplug_io_size = memparse(str + 9, &str);
5692 } else if (!strncmp(str, "hpmemsize=", 10)) {
5693 pci_hotplug_mem_size = memparse(str + 10, &str);
5694 } else if (!strncmp(str, "hpbussize=", 10)) {
5695 pci_hotplug_bus_size =
5696 simple_strtoul(str + 10, &str, 0);
5697 if (pci_hotplug_bus_size > 0xff)
5698 pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
5699 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
5700 pcie_bus_config = PCIE_BUS_TUNE_OFF;
5701 } else if (!strncmp(str, "pcie_bus_safe", 13)) {
5702 pcie_bus_config = PCIE_BUS_SAFE;
5703 } else if (!strncmp(str, "pcie_bus_perf", 13)) {
5704 pcie_bus_config = PCIE_BUS_PERFORMANCE;
5705 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
5706 pcie_bus_config = PCIE_BUS_PEER2PEER;
5707 } else if (!strncmp(str, "pcie_scan_all", 13)) {
5708 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
5710 printk(KERN_ERR "PCI: Unknown option `%s'\n",
5718 early_param("pci", pci_setup);