2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #include <linux/aer.h>
16 #include <linux/bitops.h>
17 #include <linux/blkdev.h>
18 #include <linux/blk-mq.h>
19 #include <linux/cpu.h>
20 #include <linux/delay.h>
21 #include <linux/errno.h>
23 #include <linux/genhd.h>
24 #include <linux/hdreg.h>
25 #include <linux/idr.h>
26 #include <linux/init.h>
27 #include <linux/interrupt.h>
29 #include <linux/kdev_t.h>
30 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/moduleparam.h>
34 #include <linux/mutex.h>
35 #include <linux/pci.h>
36 #include <linux/poison.h>
37 #include <linux/ptrace.h>
38 #include <linux/sched.h>
39 #include <linux/slab.h>
40 #include <linux/t10-pi.h>
41 #include <linux/timer.h>
42 #include <linux/types.h>
43 #include <linux/io-64-nonatomic-lo-hi.h>
44 #include <asm/unaligned.h>
48 #define NVME_Q_DEPTH 1024
49 #define NVME_AQ_DEPTH 256
50 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
51 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
54 * We handle AEN commands ourselves and don't even let the
55 * block layer know about them.
57 #define NVME_AQ_BLKMQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AERS)
59 static int use_threaded_interrupts;
60 module_param(use_threaded_interrupts, int, 0);
62 static bool use_cmb_sqes = true;
63 module_param(use_cmb_sqes, bool, 0644);
64 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
66 static struct workqueue_struct *nvme_workq;
71 static int nvme_reset(struct nvme_dev *dev);
72 static void nvme_process_cq(struct nvme_queue *nvmeq);
73 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
76 * Represents an NVM Express device. Each nvme_dev is a PCI function.
79 struct nvme_queue **queues;
80 struct blk_mq_tag_set tagset;
81 struct blk_mq_tag_set admin_tagset;
84 struct dma_pool *prp_page_pool;
85 struct dma_pool *prp_small_pool;
87 unsigned online_queues;
91 struct msix_entry *entry;
93 struct work_struct reset_work;
94 struct work_struct remove_work;
95 struct timer_list watchdog_timer;
96 struct mutex shutdown_lock;
99 dma_addr_t cmb_dma_addr;
102 struct nvme_ctrl ctrl;
103 struct completion ioq_wait;
106 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
108 return container_of(ctrl, struct nvme_dev, ctrl);
112 * An NVM Express queue. Each device has at least two (one for admin
113 * commands and one for I/O commands).
116 struct device *q_dmadev;
117 struct nvme_dev *dev;
118 char irqname[24]; /* nvme4294967295-65535\0 */
120 struct nvme_command *sq_cmds;
121 struct nvme_command __iomem *sq_cmds_io;
122 volatile struct nvme_completion *cqes;
123 struct blk_mq_tags **tags;
124 dma_addr_t sq_dma_addr;
125 dma_addr_t cq_dma_addr;
137 * The nvme_iod describes the data in an I/O, including the list of PRP
138 * entries. You can't see it in this data structure because C doesn't let
139 * me express that. Use nvme_init_iod to ensure there's enough space
140 * allocated to store the PRP list.
143 struct nvme_queue *nvmeq;
145 int npages; /* In the PRP list. 0 means small pool in use */
146 int nents; /* Used in scatterlist */
147 int length; /* Of data, in bytes */
148 dma_addr_t first_dma;
149 struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
150 struct scatterlist *sg;
151 struct scatterlist inline_sg[0];
155 * Check we didin't inadvertently grow the command struct
157 static inline void _nvme_check_size(void)
159 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
160 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
161 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
162 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
163 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
164 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
165 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
166 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
167 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
168 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
169 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
170 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
174 * Max size of iod being embedded in the request payload
176 #define NVME_INT_PAGES 2
177 #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size)
180 * Will slightly overestimate the number of pages needed. This is OK
181 * as it only leads to a small amount of wasted memory for the lifetime of
184 static int nvme_npages(unsigned size, struct nvme_dev *dev)
186 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
187 dev->ctrl.page_size);
188 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
191 static unsigned int nvme_iod_alloc_size(struct nvme_dev *dev,
192 unsigned int size, unsigned int nseg)
194 return sizeof(__le64 *) * nvme_npages(size, dev) +
195 sizeof(struct scatterlist) * nseg;
198 static unsigned int nvme_cmd_size(struct nvme_dev *dev)
200 return sizeof(struct nvme_iod) +
201 nvme_iod_alloc_size(dev, NVME_INT_BYTES(dev), NVME_INT_PAGES);
204 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
205 unsigned int hctx_idx)
207 struct nvme_dev *dev = data;
208 struct nvme_queue *nvmeq = dev->queues[0];
210 WARN_ON(hctx_idx != 0);
211 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
212 WARN_ON(nvmeq->tags);
214 hctx->driver_data = nvmeq;
215 nvmeq->tags = &dev->admin_tagset.tags[0];
219 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
221 struct nvme_queue *nvmeq = hctx->driver_data;
226 static int nvme_admin_init_request(void *data, struct request *req,
227 unsigned int hctx_idx, unsigned int rq_idx,
228 unsigned int numa_node)
230 struct nvme_dev *dev = data;
231 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
232 struct nvme_queue *nvmeq = dev->queues[0];
239 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
240 unsigned int hctx_idx)
242 struct nvme_dev *dev = data;
243 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
246 nvmeq->tags = &dev->tagset.tags[hctx_idx];
248 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
249 hctx->driver_data = nvmeq;
253 static int nvme_init_request(void *data, struct request *req,
254 unsigned int hctx_idx, unsigned int rq_idx,
255 unsigned int numa_node)
257 struct nvme_dev *dev = data;
258 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
259 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
267 * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
268 * @nvmeq: The queue to use
269 * @cmd: The command to send
271 * Safe to use from interrupt context
273 static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
274 struct nvme_command *cmd)
276 u16 tail = nvmeq->sq_tail;
278 if (nvmeq->sq_cmds_io)
279 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
281 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
283 if (++tail == nvmeq->q_depth)
285 writel(tail, nvmeq->q_db);
286 nvmeq->sq_tail = tail;
289 static __le64 **iod_list(struct request *req)
291 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
292 return (__le64 **)(iod->sg + req->nr_phys_segments);
295 static int nvme_init_iod(struct request *rq, unsigned size,
296 struct nvme_dev *dev)
298 struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
299 int nseg = rq->nr_phys_segments;
301 if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
302 iod->sg = kmalloc(nvme_iod_alloc_size(dev, size, nseg), GFP_ATOMIC);
304 return BLK_MQ_RQ_QUEUE_BUSY;
306 iod->sg = iod->inline_sg;
316 static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
318 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
319 const int last_prp = dev->ctrl.page_size / 8 - 1;
321 __le64 **list = iod_list(req);
322 dma_addr_t prp_dma = iod->first_dma;
324 if (req->cmd_flags & REQ_DISCARD)
325 kfree(req->completion_data);
327 if (iod->npages == 0)
328 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
329 for (i = 0; i < iod->npages; i++) {
330 __le64 *prp_list = list[i];
331 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
332 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
333 prp_dma = next_prp_dma;
336 if (iod->sg != iod->inline_sg)
340 #ifdef CONFIG_BLK_DEV_INTEGRITY
341 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
343 if (be32_to_cpu(pi->ref_tag) == v)
344 pi->ref_tag = cpu_to_be32(p);
347 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
349 if (be32_to_cpu(pi->ref_tag) == p)
350 pi->ref_tag = cpu_to_be32(v);
354 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
356 * The virtual start sector is the one that was originally submitted by the
357 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
358 * start sector may be different. Remap protection information to match the
359 * physical LBA on writes, and back to the original seed on reads.
361 * Type 0 and 3 do not have a ref tag, so no remapping required.
363 static void nvme_dif_remap(struct request *req,
364 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
366 struct nvme_ns *ns = req->rq_disk->private_data;
367 struct bio_integrity_payload *bip;
368 struct t10_pi_tuple *pi;
370 u32 i, nlb, ts, phys, virt;
372 if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
375 bip = bio_integrity(req->bio);
379 pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
382 virt = bip_get_seed(bip);
383 phys = nvme_block_nr(ns, blk_rq_pos(req));
384 nlb = (blk_rq_bytes(req) >> ns->lba_shift);
385 ts = ns->disk->queue->integrity.tuple_size;
387 for (i = 0; i < nlb; i++, virt++, phys++) {
388 pi = (struct t10_pi_tuple *)p;
389 dif_swap(phys, virt, pi);
394 #else /* CONFIG_BLK_DEV_INTEGRITY */
395 static void nvme_dif_remap(struct request *req,
396 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
399 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
402 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
407 static bool nvme_setup_prps(struct nvme_dev *dev, struct request *req,
410 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
411 struct dma_pool *pool;
412 int length = total_len;
413 struct scatterlist *sg = iod->sg;
414 int dma_len = sg_dma_len(sg);
415 u64 dma_addr = sg_dma_address(sg);
416 u32 page_size = dev->ctrl.page_size;
417 int offset = dma_addr & (page_size - 1);
419 __le64 **list = iod_list(req);
423 length -= (page_size - offset);
427 dma_len -= (page_size - offset);
429 dma_addr += (page_size - offset);
432 dma_addr = sg_dma_address(sg);
433 dma_len = sg_dma_len(sg);
436 if (length <= page_size) {
437 iod->first_dma = dma_addr;
441 nprps = DIV_ROUND_UP(length, page_size);
442 if (nprps <= (256 / 8)) {
443 pool = dev->prp_small_pool;
446 pool = dev->prp_page_pool;
450 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
452 iod->first_dma = dma_addr;
457 iod->first_dma = prp_dma;
460 if (i == page_size >> 3) {
461 __le64 *old_prp_list = prp_list;
462 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
465 list[iod->npages++] = prp_list;
466 prp_list[0] = old_prp_list[i - 1];
467 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
470 prp_list[i++] = cpu_to_le64(dma_addr);
471 dma_len -= page_size;
472 dma_addr += page_size;
480 dma_addr = sg_dma_address(sg);
481 dma_len = sg_dma_len(sg);
487 static int nvme_map_data(struct nvme_dev *dev, struct request *req,
488 unsigned size, struct nvme_command *cmnd)
490 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
491 struct request_queue *q = req->q;
492 enum dma_data_direction dma_dir = rq_data_dir(req) ?
493 DMA_TO_DEVICE : DMA_FROM_DEVICE;
494 int ret = BLK_MQ_RQ_QUEUE_ERROR;
496 sg_init_table(iod->sg, req->nr_phys_segments);
497 iod->nents = blk_rq_map_sg(q, req, iod->sg);
501 ret = BLK_MQ_RQ_QUEUE_BUSY;
502 if (!dma_map_sg(dev->dev, iod->sg, iod->nents, dma_dir))
505 if (!nvme_setup_prps(dev, req, size))
508 ret = BLK_MQ_RQ_QUEUE_ERROR;
509 if (blk_integrity_rq(req)) {
510 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
513 sg_init_table(&iod->meta_sg, 1);
514 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
517 if (rq_data_dir(req))
518 nvme_dif_remap(req, nvme_dif_prep);
520 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
524 cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
525 cmnd->rw.prp2 = cpu_to_le64(iod->first_dma);
526 if (blk_integrity_rq(req))
527 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
528 return BLK_MQ_RQ_QUEUE_OK;
531 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
536 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
538 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
539 enum dma_data_direction dma_dir = rq_data_dir(req) ?
540 DMA_TO_DEVICE : DMA_FROM_DEVICE;
543 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
544 if (blk_integrity_rq(req)) {
545 if (!rq_data_dir(req))
546 nvme_dif_remap(req, nvme_dif_complete);
547 dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
551 nvme_free_iod(dev, req);
555 * NOTE: ns is NULL when called on the admin queue.
557 static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
558 const struct blk_mq_queue_data *bd)
560 struct nvme_ns *ns = hctx->queue->queuedata;
561 struct nvme_queue *nvmeq = hctx->driver_data;
562 struct nvme_dev *dev = nvmeq->dev;
563 struct request *req = bd->rq;
564 struct nvme_command cmnd;
566 int ret = BLK_MQ_RQ_QUEUE_OK;
569 * If formated with metadata, require the block layer provide a buffer
570 * unless this namespace is formated such that the metadata can be
571 * stripped/generated by the controller with PRACT=1.
573 if (ns && ns->ms && !blk_integrity_rq(req)) {
574 if (!(ns->pi_type && ns->ms == 8) &&
575 req->cmd_type != REQ_TYPE_DRV_PRIV) {
576 blk_mq_end_request(req, -EFAULT);
577 return BLK_MQ_RQ_QUEUE_OK;
581 map_len = nvme_map_len(req);
582 ret = nvme_init_iod(req, map_len, dev);
586 ret = nvme_setup_cmd(ns, req, &cmnd);
590 if (req->nr_phys_segments)
591 ret = nvme_map_data(dev, req, map_len, &cmnd);
596 cmnd.common.command_id = req->tag;
597 blk_mq_start_request(req);
599 spin_lock_irq(&nvmeq->q_lock);
600 if (unlikely(nvmeq->cq_vector < 0)) {
601 if (ns && !test_bit(NVME_NS_DEAD, &ns->flags))
602 ret = BLK_MQ_RQ_QUEUE_BUSY;
604 ret = BLK_MQ_RQ_QUEUE_ERROR;
605 spin_unlock_irq(&nvmeq->q_lock);
608 __nvme_submit_cmd(nvmeq, &cmnd);
609 nvme_process_cq(nvmeq);
610 spin_unlock_irq(&nvmeq->q_lock);
611 return BLK_MQ_RQ_QUEUE_OK;
613 nvme_free_iod(dev, req);
617 static void nvme_complete_rq(struct request *req)
619 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
620 struct nvme_dev *dev = iod->nvmeq->dev;
623 nvme_unmap_data(dev, req);
625 if (unlikely(req->errors)) {
626 if (nvme_req_needs_retry(req, req->errors)) {
627 nvme_requeue_req(req);
631 if (req->cmd_type == REQ_TYPE_DRV_PRIV)
634 error = nvme_error_status(req->errors);
637 if (unlikely(iod->aborted)) {
638 dev_warn(dev->ctrl.device,
639 "completing aborted command with status: %04x\n",
643 blk_mq_end_request(req, error);
646 /* We read the CQE phase first to check if the rest of the entry is valid */
647 static inline bool nvme_cqe_valid(struct nvme_queue *nvmeq, u16 head,
650 return (le16_to_cpu(nvmeq->cqes[head].status) & 1) == phase;
653 static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag)
657 head = nvmeq->cq_head;
658 phase = nvmeq->cq_phase;
660 while (nvme_cqe_valid(nvmeq, head, phase)) {
661 struct nvme_completion cqe = nvmeq->cqes[head];
664 if (++head == nvmeq->q_depth) {
669 if (tag && *tag == cqe.command_id)
672 if (unlikely(cqe.command_id >= nvmeq->q_depth)) {
673 dev_warn(nvmeq->dev->ctrl.device,
674 "invalid id %d completed on queue %d\n",
675 cqe.command_id, le16_to_cpu(cqe.sq_id));
680 * AEN requests are special as they don't time out and can
681 * survive any kind of queue freeze and often don't respond to
682 * aborts. We don't even bother to allocate a struct request
683 * for them but rather special case them here.
685 if (unlikely(nvmeq->qid == 0 &&
686 cqe.command_id >= NVME_AQ_BLKMQ_DEPTH)) {
687 nvme_complete_async_event(&nvmeq->dev->ctrl, &cqe);
691 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe.command_id);
692 if (req->cmd_type == REQ_TYPE_DRV_PRIV && req->special)
693 memcpy(req->special, &cqe, sizeof(cqe));
694 blk_mq_complete_request(req, le16_to_cpu(cqe.status) >> 1);
698 /* If the controller ignores the cq head doorbell and continuously
699 * writes to the queue, it is theoretically possible to wrap around
700 * the queue twice and mistakenly return IRQ_NONE. Linux only
701 * requires that 0.1% of your interrupts are handled, so this isn't
704 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
707 if (likely(nvmeq->cq_vector >= 0))
708 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
709 nvmeq->cq_head = head;
710 nvmeq->cq_phase = phase;
715 static void nvme_process_cq(struct nvme_queue *nvmeq)
717 __nvme_process_cq(nvmeq, NULL);
720 static irqreturn_t nvme_irq(int irq, void *data)
723 struct nvme_queue *nvmeq = data;
724 spin_lock(&nvmeq->q_lock);
725 nvme_process_cq(nvmeq);
726 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
728 spin_unlock(&nvmeq->q_lock);
732 static irqreturn_t nvme_irq_check(int irq, void *data)
734 struct nvme_queue *nvmeq = data;
735 if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase))
736 return IRQ_WAKE_THREAD;
740 static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
742 struct nvme_queue *nvmeq = hctx->driver_data;
744 if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) {
745 spin_lock_irq(&nvmeq->q_lock);
746 __nvme_process_cq(nvmeq, &tag);
747 spin_unlock_irq(&nvmeq->q_lock);
756 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl, int aer_idx)
758 struct nvme_dev *dev = to_nvme_dev(ctrl);
759 struct nvme_queue *nvmeq = dev->queues[0];
760 struct nvme_command c;
762 memset(&c, 0, sizeof(c));
763 c.common.opcode = nvme_admin_async_event;
764 c.common.command_id = NVME_AQ_BLKMQ_DEPTH + aer_idx;
766 spin_lock_irq(&nvmeq->q_lock);
767 __nvme_submit_cmd(nvmeq, &c);
768 spin_unlock_irq(&nvmeq->q_lock);
771 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
773 struct nvme_command c;
775 memset(&c, 0, sizeof(c));
776 c.delete_queue.opcode = opcode;
777 c.delete_queue.qid = cpu_to_le16(id);
779 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
782 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
783 struct nvme_queue *nvmeq)
785 struct nvme_command c;
786 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
789 * Note: we (ab)use the fact the the prp fields survive if no data
790 * is attached to the request.
792 memset(&c, 0, sizeof(c));
793 c.create_cq.opcode = nvme_admin_create_cq;
794 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
795 c.create_cq.cqid = cpu_to_le16(qid);
796 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
797 c.create_cq.cq_flags = cpu_to_le16(flags);
798 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
800 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
803 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
804 struct nvme_queue *nvmeq)
806 struct nvme_command c;
807 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
810 * Note: we (ab)use the fact the the prp fields survive if no data
811 * is attached to the request.
813 memset(&c, 0, sizeof(c));
814 c.create_sq.opcode = nvme_admin_create_sq;
815 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
816 c.create_sq.sqid = cpu_to_le16(qid);
817 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
818 c.create_sq.sq_flags = cpu_to_le16(flags);
819 c.create_sq.cqid = cpu_to_le16(qid);
821 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
824 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
826 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
829 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
831 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
834 static void abort_endio(struct request *req, int error)
836 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
837 struct nvme_queue *nvmeq = iod->nvmeq;
838 u16 status = req->errors;
840 dev_warn(nvmeq->dev->ctrl.device, "Abort status: 0x%x", status);
841 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
842 blk_mq_free_request(req);
845 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
847 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
848 struct nvme_queue *nvmeq = iod->nvmeq;
849 struct nvme_dev *dev = nvmeq->dev;
850 struct request *abort_req;
851 struct nvme_command cmd;
854 * Shutdown immediately if controller times out while starting. The
855 * reset work will see the pci device disabled when it gets the forced
856 * cancellation error. All outstanding requests are completed on
857 * shutdown, so we return BLK_EH_HANDLED.
859 if (dev->ctrl.state == NVME_CTRL_RESETTING) {
860 dev_warn(dev->ctrl.device,
861 "I/O %d QID %d timeout, disable controller\n",
862 req->tag, nvmeq->qid);
863 nvme_dev_disable(dev, false);
864 req->errors = NVME_SC_CANCELLED;
865 return BLK_EH_HANDLED;
869 * Shutdown the controller immediately and schedule a reset if the
870 * command was already aborted once before and still hasn't been
871 * returned to the driver, or if this is the admin queue.
873 if (!nvmeq->qid || iod->aborted) {
874 dev_warn(dev->ctrl.device,
875 "I/O %d QID %d timeout, reset controller\n",
876 req->tag, nvmeq->qid);
877 nvme_dev_disable(dev, false);
878 queue_work(nvme_workq, &dev->reset_work);
881 * Mark the request as handled, since the inline shutdown
882 * forces all outstanding requests to complete.
884 req->errors = NVME_SC_CANCELLED;
885 return BLK_EH_HANDLED;
890 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
891 atomic_inc(&dev->ctrl.abort_limit);
892 return BLK_EH_RESET_TIMER;
895 memset(&cmd, 0, sizeof(cmd));
896 cmd.abort.opcode = nvme_admin_abort_cmd;
897 cmd.abort.cid = req->tag;
898 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
900 dev_warn(nvmeq->dev->ctrl.device,
901 "I/O %d QID %d timeout, aborting\n",
902 req->tag, nvmeq->qid);
904 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
906 if (IS_ERR(abort_req)) {
907 atomic_inc(&dev->ctrl.abort_limit);
908 return BLK_EH_RESET_TIMER;
911 abort_req->timeout = ADMIN_TIMEOUT;
912 abort_req->end_io_data = NULL;
913 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
916 * The aborted req will be completed on receiving the abort req.
917 * We enable the timer again. If hit twice, it'll cause a device reset,
918 * as the device then is in a faulty state.
920 return BLK_EH_RESET_TIMER;
923 static void nvme_cancel_io(struct request *req, void *data, bool reserved)
927 if (!blk_mq_request_started(req))
930 dev_dbg_ratelimited(((struct nvme_dev *) data)->ctrl.device,
931 "Cancelling I/O %d", req->tag);
933 status = NVME_SC_ABORT_REQ;
934 if (blk_queue_dying(req->q))
935 status |= NVME_SC_DNR;
936 blk_mq_complete_request(req, status);
939 static void nvme_free_queue(struct nvme_queue *nvmeq)
941 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
942 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
944 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
945 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
949 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
953 for (i = dev->queue_count - 1; i >= lowest; i--) {
954 struct nvme_queue *nvmeq = dev->queues[i];
956 dev->queues[i] = NULL;
957 nvme_free_queue(nvmeq);
962 * nvme_suspend_queue - put queue into suspended state
963 * @nvmeq - queue to suspend
965 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
969 spin_lock_irq(&nvmeq->q_lock);
970 if (nvmeq->cq_vector == -1) {
971 spin_unlock_irq(&nvmeq->q_lock);
974 vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
975 nvmeq->dev->online_queues--;
976 nvmeq->cq_vector = -1;
977 spin_unlock_irq(&nvmeq->q_lock);
979 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
980 blk_mq_stop_hw_queues(nvmeq->dev->ctrl.admin_q);
982 irq_set_affinity_hint(vector, NULL);
983 free_irq(vector, nvmeq);
988 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
990 struct nvme_queue *nvmeq = dev->queues[0];
994 if (nvme_suspend_queue(nvmeq))
998 nvme_shutdown_ctrl(&dev->ctrl);
1000 nvme_disable_ctrl(&dev->ctrl, lo_hi_readq(
1001 dev->bar + NVME_REG_CAP));
1003 spin_lock_irq(&nvmeq->q_lock);
1004 nvme_process_cq(nvmeq);
1005 spin_unlock_irq(&nvmeq->q_lock);
1008 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1011 int q_depth = dev->q_depth;
1012 unsigned q_size_aligned = roundup(q_depth * entry_size,
1013 dev->ctrl.page_size);
1015 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1016 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1017 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
1018 q_depth = div_u64(mem_per_q, entry_size);
1021 * Ensure the reduced q_depth is above some threshold where it
1022 * would be better to map queues in system memory with the
1032 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1035 if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) {
1036 unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth),
1037 dev->ctrl.page_size);
1038 nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset;
1039 nvmeq->sq_cmds_io = dev->cmb + offset;
1041 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1042 &nvmeq->sq_dma_addr, GFP_KERNEL);
1043 if (!nvmeq->sq_cmds)
1050 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1053 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL);
1057 nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
1058 &nvmeq->cq_dma_addr, GFP_KERNEL);
1062 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
1065 nvmeq->q_dmadev = dev->dev;
1067 snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1068 dev->ctrl.instance, qid);
1069 spin_lock_init(&nvmeq->q_lock);
1071 nvmeq->cq_phase = 1;
1072 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1073 nvmeq->q_depth = depth;
1075 nvmeq->cq_vector = -1;
1076 dev->queues[qid] = nvmeq;
1082 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1083 nvmeq->cq_dma_addr);
1089 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1092 if (use_threaded_interrupts)
1093 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
1094 nvme_irq_check, nvme_irq, IRQF_SHARED,
1096 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
1097 IRQF_SHARED, name, nvmeq);
1100 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1102 struct nvme_dev *dev = nvmeq->dev;
1104 spin_lock_irq(&nvmeq->q_lock);
1107 nvmeq->cq_phase = 1;
1108 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1109 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1110 dev->online_queues++;
1111 spin_unlock_irq(&nvmeq->q_lock);
1114 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1116 struct nvme_dev *dev = nvmeq->dev;
1119 nvmeq->cq_vector = qid - 1;
1120 result = adapter_alloc_cq(dev, qid, nvmeq);
1124 result = adapter_alloc_sq(dev, qid, nvmeq);
1128 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1132 nvme_init_queue(nvmeq, qid);
1136 adapter_delete_sq(dev, qid);
1138 adapter_delete_cq(dev, qid);
1142 static struct blk_mq_ops nvme_mq_admin_ops = {
1143 .queue_rq = nvme_queue_rq,
1144 .complete = nvme_complete_rq,
1145 .map_queue = blk_mq_map_queue,
1146 .init_hctx = nvme_admin_init_hctx,
1147 .exit_hctx = nvme_admin_exit_hctx,
1148 .init_request = nvme_admin_init_request,
1149 .timeout = nvme_timeout,
1152 static struct blk_mq_ops nvme_mq_ops = {
1153 .queue_rq = nvme_queue_rq,
1154 .complete = nvme_complete_rq,
1155 .map_queue = blk_mq_map_queue,
1156 .init_hctx = nvme_init_hctx,
1157 .init_request = nvme_init_request,
1158 .timeout = nvme_timeout,
1162 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1164 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1166 * If the controller was reset during removal, it's possible
1167 * user requests may be waiting on a stopped queue. Start the
1168 * queue to flush these to completion.
1170 blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true);
1171 blk_cleanup_queue(dev->ctrl.admin_q);
1172 blk_mq_free_tag_set(&dev->admin_tagset);
1176 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1178 if (!dev->ctrl.admin_q) {
1179 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1180 dev->admin_tagset.nr_hw_queues = 1;
1183 * Subtract one to leave an empty queue entry for 'Full Queue'
1184 * condition. See NVM-Express 1.2 specification, section 4.1.2.
1186 dev->admin_tagset.queue_depth = NVME_AQ_BLKMQ_DEPTH - 1;
1187 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1188 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1189 dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
1190 dev->admin_tagset.driver_data = dev;
1192 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1195 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1196 if (IS_ERR(dev->ctrl.admin_q)) {
1197 blk_mq_free_tag_set(&dev->admin_tagset);
1200 if (!blk_get_queue(dev->ctrl.admin_q)) {
1201 nvme_dev_remove_admin(dev);
1202 dev->ctrl.admin_q = NULL;
1206 blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true);
1211 static int nvme_configure_admin_queue(struct nvme_dev *dev)
1215 u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1216 struct nvme_queue *nvmeq;
1218 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1) ?
1219 NVME_CAP_NSSRC(cap) : 0;
1221 if (dev->subsystem &&
1222 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1223 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1225 result = nvme_disable_ctrl(&dev->ctrl, cap);
1229 nvmeq = dev->queues[0];
1231 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1236 aqa = nvmeq->q_depth - 1;
1239 writel(aqa, dev->bar + NVME_REG_AQA);
1240 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1241 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1243 result = nvme_enable_ctrl(&dev->ctrl, cap);
1247 nvmeq->cq_vector = 0;
1248 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1250 nvmeq->cq_vector = -1;
1257 nvme_free_queues(dev, 0);
1261 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1264 /* If true, indicates loss of adapter communication, possibly by a
1265 * NVMe Subsystem reset.
1267 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1269 /* If there is a reset ongoing, we shouldn't reset again. */
1270 if (work_busy(&dev->reset_work))
1273 /* We shouldn't reset unless the controller is on fatal error state
1274 * _or_ if we lost the communication with it.
1276 if (!(csts & NVME_CSTS_CFS) && !nssro)
1279 /* If PCI error recovery process is happening, we cannot reset or
1280 * the recovery mechanism will surely fail.
1282 if (pci_channel_offline(to_pci_dev(dev->dev)))
1288 static void nvme_watchdog_timer(unsigned long data)
1290 struct nvme_dev *dev = (struct nvme_dev *)data;
1291 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1293 /* Skip controllers under certain specific conditions. */
1294 if (nvme_should_reset(dev, csts)) {
1295 if (queue_work(nvme_workq, &dev->reset_work))
1297 "Failed status: 0x%x, reset controller.\n",
1302 mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ));
1305 static int nvme_create_io_queues(struct nvme_dev *dev)
1310 for (i = dev->queue_count; i <= dev->max_qid; i++) {
1311 if (!nvme_alloc_queue(dev, i, dev->q_depth)) {
1317 max = min(dev->max_qid, dev->queue_count - 1);
1318 for (i = dev->online_queues; i <= max; i++) {
1319 ret = nvme_create_queue(dev->queues[i], i);
1321 nvme_free_queues(dev, i);
1327 * Ignore failing Create SQ/CQ commands, we can continue with less
1328 * than the desired aount of queues, and even a controller without
1329 * I/O queues an still be used to issue admin commands. This might
1330 * be useful to upgrade a buggy firmware for example.
1332 return ret >= 0 ? 0 : ret;
1335 static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
1337 u64 szu, size, offset;
1339 resource_size_t bar_size;
1340 struct pci_dev *pdev = to_pci_dev(dev->dev);
1342 dma_addr_t dma_addr;
1347 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1348 if (!(NVME_CMB_SZ(dev->cmbsz)))
1351 cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1353 szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz));
1354 size = szu * NVME_CMB_SZ(dev->cmbsz);
1355 offset = szu * NVME_CMB_OFST(cmbloc);
1356 bar_size = pci_resource_len(pdev, NVME_CMB_BIR(cmbloc));
1358 if (offset > bar_size)
1362 * Controllers may support a CMB size larger than their BAR,
1363 * for example, due to being behind a bridge. Reduce the CMB to
1364 * the reported size of the BAR
1366 if (size > bar_size - offset)
1367 size = bar_size - offset;
1369 dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(cmbloc)) + offset;
1370 cmb = ioremap_wc(dma_addr, size);
1374 dev->cmb_dma_addr = dma_addr;
1375 dev->cmb_size = size;
1379 static inline void nvme_release_cmb(struct nvme_dev *dev)
1387 static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1389 return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
1392 static int nvme_setup_io_queues(struct nvme_dev *dev)
1394 struct nvme_queue *adminq = dev->queues[0];
1395 struct pci_dev *pdev = to_pci_dev(dev->dev);
1396 int result, i, vecs, nr_io_queues, size;
1398 nr_io_queues = num_possible_cpus();
1399 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
1404 * Degraded controllers might return an error when setting the queue
1405 * count. We still want to be able to bring them online and offer
1406 * access to the admin queue, as that might be only way to fix them up.
1409 dev_err(dev->ctrl.device,
1410 "Could not set queue count (%d)\n", result);
1414 if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) {
1415 result = nvme_cmb_qdepth(dev, nr_io_queues,
1416 sizeof(struct nvme_command));
1418 dev->q_depth = result;
1420 nvme_release_cmb(dev);
1423 size = db_bar_size(dev, nr_io_queues);
1427 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1430 if (!--nr_io_queues)
1432 size = db_bar_size(dev, nr_io_queues);
1434 dev->dbs = dev->bar + 4096;
1435 adminq->q_db = dev->dbs;
1438 /* Deregister the admin queue's interrupt */
1439 free_irq(dev->entry[0].vector, adminq);
1442 * If we enable msix early due to not intx, disable it again before
1443 * setting up the full range we need.
1445 if (pdev->msi_enabled)
1446 pci_disable_msi(pdev);
1447 else if (pdev->msix_enabled)
1448 pci_disable_msix(pdev);
1450 for (i = 0; i < nr_io_queues; i++)
1451 dev->entry[i].entry = i;
1452 vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues);
1454 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32));
1458 for (i = 0; i < vecs; i++)
1459 dev->entry[i].vector = i + pdev->irq;
1464 * Should investigate if there's a performance win from allocating
1465 * more queues than interrupt vectors; it might allow the submission
1466 * path to scale better, even if the receive path is limited by the
1467 * number of interrupts.
1469 nr_io_queues = vecs;
1470 dev->max_qid = nr_io_queues;
1472 result = queue_request_irq(dev, adminq, adminq->irqname);
1474 adminq->cq_vector = -1;
1477 return nvme_create_io_queues(dev);
1480 nvme_free_queues(dev, 1);
1484 static void nvme_pci_post_scan(struct nvme_ctrl *ctrl)
1486 struct nvme_dev *dev = to_nvme_dev(ctrl);
1487 struct nvme_queue *nvmeq;
1490 for (i = 0; i < dev->online_queues; i++) {
1491 nvmeq = dev->queues[i];
1493 if (!nvmeq->tags || !(*nvmeq->tags))
1496 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
1497 blk_mq_tags_cpumask(*nvmeq->tags));
1501 static void nvme_del_queue_end(struct request *req, int error)
1503 struct nvme_queue *nvmeq = req->end_io_data;
1505 blk_mq_free_request(req);
1506 complete(&nvmeq->dev->ioq_wait);
1509 static void nvme_del_cq_end(struct request *req, int error)
1511 struct nvme_queue *nvmeq = req->end_io_data;
1514 unsigned long flags;
1517 * We might be called with the AQ q_lock held
1518 * and the I/O queue q_lock should always
1519 * nest inside the AQ one.
1521 spin_lock_irqsave_nested(&nvmeq->q_lock, flags,
1522 SINGLE_DEPTH_NESTING);
1523 nvme_process_cq(nvmeq);
1524 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
1527 nvme_del_queue_end(req, error);
1530 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
1532 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
1533 struct request *req;
1534 struct nvme_command cmd;
1536 memset(&cmd, 0, sizeof(cmd));
1537 cmd.delete_queue.opcode = opcode;
1538 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
1540 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT);
1542 return PTR_ERR(req);
1544 req->timeout = ADMIN_TIMEOUT;
1545 req->end_io_data = nvmeq;
1547 blk_execute_rq_nowait(q, NULL, req, false,
1548 opcode == nvme_admin_delete_cq ?
1549 nvme_del_cq_end : nvme_del_queue_end);
1553 static void nvme_disable_io_queues(struct nvme_dev *dev)
1556 unsigned long timeout;
1557 u8 opcode = nvme_admin_delete_sq;
1559 for (pass = 0; pass < 2; pass++) {
1560 int sent = 0, i = dev->queue_count - 1;
1562 reinit_completion(&dev->ioq_wait);
1564 timeout = ADMIN_TIMEOUT;
1565 for (; i > 0; i--) {
1566 struct nvme_queue *nvmeq = dev->queues[i];
1569 nvme_suspend_queue(nvmeq);
1570 if (nvme_delete_queue(nvmeq, opcode))
1575 timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout);
1581 opcode = nvme_admin_delete_cq;
1586 * Return: error value if an error occurred setting up the queues or calling
1587 * Identify Device. 0 if these succeeded, even if adding some of the
1588 * namespaces failed. At the moment, these failures are silent. TBD which
1589 * failures should be reported.
1591 static int nvme_dev_add(struct nvme_dev *dev)
1593 if (!dev->ctrl.tagset) {
1594 dev->tagset.ops = &nvme_mq_ops;
1595 dev->tagset.nr_hw_queues = dev->online_queues - 1;
1596 dev->tagset.timeout = NVME_IO_TIMEOUT;
1597 dev->tagset.numa_node = dev_to_node(dev->dev);
1598 dev->tagset.queue_depth =
1599 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
1600 dev->tagset.cmd_size = nvme_cmd_size(dev);
1601 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
1602 dev->tagset.driver_data = dev;
1604 if (blk_mq_alloc_tag_set(&dev->tagset))
1606 dev->ctrl.tagset = &dev->tagset;
1608 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
1610 /* Free previously allocated queues that are no longer usable */
1611 nvme_free_queues(dev, dev->online_queues);
1617 static int nvme_pci_enable(struct nvme_dev *dev)
1620 int result = -ENOMEM;
1621 struct pci_dev *pdev = to_pci_dev(dev->dev);
1623 if (pci_enable_device_mem(pdev))
1626 pci_set_master(pdev);
1628 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
1629 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
1632 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
1638 * Some devices and/or platforms don't advertise or work with INTx
1639 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
1640 * adjust this later.
1642 if (pci_enable_msix(pdev, dev->entry, 1)) {
1643 pci_enable_msi(pdev);
1644 dev->entry[0].vector = pdev->irq;
1647 if (!dev->entry[0].vector) {
1652 cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1654 dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
1655 dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
1656 dev->dbs = dev->bar + 4096;
1659 * Temporary fix for the Apple controller found in the MacBook8,1 and
1660 * some MacBook7,1 to avoid controller resets and data loss.
1662 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
1664 dev_warn(dev->dev, "detected Apple NVMe controller, set "
1665 "queue depth=%u to work around controller resets\n",
1669 if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2))
1670 dev->cmb = nvme_map_cmb(dev);
1672 pci_enable_pcie_error_reporting(pdev);
1673 pci_save_state(pdev);
1677 pci_disable_device(pdev);
1681 static void nvme_dev_unmap(struct nvme_dev *dev)
1685 pci_release_regions(to_pci_dev(dev->dev));
1688 static void nvme_pci_disable(struct nvme_dev *dev)
1690 struct pci_dev *pdev = to_pci_dev(dev->dev);
1692 if (pdev->msi_enabled)
1693 pci_disable_msi(pdev);
1694 else if (pdev->msix_enabled)
1695 pci_disable_msix(pdev);
1697 if (pci_is_enabled(pdev)) {
1698 pci_disable_pcie_error_reporting(pdev);
1699 pci_disable_device(pdev);
1703 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
1708 del_timer_sync(&dev->watchdog_timer);
1710 mutex_lock(&dev->shutdown_lock);
1711 if (pci_is_enabled(to_pci_dev(dev->dev))) {
1712 nvme_stop_queues(&dev->ctrl);
1713 csts = readl(dev->bar + NVME_REG_CSTS);
1715 if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) {
1716 for (i = dev->queue_count - 1; i >= 0; i--) {
1717 struct nvme_queue *nvmeq = dev->queues[i];
1718 nvme_suspend_queue(nvmeq);
1721 nvme_disable_io_queues(dev);
1722 nvme_disable_admin_queue(dev, shutdown);
1724 nvme_pci_disable(dev);
1726 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_io, dev);
1727 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_io, dev);
1728 mutex_unlock(&dev->shutdown_lock);
1731 static int nvme_setup_prp_pools(struct nvme_dev *dev)
1733 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
1734 PAGE_SIZE, PAGE_SIZE, 0);
1735 if (!dev->prp_page_pool)
1738 /* Optimisation for I/Os between 4k and 128k */
1739 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
1741 if (!dev->prp_small_pool) {
1742 dma_pool_destroy(dev->prp_page_pool);
1748 static void nvme_release_prp_pools(struct nvme_dev *dev)
1750 dma_pool_destroy(dev->prp_page_pool);
1751 dma_pool_destroy(dev->prp_small_pool);
1754 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
1756 struct nvme_dev *dev = to_nvme_dev(ctrl);
1758 put_device(dev->dev);
1759 if (dev->tagset.tags)
1760 blk_mq_free_tag_set(&dev->tagset);
1761 if (dev->ctrl.admin_q)
1762 blk_put_queue(dev->ctrl.admin_q);
1768 static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
1770 dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
1772 kref_get(&dev->ctrl.kref);
1773 nvme_dev_disable(dev, false);
1774 if (!schedule_work(&dev->remove_work))
1775 nvme_put_ctrl(&dev->ctrl);
1778 static void nvme_reset_work(struct work_struct *work)
1780 struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
1781 int result = -ENODEV;
1783 if (WARN_ON(dev->ctrl.state == NVME_CTRL_RESETTING))
1787 * If we're called to reset a live controller first shut it down before
1790 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
1791 nvme_dev_disable(dev, false);
1793 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING))
1796 result = nvme_pci_enable(dev);
1800 result = nvme_configure_admin_queue(dev);
1804 nvme_init_queue(dev->queues[0], 0);
1805 result = nvme_alloc_admin_tags(dev);
1809 result = nvme_init_identify(&dev->ctrl);
1813 result = nvme_setup_io_queues(dev);
1818 * A controller that can not execute IO typically requires user
1819 * intervention to correct. For such degraded controllers, the driver
1820 * should not submit commands the user did not request, so skip
1821 * registering for asynchronous event notification on this condition.
1823 if (dev->online_queues > 1)
1824 nvme_queue_async_events(&dev->ctrl);
1826 mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ));
1829 * Keep the controller around but remove all namespaces if we don't have
1830 * any working I/O queue.
1832 if (dev->online_queues < 2) {
1833 dev_warn(dev->ctrl.device, "IO queues not created\n");
1834 nvme_kill_queues(&dev->ctrl);
1835 nvme_remove_namespaces(&dev->ctrl);
1837 nvme_start_queues(&dev->ctrl);
1841 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
1842 dev_warn(dev->ctrl.device, "failed to mark controller live\n");
1846 if (dev->online_queues > 1)
1847 nvme_queue_scan(&dev->ctrl);
1851 nvme_remove_dead_ctrl(dev, result);
1854 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
1856 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
1857 struct pci_dev *pdev = to_pci_dev(dev->dev);
1859 nvme_kill_queues(&dev->ctrl);
1860 if (pci_get_drvdata(pdev))
1861 pci_stop_and_remove_bus_device_locked(pdev);
1862 nvme_put_ctrl(&dev->ctrl);
1865 static int nvme_reset(struct nvme_dev *dev)
1867 if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q))
1870 if (!queue_work(nvme_workq, &dev->reset_work))
1873 flush_work(&dev->reset_work);
1877 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
1879 *val = readl(to_nvme_dev(ctrl)->bar + off);
1883 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
1885 writel(val, to_nvme_dev(ctrl)->bar + off);
1889 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
1891 *val = readq(to_nvme_dev(ctrl)->bar + off);
1895 static int nvme_pci_reset_ctrl(struct nvme_ctrl *ctrl)
1897 return nvme_reset(to_nvme_dev(ctrl));
1900 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1901 .module = THIS_MODULE,
1902 .reg_read32 = nvme_pci_reg_read32,
1903 .reg_write32 = nvme_pci_reg_write32,
1904 .reg_read64 = nvme_pci_reg_read64,
1905 .reset_ctrl = nvme_pci_reset_ctrl,
1906 .free_ctrl = nvme_pci_free_ctrl,
1907 .post_scan = nvme_pci_post_scan,
1908 .submit_async_event = nvme_pci_submit_async_event,
1911 static int nvme_dev_map(struct nvme_dev *dev)
1914 struct pci_dev *pdev = to_pci_dev(dev->dev);
1916 bars = pci_select_bars(pdev, IORESOURCE_MEM);
1919 if (pci_request_selected_regions(pdev, bars, "nvme"))
1922 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1928 pci_release_regions(pdev);
1932 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1934 int node, result = -ENOMEM;
1935 struct nvme_dev *dev;
1937 node = dev_to_node(&pdev->dev);
1938 if (node == NUMA_NO_NODE)
1939 set_dev_node(&pdev->dev, 0);
1941 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
1944 dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry),
1948 dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
1953 dev->dev = get_device(&pdev->dev);
1954 pci_set_drvdata(pdev, dev);
1956 result = nvme_dev_map(dev);
1960 INIT_WORK(&dev->reset_work, nvme_reset_work);
1961 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
1962 setup_timer(&dev->watchdog_timer, nvme_watchdog_timer,
1963 (unsigned long)dev);
1964 mutex_init(&dev->shutdown_lock);
1965 init_completion(&dev->ioq_wait);
1967 result = nvme_setup_prp_pools(dev);
1971 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
1976 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
1978 queue_work(nvme_workq, &dev->reset_work);
1982 nvme_release_prp_pools(dev);
1984 put_device(dev->dev);
1985 nvme_dev_unmap(dev);
1993 static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
1995 struct nvme_dev *dev = pci_get_drvdata(pdev);
1998 nvme_dev_disable(dev, false);
2000 queue_work(nvme_workq, &dev->reset_work);
2003 static void nvme_shutdown(struct pci_dev *pdev)
2005 struct nvme_dev *dev = pci_get_drvdata(pdev);
2006 nvme_dev_disable(dev, true);
2010 * The driver's remove may be called on a device in a partially initialized
2011 * state. This function must not have any dependencies on the device state in
2014 static void nvme_remove(struct pci_dev *pdev)
2016 struct nvme_dev *dev = pci_get_drvdata(pdev);
2018 del_timer_sync(&dev->watchdog_timer);
2020 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2022 pci_set_drvdata(pdev, NULL);
2023 nvme_uninit_ctrl(&dev->ctrl);
2024 nvme_dev_disable(dev, true);
2025 flush_work(&dev->reset_work);
2026 nvme_dev_remove_admin(dev);
2027 nvme_free_queues(dev, 0);
2028 nvme_release_cmb(dev);
2029 nvme_release_prp_pools(dev);
2030 nvme_dev_unmap(dev);
2031 nvme_put_ctrl(&dev->ctrl);
2034 #ifdef CONFIG_PM_SLEEP
2035 static int nvme_suspend(struct device *dev)
2037 struct pci_dev *pdev = to_pci_dev(dev);
2038 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2040 nvme_dev_disable(ndev, true);
2044 static int nvme_resume(struct device *dev)
2046 struct pci_dev *pdev = to_pci_dev(dev);
2047 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2049 queue_work(nvme_workq, &ndev->reset_work);
2054 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
2056 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2057 pci_channel_state_t state)
2059 struct nvme_dev *dev = pci_get_drvdata(pdev);
2062 * A frozen channel requires a reset. When detected, this method will
2063 * shutdown the controller to quiesce. The controller will be restarted
2064 * after the slot reset through driver's slot_reset callback.
2066 dev_warn(dev->ctrl.device, "error detected: state:%d\n", state);
2068 case pci_channel_io_normal:
2069 return PCI_ERS_RESULT_CAN_RECOVER;
2070 case pci_channel_io_frozen:
2071 nvme_dev_disable(dev, false);
2072 return PCI_ERS_RESULT_NEED_RESET;
2073 case pci_channel_io_perm_failure:
2074 return PCI_ERS_RESULT_DISCONNECT;
2076 return PCI_ERS_RESULT_NEED_RESET;
2079 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2081 struct nvme_dev *dev = pci_get_drvdata(pdev);
2083 dev_info(dev->ctrl.device, "restart after slot reset\n");
2084 pci_restore_state(pdev);
2085 queue_work(nvme_workq, &dev->reset_work);
2086 return PCI_ERS_RESULT_RECOVERED;
2089 static void nvme_error_resume(struct pci_dev *pdev)
2091 pci_cleanup_aer_uncorrect_error_status(pdev);
2094 static const struct pci_error_handlers nvme_err_handler = {
2095 .error_detected = nvme_error_detected,
2096 .slot_reset = nvme_slot_reset,
2097 .resume = nvme_error_resume,
2098 .reset_notify = nvme_reset_notify,
2101 /* Move to pci_ids.h later */
2102 #define PCI_CLASS_STORAGE_EXPRESS 0x010802
2104 static const struct pci_device_id nvme_id_table[] = {
2105 { PCI_VDEVICE(INTEL, 0x0953),
2106 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2107 NVME_QUIRK_DISCARD_ZEROES, },
2108 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
2109 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
2110 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2111 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
2114 MODULE_DEVICE_TABLE(pci, nvme_id_table);
2116 static struct pci_driver nvme_driver = {
2118 .id_table = nvme_id_table,
2119 .probe = nvme_probe,
2120 .remove = nvme_remove,
2121 .shutdown = nvme_shutdown,
2123 .pm = &nvme_dev_pm_ops,
2125 .err_handler = &nvme_err_handler,
2128 static int __init nvme_init(void)
2132 nvme_workq = alloc_workqueue("nvme", WQ_UNBOUND | WQ_MEM_RECLAIM, 0);
2136 result = pci_register_driver(&nvme_driver);
2138 destroy_workqueue(nvme_workq);
2142 static void __exit nvme_exit(void)
2144 pci_unregister_driver(&nvme_driver);
2145 destroy_workqueue(nvme_workq);
2149 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2150 MODULE_LICENSE("GPL");
2151 MODULE_VERSION("1.0");
2152 module_init(nvme_init);
2153 module_exit(nvme_exit);