drivers/nvme/host/pci.c

   1 /*
   2  * NVM Express device driver
   3  * Copyright (c) 2011-2014, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  */
  14
  15 #include <linux/aer.h>
  16 #include <linux/bitops.h>
  17 #include <linux/blkdev.h>
  18 #include <linux/blk-mq.h>
  19 #include <linux/cpu.h>
  20 #include <linux/delay.h>
  21 #include <linux/errno.h>
  22 #include <linux/fs.h>
  23 #include <linux/genhd.h>
  24 #include <linux/hdreg.h>
  25 #include <linux/idr.h>
  26 #include <linux/init.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/io.h>
  29 #include <linux/kdev_t.h>
  30 #include <linux/kernel.h>
  31 #include <linux/mm.h>
  32 #include <linux/module.h>
  33 #include <linux/moduleparam.h>
  34 #include <linux/mutex.h>
  35 #include <linux/pci.h>
  36 #include <linux/poison.h>
  37 #include <linux/ptrace.h>
  38 #include <linux/sched.h>
  39 #include <linux/slab.h>
  40 #include <linux/t10-pi.h>
  41 #include <linux/timer.h>
  42 #include <linux/types.h>
  43 #include <linux/io-64-nonatomic-lo-hi.h>
  44 #include <asm/unaligned.h>
  45
  46 #include "nvme.h"
  47
  48 #define NVME_Q_DEPTH            1024
  49 #define NVME_AQ_DEPTH           256
  50 #define SQ_SIZE(depth)          (depth * sizeof(struct nvme_command))
  51 #define CQ_SIZE(depth)          (depth * sizeof(struct nvme_completion))
  52
  53 /*
  54  * We handle AEN commands ourselves and don't even let the
  55  * block layer know about them.
  56  */
  57 #define NVME_NR_AEN_COMMANDS    1
  58 #define NVME_AQ_BLKMQ_DEPTH     (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
  59
  60 static int use_threaded_interrupts;
  61 module_param(use_threaded_interrupts, int, 0);
  62
  63 static bool use_cmb_sqes = true;
  64 module_param(use_cmb_sqes, bool, 0644);
  65 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
  66
  67 static struct workqueue_struct *nvme_workq;
  68
  69 struct nvme_dev;
  70 struct nvme_queue;
  71
  72 static int nvme_reset(struct nvme_dev *dev);
  73 static void nvme_process_cq(struct nvme_queue *nvmeq);
  74 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
  75
  76 /*
  77  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
  78  */
  79 struct nvme_dev {
  80         struct nvme_queue **queues;
  81         struct blk_mq_tag_set tagset;
  82         struct blk_mq_tag_set admin_tagset;
  83         u32 __iomem *dbs;
  84         struct device *dev;
  85         struct dma_pool *prp_page_pool;
  86         struct dma_pool *prp_small_pool;
  87         unsigned queue_count;
  88         unsigned online_queues;
  89         unsigned max_qid;
  90         int q_depth;
  91         u32 db_stride;
  92         struct msix_entry *entry;
  93         void __iomem *bar;
  94         struct work_struct reset_work;
  95         struct work_struct scan_work;
  96         struct work_struct remove_work;
  97         struct work_struct async_work;
  98         struct timer_list watchdog_timer;
  99         struct mutex shutdown_lock;
 100         bool subsystem;
 101         void __iomem *cmb;
 102         dma_addr_t cmb_dma_addr;
 103         u64 cmb_size;
 104         u32 cmbsz;
 105         struct nvme_ctrl ctrl;
 106         struct completion ioq_wait;
 107 };
 108
 109 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
 110 {
 111         return container_of(ctrl, struct nvme_dev, ctrl);
 112 }
 113
 114 /*
 115  * An NVM Express queue.  Each device has at least two (one for admin
 116  * commands and one for I/O commands).
 117  */
 118 struct nvme_queue {
 119         struct device *q_dmadev;
 120         struct nvme_dev *dev;
 121         char irqname[24];       /* nvme4294967295-65535\0 */
 122         spinlock_t q_lock;
 123         struct nvme_command *sq_cmds;
 124         struct nvme_command __iomem *sq_cmds_io;
 125         volatile struct nvme_completion *cqes;
 126         struct blk_mq_tags **tags;
 127         dma_addr_t sq_dma_addr;
 128         dma_addr_t cq_dma_addr;
 129         u32 __iomem *q_db;
 130         u16 q_depth;
 131         s16 cq_vector;
 132         u16 sq_tail;
 133         u16 cq_head;
 134         u16 qid;
 135         u8 cq_phase;
 136         u8 cqe_seen;
 137 };
 138
 139 /*
 140  * The nvme_iod describes the data in an I/O, including the list of PRP
 141  * entries.  You can't see it in this data structure because C doesn't let
 142  * me express that.  Use nvme_init_iod to ensure there's enough space
 143  * allocated to store the PRP list.
 144  */
 145 struct nvme_iod {
 146         struct nvme_queue *nvmeq;
 147         int aborted;
 148         int npages;             /* In the PRP list. 0 means small pool in use */
 149         int nents;              /* Used in scatterlist */
 150         int length;             /* Of data, in bytes */
 151         dma_addr_t first_dma;
 152         struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
 153         struct scatterlist *sg;
 154         struct scatterlist inline_sg[0];
 155 };
 156
 157 /*
 158  * Check we didin't inadvertently grow the command struct
 159  */
 160 static inline void _nvme_check_size(void)
 161 {
 162         BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
 163         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
 164         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
 165         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
 166         BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
 167         BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
 168         BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
 169         BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
 170         BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
 171         BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
 172         BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
 173         BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
 174 }
 175
 176 /*
 177  * Max size of iod being embedded in the request payload
 178  */
 179 #define NVME_INT_PAGES          2
 180 #define NVME_INT_BYTES(dev)     (NVME_INT_PAGES * (dev)->ctrl.page_size)
 181
 182 /*
 183  * Will slightly overestimate the number of pages needed.  This is OK
 184  * as it only leads to a small amount of wasted memory for the lifetime of
 185  * the I/O.
 186  */
 187 static int nvme_npages(unsigned size, struct nvme_dev *dev)
 188 {
 189         unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
 190                                       dev->ctrl.page_size);
 191         return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
 192 }
 193
 194 static unsigned int nvme_iod_alloc_size(struct nvme_dev *dev,
 195                 unsigned int size, unsigned int nseg)
 196 {
 197         return sizeof(__le64 *) * nvme_npages(size, dev) +
 198                         sizeof(struct scatterlist) * nseg;
 199 }
 200
 201 static unsigned int nvme_cmd_size(struct nvme_dev *dev)
 202 {
 203         return sizeof(struct nvme_iod) +
 204                 nvme_iod_alloc_size(dev, NVME_INT_BYTES(dev), NVME_INT_PAGES);
 205 }
 206
 207 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 208                                 unsigned int hctx_idx)
 209 {
 210         struct nvme_dev *dev = data;
 211         struct nvme_queue *nvmeq = dev->queues[0];
 212
 213         WARN_ON(hctx_idx != 0);
 214         WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
 215         WARN_ON(nvmeq->tags);
 216
 217         hctx->driver_data = nvmeq;
 218         nvmeq->tags = &dev->admin_tagset.tags[0];
 219         return 0;
 220 }
 221
 222 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
 223 {
 224         struct nvme_queue *nvmeq = hctx->driver_data;
 225
 226         nvmeq->tags = NULL;
 227 }
 228
 229 static int nvme_admin_init_request(void *data, struct request *req,
 230                                 unsigned int hctx_idx, unsigned int rq_idx,
 231                                 unsigned int numa_node)
 232 {
 233         struct nvme_dev *dev = data;
 234         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 235         struct nvme_queue *nvmeq = dev->queues[0];
 236
 237         BUG_ON(!nvmeq);
 238         iod->nvmeq = nvmeq;
 239         return 0;
 240 }
 241
 242 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 243                           unsigned int hctx_idx)
 244 {
 245         struct nvme_dev *dev = data;
 246         struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
 247
 248         if (!nvmeq->tags)
 249                 nvmeq->tags = &dev->tagset.tags[hctx_idx];
 250
 251         WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
 252         hctx->driver_data = nvmeq;
 253         return 0;
 254 }
 255
 256 static int nvme_init_request(void *data, struct request *req,
 257                                 unsigned int hctx_idx, unsigned int rq_idx,
 258                                 unsigned int numa_node)
 259 {
 260         struct nvme_dev *dev = data;
 261         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 262         struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
 263
 264         BUG_ON(!nvmeq);
 265         iod->nvmeq = nvmeq;
 266         return 0;
 267 }
 268
 269 static void nvme_queue_scan(struct nvme_dev *dev)
 270 {
 271         /*
 272          * Do not queue new scan work when a controller is reset during
 273          * removal.
 274          */
 275         if (dev->ctrl.state == NVME_CTRL_LIVE)
 276                 queue_work(nvme_workq, &dev->scan_work);
 277 }
 278
 279 static void nvme_complete_async_event(struct nvme_dev *dev,
 280                 struct nvme_completion *cqe)
 281 {
 282         u16 status = le16_to_cpu(cqe->status) >> 1;
 283         u32 result = le32_to_cpu(cqe->result);
 284
 285         if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ) {
 286                 ++dev->ctrl.event_limit;
 287                 queue_work(nvme_workq, &dev->async_work);
 288         }
 289
 290         if (status != NVME_SC_SUCCESS)
 291                 return;
 292
 293         switch (result & 0xff07) {
 294         case NVME_AER_NOTICE_NS_CHANGED:
 295                 dev_info(dev->ctrl.device, "rescanning\n");
 296                 nvme_queue_scan(dev);
 297         default:
 298                 dev_warn(dev->ctrl.device, "async event result %08x\n", result);
 299         }
 300 }
 301
 302 /**
 303  * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
 304  * @nvmeq: The queue to use
 305  * @cmd: The command to send
 306  *
 307  * Safe to use from interrupt context
 308  */
 309 static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
 310                                                 struct nvme_command *cmd)
 311 {
 312         u16 tail = nvmeq->sq_tail;
 313
 314         if (nvmeq->sq_cmds_io)
 315                 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
 316         else
 317                 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
 318
 319         if (++tail == nvmeq->q_depth)
 320                 tail = 0;
 321         writel(tail, nvmeq->q_db);
 322         nvmeq->sq_tail = tail;
 323 }
 324
 325 static __le64 **iod_list(struct request *req)
 326 {
 327         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 328         return (__le64 **)(iod->sg + req->nr_phys_segments);
 329 }
 330
 331 static int nvme_init_iod(struct request *rq, unsigned size,
 332                 struct nvme_dev *dev)
 333 {
 334         struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
 335         int nseg = rq->nr_phys_segments;
 336
 337         if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
 338                 iod->sg = kmalloc(nvme_iod_alloc_size(dev, size, nseg), GFP_ATOMIC);
 339                 if (!iod->sg)
 340                         return BLK_MQ_RQ_QUEUE_BUSY;
 341         } else {
 342                 iod->sg = iod->inline_sg;
 343         }
 344
 345         iod->aborted = 0;
 346         iod->npages = -1;
 347         iod->nents = 0;
 348         iod->length = size;
 349         return 0;
 350 }
 351
 352 static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
 353 {
 354         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 355         const int last_prp = dev->ctrl.page_size / 8 - 1;
 356         int i;
 357         __le64 **list = iod_list(req);
 358         dma_addr_t prp_dma = iod->first_dma;
 359
 360         if (req->cmd_flags & REQ_DISCARD)
 361                 kfree(req->completion_data);
 362
 363         if (iod->npages == 0)
 364                 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
 365         for (i = 0; i < iod->npages; i++) {
 366                 __le64 *prp_list = list[i];
 367                 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
 368                 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
 369                 prp_dma = next_prp_dma;
 370         }
 371
 372         if (iod->sg != iod->inline_sg)
 373                 kfree(iod->sg);
 374 }
 375
 376 #ifdef CONFIG_BLK_DEV_INTEGRITY
 377 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
 378 {
 379         if (be32_to_cpu(pi->ref_tag) == v)
 380                 pi->ref_tag = cpu_to_be32(p);
 381 }
 382
 383 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
 384 {
 385         if (be32_to_cpu(pi->ref_tag) == p)
 386                 pi->ref_tag = cpu_to_be32(v);
 387 }
 388
 389 /**
 390  * nvme_dif_remap - remaps ref tags to bip seed and physical lba
 391  *
 392  * The virtual start sector is the one that was originally submitted by the
 393  * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
 394  * start sector may be different. Remap protection information to match the
 395  * physical LBA on writes, and back to the original seed on reads.
 396  *
 397  * Type 0 and 3 do not have a ref tag, so no remapping required.
 398  */
 399 static void nvme_dif_remap(struct request *req,
 400                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
 401 {
 402         struct nvme_ns *ns = req->rq_disk->private_data;
 403         struct bio_integrity_payload *bip;
 404         struct t10_pi_tuple *pi;
 405         void *p, *pmap;
 406         u32 i, nlb, ts, phys, virt;
 407
 408         if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
 409                 return;
 410
 411         bip = bio_integrity(req->bio);
 412         if (!bip)
 413                 return;
 414
 415         pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
 416
 417         p = pmap;
 418         virt = bip_get_seed(bip);
 419         phys = nvme_block_nr(ns, blk_rq_pos(req));
 420         nlb = (blk_rq_bytes(req) >> ns->lba_shift);
 421         ts = ns->disk->queue->integrity.tuple_size;
 422
 423         for (i = 0; i < nlb; i++, virt++, phys++) {
 424                 pi = (struct t10_pi_tuple *)p;
 425                 dif_swap(phys, virt, pi);
 426                 p += ts;
 427         }
 428         kunmap_atomic(pmap);
 429 }
 430 #else /* CONFIG_BLK_DEV_INTEGRITY */
 431 static void nvme_dif_remap(struct request *req,
 432                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
 433 {
 434 }
 435 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
 436 {
 437 }
 438 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
 439 {
 440 }
 441 #endif
 442
 443 static bool nvme_setup_prps(struct nvme_dev *dev, struct request *req,
 444                 int total_len)
 445 {
 446         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 447         struct dma_pool *pool;
 448         int length = total_len;
 449         struct scatterlist *sg = iod->sg;
 450         int dma_len = sg_dma_len(sg);
 451         u64 dma_addr = sg_dma_address(sg);
 452         u32 page_size = dev->ctrl.page_size;
 453         int offset = dma_addr & (page_size - 1);
 454         __le64 *prp_list;
 455         __le64 **list = iod_list(req);
 456         dma_addr_t prp_dma;
 457         int nprps, i;
 458
 459         length -= (page_size - offset);
 460         if (length <= 0)
 461                 return true;
 462
 463         dma_len -= (page_size - offset);
 464         if (dma_len) {
 465                 dma_addr += (page_size - offset);
 466         } else {
 467                 sg = sg_next(sg);
 468                 dma_addr = sg_dma_address(sg);
 469                 dma_len = sg_dma_len(sg);
 470         }
 471
 472         if (length <= page_size) {
 473                 iod->first_dma = dma_addr;
 474                 return true;
 475         }
 476
 477         nprps = DIV_ROUND_UP(length, page_size);
 478         if (nprps <= (256 / 8)) {
 479                 pool = dev->prp_small_pool;
 480                 iod->npages = 0;
 481         } else {
 482                 pool = dev->prp_page_pool;
 483                 iod->npages = 1;
 484         }
 485
 486         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 487         if (!prp_list) {
 488                 iod->first_dma = dma_addr;
 489                 iod->npages = -1;
 490                 return false;
 491         }
 492         list[0] = prp_list;
 493         iod->first_dma = prp_dma;
 494         i = 0;
 495         for (;;) {
 496                 if (i == page_size >> 3) {
 497                         __le64 *old_prp_list = prp_list;
 498                         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 499                         if (!prp_list)
 500                                 return false;
 501                         list[iod->npages++] = prp_list;
 502                         prp_list[0] = old_prp_list[i - 1];
 503                         old_prp_list[i - 1] = cpu_to_le64(prp_dma);
 504                         i = 1;
 505                 }
 506                 prp_list[i++] = cpu_to_le64(dma_addr);
 507                 dma_len -= page_size;
 508                 dma_addr += page_size;
 509                 length -= page_size;
 510                 if (length <= 0)
 511                         break;
 512                 if (dma_len > 0)
 513                         continue;
 514                 BUG_ON(dma_len < 0);
 515                 sg = sg_next(sg);
 516                 dma_addr = sg_dma_address(sg);
 517                 dma_len = sg_dma_len(sg);
 518         }
 519
 520         return true;
 521 }
 522
 523 static int nvme_map_data(struct nvme_dev *dev, struct request *req,
 524                 unsigned size, struct nvme_command *cmnd)
 525 {
 526         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 527         struct request_queue *q = req->q;
 528         enum dma_data_direction dma_dir = rq_data_dir(req) ?
 529                         DMA_TO_DEVICE : DMA_FROM_DEVICE;
 530         int ret = BLK_MQ_RQ_QUEUE_ERROR;
 531
 532         sg_init_table(iod->sg, req->nr_phys_segments);
 533         iod->nents = blk_rq_map_sg(q, req, iod->sg);
 534         if (!iod->nents)
 535                 goto out;
 536
 537         ret = BLK_MQ_RQ_QUEUE_BUSY;
 538         if (!dma_map_sg(dev->dev, iod->sg, iod->nents, dma_dir))
 539                 goto out;
 540
 541         if (!nvme_setup_prps(dev, req, size))
 542                 goto out_unmap;
 543
 544         ret = BLK_MQ_RQ_QUEUE_ERROR;
 545         if (blk_integrity_rq(req)) {
 546                 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
 547                         goto out_unmap;
 548
 549                 sg_init_table(&iod->meta_sg, 1);
 550                 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
 551                         goto out_unmap;
 552
 553                 if (rq_data_dir(req))
 554                         nvme_dif_remap(req, nvme_dif_prep);
 555
 556                 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
 557                         goto out_unmap;
 558         }
 559
 560         cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
 561         cmnd->rw.prp2 = cpu_to_le64(iod->first_dma);
 562         if (blk_integrity_rq(req))
 563                 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
 564         return BLK_MQ_RQ_QUEUE_OK;
 565
 566 out_unmap:
 567         dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
 568 out:
 569         return ret;
 570 }
 571
 572 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
 573 {
 574         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 575         enum dma_data_direction dma_dir = rq_data_dir(req) ?
 576                         DMA_TO_DEVICE : DMA_FROM_DEVICE;
 577
 578         if (iod->nents) {
 579                 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
 580                 if (blk_integrity_rq(req)) {
 581                         if (!rq_data_dir(req))
 582                                 nvme_dif_remap(req, nvme_dif_complete);
 583                         dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
 584                 }
 585         }
 586
 587         nvme_free_iod(dev, req);
 588 }
 589
 590 /*
 591  * NOTE: ns is NULL when called on the admin queue.
 592  */
 593 static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
 594                          const struct blk_mq_queue_data *bd)
 595 {
 596         struct nvme_ns *ns = hctx->queue->queuedata;
 597         struct nvme_queue *nvmeq = hctx->driver_data;
 598         struct nvme_dev *dev = nvmeq->dev;
 599         struct request *req = bd->rq;
 600         struct nvme_command cmnd;
 601         unsigned map_len;
 602         int ret = BLK_MQ_RQ_QUEUE_OK;
 603
 604         /*
 605          * If formated with metadata, require the block layer provide a buffer
 606          * unless this namespace is formated such that the metadata can be
 607          * stripped/generated by the controller with PRACT=1.
 608          */
 609         if (ns && ns->ms && !blk_integrity_rq(req)) {
 610                 if (!(ns->pi_type && ns->ms == 8) &&
 611                                         req->cmd_type != REQ_TYPE_DRV_PRIV) {
 612                         blk_mq_end_request(req, -EFAULT);
 613                         return BLK_MQ_RQ_QUEUE_OK;
 614                 }
 615         }
 616
 617         map_len = nvme_map_len(req);
 618         ret = nvme_init_iod(req, map_len, dev);
 619         if (ret)
 620                 return ret;
 621
 622         ret = nvme_setup_cmd(ns, req, &cmnd);
 623         if (ret)
 624                 goto out;
 625
 626         if (req->nr_phys_segments)
 627                 ret = nvme_map_data(dev, req, map_len, &cmnd);
 628
 629         if (ret)
 630                 goto out;
 631
 632         cmnd.common.command_id = req->tag;
 633         blk_mq_start_request(req);
 634
 635         spin_lock_irq(&nvmeq->q_lock);
 636         if (unlikely(nvmeq->cq_vector < 0)) {
 637                 if (ns && !test_bit(NVME_NS_DEAD, &ns->flags))
 638                         ret = BLK_MQ_RQ_QUEUE_BUSY;
 639                 else
 640                         ret = BLK_MQ_RQ_QUEUE_ERROR;
 641                 spin_unlock_irq(&nvmeq->q_lock);
 642                 goto out;
 643         }
 644         __nvme_submit_cmd(nvmeq, &cmnd);
 645         nvme_process_cq(nvmeq);
 646         spin_unlock_irq(&nvmeq->q_lock);
 647         return BLK_MQ_RQ_QUEUE_OK;
 648 out:
 649         nvme_free_iod(dev, req);
 650         return ret;
 651 }
 652
 653 static void nvme_complete_rq(struct request *req)
 654 {
 655         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 656         struct nvme_dev *dev = iod->nvmeq->dev;
 657         int error = 0;
 658
 659         nvme_unmap_data(dev, req);
 660
 661         if (unlikely(req->errors)) {
 662                 if (nvme_req_needs_retry(req, req->errors)) {
 663                         nvme_requeue_req(req);
 664                         return;
 665                 }
 666
 667                 if (req->cmd_type == REQ_TYPE_DRV_PRIV)
 668                         error = req->errors;
 669                 else
 670                         error = nvme_error_status(req->errors);
 671         }
 672
 673         if (unlikely(iod->aborted)) {
 674                 dev_warn(dev->ctrl.device,
 675                         "completing aborted command with status: %04x\n",
 676                         req->errors);
 677         }
 678
 679         blk_mq_end_request(req, error);
 680 }
 681
 682 /* We read the CQE phase first to check if the rest of the entry is valid */
 683 static inline bool nvme_cqe_valid(struct nvme_queue *nvmeq, u16 head,
 684                 u16 phase)
 685 {
 686         return (le16_to_cpu(nvmeq->cqes[head].status) & 1) == phase;
 687 }
 688
 689 static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag)
 690 {
 691         u16 head, phase;
 692
 693         head = nvmeq->cq_head;
 694         phase = nvmeq->cq_phase;
 695
 696         while (nvme_cqe_valid(nvmeq, head, phase)) {
 697                 struct nvme_completion cqe = nvmeq->cqes[head];
 698                 struct request *req;
 699
 700                 if (++head == nvmeq->q_depth) {
 701                         head = 0;
 702                         phase = !phase;
 703                 }
 704
 705                 if (tag && *tag == cqe.command_id)
 706                         *tag = -1;
 707
 708                 if (unlikely(cqe.command_id >= nvmeq->q_depth)) {
 709                         dev_warn(nvmeq->dev->ctrl.device,
 710                                 "invalid id %d completed on queue %d\n",
 711                                 cqe.command_id, le16_to_cpu(cqe.sq_id));
 712                         continue;
 713                 }
 714
 715                 /*
 716                  * AEN requests are special as they don't time out and can
 717                  * survive any kind of queue freeze and often don't respond to
 718                  * aborts.  We don't even bother to allocate a struct request
 719                  * for them but rather special case them here.
 720                  */
 721                 if (unlikely(nvmeq->qid == 0 &&
 722                                 cqe.command_id >= NVME_AQ_BLKMQ_DEPTH)) {
 723                         nvme_complete_async_event(nvmeq->dev, &cqe);
 724                         continue;
 725                 }
 726
 727                 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe.command_id);
 728                 if (req->cmd_type == REQ_TYPE_DRV_PRIV && req->special)
 729                         memcpy(req->special, &cqe, sizeof(cqe));
 730                 blk_mq_complete_request(req, le16_to_cpu(cqe.status) >> 1);
 731
 732         }
 733
 734         /* If the controller ignores the cq head doorbell and continuously
 735          * writes to the queue, it is theoretically possible to wrap around
 736          * the queue twice and mistakenly return IRQ_NONE.  Linux only
 737          * requires that 0.1% of your interrupts are handled, so this isn't
 738          * a big problem.
 739          */
 740         if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
 741                 return;
 742
 743         if (likely(nvmeq->cq_vector >= 0))
 744                 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
 745         nvmeq->cq_head = head;
 746         nvmeq->cq_phase = phase;
 747
 748         nvmeq->cqe_seen = 1;
 749 }
 750
 751 static void nvme_process_cq(struct nvme_queue *nvmeq)
 752 {
 753         __nvme_process_cq(nvmeq, NULL);
 754 }
 755
 756 static irqreturn_t nvme_irq(int irq, void *data)
 757 {
 758         irqreturn_t result;
 759         struct nvme_queue *nvmeq = data;
 760         spin_lock(&nvmeq->q_lock);
 761         nvme_process_cq(nvmeq);
 762         result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
 763         nvmeq->cqe_seen = 0;
 764         spin_unlock(&nvmeq->q_lock);
 765         return result;
 766 }
 767
 768 static irqreturn_t nvme_irq_check(int irq, void *data)
 769 {
 770         struct nvme_queue *nvmeq = data;
 771         if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase))
 772                 return IRQ_WAKE_THREAD;
 773         return IRQ_NONE;
 774 }
 775
 776 static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
 777 {
 778         struct nvme_queue *nvmeq = hctx->driver_data;
 779
 780         if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) {
 781                 spin_lock_irq(&nvmeq->q_lock);
 782                 __nvme_process_cq(nvmeq, &tag);
 783                 spin_unlock_irq(&nvmeq->q_lock);
 784
 785                 if (tag == -1)
 786                         return 1;
 787         }
 788
 789         return 0;
 790 }
 791
 792 static void nvme_async_event_work(struct work_struct *work)
 793 {
 794         struct nvme_dev *dev = container_of(work, struct nvme_dev, async_work);
 795         struct nvme_queue *nvmeq = dev->queues[0];
 796         struct nvme_command c;
 797
 798         memset(&c, 0, sizeof(c));
 799         c.common.opcode = nvme_admin_async_event;
 800
 801         spin_lock_irq(&nvmeq->q_lock);
 802         while (dev->ctrl.event_limit > 0) {
 803                 c.common.command_id = NVME_AQ_BLKMQ_DEPTH +
 804                         --dev->ctrl.event_limit;
 805                 __nvme_submit_cmd(nvmeq, &c);
 806         }
 807         spin_unlock_irq(&nvmeq->q_lock);
 808 }
 809
 810 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
 811 {
 812         struct nvme_command c;
 813
 814         memset(&c, 0, sizeof(c));
 815         c.delete_queue.opcode = opcode;
 816         c.delete_queue.qid = cpu_to_le16(id);
 817
 818         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 819 }
 820
 821 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
 822                                                 struct nvme_queue *nvmeq)
 823 {
 824         struct nvme_command c;
 825         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
 826
 827         /*
 828          * Note: we (ab)use the fact the the prp fields survive if no data
 829          * is attached to the request.
 830          */
 831         memset(&c, 0, sizeof(c));
 832         c.create_cq.opcode = nvme_admin_create_cq;
 833         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
 834         c.create_cq.cqid = cpu_to_le16(qid);
 835         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 836         c.create_cq.cq_flags = cpu_to_le16(flags);
 837         c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
 838
 839         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 840 }
 841
 842 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
 843                                                 struct nvme_queue *nvmeq)
 844 {
 845         struct nvme_command c;
 846         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
 847
 848         /*
 849          * Note: we (ab)use the fact the the prp fields survive if no data
 850          * is attached to the request.
 851          */
 852         memset(&c, 0, sizeof(c));
 853         c.create_sq.opcode = nvme_admin_create_sq;
 854         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
 855         c.create_sq.sqid = cpu_to_le16(qid);
 856         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 857         c.create_sq.sq_flags = cpu_to_le16(flags);
 858         c.create_sq.cqid = cpu_to_le16(qid);
 859
 860         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 861 }
 862
 863 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
 864 {
 865         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
 866 }
 867
 868 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
 869 {
 870         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
 871 }
 872
 873 static void abort_endio(struct request *req, int error)
 874 {
 875         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 876         struct nvme_queue *nvmeq = iod->nvmeq;
 877         u16 status = req->errors;
 878
 879         dev_warn(nvmeq->dev->ctrl.device, "Abort status: 0x%x", status);
 880         atomic_inc(&nvmeq->dev->ctrl.abort_limit);
 881         blk_mq_free_request(req);
 882 }
 883
 884 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
 885 {
 886         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 887         struct nvme_queue *nvmeq = iod->nvmeq;
 888         struct nvme_dev *dev = nvmeq->dev;
 889         struct request *abort_req;
 890         struct nvme_command cmd;
 891
 892         /*
 893          * Shutdown immediately if controller times out while starting. The
 894          * reset work will see the pci device disabled when it gets the forced
 895          * cancellation error. All outstanding requests are completed on
 896          * shutdown, so we return BLK_EH_HANDLED.
 897          */
 898         if (dev->ctrl.state == NVME_CTRL_RESETTING) {
 899                 dev_warn(dev->ctrl.device,
 900                          "I/O %d QID %d timeout, disable controller\n",
 901                          req->tag, nvmeq->qid);
 902                 nvme_dev_disable(dev, false);
 903                 req->errors = NVME_SC_CANCELLED;
 904                 return BLK_EH_HANDLED;
 905         }
 906
 907         /*
 908          * Shutdown the controller immediately and schedule a reset if the
 909          * command was already aborted once before and still hasn't been
 910          * returned to the driver, or if this is the admin queue.
 911          */
 912         if (!nvmeq->qid || iod->aborted) {
 913                 dev_warn(dev->ctrl.device,
 914                          "I/O %d QID %d timeout, reset controller\n",
 915                          req->tag, nvmeq->qid);
 916                 nvme_dev_disable(dev, false);
 917                 queue_work(nvme_workq, &dev->reset_work);
 918
 919                 /*
 920                  * Mark the request as handled, since the inline shutdown
 921                  * forces all outstanding requests to complete.
 922                  */
 923                 req->errors = NVME_SC_CANCELLED;
 924                 return BLK_EH_HANDLED;
 925         }
 926
 927         iod->aborted = 1;
 928
 929         if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
 930                 atomic_inc(&dev->ctrl.abort_limit);
 931                 return BLK_EH_RESET_TIMER;
 932         }
 933
 934         memset(&cmd, 0, sizeof(cmd));
 935         cmd.abort.opcode = nvme_admin_abort_cmd;
 936         cmd.abort.cid = req->tag;
 937         cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
 938
 939         dev_warn(nvmeq->dev->ctrl.device,
 940                 "I/O %d QID %d timeout, aborting\n",
 941                  req->tag, nvmeq->qid);
 942
 943         abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
 944                         BLK_MQ_REQ_NOWAIT);
 945         if (IS_ERR(abort_req)) {
 946                 atomic_inc(&dev->ctrl.abort_limit);
 947                 return BLK_EH_RESET_TIMER;
 948         }
 949
 950         abort_req->timeout = ADMIN_TIMEOUT;
 951         abort_req->end_io_data = NULL;
 952         blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
 953
 954         /*
 955          * The aborted req will be completed on receiving the abort req.
 956          * We enable the timer again. If hit twice, it'll cause a device reset,
 957          * as the device then is in a faulty state.
 958          */
 959         return BLK_EH_RESET_TIMER;
 960 }
 961
 962 static void nvme_cancel_io(struct request *req, void *data, bool reserved)
 963 {
 964         int status;
 965
 966         if (!blk_mq_request_started(req))
 967                 return;
 968
 969         dev_dbg_ratelimited(((struct nvme_dev *) data)->ctrl.device,
 970                                 "Cancelling I/O %d", req->tag);
 971
 972         status = NVME_SC_ABORT_REQ;
 973         if (blk_queue_dying(req->q))
 974                 status |= NVME_SC_DNR;
 975         blk_mq_complete_request(req, status);
 976 }
 977
 978 static void nvme_free_queue(struct nvme_queue *nvmeq)
 979 {
 980         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
 981                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
 982         if (nvmeq->sq_cmds)
 983                 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
 984                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
 985         kfree(nvmeq);
 986 }
 987
 988 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
 989 {
 990         int i;
 991
 992         for (i = dev->queue_count - 1; i >= lowest; i--) {
 993                 struct nvme_queue *nvmeq = dev->queues[i];
 994                 dev->queue_count--;
 995                 dev->queues[i] = NULL;
 996                 nvme_free_queue(nvmeq);
 997         }
 998 }
 999
1000 /**
1001  * nvme_suspend_queue - put queue into suspended state
1002  * @nvmeq - queue to suspend
1003  */
1004 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1005 {
1006         int vector;
1007
1008         spin_lock_irq(&nvmeq->q_lock);
1009         if (nvmeq->cq_vector == -1) {
1010                 spin_unlock_irq(&nvmeq->q_lock);
1011                 return 1;
1012         }
1013         vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
1014         nvmeq->dev->online_queues--;
1015         nvmeq->cq_vector = -1;
1016         spin_unlock_irq(&nvmeq->q_lock);
1017
1018         if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1019                 blk_mq_stop_hw_queues(nvmeq->dev->ctrl.admin_q);
1020
1021         irq_set_affinity_hint(vector, NULL);
1022         free_irq(vector, nvmeq);
1023
1024         return 0;
1025 }
1026
1027 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
1028 {
1029         struct nvme_queue *nvmeq = dev->queues[0];
1030
1031         if (!nvmeq)
1032                 return;
1033         if (nvme_suspend_queue(nvmeq))
1034                 return;
1035
1036         if (shutdown)
1037                 nvme_shutdown_ctrl(&dev->ctrl);
1038         else
1039                 nvme_disable_ctrl(&dev->ctrl, lo_hi_readq(
1040                                                 dev->bar + NVME_REG_CAP));
1041
1042         spin_lock_irq(&nvmeq->q_lock);
1043         nvme_process_cq(nvmeq);
1044         spin_unlock_irq(&nvmeq->q_lock);
1045 }
1046
1047 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1048                                 int entry_size)
1049 {
1050         int q_depth = dev->q_depth;
1051         unsigned q_size_aligned = roundup(q_depth * entry_size,
1052                                           dev->ctrl.page_size);
1053
1054         if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1055                 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1056                 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
1057                 q_depth = div_u64(mem_per_q, entry_size);
1058
1059                 /*
1060                  * Ensure the reduced q_depth is above some threshold where it
1061                  * would be better to map queues in system memory with the
1062                  * original depth
1063                  */
1064                 if (q_depth < 64)
1065                         return -ENOMEM;
1066         }
1067
1068         return q_depth;
1069 }
1070
1071 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1072                                 int qid, int depth)
1073 {
1074         if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) {
1075                 unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth),
1076                                                       dev->ctrl.page_size);
1077                 nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset;
1078                 nvmeq->sq_cmds_io = dev->cmb + offset;
1079         } else {
1080                 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1081                                         &nvmeq->sq_dma_addr, GFP_KERNEL);
1082                 if (!nvmeq->sq_cmds)
1083                         return -ENOMEM;
1084         }
1085
1086         return 0;
1087 }
1088
1089 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1090                                                         int depth)
1091 {
1092         struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL);
1093         if (!nvmeq)
1094                 return NULL;
1095
1096         nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
1097                                           &nvmeq->cq_dma_addr, GFP_KERNEL);
1098         if (!nvmeq->cqes)
1099                 goto free_nvmeq;
1100
1101         if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
1102                 goto free_cqdma;
1103
1104         nvmeq->q_dmadev = dev->dev;
1105         nvmeq->dev = dev;
1106         snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1107                         dev->ctrl.instance, qid);
1108         spin_lock_init(&nvmeq->q_lock);
1109         nvmeq->cq_head = 0;
1110         nvmeq->cq_phase = 1;
1111         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1112         nvmeq->q_depth = depth;
1113         nvmeq->qid = qid;
1114         nvmeq->cq_vector = -1;
1115         dev->queues[qid] = nvmeq;
1116         dev->queue_count++;
1117
1118         return nvmeq;
1119
1120  free_cqdma:
1121         dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1122                                                         nvmeq->cq_dma_addr);
1123  free_nvmeq:
1124         kfree(nvmeq);
1125         return NULL;
1126 }
1127
1128 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1129                                                         const char *name)
1130 {
1131         if (use_threaded_interrupts)
1132                 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
1133                                         nvme_irq_check, nvme_irq, IRQF_SHARED,
1134                                         name, nvmeq);
1135         return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
1136                                 IRQF_SHARED, name, nvmeq);
1137 }
1138
1139 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1140 {
1141         struct nvme_dev *dev = nvmeq->dev;
1142
1143         spin_lock_irq(&nvmeq->q_lock);
1144         nvmeq->sq_tail = 0;
1145         nvmeq->cq_head = 0;
1146         nvmeq->cq_phase = 1;
1147         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1148         memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1149         dev->online_queues++;
1150         spin_unlock_irq(&nvmeq->q_lock);
1151 }
1152
1153 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1154 {
1155         struct nvme_dev *dev = nvmeq->dev;
1156         int result;
1157
1158         nvmeq->cq_vector = qid - 1;
1159         result = adapter_alloc_cq(dev, qid, nvmeq);
1160         if (result < 0)
1161                 return result;
1162
1163         result = adapter_alloc_sq(dev, qid, nvmeq);
1164         if (result < 0)
1165                 goto release_cq;
1166
1167         result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1168         if (result < 0)
1169                 goto release_sq;
1170
1171         nvme_init_queue(nvmeq, qid);
1172         return result;
1173
1174  release_sq:
1175         adapter_delete_sq(dev, qid);
1176  release_cq:
1177         adapter_delete_cq(dev, qid);
1178         return result;
1179 }
1180
1181 static struct blk_mq_ops nvme_mq_admin_ops = {
1182         .queue_rq       = nvme_queue_rq,
1183         .complete       = nvme_complete_rq,
1184         .map_queue      = blk_mq_map_queue,
1185         .init_hctx      = nvme_admin_init_hctx,
1186         .exit_hctx      = nvme_admin_exit_hctx,
1187         .init_request   = nvme_admin_init_request,
1188         .timeout        = nvme_timeout,
1189 };
1190
1191 static struct blk_mq_ops nvme_mq_ops = {
1192         .queue_rq       = nvme_queue_rq,
1193         .complete       = nvme_complete_rq,
1194         .map_queue      = blk_mq_map_queue,
1195         .init_hctx      = nvme_init_hctx,
1196         .init_request   = nvme_init_request,
1197         .timeout        = nvme_timeout,
1198         .poll           = nvme_poll,
1199 };
1200
1201 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1202 {
1203         if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1204                 /*
1205                  * If the controller was reset during removal, it's possible
1206                  * user requests may be waiting on a stopped queue. Start the
1207                  * queue to flush these to completion.
1208                  */
1209                 blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true);
1210                 blk_cleanup_queue(dev->ctrl.admin_q);
1211                 blk_mq_free_tag_set(&dev->admin_tagset);
1212         }
1213 }
1214
1215 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1216 {
1217         if (!dev->ctrl.admin_q) {
1218                 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1219                 dev->admin_tagset.nr_hw_queues = 1;
1220
1221                 /*
1222                  * Subtract one to leave an empty queue entry for 'Full Queue'
1223                  * condition. See NVM-Express 1.2 specification, section 4.1.2.
1224                  */
1225                 dev->admin_tagset.queue_depth = NVME_AQ_BLKMQ_DEPTH - 1;
1226                 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1227                 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1228                 dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
1229                 dev->admin_tagset.driver_data = dev;
1230
1231                 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1232                         return -ENOMEM;
1233
1234                 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1235                 if (IS_ERR(dev->ctrl.admin_q)) {
1236                         blk_mq_free_tag_set(&dev->admin_tagset);
1237                         return -ENOMEM;
1238                 }
1239                 if (!blk_get_queue(dev->ctrl.admin_q)) {
1240                         nvme_dev_remove_admin(dev);
1241                         dev->ctrl.admin_q = NULL;
1242                         return -ENODEV;
1243                 }
1244         } else
1245                 blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true);
1246
1247         return 0;
1248 }
1249
1250 static int nvme_configure_admin_queue(struct nvme_dev *dev)
1251 {
1252         int result;
1253         u32 aqa;
1254         u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1255         struct nvme_queue *nvmeq;
1256
1257         dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1) ?
1258                                                 NVME_CAP_NSSRC(cap) : 0;
1259
1260         if (dev->subsystem &&
1261             (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1262                 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1263
1264         result = nvme_disable_ctrl(&dev->ctrl, cap);
1265         if (result < 0)
1266                 return result;
1267
1268         nvmeq = dev->queues[0];
1269         if (!nvmeq) {
1270                 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1271                 if (!nvmeq)
1272                         return -ENOMEM;
1273         }
1274
1275         aqa = nvmeq->q_depth - 1;
1276         aqa |= aqa << 16;
1277
1278         writel(aqa, dev->bar + NVME_REG_AQA);
1279         lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1280         lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1281
1282         result = nvme_enable_ctrl(&dev->ctrl, cap);
1283         if (result)
1284                 goto free_nvmeq;
1285
1286         nvmeq->cq_vector = 0;
1287         result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1288         if (result) {
1289                 nvmeq->cq_vector = -1;
1290                 goto free_nvmeq;
1291         }
1292
1293         return result;
1294
1295  free_nvmeq:
1296         nvme_free_queues(dev, 0);
1297         return result;
1298 }
1299
1300 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1301 {
1302
1303         /* If true, indicates loss of adapter communication, possibly by a
1304          * NVMe Subsystem reset.
1305          */
1306         bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1307
1308         /* If there is a reset ongoing, we shouldn't reset again. */
1309         if (work_busy(&dev->reset_work))
1310                 return false;
1311
1312         /* We shouldn't reset unless the controller is on fatal error state
1313          * _or_ if we lost the communication with it.
1314          */
1315         if (!(csts & NVME_CSTS_CFS) && !nssro)
1316                 return false;
1317
1318         /* If PCI error recovery process is happening, we cannot reset or
1319          * the recovery mechanism will surely fail.
1320          */
1321         if (pci_channel_offline(to_pci_dev(dev->dev)))
1322                 return false;
1323
1324         return true;
1325 }
1326
1327 static void nvme_watchdog_timer(unsigned long data)
1328 {
1329         struct nvme_dev *dev = (struct nvme_dev *)data;
1330         u32 csts = readl(dev->bar + NVME_REG_CSTS);
1331
1332         /* Skip controllers under certain specific conditions. */
1333         if (nvme_should_reset(dev, csts)) {
1334                 if (queue_work(nvme_workq, &dev->reset_work))
1335                         dev_warn(dev->dev,
1336                                 "Failed status: 0x%x, reset controller.\n",
1337                                 csts);
1338                 return;
1339         }
1340
1341         mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ));
1342 }
1343
1344 static int nvme_create_io_queues(struct nvme_dev *dev)
1345 {
1346         unsigned i, max;
1347         int ret = 0;
1348
1349         for (i = dev->queue_count; i <= dev->max_qid; i++) {
1350                 if (!nvme_alloc_queue(dev, i, dev->q_depth)) {
1351                         ret = -ENOMEM;
1352                         break;
1353                 }
1354         }
1355
1356         max = min(dev->max_qid, dev->queue_count - 1);
1357         for (i = dev->online_queues; i <= max; i++) {
1358                 ret = nvme_create_queue(dev->queues[i], i);
1359                 if (ret) {
1360                         nvme_free_queues(dev, i);
1361                         break;
1362                 }
1363         }
1364
1365         /*
1366          * Ignore failing Create SQ/CQ commands, we can continue with less
1367          * than the desired aount of queues, and even a controller without
1368          * I/O queues an still be used to issue admin commands.  This might
1369          * be useful to upgrade a buggy firmware for example.
1370          */
1371         return ret >= 0 ? 0 : ret;
1372 }
1373
1374 static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
1375 {
1376         u64 szu, size, offset;
1377         u32 cmbloc;
1378         resource_size_t bar_size;
1379         struct pci_dev *pdev = to_pci_dev(dev->dev);
1380         void __iomem *cmb;
1381         dma_addr_t dma_addr;
1382
1383         if (!use_cmb_sqes)
1384                 return NULL;
1385
1386         dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1387         if (!(NVME_CMB_SZ(dev->cmbsz)))
1388                 return NULL;
1389
1390         cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1391
1392         szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz));
1393         size = szu * NVME_CMB_SZ(dev->cmbsz);
1394         offset = szu * NVME_CMB_OFST(cmbloc);
1395         bar_size = pci_resource_len(pdev, NVME_CMB_BIR(cmbloc));
1396
1397         if (offset > bar_size)
1398                 return NULL;
1399
1400         /*
1401          * Controllers may support a CMB size larger than their BAR,
1402          * for example, due to being behind a bridge. Reduce the CMB to
1403          * the reported size of the BAR
1404          */
1405         if (size > bar_size - offset)
1406                 size = bar_size - offset;
1407
1408         dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(cmbloc)) + offset;
1409         cmb = ioremap_wc(dma_addr, size);
1410         if (!cmb)
1411                 return NULL;
1412
1413         dev->cmb_dma_addr = dma_addr;
1414         dev->cmb_size = size;
1415         return cmb;
1416 }
1417
1418 static inline void nvme_release_cmb(struct nvme_dev *dev)
1419 {
1420         if (dev->cmb) {
1421                 iounmap(dev->cmb);
1422                 dev->cmb = NULL;
1423         }
1424 }
1425
1426 static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1427 {
1428         return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
1429 }
1430
1431 static int nvme_setup_io_queues(struct nvme_dev *dev)
1432 {
1433         struct nvme_queue *adminq = dev->queues[0];
1434         struct pci_dev *pdev = to_pci_dev(dev->dev);
1435         int result, i, vecs, nr_io_queues, size;
1436
1437         nr_io_queues = num_possible_cpus();
1438         result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
1439         if (result < 0)
1440                 return result;
1441
1442         /*
1443          * Degraded controllers might return an error when setting the queue
1444          * count.  We still want to be able to bring them online and offer
1445          * access to the admin queue, as that might be only way to fix them up.
1446          */
1447         if (result > 0) {
1448                 dev_err(dev->ctrl.device,
1449                         "Could not set queue count (%d)\n", result);
1450                 return 0;
1451         }
1452
1453         if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) {
1454                 result = nvme_cmb_qdepth(dev, nr_io_queues,
1455                                 sizeof(struct nvme_command));
1456                 if (result > 0)
1457                         dev->q_depth = result;
1458                 else
1459                         nvme_release_cmb(dev);
1460         }
1461
1462         size = db_bar_size(dev, nr_io_queues);
1463         if (size > 8192) {
1464                 iounmap(dev->bar);
1465                 do {
1466                         dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1467                         if (dev->bar)
1468                                 break;
1469                         if (!--nr_io_queues)
1470                                 return -ENOMEM;
1471                         size = db_bar_size(dev, nr_io_queues);
1472                 } while (1);
1473                 dev->dbs = dev->bar + 4096;
1474                 adminq->q_db = dev->dbs;
1475         }
1476
1477         /* Deregister the admin queue's interrupt */
1478         free_irq(dev->entry[0].vector, adminq);
1479
1480         /*
1481          * If we enable msix early due to not intx, disable it again before
1482          * setting up the full range we need.
1483          */
1484         if (pdev->msi_enabled)
1485                 pci_disable_msi(pdev);
1486         else if (pdev->msix_enabled)
1487                 pci_disable_msix(pdev);
1488
1489         for (i = 0; i < nr_io_queues; i++)
1490                 dev->entry[i].entry = i;
1491         vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues);
1492         if (vecs < 0) {
1493                 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32));
1494                 if (vecs < 0) {
1495                         vecs = 1;
1496                 } else {
1497                         for (i = 0; i < vecs; i++)
1498                                 dev->entry[i].vector = i + pdev->irq;
1499                 }
1500         }
1501
1502         /*
1503          * Should investigate if there's a performance win from allocating
1504          * more queues than interrupt vectors; it might allow the submission
1505          * path to scale better, even if the receive path is limited by the
1506          * number of interrupts.
1507          */
1508         nr_io_queues = vecs;
1509         dev->max_qid = nr_io_queues;
1510
1511         result = queue_request_irq(dev, adminq, adminq->irqname);
1512         if (result) {
1513                 adminq->cq_vector = -1;
1514                 goto free_queues;
1515         }
1516         return nvme_create_io_queues(dev);
1517
1518  free_queues:
1519         nvme_free_queues(dev, 1);
1520         return result;
1521 }
1522
1523 static void nvme_set_irq_hints(struct nvme_dev *dev)
1524 {
1525         struct nvme_queue *nvmeq;
1526         int i;
1527
1528         for (i = 0; i < dev->online_queues; i++) {
1529                 nvmeq = dev->queues[i];
1530
1531                 if (!nvmeq->tags || !(*nvmeq->tags))
1532                         continue;
1533
1534                 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
1535                                         blk_mq_tags_cpumask(*nvmeq->tags));
1536         }
1537 }
1538
1539 static void nvme_dev_scan(struct work_struct *work)
1540 {
1541         struct nvme_dev *dev = container_of(work, struct nvme_dev, scan_work);
1542
1543         if (!dev->tagset.tags)
1544                 return;
1545         nvme_scan_namespaces(&dev->ctrl);
1546         nvme_set_irq_hints(dev);
1547 }
1548
1549 static void nvme_del_queue_end(struct request *req, int error)
1550 {
1551         struct nvme_queue *nvmeq = req->end_io_data;
1552
1553         blk_mq_free_request(req);
1554         complete(&nvmeq->dev->ioq_wait);
1555 }
1556
1557 static void nvme_del_cq_end(struct request *req, int error)
1558 {
1559         struct nvme_queue *nvmeq = req->end_io_data;
1560
1561         if (!error) {
1562                 unsigned long flags;
1563
1564                 /*
1565                  * We might be called with the AQ q_lock held
1566                  * and the I/O queue q_lock should always
1567                  * nest inside the AQ one.
1568                  */
1569                 spin_lock_irqsave_nested(&nvmeq->q_lock, flags,
1570                                         SINGLE_DEPTH_NESTING);
1571                 nvme_process_cq(nvmeq);
1572                 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
1573         }
1574
1575         nvme_del_queue_end(req, error);
1576 }
1577
1578 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
1579 {
1580         struct request_queue *q = nvmeq->dev->ctrl.admin_q;
1581         struct request *req;
1582         struct nvme_command cmd;
1583
1584         memset(&cmd, 0, sizeof(cmd));
1585         cmd.delete_queue.opcode = opcode;
1586         cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
1587
1588         req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT);
1589         if (IS_ERR(req))
1590                 return PTR_ERR(req);
1591
1592         req->timeout = ADMIN_TIMEOUT;
1593         req->end_io_data = nvmeq;
1594
1595         blk_execute_rq_nowait(q, NULL, req, false,
1596                         opcode == nvme_admin_delete_cq ?
1597                                 nvme_del_cq_end : nvme_del_queue_end);
1598         return 0;
1599 }
1600
1601 static void nvme_disable_io_queues(struct nvme_dev *dev)
1602 {
1603         int pass;
1604         unsigned long timeout;
1605         u8 opcode = nvme_admin_delete_sq;
1606
1607         for (pass = 0; pass < 2; pass++) {
1608                 int sent = 0, i = dev->queue_count - 1;
1609
1610                 reinit_completion(&dev->ioq_wait);
1611  retry:
1612                 timeout = ADMIN_TIMEOUT;
1613                 for (; i > 0; i--) {
1614                         struct nvme_queue *nvmeq = dev->queues[i];
1615
1616                         if (!pass)
1617                                 nvme_suspend_queue(nvmeq);
1618                         if (nvme_delete_queue(nvmeq, opcode))
1619                                 break;
1620                         ++sent;
1621                 }
1622                 while (sent--) {
1623                         timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout);
1624                         if (timeout == 0)
1625                                 return;
1626                         if (i)
1627                                 goto retry;
1628                 }
1629                 opcode = nvme_admin_delete_cq;
1630         }
1631 }
1632
1633 /*
1634  * Return: error value if an error occurred setting up the queues or calling
1635  * Identify Device.  0 if these succeeded, even if adding some of the
1636  * namespaces failed.  At the moment, these failures are silent.  TBD which
1637  * failures should be reported.
1638  */
1639 static int nvme_dev_add(struct nvme_dev *dev)
1640 {
1641         if (!dev->ctrl.tagset) {
1642                 dev->tagset.ops = &nvme_mq_ops;
1643                 dev->tagset.nr_hw_queues = dev->online_queues - 1;
1644                 dev->tagset.timeout = NVME_IO_TIMEOUT;
1645                 dev->tagset.numa_node = dev_to_node(dev->dev);
1646                 dev->tagset.queue_depth =
1647                                 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
1648                 dev->tagset.cmd_size = nvme_cmd_size(dev);
1649                 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
1650                 dev->tagset.driver_data = dev;
1651
1652                 if (blk_mq_alloc_tag_set(&dev->tagset))
1653                         return 0;
1654                 dev->ctrl.tagset = &dev->tagset;
1655         } else {
1656                 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
1657
1658                 /* Free previously allocated queues that are no longer usable */
1659                 nvme_free_queues(dev, dev->online_queues);
1660         }
1661
1662         return 0;
1663 }
1664
1665 static int nvme_pci_enable(struct nvme_dev *dev)
1666 {
1667         u64 cap;
1668         int result = -ENOMEM;
1669         struct pci_dev *pdev = to_pci_dev(dev->dev);
1670
1671         if (pci_enable_device_mem(pdev))
1672                 return result;
1673
1674         pci_set_master(pdev);
1675
1676         if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
1677             dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
1678                 goto disable;
1679
1680         if (readl(dev->bar + NVME_REG_CSTS) == -1) {
1681                 result = -ENODEV;
1682                 goto disable;
1683         }
1684
1685         /*
1686          * Some devices and/or platforms don't advertise or work with INTx
1687          * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
1688          * adjust this later.
1689          */
1690         if (pci_enable_msix(pdev, dev->entry, 1)) {
1691                 pci_enable_msi(pdev);
1692                 dev->entry[0].vector = pdev->irq;
1693         }
1694
1695         if (!dev->entry[0].vector) {
1696                 result = -ENODEV;
1697                 goto disable;
1698         }
1699
1700         cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1701
1702         dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
1703         dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
1704         dev->dbs = dev->bar + 4096;
1705
1706         /*
1707          * Temporary fix for the Apple controller found in the MacBook8,1 and
1708          * some MacBook7,1 to avoid controller resets and data loss.
1709          */
1710         if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
1711                 dev->q_depth = 2;
1712                 dev_warn(dev->dev, "detected Apple NVMe controller, set "
1713                         "queue depth=%u to work around controller resets\n",
1714                         dev->q_depth);
1715         }
1716
1717         if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2))
1718                 dev->cmb = nvme_map_cmb(dev);
1719
1720         pci_enable_pcie_error_reporting(pdev);
1721         pci_save_state(pdev);
1722         return 0;
1723
1724  disable:
1725         pci_disable_device(pdev);
1726         return result;
1727 }
1728
1729 static void nvme_dev_unmap(struct nvme_dev *dev)
1730 {
1731         if (dev->bar)
1732                 iounmap(dev->bar);
1733         pci_release_regions(to_pci_dev(dev->dev));
1734 }
1735
1736 static void nvme_pci_disable(struct nvme_dev *dev)
1737 {
1738         struct pci_dev *pdev = to_pci_dev(dev->dev);
1739
1740         if (pdev->msi_enabled)
1741                 pci_disable_msi(pdev);
1742         else if (pdev->msix_enabled)
1743                 pci_disable_msix(pdev);
1744
1745         if (pci_is_enabled(pdev)) {
1746                 pci_disable_pcie_error_reporting(pdev);
1747                 pci_disable_device(pdev);
1748         }
1749 }
1750
1751 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
1752 {
1753         int i;
1754         u32 csts = -1;
1755
1756         del_timer_sync(&dev->watchdog_timer);
1757
1758         mutex_lock(&dev->shutdown_lock);
1759         if (pci_is_enabled(to_pci_dev(dev->dev))) {
1760                 nvme_stop_queues(&dev->ctrl);
1761                 csts = readl(dev->bar + NVME_REG_CSTS);
1762         }
1763         if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) {
1764                 for (i = dev->queue_count - 1; i >= 0; i--) {
1765                         struct nvme_queue *nvmeq = dev->queues[i];
1766                         nvme_suspend_queue(nvmeq);
1767                 }
1768         } else {
1769                 nvme_disable_io_queues(dev);
1770                 nvme_disable_admin_queue(dev, shutdown);
1771         }
1772         nvme_pci_disable(dev);
1773
1774         blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_io, dev);
1775         blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_io, dev);
1776         mutex_unlock(&dev->shutdown_lock);
1777 }
1778
1779 static int nvme_setup_prp_pools(struct nvme_dev *dev)
1780 {
1781         dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
1782                                                 PAGE_SIZE, PAGE_SIZE, 0);
1783         if (!dev->prp_page_pool)
1784                 return -ENOMEM;
1785
1786         /* Optimisation for I/Os between 4k and 128k */
1787         dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
1788                                                 256, 256, 0);
1789         if (!dev->prp_small_pool) {
1790                 dma_pool_destroy(dev->prp_page_pool);
1791                 return -ENOMEM;
1792         }
1793         return 0;
1794 }
1795
1796 static void nvme_release_prp_pools(struct nvme_dev *dev)
1797 {
1798         dma_pool_destroy(dev->prp_page_pool);
1799         dma_pool_destroy(dev->prp_small_pool);
1800 }
1801
1802 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
1803 {
1804         struct nvme_dev *dev = to_nvme_dev(ctrl);
1805
1806         put_device(dev->dev);
1807         if (dev->tagset.tags)
1808                 blk_mq_free_tag_set(&dev->tagset);
1809         if (dev->ctrl.admin_q)
1810                 blk_put_queue(dev->ctrl.admin_q);
1811         kfree(dev->queues);
1812         kfree(dev->entry);
1813         kfree(dev);
1814 }
1815
1816 static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
1817 {
1818         dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
1819
1820         kref_get(&dev->ctrl.kref);
1821         nvme_dev_disable(dev, false);
1822         if (!schedule_work(&dev->remove_work))
1823                 nvme_put_ctrl(&dev->ctrl);
1824 }
1825
1826 static void nvme_reset_work(struct work_struct *work)
1827 {
1828         struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
1829         int result = -ENODEV;
1830
1831         if (WARN_ON(dev->ctrl.state == NVME_CTRL_RESETTING))
1832                 goto out;
1833
1834         /*
1835          * If we're called to reset a live controller first shut it down before
1836          * moving on.
1837          */
1838         if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
1839                 nvme_dev_disable(dev, false);
1840
1841         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING))
1842                 goto out;
1843
1844         result = nvme_pci_enable(dev);
1845         if (result)
1846                 goto out;
1847
1848         result = nvme_configure_admin_queue(dev);
1849         if (result)
1850                 goto out;
1851
1852         nvme_init_queue(dev->queues[0], 0);
1853         result = nvme_alloc_admin_tags(dev);
1854         if (result)
1855                 goto out;
1856
1857         result = nvme_init_identify(&dev->ctrl);
1858         if (result)
1859                 goto out;
1860
1861         result = nvme_setup_io_queues(dev);
1862         if (result)
1863                 goto out;
1864
1865         /*
1866          * A controller that can not execute IO typically requires user
1867          * intervention to correct. For such degraded controllers, the driver
1868          * should not submit commands the user did not request, so skip
1869          * registering for asynchronous event notification on this condition.
1870          */
1871         if (dev->online_queues > 1) {
1872                 dev->ctrl.event_limit = NVME_NR_AEN_COMMANDS;
1873                 queue_work(nvme_workq, &dev->async_work);
1874         }
1875
1876         mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ));
1877
1878         /*
1879          * Keep the controller around but remove all namespaces if we don't have
1880          * any working I/O queue.
1881          */
1882         if (dev->online_queues < 2) {
1883                 dev_warn(dev->ctrl.device, "IO queues not created\n");
1884                 nvme_kill_queues(&dev->ctrl);
1885                 nvme_remove_namespaces(&dev->ctrl);
1886         } else {
1887                 nvme_start_queues(&dev->ctrl);
1888                 nvme_dev_add(dev);
1889         }
1890
1891         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
1892                 dev_warn(dev->ctrl.device, "failed to mark controller live\n");
1893                 goto out;
1894         }
1895
1896         if (dev->online_queues > 1)
1897                 nvme_queue_scan(dev);
1898         return;
1899
1900  out:
1901         nvme_remove_dead_ctrl(dev, result);
1902 }
1903
1904 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
1905 {
1906         struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
1907         struct pci_dev *pdev = to_pci_dev(dev->dev);
1908
1909         nvme_kill_queues(&dev->ctrl);
1910         if (pci_get_drvdata(pdev))
1911                 pci_stop_and_remove_bus_device_locked(pdev);
1912         nvme_put_ctrl(&dev->ctrl);
1913 }
1914
1915 static int nvme_reset(struct nvme_dev *dev)
1916 {
1917         if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q))
1918                 return -ENODEV;
1919
1920         if (!queue_work(nvme_workq, &dev->reset_work))
1921                 return -EBUSY;
1922
1923         flush_work(&dev->reset_work);
1924         return 0;
1925 }
1926
1927 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
1928 {
1929         *val = readl(to_nvme_dev(ctrl)->bar + off);
1930         return 0;
1931 }
1932
1933 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
1934 {
1935         writel(val, to_nvme_dev(ctrl)->bar + off);
1936         return 0;
1937 }
1938
1939 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
1940 {
1941         *val = readq(to_nvme_dev(ctrl)->bar + off);
1942         return 0;
1943 }
1944
1945 static int nvme_pci_reset_ctrl(struct nvme_ctrl *ctrl)
1946 {
1947         return nvme_reset(to_nvme_dev(ctrl));
1948 }
1949
1950 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1951         .module                 = THIS_MODULE,
1952         .reg_read32             = nvme_pci_reg_read32,
1953         .reg_write32            = nvme_pci_reg_write32,
1954         .reg_read64             = nvme_pci_reg_read64,
1955         .reset_ctrl             = nvme_pci_reset_ctrl,
1956         .free_ctrl              = nvme_pci_free_ctrl,
1957 };
1958
1959 static int nvme_dev_map(struct nvme_dev *dev)
1960 {
1961         int bars;
1962         struct pci_dev *pdev = to_pci_dev(dev->dev);
1963
1964         bars = pci_select_bars(pdev, IORESOURCE_MEM);
1965         if (!bars)
1966                 return -ENODEV;
1967         if (pci_request_selected_regions(pdev, bars, "nvme"))
1968                 return -ENODEV;
1969
1970         dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1971         if (!dev->bar)
1972                 goto release;
1973
1974        return 0;
1975   release:
1976        pci_release_regions(pdev);
1977        return -ENODEV;
1978 }
1979
1980 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1981 {
1982         int node, result = -ENOMEM;
1983         struct nvme_dev *dev;
1984
1985         node = dev_to_node(&pdev->dev);
1986         if (node == NUMA_NO_NODE)
1987                 set_dev_node(&pdev->dev, 0);
1988
1989         dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
1990         if (!dev)
1991                 return -ENOMEM;
1992         dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry),
1993                                                         GFP_KERNEL, node);
1994         if (!dev->entry)
1995                 goto free;
1996         dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
1997                                                         GFP_KERNEL, node);
1998         if (!dev->queues)
1999                 goto free;
2000
2001         dev->dev = get_device(&pdev->dev);
2002         pci_set_drvdata(pdev, dev);
2003
2004         result = nvme_dev_map(dev);
2005         if (result)
2006                 goto free;
2007
2008         INIT_WORK(&dev->scan_work, nvme_dev_scan);
2009         INIT_WORK(&dev->reset_work, nvme_reset_work);
2010         INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
2011         INIT_WORK(&dev->async_work, nvme_async_event_work);
2012         setup_timer(&dev->watchdog_timer, nvme_watchdog_timer,
2013                 (unsigned long)dev);
2014         mutex_init(&dev->shutdown_lock);
2015         init_completion(&dev->ioq_wait);
2016
2017         result = nvme_setup_prp_pools(dev);
2018         if (result)
2019                 goto put_pci;
2020
2021         result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2022                         id->driver_data);
2023         if (result)
2024                 goto release_pools;
2025
2026         dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2027
2028         queue_work(nvme_workq, &dev->reset_work);
2029         return 0;
2030
2031  release_pools:
2032         nvme_release_prp_pools(dev);
2033  put_pci:
2034         put_device(dev->dev);
2035         nvme_dev_unmap(dev);
2036  free:
2037         kfree(dev->queues);
2038         kfree(dev->entry);
2039         kfree(dev);
2040         return result;
2041 }
2042
2043 static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
2044 {
2045         struct nvme_dev *dev = pci_get_drvdata(pdev);
2046
2047         if (prepare)
2048                 nvme_dev_disable(dev, false);
2049         else
2050                 queue_work(nvme_workq, &dev->reset_work);
2051 }
2052
2053 static void nvme_shutdown(struct pci_dev *pdev)
2054 {
2055         struct nvme_dev *dev = pci_get_drvdata(pdev);
2056         nvme_dev_disable(dev, true);
2057 }
2058
2059 /*
2060  * The driver's remove may be called on a device in a partially initialized
2061  * state. This function must not have any dependencies on the device state in
2062  * order to proceed.
2063  */
2064 static void nvme_remove(struct pci_dev *pdev)
2065 {
2066         struct nvme_dev *dev = pci_get_drvdata(pdev);
2067
2068         del_timer_sync(&dev->watchdog_timer);
2069
2070         nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2071
2072         pci_set_drvdata(pdev, NULL);
2073         flush_work(&dev->async_work);
2074         flush_work(&dev->scan_work);
2075         nvme_remove_namespaces(&dev->ctrl);
2076         nvme_uninit_ctrl(&dev->ctrl);
2077         nvme_dev_disable(dev, true);
2078         flush_work(&dev->reset_work);
2079         nvme_dev_remove_admin(dev);
2080         nvme_free_queues(dev, 0);
2081         nvme_release_cmb(dev);
2082         nvme_release_prp_pools(dev);
2083         nvme_dev_unmap(dev);
2084         nvme_put_ctrl(&dev->ctrl);
2085 }
2086
2087 #ifdef CONFIG_PM_SLEEP
2088 static int nvme_suspend(struct device *dev)
2089 {
2090         struct pci_dev *pdev = to_pci_dev(dev);
2091         struct nvme_dev *ndev = pci_get_drvdata(pdev);
2092
2093         nvme_dev_disable(ndev, true);
2094         return 0;
2095 }
2096
2097 static int nvme_resume(struct device *dev)
2098 {
2099         struct pci_dev *pdev = to_pci_dev(dev);
2100         struct nvme_dev *ndev = pci_get_drvdata(pdev);
2101
2102         queue_work(nvme_workq, &ndev->reset_work);
2103         return 0;
2104 }
2105 #endif
2106
2107 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
2108
2109 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2110                                                 pci_channel_state_t state)
2111 {
2112         struct nvme_dev *dev = pci_get_drvdata(pdev);
2113
2114         /*
2115          * A frozen channel requires a reset. When detected, this method will
2116          * shutdown the controller to quiesce. The controller will be restarted
2117          * after the slot reset through driver's slot_reset callback.
2118          */
2119         dev_warn(dev->ctrl.device, "error detected: state:%d\n", state);
2120         switch (state) {
2121         case pci_channel_io_normal:
2122                 return PCI_ERS_RESULT_CAN_RECOVER;
2123         case pci_channel_io_frozen:
2124                 nvme_dev_disable(dev, false);
2125                 return PCI_ERS_RESULT_NEED_RESET;
2126         case pci_channel_io_perm_failure:
2127                 return PCI_ERS_RESULT_DISCONNECT;
2128         }
2129         return PCI_ERS_RESULT_NEED_RESET;
2130 }
2131
2132 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2133 {
2134         struct nvme_dev *dev = pci_get_drvdata(pdev);
2135
2136         dev_info(dev->ctrl.device, "restart after slot reset\n");
2137         pci_restore_state(pdev);
2138         queue_work(nvme_workq, &dev->reset_work);
2139         return PCI_ERS_RESULT_RECOVERED;
2140 }
2141
2142 static void nvme_error_resume(struct pci_dev *pdev)
2143 {
2144         pci_cleanup_aer_uncorrect_error_status(pdev);
2145 }
2146
2147 static const struct pci_error_handlers nvme_err_handler = {
2148         .error_detected = nvme_error_detected,
2149         .slot_reset     = nvme_slot_reset,
2150         .resume         = nvme_error_resume,
2151         .reset_notify   = nvme_reset_notify,
2152 };
2153
2154 /* Move to pci_ids.h later */
2155 #define PCI_CLASS_STORAGE_EXPRESS       0x010802
2156
2157 static const struct pci_device_id nvme_id_table[] = {
2158         { PCI_VDEVICE(INTEL, 0x0953),
2159                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2160                                 NVME_QUIRK_DISCARD_ZEROES, },
2161         { PCI_VDEVICE(INTEL, 0x5845),   /* Qemu emulated controller */
2162                 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
2163         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2164         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
2165         { 0, }
2166 };
2167 MODULE_DEVICE_TABLE(pci, nvme_id_table);
2168
2169 static struct pci_driver nvme_driver = {
2170         .name           = "nvme",
2171         .id_table       = nvme_id_table,
2172         .probe          = nvme_probe,
2173         .remove         = nvme_remove,
2174         .shutdown       = nvme_shutdown,
2175         .driver         = {
2176                 .pm     = &nvme_dev_pm_ops,
2177         },
2178         .err_handler    = &nvme_err_handler,
2179 };
2180
2181 static int __init nvme_init(void)
2182 {
2183         int result;
2184
2185         nvme_workq = alloc_workqueue("nvme", WQ_UNBOUND | WQ_MEM_RECLAIM, 0);
2186         if (!nvme_workq)
2187                 return -ENOMEM;
2188
2189         result = pci_register_driver(&nvme_driver);
2190         if (result)
2191                 destroy_workqueue(nvme_workq);
2192         return result;
2193 }
2194
2195 static void __exit nvme_exit(void)
2196 {
2197         pci_unregister_driver(&nvme_driver);
2198         destroy_workqueue(nvme_workq);
2199         _nvme_check_size();
2200 }
2201
2202 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2203 MODULE_LICENSE("GPL");
2204 MODULE_VERSION("1.0");
2205 module_init(nvme_init);
2206 module_exit(nvme_exit);