drivers/nvme/host/pci.c

   1 /*
   2  * NVM Express device driver
   3  * Copyright (c) 2011-2014, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  */
  14
  15 #include <linux/aer.h>
  16 #include <linux/bitops.h>
  17 #include <linux/blkdev.h>
  18 #include <linux/blk-mq.h>
  19 #include <linux/cpu.h>
  20 #include <linux/delay.h>
  21 #include <linux/errno.h>
  22 #include <linux/fs.h>
  23 #include <linux/genhd.h>
  24 #include <linux/hdreg.h>
  25 #include <linux/idr.h>
  26 #include <linux/init.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/io.h>
  29 #include <linux/kdev_t.h>
  30 #include <linux/kernel.h>
  31 #include <linux/mm.h>
  32 #include <linux/module.h>
  33 #include <linux/moduleparam.h>
  34 #include <linux/mutex.h>
  35 #include <linux/pci.h>
  36 #include <linux/poison.h>
  37 #include <linux/ptrace.h>
  38 #include <linux/sched.h>
  39 #include <linux/slab.h>
  40 #include <linux/t10-pi.h>
  41 #include <linux/timer.h>
  42 #include <linux/types.h>
  43 #include <linux/io-64-nonatomic-lo-hi.h>
  44 #include <asm/unaligned.h>
  45
  46 #include "nvme.h"
  47
  48 #define NVME_Q_DEPTH            1024
  49 #define NVME_AQ_DEPTH           256
  50 #define SQ_SIZE(depth)          (depth * sizeof(struct nvme_command))
  51 #define CQ_SIZE(depth)          (depth * sizeof(struct nvme_completion))
  52
  53 /*
  54  * We handle AEN commands ourselves and don't even let the
  55  * block layer know about them.
  56  */
  57 #define NVME_NR_AEN_COMMANDS    1
  58 #define NVME_AQ_BLKMQ_DEPTH     (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
  59
  60 static int use_threaded_interrupts;
  61 module_param(use_threaded_interrupts, int, 0);
  62
  63 static bool use_cmb_sqes = true;
  64 module_param(use_cmb_sqes, bool, 0644);
  65 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
  66
  67 static struct workqueue_struct *nvme_workq;
  68
  69 struct nvme_dev;
  70 struct nvme_queue;
  71
  72 static int nvme_reset(struct nvme_dev *dev);
  73 static void nvme_process_cq(struct nvme_queue *nvmeq);
  74 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
  75
  76 /*
  77  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
  78  */
  79 struct nvme_dev {
  80         struct nvme_queue **queues;
  81         struct blk_mq_tag_set tagset;
  82         struct blk_mq_tag_set admin_tagset;
  83         u32 __iomem *dbs;
  84         struct device *dev;
  85         struct dma_pool *prp_page_pool;
  86         struct dma_pool *prp_small_pool;
  87         unsigned queue_count;
  88         unsigned online_queues;
  89         unsigned max_qid;
  90         int q_depth;
  91         u32 db_stride;
  92         struct msix_entry *entry;
  93         void __iomem *bar;
  94         struct work_struct reset_work;
  95         struct work_struct remove_work;
  96         struct work_struct async_work;
  97         struct timer_list watchdog_timer;
  98         struct mutex shutdown_lock;
  99         bool subsystem;
 100         void __iomem *cmb;
 101         dma_addr_t cmb_dma_addr;
 102         u64 cmb_size;
 103         u32 cmbsz;
 104         struct nvme_ctrl ctrl;
 105         struct completion ioq_wait;
 106 };
 107
 108 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
 109 {
 110         return container_of(ctrl, struct nvme_dev, ctrl);
 111 }
 112
 113 /*
 114  * An NVM Express queue.  Each device has at least two (one for admin
 115  * commands and one for I/O commands).
 116  */
 117 struct nvme_queue {
 118         struct device *q_dmadev;
 119         struct nvme_dev *dev;
 120         char irqname[24];       /* nvme4294967295-65535\0 */
 121         spinlock_t q_lock;
 122         struct nvme_command *sq_cmds;
 123         struct nvme_command __iomem *sq_cmds_io;
 124         volatile struct nvme_completion *cqes;
 125         struct blk_mq_tags **tags;
 126         dma_addr_t sq_dma_addr;
 127         dma_addr_t cq_dma_addr;
 128         u32 __iomem *q_db;
 129         u16 q_depth;
 130         s16 cq_vector;
 131         u16 sq_tail;
 132         u16 cq_head;
 133         u16 qid;
 134         u8 cq_phase;
 135         u8 cqe_seen;
 136 };
 137
 138 /*
 139  * The nvme_iod describes the data in an I/O, including the list of PRP
 140  * entries.  You can't see it in this data structure because C doesn't let
 141  * me express that.  Use nvme_init_iod to ensure there's enough space
 142  * allocated to store the PRP list.
 143  */
 144 struct nvme_iod {
 145         struct nvme_queue *nvmeq;
 146         int aborted;
 147         int npages;             /* In the PRP list. 0 means small pool in use */
 148         int nents;              /* Used in scatterlist */
 149         int length;             /* Of data, in bytes */
 150         dma_addr_t first_dma;
 151         struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
 152         struct scatterlist *sg;
 153         struct scatterlist inline_sg[0];
 154 };
 155
 156 /*
 157  * Check we didin't inadvertently grow the command struct
 158  */
 159 static inline void _nvme_check_size(void)
 160 {
 161         BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
 162         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
 163         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
 164         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
 165         BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
 166         BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
 167         BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
 168         BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
 169         BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
 170         BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
 171         BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
 172         BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
 173 }
 174
 175 /*
 176  * Max size of iod being embedded in the request payload
 177  */
 178 #define NVME_INT_PAGES          2
 179 #define NVME_INT_BYTES(dev)     (NVME_INT_PAGES * (dev)->ctrl.page_size)
 180
 181 /*
 182  * Will slightly overestimate the number of pages needed.  This is OK
 183  * as it only leads to a small amount of wasted memory for the lifetime of
 184  * the I/O.
 185  */
 186 static int nvme_npages(unsigned size, struct nvme_dev *dev)
 187 {
 188         unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
 189                                       dev->ctrl.page_size);
 190         return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
 191 }
 192
 193 static unsigned int nvme_iod_alloc_size(struct nvme_dev *dev,
 194                 unsigned int size, unsigned int nseg)
 195 {
 196         return sizeof(__le64 *) * nvme_npages(size, dev) +
 197                         sizeof(struct scatterlist) * nseg;
 198 }
 199
 200 static unsigned int nvme_cmd_size(struct nvme_dev *dev)
 201 {
 202         return sizeof(struct nvme_iod) +
 203                 nvme_iod_alloc_size(dev, NVME_INT_BYTES(dev), NVME_INT_PAGES);
 204 }
 205
 206 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 207                                 unsigned int hctx_idx)
 208 {
 209         struct nvme_dev *dev = data;
 210         struct nvme_queue *nvmeq = dev->queues[0];
 211
 212         WARN_ON(hctx_idx != 0);
 213         WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
 214         WARN_ON(nvmeq->tags);
 215
 216         hctx->driver_data = nvmeq;
 217         nvmeq->tags = &dev->admin_tagset.tags[0];
 218         return 0;
 219 }
 220
 221 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
 222 {
 223         struct nvme_queue *nvmeq = hctx->driver_data;
 224
 225         nvmeq->tags = NULL;
 226 }
 227
 228 static int nvme_admin_init_request(void *data, struct request *req,
 229                                 unsigned int hctx_idx, unsigned int rq_idx,
 230                                 unsigned int numa_node)
 231 {
 232         struct nvme_dev *dev = data;
 233         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 234         struct nvme_queue *nvmeq = dev->queues[0];
 235
 236         BUG_ON(!nvmeq);
 237         iod->nvmeq = nvmeq;
 238         return 0;
 239 }
 240
 241 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 242                           unsigned int hctx_idx)
 243 {
 244         struct nvme_dev *dev = data;
 245         struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
 246
 247         if (!nvmeq->tags)
 248                 nvmeq->tags = &dev->tagset.tags[hctx_idx];
 249
 250         WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
 251         hctx->driver_data = nvmeq;
 252         return 0;
 253 }
 254
 255 static int nvme_init_request(void *data, struct request *req,
 256                                 unsigned int hctx_idx, unsigned int rq_idx,
 257                                 unsigned int numa_node)
 258 {
 259         struct nvme_dev *dev = data;
 260         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 261         struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
 262
 263         BUG_ON(!nvmeq);
 264         iod->nvmeq = nvmeq;
 265         return 0;
 266 }
 267
 268 static void nvme_complete_async_event(struct nvme_dev *dev,
 269                 struct nvme_completion *cqe)
 270 {
 271         u16 status = le16_to_cpu(cqe->status) >> 1;
 272         u32 result = le32_to_cpu(cqe->result);
 273
 274         if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ) {
 275                 ++dev->ctrl.event_limit;
 276                 queue_work(nvme_workq, &dev->async_work);
 277         }
 278
 279         if (status != NVME_SC_SUCCESS)
 280                 return;
 281
 282         switch (result & 0xff07) {
 283         case NVME_AER_NOTICE_NS_CHANGED:
 284                 dev_info(dev->ctrl.device, "rescanning\n");
 285                 nvme_queue_scan(&dev->ctrl);
 286         default:
 287                 dev_warn(dev->ctrl.device, "async event result %08x\n", result);
 288         }
 289 }
 290
 291 /**
 292  * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
 293  * @nvmeq: The queue to use
 294  * @cmd: The command to send
 295  *
 296  * Safe to use from interrupt context
 297  */
 298 static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
 299                                                 struct nvme_command *cmd)
 300 {
 301         u16 tail = nvmeq->sq_tail;
 302
 303         if (nvmeq->sq_cmds_io)
 304                 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
 305         else
 306                 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
 307
 308         if (++tail == nvmeq->q_depth)
 309                 tail = 0;
 310         writel(tail, nvmeq->q_db);
 311         nvmeq->sq_tail = tail;
 312 }
 313
 314 static __le64 **iod_list(struct request *req)
 315 {
 316         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 317         return (__le64 **)(iod->sg + req->nr_phys_segments);
 318 }
 319
 320 static int nvme_init_iod(struct request *rq, unsigned size,
 321                 struct nvme_dev *dev)
 322 {
 323         struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
 324         int nseg = rq->nr_phys_segments;
 325
 326         if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
 327                 iod->sg = kmalloc(nvme_iod_alloc_size(dev, size, nseg), GFP_ATOMIC);
 328                 if (!iod->sg)
 329                         return BLK_MQ_RQ_QUEUE_BUSY;
 330         } else {
 331                 iod->sg = iod->inline_sg;
 332         }
 333
 334         iod->aborted = 0;
 335         iod->npages = -1;
 336         iod->nents = 0;
 337         iod->length = size;
 338         return 0;
 339 }
 340
 341 static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
 342 {
 343         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 344         const int last_prp = dev->ctrl.page_size / 8 - 1;
 345         int i;
 346         __le64 **list = iod_list(req);
 347         dma_addr_t prp_dma = iod->first_dma;
 348
 349         if (req->cmd_flags & REQ_DISCARD)
 350                 kfree(req->completion_data);
 351
 352         if (iod->npages == 0)
 353                 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
 354         for (i = 0; i < iod->npages; i++) {
 355                 __le64 *prp_list = list[i];
 356                 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
 357                 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
 358                 prp_dma = next_prp_dma;
 359         }
 360
 361         if (iod->sg != iod->inline_sg)
 362                 kfree(iod->sg);
 363 }
 364
 365 #ifdef CONFIG_BLK_DEV_INTEGRITY
 366 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
 367 {
 368         if (be32_to_cpu(pi->ref_tag) == v)
 369                 pi->ref_tag = cpu_to_be32(p);
 370 }
 371
 372 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
 373 {
 374         if (be32_to_cpu(pi->ref_tag) == p)
 375                 pi->ref_tag = cpu_to_be32(v);
 376 }
 377
 378 /**
 379  * nvme_dif_remap - remaps ref tags to bip seed and physical lba
 380  *
 381  * The virtual start sector is the one that was originally submitted by the
 382  * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
 383  * start sector may be different. Remap protection information to match the
 384  * physical LBA on writes, and back to the original seed on reads.
 385  *
 386  * Type 0 and 3 do not have a ref tag, so no remapping required.
 387  */
 388 static void nvme_dif_remap(struct request *req,
 389                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
 390 {
 391         struct nvme_ns *ns = req->rq_disk->private_data;
 392         struct bio_integrity_payload *bip;
 393         struct t10_pi_tuple *pi;
 394         void *p, *pmap;
 395         u32 i, nlb, ts, phys, virt;
 396
 397         if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
 398                 return;
 399
 400         bip = bio_integrity(req->bio);
 401         if (!bip)
 402                 return;
 403
 404         pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
 405
 406         p = pmap;
 407         virt = bip_get_seed(bip);
 408         phys = nvme_block_nr(ns, blk_rq_pos(req));
 409         nlb = (blk_rq_bytes(req) >> ns->lba_shift);
 410         ts = ns->disk->queue->integrity.tuple_size;
 411
 412         for (i = 0; i < nlb; i++, virt++, phys++) {
 413                 pi = (struct t10_pi_tuple *)p;
 414                 dif_swap(phys, virt, pi);
 415                 p += ts;
 416         }
 417         kunmap_atomic(pmap);
 418 }
 419 #else /* CONFIG_BLK_DEV_INTEGRITY */
 420 static void nvme_dif_remap(struct request *req,
 421                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
 422 {
 423 }
 424 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
 425 {
 426 }
 427 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
 428 {
 429 }
 430 #endif
 431
 432 static bool nvme_setup_prps(struct nvme_dev *dev, struct request *req,
 433                 int total_len)
 434 {
 435         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 436         struct dma_pool *pool;
 437         int length = total_len;
 438         struct scatterlist *sg = iod->sg;
 439         int dma_len = sg_dma_len(sg);
 440         u64 dma_addr = sg_dma_address(sg);
 441         u32 page_size = dev->ctrl.page_size;
 442         int offset = dma_addr & (page_size - 1);
 443         __le64 *prp_list;
 444         __le64 **list = iod_list(req);
 445         dma_addr_t prp_dma;
 446         int nprps, i;
 447
 448         length -= (page_size - offset);
 449         if (length <= 0)
 450                 return true;
 451
 452         dma_len -= (page_size - offset);
 453         if (dma_len) {
 454                 dma_addr += (page_size - offset);
 455         } else {
 456                 sg = sg_next(sg);
 457                 dma_addr = sg_dma_address(sg);
 458                 dma_len = sg_dma_len(sg);
 459         }
 460
 461         if (length <= page_size) {
 462                 iod->first_dma = dma_addr;
 463                 return true;
 464         }
 465
 466         nprps = DIV_ROUND_UP(length, page_size);
 467         if (nprps <= (256 / 8)) {
 468                 pool = dev->prp_small_pool;
 469                 iod->npages = 0;
 470         } else {
 471                 pool = dev->prp_page_pool;
 472                 iod->npages = 1;
 473         }
 474
 475         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 476         if (!prp_list) {
 477                 iod->first_dma = dma_addr;
 478                 iod->npages = -1;
 479                 return false;
 480         }
 481         list[0] = prp_list;
 482         iod->first_dma = prp_dma;
 483         i = 0;
 484         for (;;) {
 485                 if (i == page_size >> 3) {
 486                         __le64 *old_prp_list = prp_list;
 487                         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 488                         if (!prp_list)
 489                                 return false;
 490                         list[iod->npages++] = prp_list;
 491                         prp_list[0] = old_prp_list[i - 1];
 492                         old_prp_list[i - 1] = cpu_to_le64(prp_dma);
 493                         i = 1;
 494                 }
 495                 prp_list[i++] = cpu_to_le64(dma_addr);
 496                 dma_len -= page_size;
 497                 dma_addr += page_size;
 498                 length -= page_size;
 499                 if (length <= 0)
 500                         break;
 501                 if (dma_len > 0)
 502                         continue;
 503                 BUG_ON(dma_len < 0);
 504                 sg = sg_next(sg);
 505                 dma_addr = sg_dma_address(sg);
 506                 dma_len = sg_dma_len(sg);
 507         }
 508
 509         return true;
 510 }
 511
 512 static int nvme_map_data(struct nvme_dev *dev, struct request *req,
 513                 unsigned size, struct nvme_command *cmnd)
 514 {
 515         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 516         struct request_queue *q = req->q;
 517         enum dma_data_direction dma_dir = rq_data_dir(req) ?
 518                         DMA_TO_DEVICE : DMA_FROM_DEVICE;
 519         int ret = BLK_MQ_RQ_QUEUE_ERROR;
 520
 521         sg_init_table(iod->sg, req->nr_phys_segments);
 522         iod->nents = blk_rq_map_sg(q, req, iod->sg);
 523         if (!iod->nents)
 524                 goto out;
 525
 526         ret = BLK_MQ_RQ_QUEUE_BUSY;
 527         if (!dma_map_sg(dev->dev, iod->sg, iod->nents, dma_dir))
 528                 goto out;
 529
 530         if (!nvme_setup_prps(dev, req, size))
 531                 goto out_unmap;
 532
 533         ret = BLK_MQ_RQ_QUEUE_ERROR;
 534         if (blk_integrity_rq(req)) {
 535                 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
 536                         goto out_unmap;
 537
 538                 sg_init_table(&iod->meta_sg, 1);
 539                 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
 540                         goto out_unmap;
 541
 542                 if (rq_data_dir(req))
 543                         nvme_dif_remap(req, nvme_dif_prep);
 544
 545                 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
 546                         goto out_unmap;
 547         }
 548
 549         cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
 550         cmnd->rw.prp2 = cpu_to_le64(iod->first_dma);
 551         if (blk_integrity_rq(req))
 552                 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
 553         return BLK_MQ_RQ_QUEUE_OK;
 554
 555 out_unmap:
 556         dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
 557 out:
 558         return ret;
 559 }
 560
 561 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
 562 {
 563         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 564         enum dma_data_direction dma_dir = rq_data_dir(req) ?
 565                         DMA_TO_DEVICE : DMA_FROM_DEVICE;
 566
 567         if (iod->nents) {
 568                 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
 569                 if (blk_integrity_rq(req)) {
 570                         if (!rq_data_dir(req))
 571                                 nvme_dif_remap(req, nvme_dif_complete);
 572                         dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
 573                 }
 574         }
 575
 576         nvme_free_iod(dev, req);
 577 }
 578
 579 /*
 580  * NOTE: ns is NULL when called on the admin queue.
 581  */
 582 static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
 583                          const struct blk_mq_queue_data *bd)
 584 {
 585         struct nvme_ns *ns = hctx->queue->queuedata;
 586         struct nvme_queue *nvmeq = hctx->driver_data;
 587         struct nvme_dev *dev = nvmeq->dev;
 588         struct request *req = bd->rq;
 589         struct nvme_command cmnd;
 590         unsigned map_len;
 591         int ret = BLK_MQ_RQ_QUEUE_OK;
 592
 593         /*
 594          * If formated with metadata, require the block layer provide a buffer
 595          * unless this namespace is formated such that the metadata can be
 596          * stripped/generated by the controller with PRACT=1.
 597          */
 598         if (ns && ns->ms && !blk_integrity_rq(req)) {
 599                 if (!(ns->pi_type && ns->ms == 8) &&
 600                                         req->cmd_type != REQ_TYPE_DRV_PRIV) {
 601                         blk_mq_end_request(req, -EFAULT);
 602                         return BLK_MQ_RQ_QUEUE_OK;
 603                 }
 604         }
 605
 606         map_len = nvme_map_len(req);
 607         ret = nvme_init_iod(req, map_len, dev);
 608         if (ret)
 609                 return ret;
 610
 611         ret = nvme_setup_cmd(ns, req, &cmnd);
 612         if (ret)
 613                 goto out;
 614
 615         if (req->nr_phys_segments)
 616                 ret = nvme_map_data(dev, req, map_len, &cmnd);
 617
 618         if (ret)
 619                 goto out;
 620
 621         cmnd.common.command_id = req->tag;
 622         blk_mq_start_request(req);
 623
 624         spin_lock_irq(&nvmeq->q_lock);
 625         if (unlikely(nvmeq->cq_vector < 0)) {
 626                 if (ns && !test_bit(NVME_NS_DEAD, &ns->flags))
 627                         ret = BLK_MQ_RQ_QUEUE_BUSY;
 628                 else
 629                         ret = BLK_MQ_RQ_QUEUE_ERROR;
 630                 spin_unlock_irq(&nvmeq->q_lock);
 631                 goto out;
 632         }
 633         __nvme_submit_cmd(nvmeq, &cmnd);
 634         nvme_process_cq(nvmeq);
 635         spin_unlock_irq(&nvmeq->q_lock);
 636         return BLK_MQ_RQ_QUEUE_OK;
 637 out:
 638         nvme_free_iod(dev, req);
 639         return ret;
 640 }
 641
 642 static void nvme_complete_rq(struct request *req)
 643 {
 644         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 645         struct nvme_dev *dev = iod->nvmeq->dev;
 646         int error = 0;
 647
 648         nvme_unmap_data(dev, req);
 649
 650         if (unlikely(req->errors)) {
 651                 if (nvme_req_needs_retry(req, req->errors)) {
 652                         nvme_requeue_req(req);
 653                         return;
 654                 }
 655
 656                 if (req->cmd_type == REQ_TYPE_DRV_PRIV)
 657                         error = req->errors;
 658                 else
 659                         error = nvme_error_status(req->errors);
 660         }
 661
 662         if (unlikely(iod->aborted)) {
 663                 dev_warn(dev->ctrl.device,
 664                         "completing aborted command with status: %04x\n",
 665                         req->errors);
 666         }
 667
 668         blk_mq_end_request(req, error);
 669 }
 670
 671 /* We read the CQE phase first to check if the rest of the entry is valid */
 672 static inline bool nvme_cqe_valid(struct nvme_queue *nvmeq, u16 head,
 673                 u16 phase)
 674 {
 675         return (le16_to_cpu(nvmeq->cqes[head].status) & 1) == phase;
 676 }
 677
 678 static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag)
 679 {
 680         u16 head, phase;
 681
 682         head = nvmeq->cq_head;
 683         phase = nvmeq->cq_phase;
 684
 685         while (nvme_cqe_valid(nvmeq, head, phase)) {
 686                 struct nvme_completion cqe = nvmeq->cqes[head];
 687                 struct request *req;
 688
 689                 if (++head == nvmeq->q_depth) {
 690                         head = 0;
 691                         phase = !phase;
 692                 }
 693
 694                 if (tag && *tag == cqe.command_id)
 695                         *tag = -1;
 696
 697                 if (unlikely(cqe.command_id >= nvmeq->q_depth)) {
 698                         dev_warn(nvmeq->dev->ctrl.device,
 699                                 "invalid id %d completed on queue %d\n",
 700                                 cqe.command_id, le16_to_cpu(cqe.sq_id));
 701                         continue;
 702                 }
 703
 704                 /*
 705                  * AEN requests are special as they don't time out and can
 706                  * survive any kind of queue freeze and often don't respond to
 707                  * aborts.  We don't even bother to allocate a struct request
 708                  * for them but rather special case them here.
 709                  */
 710                 if (unlikely(nvmeq->qid == 0 &&
 711                                 cqe.command_id >= NVME_AQ_BLKMQ_DEPTH)) {
 712                         nvme_complete_async_event(nvmeq->dev, &cqe);
 713                         continue;
 714                 }
 715
 716                 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe.command_id);
 717                 if (req->cmd_type == REQ_TYPE_DRV_PRIV && req->special)
 718                         memcpy(req->special, &cqe, sizeof(cqe));
 719                 blk_mq_complete_request(req, le16_to_cpu(cqe.status) >> 1);
 720
 721         }
 722
 723         /* If the controller ignores the cq head doorbell and continuously
 724          * writes to the queue, it is theoretically possible to wrap around
 725          * the queue twice and mistakenly return IRQ_NONE.  Linux only
 726          * requires that 0.1% of your interrupts are handled, so this isn't
 727          * a big problem.
 728          */
 729         if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
 730                 return;
 731
 732         if (likely(nvmeq->cq_vector >= 0))
 733                 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
 734         nvmeq->cq_head = head;
 735         nvmeq->cq_phase = phase;
 736
 737         nvmeq->cqe_seen = 1;
 738 }
 739
 740 static void nvme_process_cq(struct nvme_queue *nvmeq)
 741 {
 742         __nvme_process_cq(nvmeq, NULL);
 743 }
 744
 745 static irqreturn_t nvme_irq(int irq, void *data)
 746 {
 747         irqreturn_t result;
 748         struct nvme_queue *nvmeq = data;
 749         spin_lock(&nvmeq->q_lock);
 750         nvme_process_cq(nvmeq);
 751         result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
 752         nvmeq->cqe_seen = 0;
 753         spin_unlock(&nvmeq->q_lock);
 754         return result;
 755 }
 756
 757 static irqreturn_t nvme_irq_check(int irq, void *data)
 758 {
 759         struct nvme_queue *nvmeq = data;
 760         if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase))
 761                 return IRQ_WAKE_THREAD;
 762         return IRQ_NONE;
 763 }
 764
 765 static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
 766 {
 767         struct nvme_queue *nvmeq = hctx->driver_data;
 768
 769         if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) {
 770                 spin_lock_irq(&nvmeq->q_lock);
 771                 __nvme_process_cq(nvmeq, &tag);
 772                 spin_unlock_irq(&nvmeq->q_lock);
 773
 774                 if (tag == -1)
 775                         return 1;
 776         }
 777
 778         return 0;
 779 }
 780
 781 static void nvme_async_event_work(struct work_struct *work)
 782 {
 783         struct nvme_dev *dev = container_of(work, struct nvme_dev, async_work);
 784         struct nvme_queue *nvmeq = dev->queues[0];
 785         struct nvme_command c;
 786
 787         memset(&c, 0, sizeof(c));
 788         c.common.opcode = nvme_admin_async_event;
 789
 790         spin_lock_irq(&nvmeq->q_lock);
 791         while (dev->ctrl.event_limit > 0) {
 792                 c.common.command_id = NVME_AQ_BLKMQ_DEPTH +
 793                         --dev->ctrl.event_limit;
 794                 __nvme_submit_cmd(nvmeq, &c);
 795         }
 796         spin_unlock_irq(&nvmeq->q_lock);
 797 }
 798
 799 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
 800 {
 801         struct nvme_command c;
 802
 803         memset(&c, 0, sizeof(c));
 804         c.delete_queue.opcode = opcode;
 805         c.delete_queue.qid = cpu_to_le16(id);
 806
 807         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 808 }
 809
 810 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
 811                                                 struct nvme_queue *nvmeq)
 812 {
 813         struct nvme_command c;
 814         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
 815
 816         /*
 817          * Note: we (ab)use the fact the the prp fields survive if no data
 818          * is attached to the request.
 819          */
 820         memset(&c, 0, sizeof(c));
 821         c.create_cq.opcode = nvme_admin_create_cq;
 822         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
 823         c.create_cq.cqid = cpu_to_le16(qid);
 824         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 825         c.create_cq.cq_flags = cpu_to_le16(flags);
 826         c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
 827
 828         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 829 }
 830
 831 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
 832                                                 struct nvme_queue *nvmeq)
 833 {
 834         struct nvme_command c;
 835         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
 836
 837         /*
 838          * Note: we (ab)use the fact the the prp fields survive if no data
 839          * is attached to the request.
 840          */
 841         memset(&c, 0, sizeof(c));
 842         c.create_sq.opcode = nvme_admin_create_sq;
 843         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
 844         c.create_sq.sqid = cpu_to_le16(qid);
 845         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 846         c.create_sq.sq_flags = cpu_to_le16(flags);
 847         c.create_sq.cqid = cpu_to_le16(qid);
 848
 849         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 850 }
 851
 852 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
 853 {
 854         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
 855 }
 856
 857 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
 858 {
 859         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
 860 }
 861
 862 static void abort_endio(struct request *req, int error)
 863 {
 864         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 865         struct nvme_queue *nvmeq = iod->nvmeq;
 866         u16 status = req->errors;
 867
 868         dev_warn(nvmeq->dev->ctrl.device, "Abort status: 0x%x", status);
 869         atomic_inc(&nvmeq->dev->ctrl.abort_limit);
 870         blk_mq_free_request(req);
 871 }
 872
 873 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
 874 {
 875         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 876         struct nvme_queue *nvmeq = iod->nvmeq;
 877         struct nvme_dev *dev = nvmeq->dev;
 878         struct request *abort_req;
 879         struct nvme_command cmd;
 880
 881         /*
 882          * Shutdown immediately if controller times out while starting. The
 883          * reset work will see the pci device disabled when it gets the forced
 884          * cancellation error. All outstanding requests are completed on
 885          * shutdown, so we return BLK_EH_HANDLED.
 886          */
 887         if (dev->ctrl.state == NVME_CTRL_RESETTING) {
 888                 dev_warn(dev->ctrl.device,
 889                          "I/O %d QID %d timeout, disable controller\n",
 890                          req->tag, nvmeq->qid);
 891                 nvme_dev_disable(dev, false);
 892                 req->errors = NVME_SC_CANCELLED;
 893                 return BLK_EH_HANDLED;
 894         }
 895
 896         /*
 897          * Shutdown the controller immediately and schedule a reset if the
 898          * command was already aborted once before and still hasn't been
 899          * returned to the driver, or if this is the admin queue.
 900          */
 901         if (!nvmeq->qid || iod->aborted) {
 902                 dev_warn(dev->ctrl.device,
 903                          "I/O %d QID %d timeout, reset controller\n",
 904                          req->tag, nvmeq->qid);
 905                 nvme_dev_disable(dev, false);
 906                 queue_work(nvme_workq, &dev->reset_work);
 907
 908                 /*
 909                  * Mark the request as handled, since the inline shutdown
 910                  * forces all outstanding requests to complete.
 911                  */
 912                 req->errors = NVME_SC_CANCELLED;
 913                 return BLK_EH_HANDLED;
 914         }
 915
 916         iod->aborted = 1;
 917
 918         if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
 919                 atomic_inc(&dev->ctrl.abort_limit);
 920                 return BLK_EH_RESET_TIMER;
 921         }
 922
 923         memset(&cmd, 0, sizeof(cmd));
 924         cmd.abort.opcode = nvme_admin_abort_cmd;
 925         cmd.abort.cid = req->tag;
 926         cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
 927
 928         dev_warn(nvmeq->dev->ctrl.device,
 929                 "I/O %d QID %d timeout, aborting\n",
 930                  req->tag, nvmeq->qid);
 931
 932         abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
 933                         BLK_MQ_REQ_NOWAIT);
 934         if (IS_ERR(abort_req)) {
 935                 atomic_inc(&dev->ctrl.abort_limit);
 936                 return BLK_EH_RESET_TIMER;
 937         }
 938
 939         abort_req->timeout = ADMIN_TIMEOUT;
 940         abort_req->end_io_data = NULL;
 941         blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
 942
 943         /*
 944          * The aborted req will be completed on receiving the abort req.
 945          * We enable the timer again. If hit twice, it'll cause a device reset,
 946          * as the device then is in a faulty state.
 947          */
 948         return BLK_EH_RESET_TIMER;
 949 }
 950
 951 static void nvme_cancel_io(struct request *req, void *data, bool reserved)
 952 {
 953         int status;
 954
 955         if (!blk_mq_request_started(req))
 956                 return;
 957
 958         dev_dbg_ratelimited(((struct nvme_dev *) data)->ctrl.device,
 959                                 "Cancelling I/O %d", req->tag);
 960
 961         status = NVME_SC_ABORT_REQ;
 962         if (blk_queue_dying(req->q))
 963                 status |= NVME_SC_DNR;
 964         blk_mq_complete_request(req, status);
 965 }
 966
 967 static void nvme_free_queue(struct nvme_queue *nvmeq)
 968 {
 969         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
 970                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
 971         if (nvmeq->sq_cmds)
 972                 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
 973                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
 974         kfree(nvmeq);
 975 }
 976
 977 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
 978 {
 979         int i;
 980
 981         for (i = dev->queue_count - 1; i >= lowest; i--) {
 982                 struct nvme_queue *nvmeq = dev->queues[i];
 983                 dev->queue_count--;
 984                 dev->queues[i] = NULL;
 985                 nvme_free_queue(nvmeq);
 986         }
 987 }
 988
 989 /**
 990  * nvme_suspend_queue - put queue into suspended state
 991  * @nvmeq - queue to suspend
 992  */
 993 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
 994 {
 995         int vector;
 996
 997         spin_lock_irq(&nvmeq->q_lock);
 998         if (nvmeq->cq_vector == -1) {
 999                 spin_unlock_irq(&nvmeq->q_lock);
1000                 return 1;
1001         }
1002         vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
1003         nvmeq->dev->online_queues--;
1004         nvmeq->cq_vector = -1;
1005         spin_unlock_irq(&nvmeq->q_lock);
1006
1007         if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1008                 blk_mq_stop_hw_queues(nvmeq->dev->ctrl.admin_q);
1009
1010         irq_set_affinity_hint(vector, NULL);
1011         free_irq(vector, nvmeq);
1012
1013         return 0;
1014 }
1015
1016 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
1017 {
1018         struct nvme_queue *nvmeq = dev->queues[0];
1019
1020         if (!nvmeq)
1021                 return;
1022         if (nvme_suspend_queue(nvmeq))
1023                 return;
1024
1025         if (shutdown)
1026                 nvme_shutdown_ctrl(&dev->ctrl);
1027         else
1028                 nvme_disable_ctrl(&dev->ctrl, lo_hi_readq(
1029                                                 dev->bar + NVME_REG_CAP));
1030
1031         spin_lock_irq(&nvmeq->q_lock);
1032         nvme_process_cq(nvmeq);
1033         spin_unlock_irq(&nvmeq->q_lock);
1034 }
1035
1036 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1037                                 int entry_size)
1038 {
1039         int q_depth = dev->q_depth;
1040         unsigned q_size_aligned = roundup(q_depth * entry_size,
1041                                           dev->ctrl.page_size);
1042
1043         if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1044                 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1045                 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
1046                 q_depth = div_u64(mem_per_q, entry_size);
1047
1048                 /*
1049                  * Ensure the reduced q_depth is above some threshold where it
1050                  * would be better to map queues in system memory with the
1051                  * original depth
1052                  */
1053                 if (q_depth < 64)
1054                         return -ENOMEM;
1055         }
1056
1057         return q_depth;
1058 }
1059
1060 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1061                                 int qid, int depth)
1062 {
1063         if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) {
1064                 unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth),
1065                                                       dev->ctrl.page_size);
1066                 nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset;
1067                 nvmeq->sq_cmds_io = dev->cmb + offset;
1068         } else {
1069                 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1070                                         &nvmeq->sq_dma_addr, GFP_KERNEL);
1071                 if (!nvmeq->sq_cmds)
1072                         return -ENOMEM;
1073         }
1074
1075         return 0;
1076 }
1077
1078 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1079                                                         int depth)
1080 {
1081         struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL);
1082         if (!nvmeq)
1083                 return NULL;
1084
1085         nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
1086                                           &nvmeq->cq_dma_addr, GFP_KERNEL);
1087         if (!nvmeq->cqes)
1088                 goto free_nvmeq;
1089
1090         if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
1091                 goto free_cqdma;
1092
1093         nvmeq->q_dmadev = dev->dev;
1094         nvmeq->dev = dev;
1095         snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1096                         dev->ctrl.instance, qid);
1097         spin_lock_init(&nvmeq->q_lock);
1098         nvmeq->cq_head = 0;
1099         nvmeq->cq_phase = 1;
1100         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1101         nvmeq->q_depth = depth;
1102         nvmeq->qid = qid;
1103         nvmeq->cq_vector = -1;
1104         dev->queues[qid] = nvmeq;
1105         dev->queue_count++;
1106
1107         return nvmeq;
1108
1109  free_cqdma:
1110         dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1111                                                         nvmeq->cq_dma_addr);
1112  free_nvmeq:
1113         kfree(nvmeq);
1114         return NULL;
1115 }
1116
1117 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1118                                                         const char *name)
1119 {
1120         if (use_threaded_interrupts)
1121                 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
1122                                         nvme_irq_check, nvme_irq, IRQF_SHARED,
1123                                         name, nvmeq);
1124         return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
1125                                 IRQF_SHARED, name, nvmeq);
1126 }
1127
1128 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1129 {
1130         struct nvme_dev *dev = nvmeq->dev;
1131
1132         spin_lock_irq(&nvmeq->q_lock);
1133         nvmeq->sq_tail = 0;
1134         nvmeq->cq_head = 0;
1135         nvmeq->cq_phase = 1;
1136         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1137         memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1138         dev->online_queues++;
1139         spin_unlock_irq(&nvmeq->q_lock);
1140 }
1141
1142 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1143 {
1144         struct nvme_dev *dev = nvmeq->dev;
1145         int result;
1146
1147         nvmeq->cq_vector = qid - 1;
1148         result = adapter_alloc_cq(dev, qid, nvmeq);
1149         if (result < 0)
1150                 return result;
1151
1152         result = adapter_alloc_sq(dev, qid, nvmeq);
1153         if (result < 0)
1154                 goto release_cq;
1155
1156         result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1157         if (result < 0)
1158                 goto release_sq;
1159
1160         nvme_init_queue(nvmeq, qid);
1161         return result;
1162
1163  release_sq:
1164         adapter_delete_sq(dev, qid);
1165  release_cq:
1166         adapter_delete_cq(dev, qid);
1167         return result;
1168 }
1169
1170 static struct blk_mq_ops nvme_mq_admin_ops = {
1171         .queue_rq       = nvme_queue_rq,
1172         .complete       = nvme_complete_rq,
1173         .map_queue      = blk_mq_map_queue,
1174         .init_hctx      = nvme_admin_init_hctx,
1175         .exit_hctx      = nvme_admin_exit_hctx,
1176         .init_request   = nvme_admin_init_request,
1177         .timeout        = nvme_timeout,
1178 };
1179
1180 static struct blk_mq_ops nvme_mq_ops = {
1181         .queue_rq       = nvme_queue_rq,
1182         .complete       = nvme_complete_rq,
1183         .map_queue      = blk_mq_map_queue,
1184         .init_hctx      = nvme_init_hctx,
1185         .init_request   = nvme_init_request,
1186         .timeout        = nvme_timeout,
1187         .poll           = nvme_poll,
1188 };
1189
1190 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1191 {
1192         if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1193                 /*
1194                  * If the controller was reset during removal, it's possible
1195                  * user requests may be waiting on a stopped queue. Start the
1196                  * queue to flush these to completion.
1197                  */
1198                 blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true);
1199                 blk_cleanup_queue(dev->ctrl.admin_q);
1200                 blk_mq_free_tag_set(&dev->admin_tagset);
1201         }
1202 }
1203
1204 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1205 {
1206         if (!dev->ctrl.admin_q) {
1207                 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1208                 dev->admin_tagset.nr_hw_queues = 1;
1209
1210                 /*
1211                  * Subtract one to leave an empty queue entry for 'Full Queue'
1212                  * condition. See NVM-Express 1.2 specification, section 4.1.2.
1213                  */
1214                 dev->admin_tagset.queue_depth = NVME_AQ_BLKMQ_DEPTH - 1;
1215                 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1216                 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1217                 dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
1218                 dev->admin_tagset.driver_data = dev;
1219
1220                 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1221                         return -ENOMEM;
1222
1223                 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1224                 if (IS_ERR(dev->ctrl.admin_q)) {
1225                         blk_mq_free_tag_set(&dev->admin_tagset);
1226                         return -ENOMEM;
1227                 }
1228                 if (!blk_get_queue(dev->ctrl.admin_q)) {
1229                         nvme_dev_remove_admin(dev);
1230                         dev->ctrl.admin_q = NULL;
1231                         return -ENODEV;
1232                 }
1233         } else
1234                 blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true);
1235
1236         return 0;
1237 }
1238
1239 static int nvme_configure_admin_queue(struct nvme_dev *dev)
1240 {
1241         int result;
1242         u32 aqa;
1243         u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1244         struct nvme_queue *nvmeq;
1245
1246         dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1) ?
1247                                                 NVME_CAP_NSSRC(cap) : 0;
1248
1249         if (dev->subsystem &&
1250             (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1251                 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1252
1253         result = nvme_disable_ctrl(&dev->ctrl, cap);
1254         if (result < 0)
1255                 return result;
1256
1257         nvmeq = dev->queues[0];
1258         if (!nvmeq) {
1259                 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1260                 if (!nvmeq)
1261                         return -ENOMEM;
1262         }
1263
1264         aqa = nvmeq->q_depth - 1;
1265         aqa |= aqa << 16;
1266
1267         writel(aqa, dev->bar + NVME_REG_AQA);
1268         lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1269         lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1270
1271         result = nvme_enable_ctrl(&dev->ctrl, cap);
1272         if (result)
1273                 goto free_nvmeq;
1274
1275         nvmeq->cq_vector = 0;
1276         result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1277         if (result) {
1278                 nvmeq->cq_vector = -1;
1279                 goto free_nvmeq;
1280         }
1281
1282         return result;
1283
1284  free_nvmeq:
1285         nvme_free_queues(dev, 0);
1286         return result;
1287 }
1288
1289 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1290 {
1291
1292         /* If true, indicates loss of adapter communication, possibly by a
1293          * NVMe Subsystem reset.
1294          */
1295         bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1296
1297         /* If there is a reset ongoing, we shouldn't reset again. */
1298         if (work_busy(&dev->reset_work))
1299                 return false;
1300
1301         /* We shouldn't reset unless the controller is on fatal error state
1302          * _or_ if we lost the communication with it.
1303          */
1304         if (!(csts & NVME_CSTS_CFS) && !nssro)
1305                 return false;
1306
1307         /* If PCI error recovery process is happening, we cannot reset or
1308          * the recovery mechanism will surely fail.
1309          */
1310         if (pci_channel_offline(to_pci_dev(dev->dev)))
1311                 return false;
1312
1313         return true;
1314 }
1315
1316 static void nvme_watchdog_timer(unsigned long data)
1317 {
1318         struct nvme_dev *dev = (struct nvme_dev *)data;
1319         u32 csts = readl(dev->bar + NVME_REG_CSTS);
1320
1321         /* Skip controllers under certain specific conditions. */
1322         if (nvme_should_reset(dev, csts)) {
1323                 if (queue_work(nvme_workq, &dev->reset_work))
1324                         dev_warn(dev->dev,
1325                                 "Failed status: 0x%x, reset controller.\n",
1326                                 csts);
1327                 return;
1328         }
1329
1330         mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ));
1331 }
1332
1333 static int nvme_create_io_queues(struct nvme_dev *dev)
1334 {
1335         unsigned i, max;
1336         int ret = 0;
1337
1338         for (i = dev->queue_count; i <= dev->max_qid; i++) {
1339                 if (!nvme_alloc_queue(dev, i, dev->q_depth)) {
1340                         ret = -ENOMEM;
1341                         break;
1342                 }
1343         }
1344
1345         max = min(dev->max_qid, dev->queue_count - 1);
1346         for (i = dev->online_queues; i <= max; i++) {
1347                 ret = nvme_create_queue(dev->queues[i], i);
1348                 if (ret) {
1349                         nvme_free_queues(dev, i);
1350                         break;
1351                 }
1352         }
1353
1354         /*
1355          * Ignore failing Create SQ/CQ commands, we can continue with less
1356          * than the desired aount of queues, and even a controller without
1357          * I/O queues an still be used to issue admin commands.  This might
1358          * be useful to upgrade a buggy firmware for example.
1359          */
1360         return ret >= 0 ? 0 : ret;
1361 }
1362
1363 static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
1364 {
1365         u64 szu, size, offset;
1366         u32 cmbloc;
1367         resource_size_t bar_size;
1368         struct pci_dev *pdev = to_pci_dev(dev->dev);
1369         void __iomem *cmb;
1370         dma_addr_t dma_addr;
1371
1372         if (!use_cmb_sqes)
1373                 return NULL;
1374
1375         dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1376         if (!(NVME_CMB_SZ(dev->cmbsz)))
1377                 return NULL;
1378
1379         cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1380
1381         szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz));
1382         size = szu * NVME_CMB_SZ(dev->cmbsz);
1383         offset = szu * NVME_CMB_OFST(cmbloc);
1384         bar_size = pci_resource_len(pdev, NVME_CMB_BIR(cmbloc));
1385
1386         if (offset > bar_size)
1387                 return NULL;
1388
1389         /*
1390          * Controllers may support a CMB size larger than their BAR,
1391          * for example, due to being behind a bridge. Reduce the CMB to
1392          * the reported size of the BAR
1393          */
1394         if (size > bar_size - offset)
1395                 size = bar_size - offset;
1396
1397         dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(cmbloc)) + offset;
1398         cmb = ioremap_wc(dma_addr, size);
1399         if (!cmb)
1400                 return NULL;
1401
1402         dev->cmb_dma_addr = dma_addr;
1403         dev->cmb_size = size;
1404         return cmb;
1405 }
1406
1407 static inline void nvme_release_cmb(struct nvme_dev *dev)
1408 {
1409         if (dev->cmb) {
1410                 iounmap(dev->cmb);
1411                 dev->cmb = NULL;
1412         }
1413 }
1414
1415 static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1416 {
1417         return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
1418 }
1419
1420 static int nvme_setup_io_queues(struct nvme_dev *dev)
1421 {
1422         struct nvme_queue *adminq = dev->queues[0];
1423         struct pci_dev *pdev = to_pci_dev(dev->dev);
1424         int result, i, vecs, nr_io_queues, size;
1425
1426         nr_io_queues = num_possible_cpus();
1427         result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
1428         if (result < 0)
1429                 return result;
1430
1431         /*
1432          * Degraded controllers might return an error when setting the queue
1433          * count.  We still want to be able to bring them online and offer
1434          * access to the admin queue, as that might be only way to fix them up.
1435          */
1436         if (result > 0) {
1437                 dev_err(dev->ctrl.device,
1438                         "Could not set queue count (%d)\n", result);
1439                 return 0;
1440         }
1441
1442         if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) {
1443                 result = nvme_cmb_qdepth(dev, nr_io_queues,
1444                                 sizeof(struct nvme_command));
1445                 if (result > 0)
1446                         dev->q_depth = result;
1447                 else
1448                         nvme_release_cmb(dev);
1449         }
1450
1451         size = db_bar_size(dev, nr_io_queues);
1452         if (size > 8192) {
1453                 iounmap(dev->bar);
1454                 do {
1455                         dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1456                         if (dev->bar)
1457                                 break;
1458                         if (!--nr_io_queues)
1459                                 return -ENOMEM;
1460                         size = db_bar_size(dev, nr_io_queues);
1461                 } while (1);
1462                 dev->dbs = dev->bar + 4096;
1463                 adminq->q_db = dev->dbs;
1464         }
1465
1466         /* Deregister the admin queue's interrupt */
1467         free_irq(dev->entry[0].vector, adminq);
1468
1469         /*
1470          * If we enable msix early due to not intx, disable it again before
1471          * setting up the full range we need.
1472          */
1473         if (pdev->msi_enabled)
1474                 pci_disable_msi(pdev);
1475         else if (pdev->msix_enabled)
1476                 pci_disable_msix(pdev);
1477
1478         for (i = 0; i < nr_io_queues; i++)
1479                 dev->entry[i].entry = i;
1480         vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues);
1481         if (vecs < 0) {
1482                 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32));
1483                 if (vecs < 0) {
1484                         vecs = 1;
1485                 } else {
1486                         for (i = 0; i < vecs; i++)
1487                                 dev->entry[i].vector = i + pdev->irq;
1488                 }
1489         }
1490
1491         /*
1492          * Should investigate if there's a performance win from allocating
1493          * more queues than interrupt vectors; it might allow the submission
1494          * path to scale better, even if the receive path is limited by the
1495          * number of interrupts.
1496          */
1497         nr_io_queues = vecs;
1498         dev->max_qid = nr_io_queues;
1499
1500         result = queue_request_irq(dev, adminq, adminq->irqname);
1501         if (result) {
1502                 adminq->cq_vector = -1;
1503                 goto free_queues;
1504         }
1505         return nvme_create_io_queues(dev);
1506
1507  free_queues:
1508         nvme_free_queues(dev, 1);
1509         return result;
1510 }
1511
1512 static void nvme_pci_post_scan(struct nvme_ctrl *ctrl)
1513 {
1514         struct nvme_dev *dev = to_nvme_dev(ctrl);
1515         struct nvme_queue *nvmeq;
1516         int i;
1517
1518         for (i = 0; i < dev->online_queues; i++) {
1519                 nvmeq = dev->queues[i];
1520
1521                 if (!nvmeq->tags || !(*nvmeq->tags))
1522                         continue;
1523
1524                 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
1525                                         blk_mq_tags_cpumask(*nvmeq->tags));
1526         }
1527 }
1528
1529 static void nvme_del_queue_end(struct request *req, int error)
1530 {
1531         struct nvme_queue *nvmeq = req->end_io_data;
1532
1533         blk_mq_free_request(req);
1534         complete(&nvmeq->dev->ioq_wait);
1535 }
1536
1537 static void nvme_del_cq_end(struct request *req, int error)
1538 {
1539         struct nvme_queue *nvmeq = req->end_io_data;
1540
1541         if (!error) {
1542                 unsigned long flags;
1543
1544                 /*
1545                  * We might be called with the AQ q_lock held
1546                  * and the I/O queue q_lock should always
1547                  * nest inside the AQ one.
1548                  */
1549                 spin_lock_irqsave_nested(&nvmeq->q_lock, flags,
1550                                         SINGLE_DEPTH_NESTING);
1551                 nvme_process_cq(nvmeq);
1552                 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
1553         }
1554
1555         nvme_del_queue_end(req, error);
1556 }
1557
1558 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
1559 {
1560         struct request_queue *q = nvmeq->dev->ctrl.admin_q;
1561         struct request *req;
1562         struct nvme_command cmd;
1563
1564         memset(&cmd, 0, sizeof(cmd));
1565         cmd.delete_queue.opcode = opcode;
1566         cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
1567
1568         req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT);
1569         if (IS_ERR(req))
1570                 return PTR_ERR(req);
1571
1572         req->timeout = ADMIN_TIMEOUT;
1573         req->end_io_data = nvmeq;
1574
1575         blk_execute_rq_nowait(q, NULL, req, false,
1576                         opcode == nvme_admin_delete_cq ?
1577                                 nvme_del_cq_end : nvme_del_queue_end);
1578         return 0;
1579 }
1580
1581 static void nvme_disable_io_queues(struct nvme_dev *dev)
1582 {
1583         int pass;
1584         unsigned long timeout;
1585         u8 opcode = nvme_admin_delete_sq;
1586
1587         for (pass = 0; pass < 2; pass++) {
1588                 int sent = 0, i = dev->queue_count - 1;
1589
1590                 reinit_completion(&dev->ioq_wait);
1591  retry:
1592                 timeout = ADMIN_TIMEOUT;
1593                 for (; i > 0; i--) {
1594                         struct nvme_queue *nvmeq = dev->queues[i];
1595
1596                         if (!pass)
1597                                 nvme_suspend_queue(nvmeq);
1598                         if (nvme_delete_queue(nvmeq, opcode))
1599                                 break;
1600                         ++sent;
1601                 }
1602                 while (sent--) {
1603                         timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout);
1604                         if (timeout == 0)
1605                                 return;
1606                         if (i)
1607                                 goto retry;
1608                 }
1609                 opcode = nvme_admin_delete_cq;
1610         }
1611 }
1612
1613 /*
1614  * Return: error value if an error occurred setting up the queues or calling
1615  * Identify Device.  0 if these succeeded, even if adding some of the
1616  * namespaces failed.  At the moment, these failures are silent.  TBD which
1617  * failures should be reported.
1618  */
1619 static int nvme_dev_add(struct nvme_dev *dev)
1620 {
1621         if (!dev->ctrl.tagset) {
1622                 dev->tagset.ops = &nvme_mq_ops;
1623                 dev->tagset.nr_hw_queues = dev->online_queues - 1;
1624                 dev->tagset.timeout = NVME_IO_TIMEOUT;
1625                 dev->tagset.numa_node = dev_to_node(dev->dev);
1626                 dev->tagset.queue_depth =
1627                                 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
1628                 dev->tagset.cmd_size = nvme_cmd_size(dev);
1629                 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
1630                 dev->tagset.driver_data = dev;
1631
1632                 if (blk_mq_alloc_tag_set(&dev->tagset))
1633                         return 0;
1634                 dev->ctrl.tagset = &dev->tagset;
1635         } else {
1636                 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
1637
1638                 /* Free previously allocated queues that are no longer usable */
1639                 nvme_free_queues(dev, dev->online_queues);
1640         }
1641
1642         return 0;
1643 }
1644
1645 static int nvme_pci_enable(struct nvme_dev *dev)
1646 {
1647         u64 cap;
1648         int result = -ENOMEM;
1649         struct pci_dev *pdev = to_pci_dev(dev->dev);
1650
1651         if (pci_enable_device_mem(pdev))
1652                 return result;
1653
1654         pci_set_master(pdev);
1655
1656         if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
1657             dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
1658                 goto disable;
1659
1660         if (readl(dev->bar + NVME_REG_CSTS) == -1) {
1661                 result = -ENODEV;
1662                 goto disable;
1663         }
1664
1665         /*
1666          * Some devices and/or platforms don't advertise or work with INTx
1667          * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
1668          * adjust this later.
1669          */
1670         if (pci_enable_msix(pdev, dev->entry, 1)) {
1671                 pci_enable_msi(pdev);
1672                 dev->entry[0].vector = pdev->irq;
1673         }
1674
1675         if (!dev->entry[0].vector) {
1676                 result = -ENODEV;
1677                 goto disable;
1678         }
1679
1680         cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1681
1682         dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
1683         dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
1684         dev->dbs = dev->bar + 4096;
1685
1686         /*
1687          * Temporary fix for the Apple controller found in the MacBook8,1 and
1688          * some MacBook7,1 to avoid controller resets and data loss.
1689          */
1690         if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
1691                 dev->q_depth = 2;
1692                 dev_warn(dev->dev, "detected Apple NVMe controller, set "
1693                         "queue depth=%u to work around controller resets\n",
1694                         dev->q_depth);
1695         }
1696
1697         if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2))
1698                 dev->cmb = nvme_map_cmb(dev);
1699
1700         pci_enable_pcie_error_reporting(pdev);
1701         pci_save_state(pdev);
1702         return 0;
1703
1704  disable:
1705         pci_disable_device(pdev);
1706         return result;
1707 }
1708
1709 static void nvme_dev_unmap(struct nvme_dev *dev)
1710 {
1711         if (dev->bar)
1712                 iounmap(dev->bar);
1713         pci_release_regions(to_pci_dev(dev->dev));
1714 }
1715
1716 static void nvme_pci_disable(struct nvme_dev *dev)
1717 {
1718         struct pci_dev *pdev = to_pci_dev(dev->dev);
1719
1720         if (pdev->msi_enabled)
1721                 pci_disable_msi(pdev);
1722         else if (pdev->msix_enabled)
1723                 pci_disable_msix(pdev);
1724
1725         if (pci_is_enabled(pdev)) {
1726                 pci_disable_pcie_error_reporting(pdev);
1727                 pci_disable_device(pdev);
1728         }
1729 }
1730
1731 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
1732 {
1733         int i;
1734         u32 csts = -1;
1735
1736         del_timer_sync(&dev->watchdog_timer);
1737
1738         mutex_lock(&dev->shutdown_lock);
1739         if (pci_is_enabled(to_pci_dev(dev->dev))) {
1740                 nvme_stop_queues(&dev->ctrl);
1741                 csts = readl(dev->bar + NVME_REG_CSTS);
1742         }
1743         if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) {
1744                 for (i = dev->queue_count - 1; i >= 0; i--) {
1745                         struct nvme_queue *nvmeq = dev->queues[i];
1746                         nvme_suspend_queue(nvmeq);
1747                 }
1748         } else {
1749                 nvme_disable_io_queues(dev);
1750                 nvme_disable_admin_queue(dev, shutdown);
1751         }
1752         nvme_pci_disable(dev);
1753
1754         blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_io, dev);
1755         blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_io, dev);
1756         mutex_unlock(&dev->shutdown_lock);
1757 }
1758
1759 static int nvme_setup_prp_pools(struct nvme_dev *dev)
1760 {
1761         dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
1762                                                 PAGE_SIZE, PAGE_SIZE, 0);
1763         if (!dev->prp_page_pool)
1764                 return -ENOMEM;
1765
1766         /* Optimisation for I/Os between 4k and 128k */
1767         dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
1768                                                 256, 256, 0);
1769         if (!dev->prp_small_pool) {
1770                 dma_pool_destroy(dev->prp_page_pool);
1771                 return -ENOMEM;
1772         }
1773         return 0;
1774 }
1775
1776 static void nvme_release_prp_pools(struct nvme_dev *dev)
1777 {
1778         dma_pool_destroy(dev->prp_page_pool);
1779         dma_pool_destroy(dev->prp_small_pool);
1780 }
1781
1782 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
1783 {
1784         struct nvme_dev *dev = to_nvme_dev(ctrl);
1785
1786         put_device(dev->dev);
1787         if (dev->tagset.tags)
1788                 blk_mq_free_tag_set(&dev->tagset);
1789         if (dev->ctrl.admin_q)
1790                 blk_put_queue(dev->ctrl.admin_q);
1791         kfree(dev->queues);
1792         kfree(dev->entry);
1793         kfree(dev);
1794 }
1795
1796 static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
1797 {
1798         dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
1799
1800         kref_get(&dev->ctrl.kref);
1801         nvme_dev_disable(dev, false);
1802         if (!schedule_work(&dev->remove_work))
1803                 nvme_put_ctrl(&dev->ctrl);
1804 }
1805
1806 static void nvme_reset_work(struct work_struct *work)
1807 {
1808         struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
1809         int result = -ENODEV;
1810
1811         if (WARN_ON(dev->ctrl.state == NVME_CTRL_RESETTING))
1812                 goto out;
1813
1814         /*
1815          * If we're called to reset a live controller first shut it down before
1816          * moving on.
1817          */
1818         if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
1819                 nvme_dev_disable(dev, false);
1820
1821         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING))
1822                 goto out;
1823
1824         result = nvme_pci_enable(dev);
1825         if (result)
1826                 goto out;
1827
1828         result = nvme_configure_admin_queue(dev);
1829         if (result)
1830                 goto out;
1831
1832         nvme_init_queue(dev->queues[0], 0);
1833         result = nvme_alloc_admin_tags(dev);
1834         if (result)
1835                 goto out;
1836
1837         result = nvme_init_identify(&dev->ctrl);
1838         if (result)
1839                 goto out;
1840
1841         result = nvme_setup_io_queues(dev);
1842         if (result)
1843                 goto out;
1844
1845         /*
1846          * A controller that can not execute IO typically requires user
1847          * intervention to correct. For such degraded controllers, the driver
1848          * should not submit commands the user did not request, so skip
1849          * registering for asynchronous event notification on this condition.
1850          */
1851         if (dev->online_queues > 1) {
1852                 dev->ctrl.event_limit = NVME_NR_AEN_COMMANDS;
1853                 queue_work(nvme_workq, &dev->async_work);
1854         }
1855
1856         mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ));
1857
1858         /*
1859          * Keep the controller around but remove all namespaces if we don't have
1860          * any working I/O queue.
1861          */
1862         if (dev->online_queues < 2) {
1863                 dev_warn(dev->ctrl.device, "IO queues not created\n");
1864                 nvme_kill_queues(&dev->ctrl);
1865                 nvme_remove_namespaces(&dev->ctrl);
1866         } else {
1867                 nvme_start_queues(&dev->ctrl);
1868                 nvme_dev_add(dev);
1869         }
1870
1871         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
1872                 dev_warn(dev->ctrl.device, "failed to mark controller live\n");
1873                 goto out;
1874         }
1875
1876         if (dev->online_queues > 1)
1877                 nvme_queue_scan(&dev->ctrl);
1878         return;
1879
1880  out:
1881         nvme_remove_dead_ctrl(dev, result);
1882 }
1883
1884 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
1885 {
1886         struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
1887         struct pci_dev *pdev = to_pci_dev(dev->dev);
1888
1889         nvme_kill_queues(&dev->ctrl);
1890         if (pci_get_drvdata(pdev))
1891                 pci_stop_and_remove_bus_device_locked(pdev);
1892         nvme_put_ctrl(&dev->ctrl);
1893 }
1894
1895 static int nvme_reset(struct nvme_dev *dev)
1896 {
1897         if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q))
1898                 return -ENODEV;
1899
1900         if (!queue_work(nvme_workq, &dev->reset_work))
1901                 return -EBUSY;
1902
1903         flush_work(&dev->reset_work);
1904         return 0;
1905 }
1906
1907 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
1908 {
1909         *val = readl(to_nvme_dev(ctrl)->bar + off);
1910         return 0;
1911 }
1912
1913 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
1914 {
1915         writel(val, to_nvme_dev(ctrl)->bar + off);
1916         return 0;
1917 }
1918
1919 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
1920 {
1921         *val = readq(to_nvme_dev(ctrl)->bar + off);
1922         return 0;
1923 }
1924
1925 static int nvme_pci_reset_ctrl(struct nvme_ctrl *ctrl)
1926 {
1927         return nvme_reset(to_nvme_dev(ctrl));
1928 }
1929
1930 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1931         .module                 = THIS_MODULE,
1932         .reg_read32             = nvme_pci_reg_read32,
1933         .reg_write32            = nvme_pci_reg_write32,
1934         .reg_read64             = nvme_pci_reg_read64,
1935         .reset_ctrl             = nvme_pci_reset_ctrl,
1936         .free_ctrl              = nvme_pci_free_ctrl,
1937         .post_scan              = nvme_pci_post_scan,
1938 };
1939
1940 static int nvme_dev_map(struct nvme_dev *dev)
1941 {
1942         int bars;
1943         struct pci_dev *pdev = to_pci_dev(dev->dev);
1944
1945         bars = pci_select_bars(pdev, IORESOURCE_MEM);
1946         if (!bars)
1947                 return -ENODEV;
1948         if (pci_request_selected_regions(pdev, bars, "nvme"))
1949                 return -ENODEV;
1950
1951         dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1952         if (!dev->bar)
1953                 goto release;
1954
1955        return 0;
1956   release:
1957        pci_release_regions(pdev);
1958        return -ENODEV;
1959 }
1960
1961 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1962 {
1963         int node, result = -ENOMEM;
1964         struct nvme_dev *dev;
1965
1966         node = dev_to_node(&pdev->dev);
1967         if (node == NUMA_NO_NODE)
1968                 set_dev_node(&pdev->dev, 0);
1969
1970         dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
1971         if (!dev)
1972                 return -ENOMEM;
1973         dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry),
1974                                                         GFP_KERNEL, node);
1975         if (!dev->entry)
1976                 goto free;
1977         dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
1978                                                         GFP_KERNEL, node);
1979         if (!dev->queues)
1980                 goto free;
1981
1982         dev->dev = get_device(&pdev->dev);
1983         pci_set_drvdata(pdev, dev);
1984
1985         result = nvme_dev_map(dev);
1986         if (result)
1987                 goto free;
1988
1989         INIT_WORK(&dev->reset_work, nvme_reset_work);
1990         INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
1991         INIT_WORK(&dev->async_work, nvme_async_event_work);
1992         setup_timer(&dev->watchdog_timer, nvme_watchdog_timer,
1993                 (unsigned long)dev);
1994         mutex_init(&dev->shutdown_lock);
1995         init_completion(&dev->ioq_wait);
1996
1997         result = nvme_setup_prp_pools(dev);
1998         if (result)
1999                 goto put_pci;
2000
2001         result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2002                         id->driver_data);
2003         if (result)
2004                 goto release_pools;
2005
2006         dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2007
2008         queue_work(nvme_workq, &dev->reset_work);
2009         return 0;
2010
2011  release_pools:
2012         nvme_release_prp_pools(dev);
2013  put_pci:
2014         put_device(dev->dev);
2015         nvme_dev_unmap(dev);
2016  free:
2017         kfree(dev->queues);
2018         kfree(dev->entry);
2019         kfree(dev);
2020         return result;
2021 }
2022
2023 static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
2024 {
2025         struct nvme_dev *dev = pci_get_drvdata(pdev);
2026
2027         if (prepare)
2028                 nvme_dev_disable(dev, false);
2029         else
2030                 queue_work(nvme_workq, &dev->reset_work);
2031 }
2032
2033 static void nvme_shutdown(struct pci_dev *pdev)
2034 {
2035         struct nvme_dev *dev = pci_get_drvdata(pdev);
2036         nvme_dev_disable(dev, true);
2037 }
2038
2039 /*
2040  * The driver's remove may be called on a device in a partially initialized
2041  * state. This function must not have any dependencies on the device state in
2042  * order to proceed.
2043  */
2044 static void nvme_remove(struct pci_dev *pdev)
2045 {
2046         struct nvme_dev *dev = pci_get_drvdata(pdev);
2047
2048         del_timer_sync(&dev->watchdog_timer);
2049
2050         nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2051
2052         pci_set_drvdata(pdev, NULL);
2053         flush_work(&dev->async_work);
2054         nvme_uninit_ctrl(&dev->ctrl);
2055         nvme_dev_disable(dev, true);
2056         flush_work(&dev->reset_work);
2057         nvme_dev_remove_admin(dev);
2058         nvme_free_queues(dev, 0);
2059         nvme_release_cmb(dev);
2060         nvme_release_prp_pools(dev);
2061         nvme_dev_unmap(dev);
2062         nvme_put_ctrl(&dev->ctrl);
2063 }
2064
2065 #ifdef CONFIG_PM_SLEEP
2066 static int nvme_suspend(struct device *dev)
2067 {
2068         struct pci_dev *pdev = to_pci_dev(dev);
2069         struct nvme_dev *ndev = pci_get_drvdata(pdev);
2070
2071         nvme_dev_disable(ndev, true);
2072         return 0;
2073 }
2074
2075 static int nvme_resume(struct device *dev)
2076 {
2077         struct pci_dev *pdev = to_pci_dev(dev);
2078         struct nvme_dev *ndev = pci_get_drvdata(pdev);
2079
2080         queue_work(nvme_workq, &ndev->reset_work);
2081         return 0;
2082 }
2083 #endif
2084
2085 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
2086
2087 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2088                                                 pci_channel_state_t state)
2089 {
2090         struct nvme_dev *dev = pci_get_drvdata(pdev);
2091
2092         /*
2093          * A frozen channel requires a reset. When detected, this method will
2094          * shutdown the controller to quiesce. The controller will be restarted
2095          * after the slot reset through driver's slot_reset callback.
2096          */
2097         dev_warn(dev->ctrl.device, "error detected: state:%d\n", state);
2098         switch (state) {
2099         case pci_channel_io_normal:
2100                 return PCI_ERS_RESULT_CAN_RECOVER;
2101         case pci_channel_io_frozen:
2102                 nvme_dev_disable(dev, false);
2103                 return PCI_ERS_RESULT_NEED_RESET;
2104         case pci_channel_io_perm_failure:
2105                 return PCI_ERS_RESULT_DISCONNECT;
2106         }
2107         return PCI_ERS_RESULT_NEED_RESET;
2108 }
2109
2110 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2111 {
2112         struct nvme_dev *dev = pci_get_drvdata(pdev);
2113
2114         dev_info(dev->ctrl.device, "restart after slot reset\n");
2115         pci_restore_state(pdev);
2116         queue_work(nvme_workq, &dev->reset_work);
2117         return PCI_ERS_RESULT_RECOVERED;
2118 }
2119
2120 static void nvme_error_resume(struct pci_dev *pdev)
2121 {
2122         pci_cleanup_aer_uncorrect_error_status(pdev);
2123 }
2124
2125 static const struct pci_error_handlers nvme_err_handler = {
2126         .error_detected = nvme_error_detected,
2127         .slot_reset     = nvme_slot_reset,
2128         .resume         = nvme_error_resume,
2129         .reset_notify   = nvme_reset_notify,
2130 };
2131
2132 /* Move to pci_ids.h later */
2133 #define PCI_CLASS_STORAGE_EXPRESS       0x010802
2134
2135 static const struct pci_device_id nvme_id_table[] = {
2136         { PCI_VDEVICE(INTEL, 0x0953),
2137                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2138                                 NVME_QUIRK_DISCARD_ZEROES, },
2139         { PCI_VDEVICE(INTEL, 0x5845),   /* Qemu emulated controller */
2140                 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
2141         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2142         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
2143         { 0, }
2144 };
2145 MODULE_DEVICE_TABLE(pci, nvme_id_table);
2146
2147 static struct pci_driver nvme_driver = {
2148         .name           = "nvme",
2149         .id_table       = nvme_id_table,
2150         .probe          = nvme_probe,
2151         .remove         = nvme_remove,
2152         .shutdown       = nvme_shutdown,
2153         .driver         = {
2154                 .pm     = &nvme_dev_pm_ops,
2155         },
2156         .err_handler    = &nvme_err_handler,
2157 };
2158
2159 static int __init nvme_init(void)
2160 {
2161         int result;
2162
2163         nvme_workq = alloc_workqueue("nvme", WQ_UNBOUND | WQ_MEM_RECLAIM, 0);
2164         if (!nvme_workq)
2165                 return -ENOMEM;
2166
2167         result = pci_register_driver(&nvme_driver);
2168         if (result)
2169                 destroy_workqueue(nvme_workq);
2170         return result;
2171 }
2172
2173 static void __exit nvme_exit(void)
2174 {
2175         pci_unregister_driver(&nvme_driver);
2176         destroy_workqueue(nvme_workq);
2177         _nvme_check_size();
2178 }
2179
2180 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2181 MODULE_LICENSE("GPL");
2182 MODULE_VERSION("1.0");
2183 module_init(nvme_init);
2184 module_exit(nvme_exit);