drivers/nvme/host/pci.c

   1 /*
   2  * NVM Express device driver
   3  * Copyright (c) 2011-2014, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  */
  14
  15 #include <linux/aer.h>
  16 #include <linux/bitops.h>
  17 #include <linux/blkdev.h>
  18 #include <linux/blk-mq.h>
  19 #include <linux/cpu.h>
  20 #include <linux/delay.h>
  21 #include <linux/errno.h>
  22 #include <linux/fs.h>
  23 #include <linux/genhd.h>
  24 #include <linux/hdreg.h>
  25 #include <linux/idr.h>
  26 #include <linux/init.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/io.h>
  29 #include <linux/kdev_t.h>
  30 #include <linux/kernel.h>
  31 #include <linux/mm.h>
  32 #include <linux/module.h>
  33 #include <linux/moduleparam.h>
  34 #include <linux/mutex.h>
  35 #include <linux/pci.h>
  36 #include <linux/poison.h>
  37 #include <linux/ptrace.h>
  38 #include <linux/sched.h>
  39 #include <linux/slab.h>
  40 #include <linux/t10-pi.h>
  41 #include <linux/timer.h>
  42 #include <linux/types.h>
  43 #include <linux/io-64-nonatomic-lo-hi.h>
  44 #include <asm/unaligned.h>
  45
  46 #include "nvme.h"
  47
  48 #define NVME_Q_DEPTH            1024
  49 #define NVME_AQ_DEPTH           256
  50 #define SQ_SIZE(depth)          (depth * sizeof(struct nvme_command))
  51 #define CQ_SIZE(depth)          (depth * sizeof(struct nvme_completion))
  52
  53 /*
  54  * We handle AEN commands ourselves and don't even let the
  55  * block layer know about them.
  56  */
  57 #define NVME_NR_AEN_COMMANDS    1
  58 #define NVME_AQ_BLKMQ_DEPTH     (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
  59
  60 static int use_threaded_interrupts;
  61 module_param(use_threaded_interrupts, int, 0);
  62
  63 static bool use_cmb_sqes = true;
  64 module_param(use_cmb_sqes, bool, 0644);
  65 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
  66
  67 static struct workqueue_struct *nvme_workq;
  68
  69 struct nvme_dev;
  70 struct nvme_queue;
  71
  72 static int nvme_reset(struct nvme_dev *dev);
  73 static void nvme_process_cq(struct nvme_queue *nvmeq);
  74 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
  75
  76 /*
  77  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
  78  */
  79 struct nvme_dev {
  80         struct nvme_queue **queues;
  81         struct blk_mq_tag_set tagset;
  82         struct blk_mq_tag_set admin_tagset;
  83         u32 __iomem *dbs;
  84         struct device *dev;
  85         struct dma_pool *prp_page_pool;
  86         struct dma_pool *prp_small_pool;
  87         unsigned queue_count;
  88         unsigned online_queues;
  89         unsigned max_qid;
  90         int q_depth;
  91         u32 db_stride;
  92         struct msix_entry *entry;
  93         void __iomem *bar;
  94         struct work_struct reset_work;
  95         struct work_struct scan_work;
  96         struct work_struct remove_work;
  97         struct work_struct async_work;
  98         struct timer_list watchdog_timer;
  99         struct mutex shutdown_lock;
 100         bool subsystem;
 101         void __iomem *cmb;
 102         dma_addr_t cmb_dma_addr;
 103         u64 cmb_size;
 104         u32 cmbsz;
 105         unsigned long flags;
 106
 107 #define NVME_CTRL_RESETTING    0
 108 #define NVME_CTRL_REMOVING     1
 109
 110         struct nvme_ctrl ctrl;
 111         struct completion ioq_wait;
 112 };
 113
 114 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
 115 {
 116         return container_of(ctrl, struct nvme_dev, ctrl);
 117 }
 118
 119 /*
 120  * An NVM Express queue.  Each device has at least two (one for admin
 121  * commands and one for I/O commands).
 122  */
 123 struct nvme_queue {
 124         struct device *q_dmadev;
 125         struct nvme_dev *dev;
 126         char irqname[24];       /* nvme4294967295-65535\0 */
 127         spinlock_t q_lock;
 128         struct nvme_command *sq_cmds;
 129         struct nvme_command __iomem *sq_cmds_io;
 130         volatile struct nvme_completion *cqes;
 131         struct blk_mq_tags **tags;
 132         dma_addr_t sq_dma_addr;
 133         dma_addr_t cq_dma_addr;
 134         u32 __iomem *q_db;
 135         u16 q_depth;
 136         s16 cq_vector;
 137         u16 sq_tail;
 138         u16 cq_head;
 139         u16 qid;
 140         u8 cq_phase;
 141         u8 cqe_seen;
 142 };
 143
 144 /*
 145  * The nvme_iod describes the data in an I/O, including the list of PRP
 146  * entries.  You can't see it in this data structure because C doesn't let
 147  * me express that.  Use nvme_init_iod to ensure there's enough space
 148  * allocated to store the PRP list.
 149  */
 150 struct nvme_iod {
 151         struct nvme_queue *nvmeq;
 152         int aborted;
 153         int npages;             /* In the PRP list. 0 means small pool in use */
 154         int nents;              /* Used in scatterlist */
 155         int length;             /* Of data, in bytes */
 156         dma_addr_t first_dma;
 157         struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
 158         struct scatterlist *sg;
 159         struct scatterlist inline_sg[0];
 160 };
 161
 162 /*
 163  * Check we didin't inadvertently grow the command struct
 164  */
 165 static inline void _nvme_check_size(void)
 166 {
 167         BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
 168         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
 169         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
 170         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
 171         BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
 172         BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
 173         BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
 174         BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
 175         BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
 176         BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
 177         BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
 178         BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
 179 }
 180
 181 /*
 182  * Max size of iod being embedded in the request payload
 183  */
 184 #define NVME_INT_PAGES          2
 185 #define NVME_INT_BYTES(dev)     (NVME_INT_PAGES * (dev)->ctrl.page_size)
 186
 187 /*
 188  * Will slightly overestimate the number of pages needed.  This is OK
 189  * as it only leads to a small amount of wasted memory for the lifetime of
 190  * the I/O.
 191  */
 192 static int nvme_npages(unsigned size, struct nvme_dev *dev)
 193 {
 194         unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
 195                                       dev->ctrl.page_size);
 196         return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
 197 }
 198
 199 static unsigned int nvme_iod_alloc_size(struct nvme_dev *dev,
 200                 unsigned int size, unsigned int nseg)
 201 {
 202         return sizeof(__le64 *) * nvme_npages(size, dev) +
 203                         sizeof(struct scatterlist) * nseg;
 204 }
 205
 206 static unsigned int nvme_cmd_size(struct nvme_dev *dev)
 207 {
 208         return sizeof(struct nvme_iod) +
 209                 nvme_iod_alloc_size(dev, NVME_INT_BYTES(dev), NVME_INT_PAGES);
 210 }
 211
 212 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 213                                 unsigned int hctx_idx)
 214 {
 215         struct nvme_dev *dev = data;
 216         struct nvme_queue *nvmeq = dev->queues[0];
 217
 218         WARN_ON(hctx_idx != 0);
 219         WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
 220         WARN_ON(nvmeq->tags);
 221
 222         hctx->driver_data = nvmeq;
 223         nvmeq->tags = &dev->admin_tagset.tags[0];
 224         return 0;
 225 }
 226
 227 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
 228 {
 229         struct nvme_queue *nvmeq = hctx->driver_data;
 230
 231         nvmeq->tags = NULL;
 232 }
 233
 234 static int nvme_admin_init_request(void *data, struct request *req,
 235                                 unsigned int hctx_idx, unsigned int rq_idx,
 236                                 unsigned int numa_node)
 237 {
 238         struct nvme_dev *dev = data;
 239         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 240         struct nvme_queue *nvmeq = dev->queues[0];
 241
 242         BUG_ON(!nvmeq);
 243         iod->nvmeq = nvmeq;
 244         return 0;
 245 }
 246
 247 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 248                           unsigned int hctx_idx)
 249 {
 250         struct nvme_dev *dev = data;
 251         struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
 252
 253         if (!nvmeq->tags)
 254                 nvmeq->tags = &dev->tagset.tags[hctx_idx];
 255
 256         WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
 257         hctx->driver_data = nvmeq;
 258         return 0;
 259 }
 260
 261 static int nvme_init_request(void *data, struct request *req,
 262                                 unsigned int hctx_idx, unsigned int rq_idx,
 263                                 unsigned int numa_node)
 264 {
 265         struct nvme_dev *dev = data;
 266         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 267         struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
 268
 269         BUG_ON(!nvmeq);
 270         iod->nvmeq = nvmeq;
 271         return 0;
 272 }
 273
 274 static void nvme_queue_scan(struct nvme_dev *dev)
 275 {
 276         /*
 277          * Do not queue new scan work when a controller is reset during
 278          * removal.
 279          */
 280         if (test_bit(NVME_CTRL_REMOVING, &dev->flags))
 281                 return;
 282         queue_work(nvme_workq, &dev->scan_work);
 283 }
 284
 285 static void nvme_complete_async_event(struct nvme_dev *dev,
 286                 struct nvme_completion *cqe)
 287 {
 288         u16 status = le16_to_cpu(cqe->status) >> 1;
 289         u32 result = le32_to_cpu(cqe->result);
 290
 291         if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ) {
 292                 ++dev->ctrl.event_limit;
 293                 queue_work(nvme_workq, &dev->async_work);
 294         }
 295
 296         if (status != NVME_SC_SUCCESS)
 297                 return;
 298
 299         switch (result & 0xff07) {
 300         case NVME_AER_NOTICE_NS_CHANGED:
 301                 dev_info(dev->ctrl.device, "rescanning\n");
 302                 nvme_queue_scan(dev);
 303         default:
 304                 dev_warn(dev->ctrl.device, "async event result %08x\n", result);
 305         }
 306 }
 307
 308 /**
 309  * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
 310  * @nvmeq: The queue to use
 311  * @cmd: The command to send
 312  *
 313  * Safe to use from interrupt context
 314  */
 315 static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
 316                                                 struct nvme_command *cmd)
 317 {
 318         u16 tail = nvmeq->sq_tail;
 319
 320         if (nvmeq->sq_cmds_io)
 321                 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
 322         else
 323                 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
 324
 325         if (++tail == nvmeq->q_depth)
 326                 tail = 0;
 327         writel(tail, nvmeq->q_db);
 328         nvmeq->sq_tail = tail;
 329 }
 330
 331 static __le64 **iod_list(struct request *req)
 332 {
 333         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 334         return (__le64 **)(iod->sg + req->nr_phys_segments);
 335 }
 336
 337 static int nvme_init_iod(struct request *rq, unsigned size,
 338                 struct nvme_dev *dev)
 339 {
 340         struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
 341         int nseg = rq->nr_phys_segments;
 342
 343         if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
 344                 iod->sg = kmalloc(nvme_iod_alloc_size(dev, size, nseg), GFP_ATOMIC);
 345                 if (!iod->sg)
 346                         return BLK_MQ_RQ_QUEUE_BUSY;
 347         } else {
 348                 iod->sg = iod->inline_sg;
 349         }
 350
 351         iod->aborted = 0;
 352         iod->npages = -1;
 353         iod->nents = 0;
 354         iod->length = size;
 355         return 0;
 356 }
 357
 358 static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
 359 {
 360         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 361         const int last_prp = dev->ctrl.page_size / 8 - 1;
 362         int i;
 363         __le64 **list = iod_list(req);
 364         dma_addr_t prp_dma = iod->first_dma;
 365
 366         if (req->cmd_flags & REQ_DISCARD)
 367                 kfree(req->completion_data);
 368
 369         if (iod->npages == 0)
 370                 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
 371         for (i = 0; i < iod->npages; i++) {
 372                 __le64 *prp_list = list[i];
 373                 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
 374                 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
 375                 prp_dma = next_prp_dma;
 376         }
 377
 378         if (iod->sg != iod->inline_sg)
 379                 kfree(iod->sg);
 380 }
 381
 382 #ifdef CONFIG_BLK_DEV_INTEGRITY
 383 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
 384 {
 385         if (be32_to_cpu(pi->ref_tag) == v)
 386                 pi->ref_tag = cpu_to_be32(p);
 387 }
 388
 389 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
 390 {
 391         if (be32_to_cpu(pi->ref_tag) == p)
 392                 pi->ref_tag = cpu_to_be32(v);
 393 }
 394
 395 /**
 396  * nvme_dif_remap - remaps ref tags to bip seed and physical lba
 397  *
 398  * The virtual start sector is the one that was originally submitted by the
 399  * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
 400  * start sector may be different. Remap protection information to match the
 401  * physical LBA on writes, and back to the original seed on reads.
 402  *
 403  * Type 0 and 3 do not have a ref tag, so no remapping required.
 404  */
 405 static void nvme_dif_remap(struct request *req,
 406                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
 407 {
 408         struct nvme_ns *ns = req->rq_disk->private_data;
 409         struct bio_integrity_payload *bip;
 410         struct t10_pi_tuple *pi;
 411         void *p, *pmap;
 412         u32 i, nlb, ts, phys, virt;
 413
 414         if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
 415                 return;
 416
 417         bip = bio_integrity(req->bio);
 418         if (!bip)
 419                 return;
 420
 421         pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
 422
 423         p = pmap;
 424         virt = bip_get_seed(bip);
 425         phys = nvme_block_nr(ns, blk_rq_pos(req));
 426         nlb = (blk_rq_bytes(req) >> ns->lba_shift);
 427         ts = ns->disk->queue->integrity.tuple_size;
 428
 429         for (i = 0; i < nlb; i++, virt++, phys++) {
 430                 pi = (struct t10_pi_tuple *)p;
 431                 dif_swap(phys, virt, pi);
 432                 p += ts;
 433         }
 434         kunmap_atomic(pmap);
 435 }
 436 #else /* CONFIG_BLK_DEV_INTEGRITY */
 437 static void nvme_dif_remap(struct request *req,
 438                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
 439 {
 440 }
 441 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
 442 {
 443 }
 444 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
 445 {
 446 }
 447 #endif
 448
 449 static bool nvme_setup_prps(struct nvme_dev *dev, struct request *req,
 450                 int total_len)
 451 {
 452         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 453         struct dma_pool *pool;
 454         int length = total_len;
 455         struct scatterlist *sg = iod->sg;
 456         int dma_len = sg_dma_len(sg);
 457         u64 dma_addr = sg_dma_address(sg);
 458         u32 page_size = dev->ctrl.page_size;
 459         int offset = dma_addr & (page_size - 1);
 460         __le64 *prp_list;
 461         __le64 **list = iod_list(req);
 462         dma_addr_t prp_dma;
 463         int nprps, i;
 464
 465         length -= (page_size - offset);
 466         if (length <= 0)
 467                 return true;
 468
 469         dma_len -= (page_size - offset);
 470         if (dma_len) {
 471                 dma_addr += (page_size - offset);
 472         } else {
 473                 sg = sg_next(sg);
 474                 dma_addr = sg_dma_address(sg);
 475                 dma_len = sg_dma_len(sg);
 476         }
 477
 478         if (length <= page_size) {
 479                 iod->first_dma = dma_addr;
 480                 return true;
 481         }
 482
 483         nprps = DIV_ROUND_UP(length, page_size);
 484         if (nprps <= (256 / 8)) {
 485                 pool = dev->prp_small_pool;
 486                 iod->npages = 0;
 487         } else {
 488                 pool = dev->prp_page_pool;
 489                 iod->npages = 1;
 490         }
 491
 492         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 493         if (!prp_list) {
 494                 iod->first_dma = dma_addr;
 495                 iod->npages = -1;
 496                 return false;
 497         }
 498         list[0] = prp_list;
 499         iod->first_dma = prp_dma;
 500         i = 0;
 501         for (;;) {
 502                 if (i == page_size >> 3) {
 503                         __le64 *old_prp_list = prp_list;
 504                         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 505                         if (!prp_list)
 506                                 return false;
 507                         list[iod->npages++] = prp_list;
 508                         prp_list[0] = old_prp_list[i - 1];
 509                         old_prp_list[i - 1] = cpu_to_le64(prp_dma);
 510                         i = 1;
 511                 }
 512                 prp_list[i++] = cpu_to_le64(dma_addr);
 513                 dma_len -= page_size;
 514                 dma_addr += page_size;
 515                 length -= page_size;
 516                 if (length <= 0)
 517                         break;
 518                 if (dma_len > 0)
 519                         continue;
 520                 BUG_ON(dma_len < 0);
 521                 sg = sg_next(sg);
 522                 dma_addr = sg_dma_address(sg);
 523                 dma_len = sg_dma_len(sg);
 524         }
 525
 526         return true;
 527 }
 528
 529 static int nvme_map_data(struct nvme_dev *dev, struct request *req,
 530                 unsigned size, struct nvme_command *cmnd)
 531 {
 532         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 533         struct request_queue *q = req->q;
 534         enum dma_data_direction dma_dir = rq_data_dir(req) ?
 535                         DMA_TO_DEVICE : DMA_FROM_DEVICE;
 536         int ret = BLK_MQ_RQ_QUEUE_ERROR;
 537
 538         sg_init_table(iod->sg, req->nr_phys_segments);
 539         iod->nents = blk_rq_map_sg(q, req, iod->sg);
 540         if (!iod->nents)
 541                 goto out;
 542
 543         ret = BLK_MQ_RQ_QUEUE_BUSY;
 544         if (!dma_map_sg(dev->dev, iod->sg, iod->nents, dma_dir))
 545                 goto out;
 546
 547         if (!nvme_setup_prps(dev, req, size))
 548                 goto out_unmap;
 549
 550         ret = BLK_MQ_RQ_QUEUE_ERROR;
 551         if (blk_integrity_rq(req)) {
 552                 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
 553                         goto out_unmap;
 554
 555                 sg_init_table(&iod->meta_sg, 1);
 556                 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
 557                         goto out_unmap;
 558
 559                 if (rq_data_dir(req))
 560                         nvme_dif_remap(req, nvme_dif_prep);
 561
 562                 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
 563                         goto out_unmap;
 564         }
 565
 566         cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
 567         cmnd->rw.prp2 = cpu_to_le64(iod->first_dma);
 568         if (blk_integrity_rq(req))
 569                 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
 570         return BLK_MQ_RQ_QUEUE_OK;
 571
 572 out_unmap:
 573         dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
 574 out:
 575         return ret;
 576 }
 577
 578 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
 579 {
 580         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 581         enum dma_data_direction dma_dir = rq_data_dir(req) ?
 582                         DMA_TO_DEVICE : DMA_FROM_DEVICE;
 583
 584         if (iod->nents) {
 585                 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
 586                 if (blk_integrity_rq(req)) {
 587                         if (!rq_data_dir(req))
 588                                 nvme_dif_remap(req, nvme_dif_complete);
 589                         dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
 590                 }
 591         }
 592
 593         nvme_free_iod(dev, req);
 594 }
 595
 596 /*
 597  * NOTE: ns is NULL when called on the admin queue.
 598  */
 599 static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
 600                          const struct blk_mq_queue_data *bd)
 601 {
 602         struct nvme_ns *ns = hctx->queue->queuedata;
 603         struct nvme_queue *nvmeq = hctx->driver_data;
 604         struct nvme_dev *dev = nvmeq->dev;
 605         struct request *req = bd->rq;
 606         struct nvme_command cmnd;
 607         unsigned map_len;
 608         int ret = BLK_MQ_RQ_QUEUE_OK;
 609
 610         /*
 611          * If formated with metadata, require the block layer provide a buffer
 612          * unless this namespace is formated such that the metadata can be
 613          * stripped/generated by the controller with PRACT=1.
 614          */
 615         if (ns && ns->ms && !blk_integrity_rq(req)) {
 616                 if (!(ns->pi_type && ns->ms == 8) &&
 617                                         req->cmd_type != REQ_TYPE_DRV_PRIV) {
 618                         blk_mq_end_request(req, -EFAULT);
 619                         return BLK_MQ_RQ_QUEUE_OK;
 620                 }
 621         }
 622
 623         map_len = nvme_map_len(req);
 624         ret = nvme_init_iod(req, map_len, dev);
 625         if (ret)
 626                 return ret;
 627
 628         ret = nvme_setup_cmd(ns, req, &cmnd);
 629         if (ret)
 630                 goto out;
 631
 632         if (req->nr_phys_segments)
 633                 ret = nvme_map_data(dev, req, map_len, &cmnd);
 634
 635         if (ret)
 636                 goto out;
 637
 638         cmnd.common.command_id = req->tag;
 639         blk_mq_start_request(req);
 640
 641         spin_lock_irq(&nvmeq->q_lock);
 642         if (unlikely(nvmeq->cq_vector < 0)) {
 643                 if (ns && !test_bit(NVME_NS_DEAD, &ns->flags))
 644                         ret = BLK_MQ_RQ_QUEUE_BUSY;
 645                 else
 646                         ret = BLK_MQ_RQ_QUEUE_ERROR;
 647                 spin_unlock_irq(&nvmeq->q_lock);
 648                 goto out;
 649         }
 650         __nvme_submit_cmd(nvmeq, &cmnd);
 651         nvme_process_cq(nvmeq);
 652         spin_unlock_irq(&nvmeq->q_lock);
 653         return BLK_MQ_RQ_QUEUE_OK;
 654 out:
 655         nvme_free_iod(dev, req);
 656         return ret;
 657 }
 658
 659 static void nvme_complete_rq(struct request *req)
 660 {
 661         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 662         struct nvme_dev *dev = iod->nvmeq->dev;
 663         int error = 0;
 664
 665         nvme_unmap_data(dev, req);
 666
 667         if (unlikely(req->errors)) {
 668                 if (nvme_req_needs_retry(req, req->errors)) {
 669                         nvme_requeue_req(req);
 670                         return;
 671                 }
 672
 673                 if (req->cmd_type == REQ_TYPE_DRV_PRIV)
 674                         error = req->errors;
 675                 else
 676                         error = nvme_error_status(req->errors);
 677         }
 678
 679         if (unlikely(iod->aborted)) {
 680                 dev_warn(dev->ctrl.device,
 681                         "completing aborted command with status: %04x\n",
 682                         req->errors);
 683         }
 684
 685         blk_mq_end_request(req, error);
 686 }
 687
 688 /* We read the CQE phase first to check if the rest of the entry is valid */
 689 static inline bool nvme_cqe_valid(struct nvme_queue *nvmeq, u16 head,
 690                 u16 phase)
 691 {
 692         return (le16_to_cpu(nvmeq->cqes[head].status) & 1) == phase;
 693 }
 694
 695 static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag)
 696 {
 697         u16 head, phase;
 698
 699         head = nvmeq->cq_head;
 700         phase = nvmeq->cq_phase;
 701
 702         while (nvme_cqe_valid(nvmeq, head, phase)) {
 703                 struct nvme_completion cqe = nvmeq->cqes[head];
 704                 struct request *req;
 705
 706                 if (++head == nvmeq->q_depth) {
 707                         head = 0;
 708                         phase = !phase;
 709                 }
 710
 711                 if (tag && *tag == cqe.command_id)
 712                         *tag = -1;
 713
 714                 if (unlikely(cqe.command_id >= nvmeq->q_depth)) {
 715                         dev_warn(nvmeq->dev->ctrl.device,
 716                                 "invalid id %d completed on queue %d\n",
 717                                 cqe.command_id, le16_to_cpu(cqe.sq_id));
 718                         continue;
 719                 }
 720
 721                 /*
 722                  * AEN requests are special as they don't time out and can
 723                  * survive any kind of queue freeze and often don't respond to
 724                  * aborts.  We don't even bother to allocate a struct request
 725                  * for them but rather special case them here.
 726                  */
 727                 if (unlikely(nvmeq->qid == 0 &&
 728                                 cqe.command_id >= NVME_AQ_BLKMQ_DEPTH)) {
 729                         nvme_complete_async_event(nvmeq->dev, &cqe);
 730                         continue;
 731                 }
 732
 733                 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe.command_id);
 734                 if (req->cmd_type == REQ_TYPE_DRV_PRIV && req->special)
 735                         memcpy(req->special, &cqe, sizeof(cqe));
 736                 blk_mq_complete_request(req, le16_to_cpu(cqe.status) >> 1);
 737
 738         }
 739
 740         /* If the controller ignores the cq head doorbell and continuously
 741          * writes to the queue, it is theoretically possible to wrap around
 742          * the queue twice and mistakenly return IRQ_NONE.  Linux only
 743          * requires that 0.1% of your interrupts are handled, so this isn't
 744          * a big problem.
 745          */
 746         if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
 747                 return;
 748
 749         if (likely(nvmeq->cq_vector >= 0))
 750                 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
 751         nvmeq->cq_head = head;
 752         nvmeq->cq_phase = phase;
 753
 754         nvmeq->cqe_seen = 1;
 755 }
 756
 757 static void nvme_process_cq(struct nvme_queue *nvmeq)
 758 {
 759         __nvme_process_cq(nvmeq, NULL);
 760 }
 761
 762 static irqreturn_t nvme_irq(int irq, void *data)
 763 {
 764         irqreturn_t result;
 765         struct nvme_queue *nvmeq = data;
 766         spin_lock(&nvmeq->q_lock);
 767         nvme_process_cq(nvmeq);
 768         result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
 769         nvmeq->cqe_seen = 0;
 770         spin_unlock(&nvmeq->q_lock);
 771         return result;
 772 }
 773
 774 static irqreturn_t nvme_irq_check(int irq, void *data)
 775 {
 776         struct nvme_queue *nvmeq = data;
 777         if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase))
 778                 return IRQ_WAKE_THREAD;
 779         return IRQ_NONE;
 780 }
 781
 782 static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
 783 {
 784         struct nvme_queue *nvmeq = hctx->driver_data;
 785
 786         if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) {
 787                 spin_lock_irq(&nvmeq->q_lock);
 788                 __nvme_process_cq(nvmeq, &tag);
 789                 spin_unlock_irq(&nvmeq->q_lock);
 790
 791                 if (tag == -1)
 792                         return 1;
 793         }
 794
 795         return 0;
 796 }
 797
 798 static void nvme_async_event_work(struct work_struct *work)
 799 {
 800         struct nvme_dev *dev = container_of(work, struct nvme_dev, async_work);
 801         struct nvme_queue *nvmeq = dev->queues[0];
 802         struct nvme_command c;
 803
 804         memset(&c, 0, sizeof(c));
 805         c.common.opcode = nvme_admin_async_event;
 806
 807         spin_lock_irq(&nvmeq->q_lock);
 808         while (dev->ctrl.event_limit > 0) {
 809                 c.common.command_id = NVME_AQ_BLKMQ_DEPTH +
 810                         --dev->ctrl.event_limit;
 811                 __nvme_submit_cmd(nvmeq, &c);
 812         }
 813         spin_unlock_irq(&nvmeq->q_lock);
 814 }
 815
 816 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
 817 {
 818         struct nvme_command c;
 819
 820         memset(&c, 0, sizeof(c));
 821         c.delete_queue.opcode = opcode;
 822         c.delete_queue.qid = cpu_to_le16(id);
 823
 824         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 825 }
 826
 827 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
 828                                                 struct nvme_queue *nvmeq)
 829 {
 830         struct nvme_command c;
 831         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
 832
 833         /*
 834          * Note: we (ab)use the fact the the prp fields survive if no data
 835          * is attached to the request.
 836          */
 837         memset(&c, 0, sizeof(c));
 838         c.create_cq.opcode = nvme_admin_create_cq;
 839         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
 840         c.create_cq.cqid = cpu_to_le16(qid);
 841         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 842         c.create_cq.cq_flags = cpu_to_le16(flags);
 843         c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
 844
 845         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 846 }
 847
 848 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
 849                                                 struct nvme_queue *nvmeq)
 850 {
 851         struct nvme_command c;
 852         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
 853
 854         /*
 855          * Note: we (ab)use the fact the the prp fields survive if no data
 856          * is attached to the request.
 857          */
 858         memset(&c, 0, sizeof(c));
 859         c.create_sq.opcode = nvme_admin_create_sq;
 860         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
 861         c.create_sq.sqid = cpu_to_le16(qid);
 862         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 863         c.create_sq.sq_flags = cpu_to_le16(flags);
 864         c.create_sq.cqid = cpu_to_le16(qid);
 865
 866         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 867 }
 868
 869 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
 870 {
 871         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
 872 }
 873
 874 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
 875 {
 876         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
 877 }
 878
 879 static void abort_endio(struct request *req, int error)
 880 {
 881         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 882         struct nvme_queue *nvmeq = iod->nvmeq;
 883         u16 status = req->errors;
 884
 885         dev_warn(nvmeq->dev->ctrl.device, "Abort status: 0x%x", status);
 886         atomic_inc(&nvmeq->dev->ctrl.abort_limit);
 887         blk_mq_free_request(req);
 888 }
 889
 890 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
 891 {
 892         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 893         struct nvme_queue *nvmeq = iod->nvmeq;
 894         struct nvme_dev *dev = nvmeq->dev;
 895         struct request *abort_req;
 896         struct nvme_command cmd;
 897
 898         /*
 899          * Shutdown immediately if controller times out while starting. The
 900          * reset work will see the pci device disabled when it gets the forced
 901          * cancellation error. All outstanding requests are completed on
 902          * shutdown, so we return BLK_EH_HANDLED.
 903          */
 904         if (test_bit(NVME_CTRL_RESETTING, &dev->flags)) {
 905                 dev_warn(dev->ctrl.device,
 906                          "I/O %d QID %d timeout, disable controller\n",
 907                          req->tag, nvmeq->qid);
 908                 nvme_dev_disable(dev, false);
 909                 req->errors = NVME_SC_CANCELLED;
 910                 return BLK_EH_HANDLED;
 911         }
 912
 913         /*
 914          * Shutdown the controller immediately and schedule a reset if the
 915          * command was already aborted once before and still hasn't been
 916          * returned to the driver, or if this is the admin queue.
 917          */
 918         if (!nvmeq->qid || iod->aborted) {
 919                 dev_warn(dev->ctrl.device,
 920                          "I/O %d QID %d timeout, reset controller\n",
 921                          req->tag, nvmeq->qid);
 922                 nvme_dev_disable(dev, false);
 923                 queue_work(nvme_workq, &dev->reset_work);
 924
 925                 /*
 926                  * Mark the request as handled, since the inline shutdown
 927                  * forces all outstanding requests to complete.
 928                  */
 929                 req->errors = NVME_SC_CANCELLED;
 930                 return BLK_EH_HANDLED;
 931         }
 932
 933         iod->aborted = 1;
 934
 935         if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
 936                 atomic_inc(&dev->ctrl.abort_limit);
 937                 return BLK_EH_RESET_TIMER;
 938         }
 939
 940         memset(&cmd, 0, sizeof(cmd));
 941         cmd.abort.opcode = nvme_admin_abort_cmd;
 942         cmd.abort.cid = req->tag;
 943         cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
 944
 945         dev_warn(nvmeq->dev->ctrl.device,
 946                 "I/O %d QID %d timeout, aborting\n",
 947                  req->tag, nvmeq->qid);
 948
 949         abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
 950                         BLK_MQ_REQ_NOWAIT);
 951         if (IS_ERR(abort_req)) {
 952                 atomic_inc(&dev->ctrl.abort_limit);
 953                 return BLK_EH_RESET_TIMER;
 954         }
 955
 956         abort_req->timeout = ADMIN_TIMEOUT;
 957         abort_req->end_io_data = NULL;
 958         blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
 959
 960         /*
 961          * The aborted req will be completed on receiving the abort req.
 962          * We enable the timer again. If hit twice, it'll cause a device reset,
 963          * as the device then is in a faulty state.
 964          */
 965         return BLK_EH_RESET_TIMER;
 966 }
 967
 968 static void nvme_cancel_io(struct request *req, void *data, bool reserved)
 969 {
 970         int status;
 971
 972         if (!blk_mq_request_started(req))
 973                 return;
 974
 975         dev_dbg_ratelimited(((struct nvme_dev *) data)->ctrl.device,
 976                                 "Cancelling I/O %d", req->tag);
 977
 978         status = NVME_SC_ABORT_REQ;
 979         if (blk_queue_dying(req->q))
 980                 status |= NVME_SC_DNR;
 981         blk_mq_complete_request(req, status);
 982 }
 983
 984 static void nvme_free_queue(struct nvme_queue *nvmeq)
 985 {
 986         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
 987                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
 988         if (nvmeq->sq_cmds)
 989                 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
 990                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
 991         kfree(nvmeq);
 992 }
 993
 994 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
 995 {
 996         int i;
 997
 998         for (i = dev->queue_count - 1; i >= lowest; i--) {
 999                 struct nvme_queue *nvmeq = dev->queues[i];
1000                 dev->queue_count--;
1001                 dev->queues[i] = NULL;
1002                 nvme_free_queue(nvmeq);
1003         }
1004 }
1005
1006 /**
1007  * nvme_suspend_queue - put queue into suspended state
1008  * @nvmeq - queue to suspend
1009  */
1010 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1011 {
1012         int vector;
1013
1014         spin_lock_irq(&nvmeq->q_lock);
1015         if (nvmeq->cq_vector == -1) {
1016                 spin_unlock_irq(&nvmeq->q_lock);
1017                 return 1;
1018         }
1019         vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
1020         nvmeq->dev->online_queues--;
1021         nvmeq->cq_vector = -1;
1022         spin_unlock_irq(&nvmeq->q_lock);
1023
1024         if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1025                 blk_mq_stop_hw_queues(nvmeq->dev->ctrl.admin_q);
1026
1027         irq_set_affinity_hint(vector, NULL);
1028         free_irq(vector, nvmeq);
1029
1030         return 0;
1031 }
1032
1033 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
1034 {
1035         struct nvme_queue *nvmeq = dev->queues[0];
1036
1037         if (!nvmeq)
1038                 return;
1039         if (nvme_suspend_queue(nvmeq))
1040                 return;
1041
1042         if (shutdown)
1043                 nvme_shutdown_ctrl(&dev->ctrl);
1044         else
1045                 nvme_disable_ctrl(&dev->ctrl, lo_hi_readq(
1046                                                 dev->bar + NVME_REG_CAP));
1047
1048         spin_lock_irq(&nvmeq->q_lock);
1049         nvme_process_cq(nvmeq);
1050         spin_unlock_irq(&nvmeq->q_lock);
1051 }
1052
1053 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1054                                 int entry_size)
1055 {
1056         int q_depth = dev->q_depth;
1057         unsigned q_size_aligned = roundup(q_depth * entry_size,
1058                                           dev->ctrl.page_size);
1059
1060         if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1061                 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1062                 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
1063                 q_depth = div_u64(mem_per_q, entry_size);
1064
1065                 /*
1066                  * Ensure the reduced q_depth is above some threshold where it
1067                  * would be better to map queues in system memory with the
1068                  * original depth
1069                  */
1070                 if (q_depth < 64)
1071                         return -ENOMEM;
1072         }
1073
1074         return q_depth;
1075 }
1076
1077 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1078                                 int qid, int depth)
1079 {
1080         if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) {
1081                 unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth),
1082                                                       dev->ctrl.page_size);
1083                 nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset;
1084                 nvmeq->sq_cmds_io = dev->cmb + offset;
1085         } else {
1086                 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1087                                         &nvmeq->sq_dma_addr, GFP_KERNEL);
1088                 if (!nvmeq->sq_cmds)
1089                         return -ENOMEM;
1090         }
1091
1092         return 0;
1093 }
1094
1095 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1096                                                         int depth)
1097 {
1098         struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL);
1099         if (!nvmeq)
1100                 return NULL;
1101
1102         nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
1103                                           &nvmeq->cq_dma_addr, GFP_KERNEL);
1104         if (!nvmeq->cqes)
1105                 goto free_nvmeq;
1106
1107         if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
1108                 goto free_cqdma;
1109
1110         nvmeq->q_dmadev = dev->dev;
1111         nvmeq->dev = dev;
1112         snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1113                         dev->ctrl.instance, qid);
1114         spin_lock_init(&nvmeq->q_lock);
1115         nvmeq->cq_head = 0;
1116         nvmeq->cq_phase = 1;
1117         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1118         nvmeq->q_depth = depth;
1119         nvmeq->qid = qid;
1120         nvmeq->cq_vector = -1;
1121         dev->queues[qid] = nvmeq;
1122         dev->queue_count++;
1123
1124         return nvmeq;
1125
1126  free_cqdma:
1127         dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1128                                                         nvmeq->cq_dma_addr);
1129  free_nvmeq:
1130         kfree(nvmeq);
1131         return NULL;
1132 }
1133
1134 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1135                                                         const char *name)
1136 {
1137         if (use_threaded_interrupts)
1138                 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
1139                                         nvme_irq_check, nvme_irq, IRQF_SHARED,
1140                                         name, nvmeq);
1141         return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
1142                                 IRQF_SHARED, name, nvmeq);
1143 }
1144
1145 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1146 {
1147         struct nvme_dev *dev = nvmeq->dev;
1148
1149         spin_lock_irq(&nvmeq->q_lock);
1150         nvmeq->sq_tail = 0;
1151         nvmeq->cq_head = 0;
1152         nvmeq->cq_phase = 1;
1153         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1154         memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1155         dev->online_queues++;
1156         spin_unlock_irq(&nvmeq->q_lock);
1157 }
1158
1159 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1160 {
1161         struct nvme_dev *dev = nvmeq->dev;
1162         int result;
1163
1164         nvmeq->cq_vector = qid - 1;
1165         result = adapter_alloc_cq(dev, qid, nvmeq);
1166         if (result < 0)
1167                 return result;
1168
1169         result = adapter_alloc_sq(dev, qid, nvmeq);
1170         if (result < 0)
1171                 goto release_cq;
1172
1173         result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1174         if (result < 0)
1175                 goto release_sq;
1176
1177         nvme_init_queue(nvmeq, qid);
1178         return result;
1179
1180  release_sq:
1181         adapter_delete_sq(dev, qid);
1182  release_cq:
1183         adapter_delete_cq(dev, qid);
1184         return result;
1185 }
1186
1187 static struct blk_mq_ops nvme_mq_admin_ops = {
1188         .queue_rq       = nvme_queue_rq,
1189         .complete       = nvme_complete_rq,
1190         .map_queue      = blk_mq_map_queue,
1191         .init_hctx      = nvme_admin_init_hctx,
1192         .exit_hctx      = nvme_admin_exit_hctx,
1193         .init_request   = nvme_admin_init_request,
1194         .timeout        = nvme_timeout,
1195 };
1196
1197 static struct blk_mq_ops nvme_mq_ops = {
1198         .queue_rq       = nvme_queue_rq,
1199         .complete       = nvme_complete_rq,
1200         .map_queue      = blk_mq_map_queue,
1201         .init_hctx      = nvme_init_hctx,
1202         .init_request   = nvme_init_request,
1203         .timeout        = nvme_timeout,
1204         .poll           = nvme_poll,
1205 };
1206
1207 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1208 {
1209         if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1210                 /*
1211                  * If the controller was reset during removal, it's possible
1212                  * user requests may be waiting on a stopped queue. Start the
1213                  * queue to flush these to completion.
1214                  */
1215                 blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true);
1216                 blk_cleanup_queue(dev->ctrl.admin_q);
1217                 blk_mq_free_tag_set(&dev->admin_tagset);
1218         }
1219 }
1220
1221 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1222 {
1223         if (!dev->ctrl.admin_q) {
1224                 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1225                 dev->admin_tagset.nr_hw_queues = 1;
1226
1227                 /*
1228                  * Subtract one to leave an empty queue entry for 'Full Queue'
1229                  * condition. See NVM-Express 1.2 specification, section 4.1.2.
1230                  */
1231                 dev->admin_tagset.queue_depth = NVME_AQ_BLKMQ_DEPTH - 1;
1232                 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1233                 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1234                 dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
1235                 dev->admin_tagset.driver_data = dev;
1236
1237                 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1238                         return -ENOMEM;
1239
1240                 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1241                 if (IS_ERR(dev->ctrl.admin_q)) {
1242                         blk_mq_free_tag_set(&dev->admin_tagset);
1243                         return -ENOMEM;
1244                 }
1245                 if (!blk_get_queue(dev->ctrl.admin_q)) {
1246                         nvme_dev_remove_admin(dev);
1247                         dev->ctrl.admin_q = NULL;
1248                         return -ENODEV;
1249                 }
1250         } else
1251                 blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true);
1252
1253         return 0;
1254 }
1255
1256 static int nvme_configure_admin_queue(struct nvme_dev *dev)
1257 {
1258         int result;
1259         u32 aqa;
1260         u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1261         struct nvme_queue *nvmeq;
1262
1263         dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1) ?
1264                                                 NVME_CAP_NSSRC(cap) : 0;
1265
1266         if (dev->subsystem &&
1267             (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1268                 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1269
1270         result = nvme_disable_ctrl(&dev->ctrl, cap);
1271         if (result < 0)
1272                 return result;
1273
1274         nvmeq = dev->queues[0];
1275         if (!nvmeq) {
1276                 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1277                 if (!nvmeq)
1278                         return -ENOMEM;
1279         }
1280
1281         aqa = nvmeq->q_depth - 1;
1282         aqa |= aqa << 16;
1283
1284         writel(aqa, dev->bar + NVME_REG_AQA);
1285         lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1286         lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1287
1288         result = nvme_enable_ctrl(&dev->ctrl, cap);
1289         if (result)
1290                 goto free_nvmeq;
1291
1292         nvmeq->cq_vector = 0;
1293         result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1294         if (result) {
1295                 nvmeq->cq_vector = -1;
1296                 goto free_nvmeq;
1297         }
1298
1299         return result;
1300
1301  free_nvmeq:
1302         nvme_free_queues(dev, 0);
1303         return result;
1304 }
1305
1306 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1307 {
1308
1309         /* If true, indicates loss of adapter communication, possibly by a
1310          * NVMe Subsystem reset.
1311          */
1312         bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1313
1314         /* If there is a reset ongoing, we shouldn't reset again. */
1315         if (work_busy(&dev->reset_work))
1316                 return false;
1317
1318         /* We shouldn't reset unless the controller is on fatal error state
1319          * _or_ if we lost the communication with it.
1320          */
1321         if (!(csts & NVME_CSTS_CFS) && !nssro)
1322                 return false;
1323
1324         /* If PCI error recovery process is happening, we cannot reset or
1325          * the recovery mechanism will surely fail.
1326          */
1327         if (pci_channel_offline(to_pci_dev(dev->dev)))
1328                 return false;
1329
1330         return true;
1331 }
1332
1333 static void nvme_watchdog_timer(unsigned long data)
1334 {
1335         struct nvme_dev *dev = (struct nvme_dev *)data;
1336         u32 csts = readl(dev->bar + NVME_REG_CSTS);
1337
1338         /* Skip controllers under certain specific conditions. */
1339         if (nvme_should_reset(dev, csts)) {
1340                 if (queue_work(nvme_workq, &dev->reset_work))
1341                         dev_warn(dev->dev,
1342                                 "Failed status: 0x%x, reset controller.\n",
1343                                 csts);
1344                 return;
1345         }
1346
1347         mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ));
1348 }
1349
1350 static int nvme_create_io_queues(struct nvme_dev *dev)
1351 {
1352         unsigned i, max;
1353         int ret = 0;
1354
1355         for (i = dev->queue_count; i <= dev->max_qid; i++) {
1356                 if (!nvme_alloc_queue(dev, i, dev->q_depth)) {
1357                         ret = -ENOMEM;
1358                         break;
1359                 }
1360         }
1361
1362         max = min(dev->max_qid, dev->queue_count - 1);
1363         for (i = dev->online_queues; i <= max; i++) {
1364                 ret = nvme_create_queue(dev->queues[i], i);
1365                 if (ret) {
1366                         nvme_free_queues(dev, i);
1367                         break;
1368                 }
1369         }
1370
1371         /*
1372          * Ignore failing Create SQ/CQ commands, we can continue with less
1373          * than the desired aount of queues, and even a controller without
1374          * I/O queues an still be used to issue admin commands.  This might
1375          * be useful to upgrade a buggy firmware for example.
1376          */
1377         return ret >= 0 ? 0 : ret;
1378 }
1379
1380 static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
1381 {
1382         u64 szu, size, offset;
1383         u32 cmbloc;
1384         resource_size_t bar_size;
1385         struct pci_dev *pdev = to_pci_dev(dev->dev);
1386         void __iomem *cmb;
1387         dma_addr_t dma_addr;
1388
1389         if (!use_cmb_sqes)
1390                 return NULL;
1391
1392         dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1393         if (!(NVME_CMB_SZ(dev->cmbsz)))
1394                 return NULL;
1395
1396         cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1397
1398         szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz));
1399         size = szu * NVME_CMB_SZ(dev->cmbsz);
1400         offset = szu * NVME_CMB_OFST(cmbloc);
1401         bar_size = pci_resource_len(pdev, NVME_CMB_BIR(cmbloc));
1402
1403         if (offset > bar_size)
1404                 return NULL;
1405
1406         /*
1407          * Controllers may support a CMB size larger than their BAR,
1408          * for example, due to being behind a bridge. Reduce the CMB to
1409          * the reported size of the BAR
1410          */
1411         if (size > bar_size - offset)
1412                 size = bar_size - offset;
1413
1414         dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(cmbloc)) + offset;
1415         cmb = ioremap_wc(dma_addr, size);
1416         if (!cmb)
1417                 return NULL;
1418
1419         dev->cmb_dma_addr = dma_addr;
1420         dev->cmb_size = size;
1421         return cmb;
1422 }
1423
1424 static inline void nvme_release_cmb(struct nvme_dev *dev)
1425 {
1426         if (dev->cmb) {
1427                 iounmap(dev->cmb);
1428                 dev->cmb = NULL;
1429         }
1430 }
1431
1432 static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1433 {
1434         return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
1435 }
1436
1437 static int nvme_setup_io_queues(struct nvme_dev *dev)
1438 {
1439         struct nvme_queue *adminq = dev->queues[0];
1440         struct pci_dev *pdev = to_pci_dev(dev->dev);
1441         int result, i, vecs, nr_io_queues, size;
1442
1443         nr_io_queues = num_possible_cpus();
1444         result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
1445         if (result < 0)
1446                 return result;
1447
1448         /*
1449          * Degraded controllers might return an error when setting the queue
1450          * count.  We still want to be able to bring them online and offer
1451          * access to the admin queue, as that might be only way to fix them up.
1452          */
1453         if (result > 0) {
1454                 dev_err(dev->ctrl.device,
1455                         "Could not set queue count (%d)\n", result);
1456                 return 0;
1457         }
1458
1459         if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) {
1460                 result = nvme_cmb_qdepth(dev, nr_io_queues,
1461                                 sizeof(struct nvme_command));
1462                 if (result > 0)
1463                         dev->q_depth = result;
1464                 else
1465                         nvme_release_cmb(dev);
1466         }
1467
1468         size = db_bar_size(dev, nr_io_queues);
1469         if (size > 8192) {
1470                 iounmap(dev->bar);
1471                 do {
1472                         dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1473                         if (dev->bar)
1474                                 break;
1475                         if (!--nr_io_queues)
1476                                 return -ENOMEM;
1477                         size = db_bar_size(dev, nr_io_queues);
1478                 } while (1);
1479                 dev->dbs = dev->bar + 4096;
1480                 adminq->q_db = dev->dbs;
1481         }
1482
1483         /* Deregister the admin queue's interrupt */
1484         free_irq(dev->entry[0].vector, adminq);
1485
1486         /*
1487          * If we enable msix early due to not intx, disable it again before
1488          * setting up the full range we need.
1489          */
1490         if (pdev->msi_enabled)
1491                 pci_disable_msi(pdev);
1492         else if (pdev->msix_enabled)
1493                 pci_disable_msix(pdev);
1494
1495         for (i = 0; i < nr_io_queues; i++)
1496                 dev->entry[i].entry = i;
1497         vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues);
1498         if (vecs < 0) {
1499                 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32));
1500                 if (vecs < 0) {
1501                         vecs = 1;
1502                 } else {
1503                         for (i = 0; i < vecs; i++)
1504                                 dev->entry[i].vector = i + pdev->irq;
1505                 }
1506         }
1507
1508         /*
1509          * Should investigate if there's a performance win from allocating
1510          * more queues than interrupt vectors; it might allow the submission
1511          * path to scale better, even if the receive path is limited by the
1512          * number of interrupts.
1513          */
1514         nr_io_queues = vecs;
1515         dev->max_qid = nr_io_queues;
1516
1517         result = queue_request_irq(dev, adminq, adminq->irqname);
1518         if (result) {
1519                 adminq->cq_vector = -1;
1520                 goto free_queues;
1521         }
1522         return nvme_create_io_queues(dev);
1523
1524  free_queues:
1525         nvme_free_queues(dev, 1);
1526         return result;
1527 }
1528
1529 static void nvme_set_irq_hints(struct nvme_dev *dev)
1530 {
1531         struct nvme_queue *nvmeq;
1532         int i;
1533
1534         for (i = 0; i < dev->online_queues; i++) {
1535                 nvmeq = dev->queues[i];
1536
1537                 if (!nvmeq->tags || !(*nvmeq->tags))
1538                         continue;
1539
1540                 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
1541                                         blk_mq_tags_cpumask(*nvmeq->tags));
1542         }
1543 }
1544
1545 static void nvme_dev_scan(struct work_struct *work)
1546 {
1547         struct nvme_dev *dev = container_of(work, struct nvme_dev, scan_work);
1548
1549         if (!dev->tagset.tags)
1550                 return;
1551         nvme_scan_namespaces(&dev->ctrl);
1552         nvme_set_irq_hints(dev);
1553 }
1554
1555 static void nvme_del_queue_end(struct request *req, int error)
1556 {
1557         struct nvme_queue *nvmeq = req->end_io_data;
1558
1559         blk_mq_free_request(req);
1560         complete(&nvmeq->dev->ioq_wait);
1561 }
1562
1563 static void nvme_del_cq_end(struct request *req, int error)
1564 {
1565         struct nvme_queue *nvmeq = req->end_io_data;
1566
1567         if (!error) {
1568                 unsigned long flags;
1569
1570                 /*
1571                  * We might be called with the AQ q_lock held
1572                  * and the I/O queue q_lock should always
1573                  * nest inside the AQ one.
1574                  */
1575                 spin_lock_irqsave_nested(&nvmeq->q_lock, flags,
1576                                         SINGLE_DEPTH_NESTING);
1577                 nvme_process_cq(nvmeq);
1578                 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
1579         }
1580
1581         nvme_del_queue_end(req, error);
1582 }
1583
1584 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
1585 {
1586         struct request_queue *q = nvmeq->dev->ctrl.admin_q;
1587         struct request *req;
1588         struct nvme_command cmd;
1589
1590         memset(&cmd, 0, sizeof(cmd));
1591         cmd.delete_queue.opcode = opcode;
1592         cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
1593
1594         req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT);
1595         if (IS_ERR(req))
1596                 return PTR_ERR(req);
1597
1598         req->timeout = ADMIN_TIMEOUT;
1599         req->end_io_data = nvmeq;
1600
1601         blk_execute_rq_nowait(q, NULL, req, false,
1602                         opcode == nvme_admin_delete_cq ?
1603                                 nvme_del_cq_end : nvme_del_queue_end);
1604         return 0;
1605 }
1606
1607 static void nvme_disable_io_queues(struct nvme_dev *dev)
1608 {
1609         int pass;
1610         unsigned long timeout;
1611         u8 opcode = nvme_admin_delete_sq;
1612
1613         for (pass = 0; pass < 2; pass++) {
1614                 int sent = 0, i = dev->queue_count - 1;
1615
1616                 reinit_completion(&dev->ioq_wait);
1617  retry:
1618                 timeout = ADMIN_TIMEOUT;
1619                 for (; i > 0; i--) {
1620                         struct nvme_queue *nvmeq = dev->queues[i];
1621
1622                         if (!pass)
1623                                 nvme_suspend_queue(nvmeq);
1624                         if (nvme_delete_queue(nvmeq, opcode))
1625                                 break;
1626                         ++sent;
1627                 }
1628                 while (sent--) {
1629                         timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout);
1630                         if (timeout == 0)
1631                                 return;
1632                         if (i)
1633                                 goto retry;
1634                 }
1635                 opcode = nvme_admin_delete_cq;
1636         }
1637 }
1638
1639 /*
1640  * Return: error value if an error occurred setting up the queues or calling
1641  * Identify Device.  0 if these succeeded, even if adding some of the
1642  * namespaces failed.  At the moment, these failures are silent.  TBD which
1643  * failures should be reported.
1644  */
1645 static int nvme_dev_add(struct nvme_dev *dev)
1646 {
1647         if (!dev->ctrl.tagset) {
1648                 dev->tagset.ops = &nvme_mq_ops;
1649                 dev->tagset.nr_hw_queues = dev->online_queues - 1;
1650                 dev->tagset.timeout = NVME_IO_TIMEOUT;
1651                 dev->tagset.numa_node = dev_to_node(dev->dev);
1652                 dev->tagset.queue_depth =
1653                                 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
1654                 dev->tagset.cmd_size = nvme_cmd_size(dev);
1655                 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
1656                 dev->tagset.driver_data = dev;
1657
1658                 if (blk_mq_alloc_tag_set(&dev->tagset))
1659                         return 0;
1660                 dev->ctrl.tagset = &dev->tagset;
1661         } else {
1662                 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
1663
1664                 /* Free previously allocated queues that are no longer usable */
1665                 nvme_free_queues(dev, dev->online_queues);
1666         }
1667
1668         nvme_queue_scan(dev);
1669         return 0;
1670 }
1671
1672 static int nvme_pci_enable(struct nvme_dev *dev)
1673 {
1674         u64 cap;
1675         int result = -ENOMEM;
1676         struct pci_dev *pdev = to_pci_dev(dev->dev);
1677
1678         if (pci_enable_device_mem(pdev))
1679                 return result;
1680
1681         pci_set_master(pdev);
1682
1683         if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
1684             dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
1685                 goto disable;
1686
1687         if (readl(dev->bar + NVME_REG_CSTS) == -1) {
1688                 result = -ENODEV;
1689                 goto disable;
1690         }
1691
1692         /*
1693          * Some devices and/or platforms don't advertise or work with INTx
1694          * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
1695          * adjust this later.
1696          */
1697         if (pci_enable_msix(pdev, dev->entry, 1)) {
1698                 pci_enable_msi(pdev);
1699                 dev->entry[0].vector = pdev->irq;
1700         }
1701
1702         if (!dev->entry[0].vector) {
1703                 result = -ENODEV;
1704                 goto disable;
1705         }
1706
1707         cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1708
1709         dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
1710         dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
1711         dev->dbs = dev->bar + 4096;
1712
1713         /*
1714          * Temporary fix for the Apple controller found in the MacBook8,1 and
1715          * some MacBook7,1 to avoid controller resets and data loss.
1716          */
1717         if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
1718                 dev->q_depth = 2;
1719                 dev_warn(dev->dev, "detected Apple NVMe controller, set "
1720                         "queue depth=%u to work around controller resets\n",
1721                         dev->q_depth);
1722         }
1723
1724         if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2))
1725                 dev->cmb = nvme_map_cmb(dev);
1726
1727         pci_enable_pcie_error_reporting(pdev);
1728         pci_save_state(pdev);
1729         return 0;
1730
1731  disable:
1732         pci_disable_device(pdev);
1733         return result;
1734 }
1735
1736 static void nvme_dev_unmap(struct nvme_dev *dev)
1737 {
1738         if (dev->bar)
1739                 iounmap(dev->bar);
1740         pci_release_regions(to_pci_dev(dev->dev));
1741 }
1742
1743 static void nvme_pci_disable(struct nvme_dev *dev)
1744 {
1745         struct pci_dev *pdev = to_pci_dev(dev->dev);
1746
1747         if (pdev->msi_enabled)
1748                 pci_disable_msi(pdev);
1749         else if (pdev->msix_enabled)
1750                 pci_disable_msix(pdev);
1751
1752         if (pci_is_enabled(pdev)) {
1753                 pci_disable_pcie_error_reporting(pdev);
1754                 pci_disable_device(pdev);
1755         }
1756 }
1757
1758 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
1759 {
1760         int i;
1761         u32 csts = -1;
1762
1763         del_timer_sync(&dev->watchdog_timer);
1764
1765         mutex_lock(&dev->shutdown_lock);
1766         if (pci_is_enabled(to_pci_dev(dev->dev))) {
1767                 nvme_stop_queues(&dev->ctrl);
1768                 csts = readl(dev->bar + NVME_REG_CSTS);
1769         }
1770         if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) {
1771                 for (i = dev->queue_count - 1; i >= 0; i--) {
1772                         struct nvme_queue *nvmeq = dev->queues[i];
1773                         nvme_suspend_queue(nvmeq);
1774                 }
1775         } else {
1776                 nvme_disable_io_queues(dev);
1777                 nvme_disable_admin_queue(dev, shutdown);
1778         }
1779         nvme_pci_disable(dev);
1780
1781         blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_io, dev);
1782         blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_io, dev);
1783         mutex_unlock(&dev->shutdown_lock);
1784 }
1785
1786 static int nvme_setup_prp_pools(struct nvme_dev *dev)
1787 {
1788         dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
1789                                                 PAGE_SIZE, PAGE_SIZE, 0);
1790         if (!dev->prp_page_pool)
1791                 return -ENOMEM;
1792
1793         /* Optimisation for I/Os between 4k and 128k */
1794         dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
1795                                                 256, 256, 0);
1796         if (!dev->prp_small_pool) {
1797                 dma_pool_destroy(dev->prp_page_pool);
1798                 return -ENOMEM;
1799         }
1800         return 0;
1801 }
1802
1803 static void nvme_release_prp_pools(struct nvme_dev *dev)
1804 {
1805         dma_pool_destroy(dev->prp_page_pool);
1806         dma_pool_destroy(dev->prp_small_pool);
1807 }
1808
1809 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
1810 {
1811         struct nvme_dev *dev = to_nvme_dev(ctrl);
1812
1813         put_device(dev->dev);
1814         if (dev->tagset.tags)
1815                 blk_mq_free_tag_set(&dev->tagset);
1816         if (dev->ctrl.admin_q)
1817                 blk_put_queue(dev->ctrl.admin_q);
1818         kfree(dev->queues);
1819         kfree(dev->entry);
1820         kfree(dev);
1821 }
1822
1823 static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
1824 {
1825         dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
1826
1827         kref_get(&dev->ctrl.kref);
1828         nvme_dev_disable(dev, false);
1829         if (!schedule_work(&dev->remove_work))
1830                 nvme_put_ctrl(&dev->ctrl);
1831 }
1832
1833 static void nvme_reset_work(struct work_struct *work)
1834 {
1835         struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
1836         int result = -ENODEV;
1837
1838         if (WARN_ON(test_bit(NVME_CTRL_RESETTING, &dev->flags)))
1839                 goto out;
1840
1841         /*
1842          * If we're called to reset a live controller first shut it down before
1843          * moving on.
1844          */
1845         if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
1846                 nvme_dev_disable(dev, false);
1847
1848         set_bit(NVME_CTRL_RESETTING, &dev->flags);
1849
1850         result = nvme_pci_enable(dev);
1851         if (result)
1852                 goto out;
1853
1854         result = nvme_configure_admin_queue(dev);
1855         if (result)
1856                 goto out;
1857
1858         nvme_init_queue(dev->queues[0], 0);
1859         result = nvme_alloc_admin_tags(dev);
1860         if (result)
1861                 goto out;
1862
1863         result = nvme_init_identify(&dev->ctrl);
1864         if (result)
1865                 goto out;
1866
1867         result = nvme_setup_io_queues(dev);
1868         if (result)
1869                 goto out;
1870
1871         /*
1872          * A controller that can not execute IO typically requires user
1873          * intervention to correct. For such degraded controllers, the driver
1874          * should not submit commands the user did not request, so skip
1875          * registering for asynchronous event notification on this condition.
1876          */
1877         if (dev->online_queues > 1) {
1878                 dev->ctrl.event_limit = NVME_NR_AEN_COMMANDS;
1879                 queue_work(nvme_workq, &dev->async_work);
1880         }
1881
1882         mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ));
1883
1884         /*
1885          * Keep the controller around but remove all namespaces if we don't have
1886          * any working I/O queue.
1887          */
1888         if (dev->online_queues < 2) {
1889                 dev_warn(dev->ctrl.device, "IO queues not created\n");
1890                 nvme_kill_queues(&dev->ctrl);
1891                 nvme_remove_namespaces(&dev->ctrl);
1892         } else {
1893                 nvme_start_queues(&dev->ctrl);
1894                 nvme_dev_add(dev);
1895         }
1896
1897         clear_bit(NVME_CTRL_RESETTING, &dev->flags);
1898         return;
1899
1900  out:
1901         nvme_remove_dead_ctrl(dev, result);
1902 }
1903
1904 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
1905 {
1906         struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
1907         struct pci_dev *pdev = to_pci_dev(dev->dev);
1908
1909         nvme_kill_queues(&dev->ctrl);
1910         if (pci_get_drvdata(pdev))
1911                 pci_stop_and_remove_bus_device_locked(pdev);
1912         nvme_put_ctrl(&dev->ctrl);
1913 }
1914
1915 static int nvme_reset(struct nvme_dev *dev)
1916 {
1917         if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q))
1918                 return -ENODEV;
1919
1920         if (!queue_work(nvme_workq, &dev->reset_work))
1921                 return -EBUSY;
1922
1923         flush_work(&dev->reset_work);
1924         return 0;
1925 }
1926
1927 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
1928 {
1929         *val = readl(to_nvme_dev(ctrl)->bar + off);
1930         return 0;
1931 }
1932
1933 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
1934 {
1935         writel(val, to_nvme_dev(ctrl)->bar + off);
1936         return 0;
1937 }
1938
1939 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
1940 {
1941         *val = readq(to_nvme_dev(ctrl)->bar + off);
1942         return 0;
1943 }
1944
1945 static int nvme_pci_reset_ctrl(struct nvme_ctrl *ctrl)
1946 {
1947         return nvme_reset(to_nvme_dev(ctrl));
1948 }
1949
1950 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1951         .module                 = THIS_MODULE,
1952         .reg_read32             = nvme_pci_reg_read32,
1953         .reg_write32            = nvme_pci_reg_write32,
1954         .reg_read64             = nvme_pci_reg_read64,
1955         .reset_ctrl             = nvme_pci_reset_ctrl,
1956         .free_ctrl              = nvme_pci_free_ctrl,
1957 };
1958
1959 static int nvme_dev_map(struct nvme_dev *dev)
1960 {
1961         int bars;
1962         struct pci_dev *pdev = to_pci_dev(dev->dev);
1963
1964         bars = pci_select_bars(pdev, IORESOURCE_MEM);
1965         if (!bars)
1966                 return -ENODEV;
1967         if (pci_request_selected_regions(pdev, bars, "nvme"))
1968                 return -ENODEV;
1969
1970         dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1971         if (!dev->bar)
1972                 goto release;
1973
1974        return 0;
1975   release:
1976        pci_release_regions(pdev);
1977        return -ENODEV;
1978 }
1979
1980 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1981 {
1982         int node, result = -ENOMEM;
1983         struct nvme_dev *dev;
1984
1985         node = dev_to_node(&pdev->dev);
1986         if (node == NUMA_NO_NODE)
1987                 set_dev_node(&pdev->dev, 0);
1988
1989         dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
1990         if (!dev)
1991                 return -ENOMEM;
1992         dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry),
1993                                                         GFP_KERNEL, node);
1994         if (!dev->entry)
1995                 goto free;
1996         dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
1997                                                         GFP_KERNEL, node);
1998         if (!dev->queues)
1999                 goto free;
2000
2001         dev->dev = get_device(&pdev->dev);
2002         pci_set_drvdata(pdev, dev);
2003
2004         result = nvme_dev_map(dev);
2005         if (result)
2006                 goto free;
2007
2008         INIT_WORK(&dev->scan_work, nvme_dev_scan);
2009         INIT_WORK(&dev->reset_work, nvme_reset_work);
2010         INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
2011         INIT_WORK(&dev->async_work, nvme_async_event_work);
2012         setup_timer(&dev->watchdog_timer, nvme_watchdog_timer,
2013                 (unsigned long)dev);
2014         mutex_init(&dev->shutdown_lock);
2015         init_completion(&dev->ioq_wait);
2016
2017         result = nvme_setup_prp_pools(dev);
2018         if (result)
2019                 goto put_pci;
2020
2021         result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2022                         id->driver_data);
2023         if (result)
2024                 goto release_pools;
2025
2026         dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2027
2028         queue_work(nvme_workq, &dev->reset_work);
2029         return 0;
2030
2031  release_pools:
2032         nvme_release_prp_pools(dev);
2033  put_pci:
2034         put_device(dev->dev);
2035         nvme_dev_unmap(dev);
2036  free:
2037         kfree(dev->queues);
2038         kfree(dev->entry);
2039         kfree(dev);
2040         return result;
2041 }
2042
2043 static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
2044 {
2045         struct nvme_dev *dev = pci_get_drvdata(pdev);
2046
2047         if (prepare)
2048                 nvme_dev_disable(dev, false);
2049         else
2050                 queue_work(nvme_workq, &dev->reset_work);
2051 }
2052
2053 static void nvme_shutdown(struct pci_dev *pdev)
2054 {
2055         struct nvme_dev *dev = pci_get_drvdata(pdev);
2056         nvme_dev_disable(dev, true);
2057 }
2058
2059 /*
2060  * The driver's remove may be called on a device in a partially initialized
2061  * state. This function must not have any dependencies on the device state in
2062  * order to proceed.
2063  */
2064 static void nvme_remove(struct pci_dev *pdev)
2065 {
2066         struct nvme_dev *dev = pci_get_drvdata(pdev);
2067
2068         del_timer_sync(&dev->watchdog_timer);
2069
2070         set_bit(NVME_CTRL_REMOVING, &dev->flags);
2071         pci_set_drvdata(pdev, NULL);
2072         flush_work(&dev->async_work);
2073         flush_work(&dev->scan_work);
2074         nvme_remove_namespaces(&dev->ctrl);
2075         nvme_uninit_ctrl(&dev->ctrl);
2076         nvme_dev_disable(dev, true);
2077         flush_work(&dev->reset_work);
2078         nvme_dev_remove_admin(dev);
2079         nvme_free_queues(dev, 0);
2080         nvme_release_cmb(dev);
2081         nvme_release_prp_pools(dev);
2082         nvme_dev_unmap(dev);
2083         nvme_put_ctrl(&dev->ctrl);
2084 }
2085
2086 #ifdef CONFIG_PM_SLEEP
2087 static int nvme_suspend(struct device *dev)
2088 {
2089         struct pci_dev *pdev = to_pci_dev(dev);
2090         struct nvme_dev *ndev = pci_get_drvdata(pdev);
2091
2092         nvme_dev_disable(ndev, true);
2093         return 0;
2094 }
2095
2096 static int nvme_resume(struct device *dev)
2097 {
2098         struct pci_dev *pdev = to_pci_dev(dev);
2099         struct nvme_dev *ndev = pci_get_drvdata(pdev);
2100
2101         queue_work(nvme_workq, &ndev->reset_work);
2102         return 0;
2103 }
2104 #endif
2105
2106 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
2107
2108 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2109                                                 pci_channel_state_t state)
2110 {
2111         struct nvme_dev *dev = pci_get_drvdata(pdev);
2112
2113         /*
2114          * A frozen channel requires a reset. When detected, this method will
2115          * shutdown the controller to quiesce. The controller will be restarted
2116          * after the slot reset through driver's slot_reset callback.
2117          */
2118         dev_warn(dev->ctrl.device, "error detected: state:%d\n", state);
2119         switch (state) {
2120         case pci_channel_io_normal:
2121                 return PCI_ERS_RESULT_CAN_RECOVER;
2122         case pci_channel_io_frozen:
2123                 nvme_dev_disable(dev, false);
2124                 return PCI_ERS_RESULT_NEED_RESET;
2125         case pci_channel_io_perm_failure:
2126                 return PCI_ERS_RESULT_DISCONNECT;
2127         }
2128         return PCI_ERS_RESULT_NEED_RESET;
2129 }
2130
2131 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2132 {
2133         struct nvme_dev *dev = pci_get_drvdata(pdev);
2134
2135         dev_info(dev->ctrl.device, "restart after slot reset\n");
2136         pci_restore_state(pdev);
2137         queue_work(nvme_workq, &dev->reset_work);
2138         return PCI_ERS_RESULT_RECOVERED;
2139 }
2140
2141 static void nvme_error_resume(struct pci_dev *pdev)
2142 {
2143         pci_cleanup_aer_uncorrect_error_status(pdev);
2144 }
2145
2146 static const struct pci_error_handlers nvme_err_handler = {
2147         .error_detected = nvme_error_detected,
2148         .slot_reset     = nvme_slot_reset,
2149         .resume         = nvme_error_resume,
2150         .reset_notify   = nvme_reset_notify,
2151 };
2152
2153 /* Move to pci_ids.h later */
2154 #define PCI_CLASS_STORAGE_EXPRESS       0x010802
2155
2156 static const struct pci_device_id nvme_id_table[] = {
2157         { PCI_VDEVICE(INTEL, 0x0953),
2158                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2159                                 NVME_QUIRK_DISCARD_ZEROES, },
2160         { PCI_VDEVICE(INTEL, 0x5845),   /* Qemu emulated controller */
2161                 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
2162         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2163         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
2164         { 0, }
2165 };
2166 MODULE_DEVICE_TABLE(pci, nvme_id_table);
2167
2168 static struct pci_driver nvme_driver = {
2169         .name           = "nvme",
2170         .id_table       = nvme_id_table,
2171         .probe          = nvme_probe,
2172         .remove         = nvme_remove,
2173         .shutdown       = nvme_shutdown,
2174         .driver         = {
2175                 .pm     = &nvme_dev_pm_ops,
2176         },
2177         .err_handler    = &nvme_err_handler,
2178 };
2179
2180 static int __init nvme_init(void)
2181 {
2182         int result;
2183
2184         nvme_workq = alloc_workqueue("nvme", WQ_UNBOUND | WQ_MEM_RECLAIM, 0);
2185         if (!nvme_workq)
2186                 return -ENOMEM;
2187
2188         result = pci_register_driver(&nvme_driver);
2189         if (result)
2190                 destroy_workqueue(nvme_workq);
2191         return result;
2192 }
2193
2194 static void __exit nvme_exit(void)
2195 {
2196         pci_unregister_driver(&nvme_driver);
2197         destroy_workqueue(nvme_workq);
2198         _nvme_check_size();
2199 }
2200
2201 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2202 MODULE_LICENSE("GPL");
2203 MODULE_VERSION("1.0");
2204 module_init(nvme_init);
2205 module_exit(nvme_exit);