drivers/net/ethernet/ti/cpsw.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Texas Instruments Ethernet Switch Driver
   4  *
   5  * Copyright (C) 2012 Texas Instruments
   6  *
   7  */
   8
   9 #include <linux/kernel.h>
  10 #include <linux/io.h>
  11 #include <linux/clk.h>
  12 #include <linux/timer.h>
  13 #include <linux/module.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/irqreturn.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/if_ether.h>
  18 #include <linux/etherdevice.h>
  19 #include <linux/netdevice.h>
  20 #include <linux/net_tstamp.h>
  21 #include <linux/phy.h>
  22 #include <linux/phy/phy.h>
  23 #include <linux/workqueue.h>
  24 #include <linux/delay.h>
  25 #include <linux/pm_runtime.h>
  26 #include <linux/gpio/consumer.h>
  27 #include <linux/of.h>
  28 #include <linux/of_mdio.h>
  29 #include <linux/of_net.h>
  30 #include <linux/of_device.h>
  31 #include <linux/if_vlan.h>
  32 #include <linux/kmemleak.h>
  33 #include <linux/sys_soc.h>
  34
  35 #include <linux/pinctrl/consumer.h>
  36 #include <net/pkt_cls.h>
  37
  38 #include "cpsw.h"
  39 #include "cpsw_ale.h"
  40 #include "cpts.h"
  41 #include "davinci_cpdma.h"
  42
  43 #include <net/pkt_sched.h>
  44
  45 #define CPSW_DEBUG      (NETIF_MSG_HW           | NETIF_MSG_WOL         | \
  46                          NETIF_MSG_DRV          | NETIF_MSG_LINK        | \
  47                          NETIF_MSG_IFUP         | NETIF_MSG_INTR        | \
  48                          NETIF_MSG_PROBE        | NETIF_MSG_TIMER       | \
  49                          NETIF_MSG_IFDOWN       | NETIF_MSG_RX_ERR      | \
  50                          NETIF_MSG_TX_ERR       | NETIF_MSG_TX_DONE     | \
  51                          NETIF_MSG_PKTDATA      | NETIF_MSG_TX_QUEUED   | \
  52                          NETIF_MSG_RX_STATUS)
  53
  54 #define cpsw_info(priv, type, format, ...)              \
  55 do {                                                            \
  56         if (netif_msg_##type(priv) && net_ratelimit())          \
  57                 dev_info(priv->dev, format, ## __VA_ARGS__);    \
  58 } while (0)
  59
  60 #define cpsw_err(priv, type, format, ...)               \
  61 do {                                                            \
  62         if (netif_msg_##type(priv) && net_ratelimit())          \
  63                 dev_err(priv->dev, format, ## __VA_ARGS__);     \
  64 } while (0)
  65
  66 #define cpsw_dbg(priv, type, format, ...)               \
  67 do {                                                            \
  68         if (netif_msg_##type(priv) && net_ratelimit())          \
  69                 dev_dbg(priv->dev, format, ## __VA_ARGS__);     \
  70 } while (0)
  71
  72 #define cpsw_notice(priv, type, format, ...)            \
  73 do {                                                            \
  74         if (netif_msg_##type(priv) && net_ratelimit())          \
  75                 dev_notice(priv->dev, format, ## __VA_ARGS__);  \
  76 } while (0)
  77
  78 #define ALE_ALL_PORTS           0x7
  79
  80 #define CPSW_MAJOR_VERSION(reg)         (reg >> 8 & 0x7)
  81 #define CPSW_MINOR_VERSION(reg)         (reg & 0xff)
  82 #define CPSW_RTL_VERSION(reg)           ((reg >> 11) & 0x1f)
  83
  84 #define CPSW_VERSION_1          0x19010a
  85 #define CPSW_VERSION_2          0x19010c
  86 #define CPSW_VERSION_3          0x19010f
  87 #define CPSW_VERSION_4          0x190112
  88
  89 #define HOST_PORT_NUM           0
  90 #define CPSW_ALE_PORTS_NUM      3
  91 #define SLIVER_SIZE             0x40
  92
  93 #define CPSW1_HOST_PORT_OFFSET  0x028
  94 #define CPSW1_SLAVE_OFFSET      0x050
  95 #define CPSW1_SLAVE_SIZE        0x040
  96 #define CPSW1_CPDMA_OFFSET      0x100
  97 #define CPSW1_STATERAM_OFFSET   0x200
  98 #define CPSW1_HW_STATS          0x400
  99 #define CPSW1_CPTS_OFFSET       0x500
 100 #define CPSW1_ALE_OFFSET        0x600
 101 #define CPSW1_SLIVER_OFFSET     0x700
 102
 103 #define CPSW2_HOST_PORT_OFFSET  0x108
 104 #define CPSW2_SLAVE_OFFSET      0x200
 105 #define CPSW2_SLAVE_SIZE        0x100
 106 #define CPSW2_CPDMA_OFFSET      0x800
 107 #define CPSW2_HW_STATS          0x900
 108 #define CPSW2_STATERAM_OFFSET   0xa00
 109 #define CPSW2_CPTS_OFFSET       0xc00
 110 #define CPSW2_ALE_OFFSET        0xd00
 111 #define CPSW2_SLIVER_OFFSET     0xd80
 112 #define CPSW2_BD_OFFSET         0x2000
 113
 114 #define CPDMA_RXTHRESH          0x0c0
 115 #define CPDMA_RXFREE            0x0e0
 116 #define CPDMA_TXHDP             0x00
 117 #define CPDMA_RXHDP             0x20
 118 #define CPDMA_TXCP              0x40
 119 #define CPDMA_RXCP              0x60
 120
 121 #define CPSW_POLL_WEIGHT        64
 122 #define CPSW_RX_VLAN_ENCAP_HDR_SIZE             4
 123 #define CPSW_MIN_PACKET_SIZE    (VLAN_ETH_ZLEN)
 124 #define CPSW_MAX_PACKET_SIZE    (VLAN_ETH_FRAME_LEN +\
 125                                  ETH_FCS_LEN +\
 126                                  CPSW_RX_VLAN_ENCAP_HDR_SIZE)
 127
 128 #define RX_PRIORITY_MAPPING     0x76543210
 129 #define TX_PRIORITY_MAPPING     0x33221100
 130 #define CPDMA_TX_PRIORITY_MAP   0x76543210
 131
 132 #define CPSW_VLAN_AWARE         BIT(1)
 133 #define CPSW_RX_VLAN_ENCAP      BIT(2)
 134 #define CPSW_ALE_VLAN_AWARE     1
 135
 136 #define CPSW_FIFO_NORMAL_MODE           (0 << 16)
 137 #define CPSW_FIFO_DUAL_MAC_MODE         (1 << 16)
 138 #define CPSW_FIFO_RATE_LIMIT_MODE       (2 << 16)
 139
 140 #define CPSW_INTPACEEN          (0x3f << 16)
 141 #define CPSW_INTPRESCALE_MASK   (0x7FF << 0)
 142 #define CPSW_CMINTMAX_CNT       63
 143 #define CPSW_CMINTMIN_CNT       2
 144 #define CPSW_CMINTMAX_INTVL     (1000 / CPSW_CMINTMIN_CNT)
 145 #define CPSW_CMINTMIN_INTVL     ((1000 / CPSW_CMINTMAX_CNT) + 1)
 146
 147 #define cpsw_slave_index(cpsw, priv)                            \
 148                 ((cpsw->data.dual_emac) ? priv->emac_port :     \
 149                 cpsw->data.active_slave)
 150 #define IRQ_NUM                 2
 151 #define CPSW_MAX_QUEUES         8
 152 #define CPSW_CPDMA_DESCS_POOL_SIZE_DEFAULT 256
 153 #define CPSW_FIFO_QUEUE_TYPE_SHIFT      16
 154 #define CPSW_FIFO_SHAPE_EN_SHIFT        16
 155 #define CPSW_FIFO_RATE_EN_SHIFT         20
 156 #define CPSW_TC_NUM                     4
 157 #define CPSW_FIFO_SHAPERS_NUM           (CPSW_TC_NUM - 1)
 158 #define CPSW_PCT_MASK                   0x7f
 159
 160 #define CPSW_RX_VLAN_ENCAP_HDR_PRIO_SHIFT       29
 161 #define CPSW_RX_VLAN_ENCAP_HDR_PRIO_MSK         GENMASK(2, 0)
 162 #define CPSW_RX_VLAN_ENCAP_HDR_VID_SHIFT        16
 163 #define CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_SHIFT   8
 164 #define CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_MSK     GENMASK(1, 0)
 165 enum {
 166         CPSW_RX_VLAN_ENCAP_HDR_PKT_VLAN_TAG = 0,
 167         CPSW_RX_VLAN_ENCAP_HDR_PKT_RESERV,
 168         CPSW_RX_VLAN_ENCAP_HDR_PKT_PRIO_TAG,
 169         CPSW_RX_VLAN_ENCAP_HDR_PKT_UNTAG,
 170 };
 171
 172 static int debug_level;
 173 module_param(debug_level, int, 0);
 174 MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
 175
 176 static int ale_ageout = 10;
 177 module_param(ale_ageout, int, 0);
 178 MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
 179
 180 static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
 181 module_param(rx_packet_max, int, 0);
 182 MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
 183
 184 static int descs_pool_size = CPSW_CPDMA_DESCS_POOL_SIZE_DEFAULT;
 185 module_param(descs_pool_size, int, 0444);
 186 MODULE_PARM_DESC(descs_pool_size, "Number of CPDMA CPPI descriptors in pool");
 187
 188 struct cpsw_wr_regs {
 189         u32     id_ver;
 190         u32     soft_reset;
 191         u32     control;
 192         u32     int_control;
 193         u32     rx_thresh_en;
 194         u32     rx_en;
 195         u32     tx_en;
 196         u32     misc_en;
 197         u32     mem_allign1[8];
 198         u32     rx_thresh_stat;
 199         u32     rx_stat;
 200         u32     tx_stat;
 201         u32     misc_stat;
 202         u32     mem_allign2[8];
 203         u32     rx_imax;
 204         u32     tx_imax;
 205
 206 };
 207
 208 struct cpsw_ss_regs {
 209         u32     id_ver;
 210         u32     control;
 211         u32     soft_reset;
 212         u32     stat_port_en;
 213         u32     ptype;
 214         u32     soft_idle;
 215         u32     thru_rate;
 216         u32     gap_thresh;
 217         u32     tx_start_wds;
 218         u32     flow_control;
 219         u32     vlan_ltype;
 220         u32     ts_ltype;
 221         u32     dlr_ltype;
 222 };
 223
 224 /* CPSW_PORT_V1 */
 225 #define CPSW1_MAX_BLKS      0x00 /* Maximum FIFO Blocks */
 226 #define CPSW1_BLK_CNT       0x04 /* FIFO Block Usage Count (Read Only) */
 227 #define CPSW1_TX_IN_CTL     0x08 /* Transmit FIFO Control */
 228 #define CPSW1_PORT_VLAN     0x0c /* VLAN Register */
 229 #define CPSW1_TX_PRI_MAP    0x10 /* Tx Header Priority to Switch Pri Mapping */
 230 #define CPSW1_TS_CTL        0x14 /* Time Sync Control */
 231 #define CPSW1_TS_SEQ_LTYPE  0x18 /* Time Sync Sequence ID Offset and Msg Type */
 232 #define CPSW1_TS_VLAN       0x1c /* Time Sync VLAN1 and VLAN2 */
 233
 234 /* CPSW_PORT_V2 */
 235 #define CPSW2_CONTROL       0x00 /* Control Register */
 236 #define CPSW2_MAX_BLKS      0x08 /* Maximum FIFO Blocks */
 237 #define CPSW2_BLK_CNT       0x0c /* FIFO Block Usage Count (Read Only) */
 238 #define CPSW2_TX_IN_CTL     0x10 /* Transmit FIFO Control */
 239 #define CPSW2_PORT_VLAN     0x14 /* VLAN Register */
 240 #define CPSW2_TX_PRI_MAP    0x18 /* Tx Header Priority to Switch Pri Mapping */
 241 #define CPSW2_TS_SEQ_MTYPE  0x1c /* Time Sync Sequence ID Offset and Msg Type */
 242
 243 /* CPSW_PORT_V1 and V2 */
 244 #define SA_LO               0x20 /* CPGMAC_SL Source Address Low */
 245 #define SA_HI               0x24 /* CPGMAC_SL Source Address High */
 246 #define SEND_PERCENT        0x28 /* Transmit Queue Send Percentages */
 247
 248 /* CPSW_PORT_V2 only */
 249 #define RX_DSCP_PRI_MAP0    0x30 /* Rx DSCP Priority to Rx Packet Mapping */
 250 #define RX_DSCP_PRI_MAP1    0x34 /* Rx DSCP Priority to Rx Packet Mapping */
 251 #define RX_DSCP_PRI_MAP2    0x38 /* Rx DSCP Priority to Rx Packet Mapping */
 252 #define RX_DSCP_PRI_MAP3    0x3c /* Rx DSCP Priority to Rx Packet Mapping */
 253 #define RX_DSCP_PRI_MAP4    0x40 /* Rx DSCP Priority to Rx Packet Mapping */
 254 #define RX_DSCP_PRI_MAP5    0x44 /* Rx DSCP Priority to Rx Packet Mapping */
 255 #define RX_DSCP_PRI_MAP6    0x48 /* Rx DSCP Priority to Rx Packet Mapping */
 256 #define RX_DSCP_PRI_MAP7    0x4c /* Rx DSCP Priority to Rx Packet Mapping */
 257
 258 /* Bit definitions for the CPSW2_CONTROL register */
 259 #define PASS_PRI_TAGGED     BIT(24) /* Pass Priority Tagged */
 260 #define VLAN_LTYPE2_EN      BIT(21) /* VLAN LTYPE 2 enable */
 261 #define VLAN_LTYPE1_EN      BIT(20) /* VLAN LTYPE 1 enable */
 262 #define DSCP_PRI_EN         BIT(16) /* DSCP Priority Enable */
 263 #define TS_107              BIT(15) /* Tyme Sync Dest IP Address 107 */
 264 #define TS_320              BIT(14) /* Time Sync Dest Port 320 enable */
 265 #define TS_319              BIT(13) /* Time Sync Dest Port 319 enable */
 266 #define TS_132              BIT(12) /* Time Sync Dest IP Addr 132 enable */
 267 #define TS_131              BIT(11) /* Time Sync Dest IP Addr 131 enable */
 268 #define TS_130              BIT(10) /* Time Sync Dest IP Addr 130 enable */
 269 #define TS_129              BIT(9)  /* Time Sync Dest IP Addr 129 enable */
 270 #define TS_TTL_NONZERO      BIT(8)  /* Time Sync Time To Live Non-zero enable */
 271 #define TS_ANNEX_F_EN       BIT(6)  /* Time Sync Annex F enable */
 272 #define TS_ANNEX_D_EN       BIT(4)  /* Time Sync Annex D enable */
 273 #define TS_LTYPE2_EN        BIT(3)  /* Time Sync LTYPE 2 enable */
 274 #define TS_LTYPE1_EN        BIT(2)  /* Time Sync LTYPE 1 enable */
 275 #define TS_TX_EN            BIT(1)  /* Time Sync Transmit Enable */
 276 #define TS_RX_EN            BIT(0)  /* Time Sync Receive Enable */
 277
 278 #define CTRL_V2_TS_BITS \
 279         (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
 280          TS_TTL_NONZERO  | TS_ANNEX_D_EN | TS_LTYPE1_EN | VLAN_LTYPE1_EN)
 281
 282 #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
 283 #define CTRL_V2_TX_TS_BITS  (CTRL_V2_TS_BITS | TS_TX_EN)
 284 #define CTRL_V2_RX_TS_BITS  (CTRL_V2_TS_BITS | TS_RX_EN)
 285
 286
 287 #define CTRL_V3_TS_BITS \
 288         (TS_107 | TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
 289          TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
 290          TS_LTYPE1_EN | VLAN_LTYPE1_EN)
 291
 292 #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
 293 #define CTRL_V3_TX_TS_BITS  (CTRL_V3_TS_BITS | TS_TX_EN)
 294 #define CTRL_V3_RX_TS_BITS  (CTRL_V3_TS_BITS | TS_RX_EN)
 295
 296 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
 297 #define TS_SEQ_ID_OFFSET_SHIFT   (16)    /* Time Sync Sequence ID Offset */
 298 #define TS_SEQ_ID_OFFSET_MASK    (0x3f)
 299 #define TS_MSG_TYPE_EN_SHIFT     (0)     /* Time Sync Message Type Enable */
 300 #define TS_MSG_TYPE_EN_MASK      (0xffff)
 301
 302 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
 303 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
 304
 305 /* Bit definitions for the CPSW1_TS_CTL register */
 306 #define CPSW_V1_TS_RX_EN                BIT(0)
 307 #define CPSW_V1_TS_TX_EN                BIT(4)
 308 #define CPSW_V1_MSG_TYPE_OFS            16
 309
 310 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
 311 #define CPSW_V1_SEQ_ID_OFS_SHIFT        16
 312
 313 #define CPSW_MAX_BLKS_TX                15
 314 #define CPSW_MAX_BLKS_TX_SHIFT          4
 315 #define CPSW_MAX_BLKS_RX                5
 316
 317 struct cpsw_host_regs {
 318         u32     max_blks;
 319         u32     blk_cnt;
 320         u32     tx_in_ctl;
 321         u32     port_vlan;
 322         u32     tx_pri_map;
 323         u32     cpdma_tx_pri_map;
 324         u32     cpdma_rx_chan_map;
 325 };
 326
 327 struct cpsw_sliver_regs {
 328         u32     id_ver;
 329         u32     mac_control;
 330         u32     mac_status;
 331         u32     soft_reset;
 332         u32     rx_maxlen;
 333         u32     __reserved_0;
 334         u32     rx_pause;
 335         u32     tx_pause;
 336         u32     __reserved_1;
 337         u32     rx_pri_map;
 338 };
 339
 340 struct cpsw_hw_stats {
 341         u32     rxgoodframes;
 342         u32     rxbroadcastframes;
 343         u32     rxmulticastframes;
 344         u32     rxpauseframes;
 345         u32     rxcrcerrors;
 346         u32     rxaligncodeerrors;
 347         u32     rxoversizedframes;
 348         u32     rxjabberframes;
 349         u32     rxundersizedframes;
 350         u32     rxfragments;
 351         u32     __pad_0[2];
 352         u32     rxoctets;
 353         u32     txgoodframes;
 354         u32     txbroadcastframes;
 355         u32     txmulticastframes;
 356         u32     txpauseframes;
 357         u32     txdeferredframes;
 358         u32     txcollisionframes;
 359         u32     txsinglecollframes;
 360         u32     txmultcollframes;
 361         u32     txexcessivecollisions;
 362         u32     txlatecollisions;
 363         u32     txunderrun;
 364         u32     txcarriersenseerrors;
 365         u32     txoctets;
 366         u32     octetframes64;
 367         u32     octetframes65t127;
 368         u32     octetframes128t255;
 369         u32     octetframes256t511;
 370         u32     octetframes512t1023;
 371         u32     octetframes1024tup;
 372         u32     netoctets;
 373         u32     rxsofoverruns;
 374         u32     rxmofoverruns;
 375         u32     rxdmaoverruns;
 376 };
 377
 378 struct cpsw_slave_data {
 379         struct device_node *phy_node;
 380         char            phy_id[MII_BUS_ID_SIZE];
 381         int             phy_if;
 382         u8              mac_addr[ETH_ALEN];
 383         u16             dual_emac_res_vlan;     /* Reserved VLAN for DualEMAC */
 384         struct phy      *ifphy;
 385 };
 386
 387 struct cpsw_platform_data {
 388         struct cpsw_slave_data  *slave_data;
 389         u32     ss_reg_ofs;     /* Subsystem control register offset */
 390         u32     channels;       /* number of cpdma channels (symmetric) */
 391         u32     slaves;         /* number of slave cpgmac ports */
 392         u32     active_slave; /* time stamping, ethtool and SIOCGMIIPHY slave */
 393         u32     ale_entries;    /* ale table size */
 394         u32     bd_ram_size;  /*buffer descriptor ram size */
 395         u32     mac_control;    /* Mac control register */
 396         u16     default_vlan;   /* Def VLAN for ALE lookup in VLAN aware mode*/
 397         bool    dual_emac;      /* Enable Dual EMAC mode */
 398 };
 399
 400 struct cpsw_slave {
 401         void __iomem                    *regs;
 402         struct cpsw_sliver_regs __iomem *sliver;
 403         int                             slave_num;
 404         u32                             mac_control;
 405         struct cpsw_slave_data          *data;
 406         struct phy_device               *phy;
 407         struct net_device               *ndev;
 408         u32                             port_vlan;
 409 };
 410
 411 static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
 412 {
 413         return readl_relaxed(slave->regs + offset);
 414 }
 415
 416 static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
 417 {
 418         writel_relaxed(val, slave->regs + offset);
 419 }
 420
 421 struct cpsw_vector {
 422         struct cpdma_chan *ch;
 423         int budget;
 424 };
 425
 426 struct cpsw_common {
 427         struct device                   *dev;
 428         struct cpsw_platform_data       data;
 429         struct napi_struct              napi_rx;
 430         struct napi_struct              napi_tx;
 431         struct cpsw_ss_regs __iomem     *regs;
 432         struct cpsw_wr_regs __iomem     *wr_regs;
 433         u8 __iomem                      *hw_stats;
 434         struct cpsw_host_regs __iomem   *host_port_regs;
 435         u32                             version;
 436         u32                             coal_intvl;
 437         u32                             bus_freq_mhz;
 438         int                             rx_packet_max;
 439         struct cpsw_slave               *slaves;
 440         struct cpdma_ctlr               *dma;
 441         struct cpsw_vector              txv[CPSW_MAX_QUEUES];
 442         struct cpsw_vector              rxv[CPSW_MAX_QUEUES];
 443         struct cpsw_ale                 *ale;
 444         bool                            quirk_irq;
 445         bool                            rx_irq_disabled;
 446         bool                            tx_irq_disabled;
 447         u32 irqs_table[IRQ_NUM];
 448         struct cpts                     *cpts;
 449         int                             rx_ch_num, tx_ch_num;
 450         int                             speed;
 451         int                             usage_count;
 452 };
 453
 454 struct cpsw_priv {
 455         struct net_device               *ndev;
 456         struct device                   *dev;
 457         u32                             msg_enable;
 458         u8                              mac_addr[ETH_ALEN];
 459         bool                            rx_pause;
 460         bool                            tx_pause;
 461         bool                            mqprio_hw;
 462         int                             fifo_bw[CPSW_TC_NUM];
 463         int                             shp_cfg_speed;
 464         int                             tx_ts_enabled;
 465         int                             rx_ts_enabled;
 466         u32 emac_port;
 467         struct cpsw_common *cpsw;
 468 };
 469
 470 struct cpsw_stats {
 471         char stat_string[ETH_GSTRING_LEN];
 472         int type;
 473         int sizeof_stat;
 474         int stat_offset;
 475 };
 476
 477 enum {
 478         CPSW_STATS,
 479         CPDMA_RX_STATS,
 480         CPDMA_TX_STATS,
 481 };
 482
 483 #define CPSW_STAT(m)            CPSW_STATS,                             \
 484                                 FIELD_SIZEOF(struct cpsw_hw_stats, m), \
 485                                 offsetof(struct cpsw_hw_stats, m)
 486 #define CPDMA_RX_STAT(m)        CPDMA_RX_STATS,                            \
 487                                 FIELD_SIZEOF(struct cpdma_chan_stats, m), \
 488                                 offsetof(struct cpdma_chan_stats, m)
 489 #define CPDMA_TX_STAT(m)        CPDMA_TX_STATS,                            \
 490                                 FIELD_SIZEOF(struct cpdma_chan_stats, m), \
 491                                 offsetof(struct cpdma_chan_stats, m)
 492
 493 static const struct cpsw_stats cpsw_gstrings_stats[] = {
 494         { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
 495         { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
 496         { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
 497         { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
 498         { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
 499         { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
 500         { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
 501         { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
 502         { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
 503         { "Rx Fragments", CPSW_STAT(rxfragments) },
 504         { "Rx Octets", CPSW_STAT(rxoctets) },
 505         { "Good Tx Frames", CPSW_STAT(txgoodframes) },
 506         { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
 507         { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
 508         { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
 509         { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
 510         { "Collisions", CPSW_STAT(txcollisionframes) },
 511         { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
 512         { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
 513         { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
 514         { "Late Collisions", CPSW_STAT(txlatecollisions) },
 515         { "Tx Underrun", CPSW_STAT(txunderrun) },
 516         { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
 517         { "Tx Octets", CPSW_STAT(txoctets) },
 518         { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
 519         { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
 520         { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
 521         { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
 522         { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
 523         { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
 524         { "Net Octets", CPSW_STAT(netoctets) },
 525         { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
 526         { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
 527         { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
 528 };
 529
 530 static const struct cpsw_stats cpsw_gstrings_ch_stats[] = {
 531         { "head_enqueue", CPDMA_RX_STAT(head_enqueue) },
 532         { "tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
 533         { "pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
 534         { "misqueued", CPDMA_RX_STAT(misqueued) },
 535         { "desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
 536         { "pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
 537         { "runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
 538         { "runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
 539         { "empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
 540         { "busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
 541         { "good_dequeue", CPDMA_RX_STAT(good_dequeue) },
 542         { "requeue", CPDMA_RX_STAT(requeue) },
 543         { "teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
 544 };
 545
 546 #define CPSW_STATS_COMMON_LEN   ARRAY_SIZE(cpsw_gstrings_stats)
 547 #define CPSW_STATS_CH_LEN       ARRAY_SIZE(cpsw_gstrings_ch_stats)
 548
 549 #define ndev_to_cpsw(ndev) (((struct cpsw_priv *)netdev_priv(ndev))->cpsw)
 550 #define napi_to_cpsw(napi)      container_of(napi, struct cpsw_common, napi)
 551 #define for_each_slave(priv, func, arg...)                              \
 552         do {                                                            \
 553                 struct cpsw_slave *slave;                               \
 554                 struct cpsw_common *cpsw = (priv)->cpsw;                \
 555                 int n;                                                  \
 556                 if (cpsw->data.dual_emac)                               \
 557                         (func)((cpsw)->slaves + priv->emac_port, ##arg);\
 558                 else                                                    \
 559                         for (n = cpsw->data.slaves,                     \
 560                                         slave = cpsw->slaves;           \
 561                                         n; n--)                         \
 562                                 (func)(slave++, ##arg);                 \
 563         } while (0)
 564
 565 static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
 566                                     __be16 proto, u16 vid);
 567
 568 static inline int cpsw_get_slave_port(u32 slave_num)
 569 {
 570         return slave_num + 1;
 571 }
 572
 573 static void cpsw_set_promiscious(struct net_device *ndev, bool enable)
 574 {
 575         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
 576         struct cpsw_ale *ale = cpsw->ale;
 577         int i;
 578
 579         if (cpsw->data.dual_emac) {
 580                 bool flag = false;
 581
 582                 /* Enabling promiscuous mode for one interface will be
 583                  * common for both the interface as the interface shares
 584                  * the same hardware resource.
 585                  */
 586                 for (i = 0; i < cpsw->data.slaves; i++)
 587                         if (cpsw->slaves[i].ndev->flags & IFF_PROMISC)
 588                                 flag = true;
 589
 590                 if (!enable && flag) {
 591                         enable = true;
 592                         dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
 593                 }
 594
 595                 if (enable) {
 596                         /* Enable Bypass */
 597                         cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);
 598
 599                         dev_dbg(&ndev->dev, "promiscuity enabled\n");
 600                 } else {
 601                         /* Disable Bypass */
 602                         cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);
 603                         dev_dbg(&ndev->dev, "promiscuity disabled\n");
 604                 }
 605         } else {
 606                 if (enable) {
 607                         unsigned long timeout = jiffies + HZ;
 608
 609                         /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */
 610                         for (i = 0; i <= cpsw->data.slaves; i++) {
 611                                 cpsw_ale_control_set(ale, i,
 612                                                      ALE_PORT_NOLEARN, 1);
 613                                 cpsw_ale_control_set(ale, i,
 614                                                      ALE_PORT_NO_SA_UPDATE, 1);
 615                         }
 616
 617                         /* Clear All Untouched entries */
 618                         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
 619                         do {
 620                                 cpu_relax();
 621                                 if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))
 622                                         break;
 623                         } while (time_after(timeout, jiffies));
 624                         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
 625
 626                         /* Clear all mcast from ALE */
 627                         cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS, -1);
 628                         __hw_addr_ref_unsync_dev(&ndev->mc, ndev, NULL);
 629
 630                         /* Flood All Unicast Packets to Host port */
 631                         cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);
 632                         dev_dbg(&ndev->dev, "promiscuity enabled\n");
 633                 } else {
 634                         /* Don't Flood All Unicast Packets to Host port */
 635                         cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);
 636
 637                         /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */
 638                         for (i = 0; i <= cpsw->data.slaves; i++) {
 639                                 cpsw_ale_control_set(ale, i,
 640                                                      ALE_PORT_NOLEARN, 0);
 641                                 cpsw_ale_control_set(ale, i,
 642                                                      ALE_PORT_NO_SA_UPDATE, 0);
 643                         }
 644                         dev_dbg(&ndev->dev, "promiscuity disabled\n");
 645                 }
 646         }
 647 }
 648
 649 struct addr_sync_ctx {
 650         struct net_device *ndev;
 651         const u8 *addr;         /* address to be synched */
 652         int consumed;           /* number of address instances */
 653         int flush;              /* flush flag */
 654 };
 655
 656 /**
 657  * cpsw_set_mc - adds multicast entry to the table if it's not added or deletes
 658  * if it's not deleted
 659  * @ndev: device to sync
 660  * @addr: address to be added or deleted
 661  * @vid: vlan id, if vid < 0 set/unset address for real device
 662  * @add: add address if the flag is set or remove otherwise
 663  */
 664 static int cpsw_set_mc(struct net_device *ndev, const u8 *addr,
 665                        int vid, int add)
 666 {
 667         struct cpsw_priv *priv = netdev_priv(ndev);
 668         struct cpsw_common *cpsw = priv->cpsw;
 669         int mask, flags, ret;
 670
 671         if (vid < 0) {
 672                 if (cpsw->data.dual_emac)
 673                         vid = cpsw->slaves[priv->emac_port].port_vlan;
 674                 else
 675                         vid = 0;
 676         }
 677
 678         mask = cpsw->data.dual_emac ? ALE_PORT_HOST : ALE_ALL_PORTS;
 679         flags = vid ? ALE_VLAN : 0;
 680
 681         if (add)
 682                 ret = cpsw_ale_add_mcast(cpsw->ale, addr, mask, flags, vid, 0);
 683         else
 684                 ret = cpsw_ale_del_mcast(cpsw->ale, addr, 0, flags, vid);
 685
 686         return ret;
 687 }
 688
 689 static int cpsw_update_vlan_mc(struct net_device *vdev, int vid, void *ctx)
 690 {
 691         struct addr_sync_ctx *sync_ctx = ctx;
 692         struct netdev_hw_addr *ha;
 693         int found = 0, ret = 0;
 694
 695         if (!vdev || !(vdev->flags & IFF_UP))
 696                 return 0;
 697
 698         /* vlan address is relevant if its sync_cnt != 0 */
 699         netdev_for_each_mc_addr(ha, vdev) {
 700                 if (ether_addr_equal(ha->addr, sync_ctx->addr)) {
 701                         found = ha->sync_cnt;
 702                         break;
 703                 }
 704         }
 705
 706         if (found)
 707                 sync_ctx->consumed++;
 708
 709         if (sync_ctx->flush) {
 710                 if (!found)
 711                         cpsw_set_mc(sync_ctx->ndev, sync_ctx->addr, vid, 0);
 712                 return 0;
 713         }
 714
 715         if (found)
 716                 ret = cpsw_set_mc(sync_ctx->ndev, sync_ctx->addr, vid, 1);
 717
 718         return ret;
 719 }
 720
 721 static int cpsw_add_mc_addr(struct net_device *ndev, const u8 *addr, int num)
 722 {
 723         struct addr_sync_ctx sync_ctx;
 724         int ret;
 725
 726         sync_ctx.consumed = 0;
 727         sync_ctx.addr = addr;
 728         sync_ctx.ndev = ndev;
 729         sync_ctx.flush = 0;
 730
 731         ret = vlan_for_each(ndev, cpsw_update_vlan_mc, &sync_ctx);
 732         if (sync_ctx.consumed < num && !ret)
 733                 ret = cpsw_set_mc(ndev, addr, -1, 1);
 734
 735         return ret;
 736 }
 737
 738 static int cpsw_del_mc_addr(struct net_device *ndev, const u8 *addr, int num)
 739 {
 740         struct addr_sync_ctx sync_ctx;
 741
 742         sync_ctx.consumed = 0;
 743         sync_ctx.addr = addr;
 744         sync_ctx.ndev = ndev;
 745         sync_ctx.flush = 1;
 746
 747         vlan_for_each(ndev, cpsw_update_vlan_mc, &sync_ctx);
 748         if (sync_ctx.consumed == num)
 749                 cpsw_set_mc(ndev, addr, -1, 0);
 750
 751         return 0;
 752 }
 753
 754 static int cpsw_purge_vlan_mc(struct net_device *vdev, int vid, void *ctx)
 755 {
 756         struct addr_sync_ctx *sync_ctx = ctx;
 757         struct netdev_hw_addr *ha;
 758         int found = 0;
 759
 760         if (!vdev || !(vdev->flags & IFF_UP))
 761                 return 0;
 762
 763         /* vlan address is relevant if its sync_cnt != 0 */
 764         netdev_for_each_mc_addr(ha, vdev) {
 765                 if (ether_addr_equal(ha->addr, sync_ctx->addr)) {
 766                         found = ha->sync_cnt;
 767                         break;
 768                 }
 769         }
 770
 771         if (!found)
 772                 return 0;
 773
 774         sync_ctx->consumed++;
 775         cpsw_set_mc(sync_ctx->ndev, sync_ctx->addr, vid, 0);
 776         return 0;
 777 }
 778
 779 static int cpsw_purge_all_mc(struct net_device *ndev, const u8 *addr, int num)
 780 {
 781         struct addr_sync_ctx sync_ctx;
 782
 783         sync_ctx.addr = addr;
 784         sync_ctx.ndev = ndev;
 785         sync_ctx.consumed = 0;
 786
 787         vlan_for_each(ndev, cpsw_purge_vlan_mc, &sync_ctx);
 788         if (sync_ctx.consumed < num)
 789                 cpsw_set_mc(ndev, addr, -1, 0);
 790
 791         return 0;
 792 }
 793
 794 static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
 795 {
 796         struct cpsw_priv *priv = netdev_priv(ndev);
 797         struct cpsw_common *cpsw = priv->cpsw;
 798         int slave_port = -1;
 799
 800         if (cpsw->data.dual_emac)
 801                 slave_port = priv->emac_port + 1;
 802
 803         if (ndev->flags & IFF_PROMISC) {
 804                 /* Enable promiscuous mode */
 805                 cpsw_set_promiscious(ndev, true);
 806                 cpsw_ale_set_allmulti(cpsw->ale, IFF_ALLMULTI, slave_port);
 807                 return;
 808         } else {
 809                 /* Disable promiscuous mode */
 810                 cpsw_set_promiscious(ndev, false);
 811         }
 812
 813         /* Restore allmulti on vlans if necessary */
 814         cpsw_ale_set_allmulti(cpsw->ale,
 815                               ndev->flags & IFF_ALLMULTI, slave_port);
 816
 817         /* add/remove mcast address either for real netdev or for vlan */
 818         __hw_addr_ref_sync_dev(&ndev->mc, ndev, cpsw_add_mc_addr,
 819                                cpsw_del_mc_addr);
 820 }
 821
 822 static void cpsw_intr_enable(struct cpsw_common *cpsw)
 823 {
 824         writel_relaxed(0xFF, &cpsw->wr_regs->tx_en);
 825         writel_relaxed(0xFF, &cpsw->wr_regs->rx_en);
 826
 827         cpdma_ctlr_int_ctrl(cpsw->dma, true);
 828         return;
 829 }
 830
 831 static void cpsw_intr_disable(struct cpsw_common *cpsw)
 832 {
 833         writel_relaxed(0, &cpsw->wr_regs->tx_en);
 834         writel_relaxed(0, &cpsw->wr_regs->rx_en);
 835
 836         cpdma_ctlr_int_ctrl(cpsw->dma, false);
 837         return;
 838 }
 839
 840 static void cpsw_tx_handler(void *token, int len, int status)
 841 {
 842         struct netdev_queue     *txq;
 843         struct sk_buff          *skb = token;
 844         struct net_device       *ndev = skb->dev;
 845         struct cpsw_common      *cpsw = ndev_to_cpsw(ndev);
 846
 847         /* Check whether the queue is stopped due to stalled tx dma, if the
 848          * queue is stopped then start the queue as we have free desc for tx
 849          */
 850         txq = netdev_get_tx_queue(ndev, skb_get_queue_mapping(skb));
 851         if (unlikely(netif_tx_queue_stopped(txq)))
 852                 netif_tx_wake_queue(txq);
 853
 854         cpts_tx_timestamp(cpsw->cpts, skb);
 855         ndev->stats.tx_packets++;
 856         ndev->stats.tx_bytes += len;
 857         dev_kfree_skb_any(skb);
 858 }
 859
 860 static void cpsw_rx_vlan_encap(struct sk_buff *skb)
 861 {
 862         struct cpsw_priv *priv = netdev_priv(skb->dev);
 863         struct cpsw_common *cpsw = priv->cpsw;
 864         u32 rx_vlan_encap_hdr = *((u32 *)skb->data);
 865         u16 vtag, vid, prio, pkt_type;
 866
 867         /* Remove VLAN header encapsulation word */
 868         skb_pull(skb, CPSW_RX_VLAN_ENCAP_HDR_SIZE);
 869
 870         pkt_type = (rx_vlan_encap_hdr >>
 871                     CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_SHIFT) &
 872                     CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_MSK;
 873         /* Ignore unknown & Priority-tagged packets*/
 874         if (pkt_type == CPSW_RX_VLAN_ENCAP_HDR_PKT_RESERV ||
 875             pkt_type == CPSW_RX_VLAN_ENCAP_HDR_PKT_PRIO_TAG)
 876                 return;
 877
 878         vid = (rx_vlan_encap_hdr >>
 879                CPSW_RX_VLAN_ENCAP_HDR_VID_SHIFT) &
 880                VLAN_VID_MASK;
 881         /* Ignore vid 0 and pass packet as is */
 882         if (!vid)
 883                 return;
 884         /* Ignore default vlans in dual mac mode */
 885         if (cpsw->data.dual_emac &&
 886             vid == cpsw->slaves[priv->emac_port].port_vlan)
 887                 return;
 888
 889         prio = (rx_vlan_encap_hdr >>
 890                 CPSW_RX_VLAN_ENCAP_HDR_PRIO_SHIFT) &
 891                 CPSW_RX_VLAN_ENCAP_HDR_PRIO_MSK;
 892
 893         vtag = (prio << VLAN_PRIO_SHIFT) | vid;
 894         __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vtag);
 895
 896         /* strip vlan tag for VLAN-tagged packet */
 897         if (pkt_type == CPSW_RX_VLAN_ENCAP_HDR_PKT_VLAN_TAG) {
 898                 memmove(skb->data + VLAN_HLEN, skb->data, 2 * ETH_ALEN);
 899                 skb_pull(skb, VLAN_HLEN);
 900         }
 901 }
 902
 903 static void cpsw_rx_handler(void *token, int len, int status)
 904 {
 905         struct cpdma_chan       *ch;
 906         struct sk_buff          *skb = token;
 907         struct sk_buff          *new_skb;
 908         struct net_device       *ndev = skb->dev;
 909         int                     ret = 0, port;
 910         struct cpsw_common      *cpsw = ndev_to_cpsw(ndev);
 911         struct cpsw_priv        *priv;
 912
 913         if (cpsw->data.dual_emac) {
 914                 port = CPDMA_RX_SOURCE_PORT(status);
 915                 if (port) {
 916                         ndev = cpsw->slaves[--port].ndev;
 917                         skb->dev = ndev;
 918                 }
 919         }
 920
 921         if (unlikely(status < 0) || unlikely(!netif_running(ndev))) {
 922                 /* In dual emac mode check for all interfaces */
 923                 if (cpsw->data.dual_emac && cpsw->usage_count &&
 924                     (status >= 0)) {
 925                         /* The packet received is for the interface which
 926                          * is already down and the other interface is up
 927                          * and running, instead of freeing which results
 928                          * in reducing of the number of rx descriptor in
 929                          * DMA engine, requeue skb back to cpdma.
 930                          */
 931                         new_skb = skb;
 932                         goto requeue;
 933                 }
 934
 935                 /* the interface is going down, skbs are purged */
 936                 dev_kfree_skb_any(skb);
 937                 return;
 938         }
 939
 940         new_skb = netdev_alloc_skb_ip_align(ndev, cpsw->rx_packet_max);
 941         if (new_skb) {
 942                 skb_copy_queue_mapping(new_skb, skb);
 943                 skb_put(skb, len);
 944                 if (status & CPDMA_RX_VLAN_ENCAP)
 945                         cpsw_rx_vlan_encap(skb);
 946                 priv = netdev_priv(ndev);
 947                 if (priv->rx_ts_enabled)
 948                         cpts_rx_timestamp(cpsw->cpts, skb);
 949                 skb->protocol = eth_type_trans(skb, ndev);
 950                 netif_receive_skb(skb);
 951                 ndev->stats.rx_bytes += len;
 952                 ndev->stats.rx_packets++;
 953                 kmemleak_not_leak(new_skb);
 954         } else {
 955                 ndev->stats.rx_dropped++;
 956                 new_skb = skb;
 957         }
 958
 959 requeue:
 960         if (netif_dormant(ndev)) {
 961                 dev_kfree_skb_any(new_skb);
 962                 return;
 963         }
 964
 965         ch = cpsw->rxv[skb_get_queue_mapping(new_skb)].ch;
 966         ret = cpdma_chan_submit(ch, new_skb, new_skb->data,
 967                                 skb_tailroom(new_skb), 0);
 968         if (WARN_ON(ret < 0))
 969                 dev_kfree_skb_any(new_skb);
 970 }
 971
 972 static void cpsw_split_res(struct cpsw_common *cpsw)
 973 {
 974         u32 consumed_rate = 0, bigest_rate = 0;
 975         struct cpsw_vector *txv = cpsw->txv;
 976         int i, ch_weight, rlim_ch_num = 0;
 977         int budget, bigest_rate_ch = 0;
 978         u32 ch_rate, max_rate;
 979         int ch_budget = 0;
 980
 981         for (i = 0; i < cpsw->tx_ch_num; i++) {
 982                 ch_rate = cpdma_chan_get_rate(txv[i].ch);
 983                 if (!ch_rate)
 984                         continue;
 985
 986                 rlim_ch_num++;
 987                 consumed_rate += ch_rate;
 988         }
 989
 990         if (cpsw->tx_ch_num == rlim_ch_num) {
 991                 max_rate = consumed_rate;
 992         } else if (!rlim_ch_num) {
 993                 ch_budget = CPSW_POLL_WEIGHT / cpsw->tx_ch_num;
 994                 bigest_rate = 0;
 995                 max_rate = consumed_rate;
 996         } else {
 997                 max_rate = cpsw->speed * 1000;
 998
 999                 /* if max_rate is less then expected due to reduced link speed,
1000                  * split proportionally according next potential max speed
1001                  */
1002                 if (max_rate < consumed_rate)
1003                         max_rate *= 10;
1004
1005                 if (max_rate < consumed_rate)
1006                         max_rate *= 10;
1007
1008                 ch_budget = (consumed_rate * CPSW_POLL_WEIGHT) / max_rate;
1009                 ch_budget = (CPSW_POLL_WEIGHT - ch_budget) /
1010                             (cpsw->tx_ch_num - rlim_ch_num);
1011                 bigest_rate = (max_rate - consumed_rate) /
1012                               (cpsw->tx_ch_num - rlim_ch_num);
1013         }
1014
1015         /* split tx weight/budget */
1016         budget = CPSW_POLL_WEIGHT;
1017         for (i = 0; i < cpsw->tx_ch_num; i++) {
1018                 ch_rate = cpdma_chan_get_rate(txv[i].ch);
1019                 if (ch_rate) {
1020                         txv[i].budget = (ch_rate * CPSW_POLL_WEIGHT) / max_rate;
1021                         if (!txv[i].budget)
1022                                 txv[i].budget++;
1023                         if (ch_rate > bigest_rate) {
1024                                 bigest_rate_ch = i;
1025                                 bigest_rate = ch_rate;
1026                         }
1027
1028                         ch_weight = (ch_rate * 100) / max_rate;
1029                         if (!ch_weight)
1030                                 ch_weight++;
1031                         cpdma_chan_set_weight(cpsw->txv[i].ch, ch_weight);
1032                 } else {
1033                         txv[i].budget = ch_budget;
1034                         if (!bigest_rate_ch)
1035                                 bigest_rate_ch = i;
1036                         cpdma_chan_set_weight(cpsw->txv[i].ch, 0);
1037                 }
1038
1039                 budget -= txv[i].budget;
1040         }
1041
1042         if (budget)
1043                 txv[bigest_rate_ch].budget += budget;
1044
1045         /* split rx budget */
1046         budget = CPSW_POLL_WEIGHT;
1047         ch_budget = budget / cpsw->rx_ch_num;
1048         for (i = 0; i < cpsw->rx_ch_num; i++) {
1049                 cpsw->rxv[i].budget = ch_budget;
1050                 budget -= ch_budget;
1051         }
1052
1053         if (budget)
1054                 cpsw->rxv[0].budget += budget;
1055 }
1056
1057 static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id)
1058 {
1059         struct cpsw_common *cpsw = dev_id;
1060
1061         writel(0, &cpsw->wr_regs->tx_en);
1062         cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_TX);
1063
1064         if (cpsw->quirk_irq) {
1065                 disable_irq_nosync(cpsw->irqs_table[1]);
1066                 cpsw->tx_irq_disabled = true;
1067         }
1068
1069         napi_schedule(&cpsw->napi_tx);
1070         return IRQ_HANDLED;
1071 }
1072
1073 static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id)
1074 {
1075         struct cpsw_common *cpsw = dev_id;
1076
1077         cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_RX);
1078         writel(0, &cpsw->wr_regs->rx_en);
1079
1080         if (cpsw->quirk_irq) {
1081                 disable_irq_nosync(cpsw->irqs_table[0]);
1082                 cpsw->rx_irq_disabled = true;
1083         }
1084
1085         napi_schedule(&cpsw->napi_rx);
1086         return IRQ_HANDLED;
1087 }
1088
1089 static int cpsw_tx_mq_poll(struct napi_struct *napi_tx, int budget)
1090 {
1091         u32                     ch_map;
1092         int                     num_tx, cur_budget, ch;
1093         struct cpsw_common      *cpsw = napi_to_cpsw(napi_tx);
1094         struct cpsw_vector      *txv;
1095
1096         /* process every unprocessed channel */
1097         ch_map = cpdma_ctrl_txchs_state(cpsw->dma);
1098         for (ch = 0, num_tx = 0; ch_map & 0xff; ch_map <<= 1, ch++) {
1099                 if (!(ch_map & 0x80))
1100                         continue;
1101
1102                 txv = &cpsw->txv[ch];
1103                 if (unlikely(txv->budget > budget - num_tx))
1104                         cur_budget = budget - num_tx;
1105                 else
1106                         cur_budget = txv->budget;
1107
1108                 num_tx += cpdma_chan_process(txv->ch, cur_budget);
1109                 if (num_tx >= budget)
1110                         break;
1111         }
1112
1113         if (num_tx < budget) {
1114                 napi_complete(napi_tx);
1115                 writel(0xff, &cpsw->wr_regs->tx_en);
1116         }
1117
1118         return num_tx;
1119 }
1120
1121 static int cpsw_tx_poll(struct napi_struct *napi_tx, int budget)
1122 {
1123         struct cpsw_common *cpsw = napi_to_cpsw(napi_tx);
1124         int num_tx;
1125
1126         num_tx = cpdma_chan_process(cpsw->txv[0].ch, budget);
1127         if (num_tx < budget) {
1128                 napi_complete(napi_tx);
1129                 writel(0xff, &cpsw->wr_regs->tx_en);
1130                 if (cpsw->tx_irq_disabled) {
1131                         cpsw->tx_irq_disabled = false;
1132                         enable_irq(cpsw->irqs_table[1]);
1133                 }
1134         }
1135
1136         return num_tx;
1137 }
1138
1139 static int cpsw_rx_mq_poll(struct napi_struct *napi_rx, int budget)
1140 {
1141         u32                     ch_map;
1142         int                     num_rx, cur_budget, ch;
1143         struct cpsw_common      *cpsw = napi_to_cpsw(napi_rx);
1144         struct cpsw_vector      *rxv;
1145
1146         /* process every unprocessed channel */
1147         ch_map = cpdma_ctrl_rxchs_state(cpsw->dma);
1148         for (ch = 0, num_rx = 0; ch_map; ch_map >>= 1, ch++) {
1149                 if (!(ch_map & 0x01))
1150                         continue;
1151
1152                 rxv = &cpsw->rxv[ch];
1153                 if (unlikely(rxv->budget > budget - num_rx))
1154                         cur_budget = budget - num_rx;
1155                 else
1156                         cur_budget = rxv->budget;
1157
1158                 num_rx += cpdma_chan_process(rxv->ch, cur_budget);
1159                 if (num_rx >= budget)
1160                         break;
1161         }
1162
1163         if (num_rx < budget) {
1164                 napi_complete_done(napi_rx, num_rx);
1165                 writel(0xff, &cpsw->wr_regs->rx_en);
1166         }
1167
1168         return num_rx;
1169 }
1170
1171 static int cpsw_rx_poll(struct napi_struct *napi_rx, int budget)
1172 {
1173         struct cpsw_common *cpsw = napi_to_cpsw(napi_rx);
1174         int num_rx;
1175
1176         num_rx = cpdma_chan_process(cpsw->rxv[0].ch, budget);
1177         if (num_rx < budget) {
1178                 napi_complete_done(napi_rx, num_rx);
1179                 writel(0xff, &cpsw->wr_regs->rx_en);
1180                 if (cpsw->rx_irq_disabled) {
1181                         cpsw->rx_irq_disabled = false;
1182                         enable_irq(cpsw->irqs_table[0]);
1183                 }
1184         }
1185
1186         return num_rx;
1187 }
1188
1189 static inline void soft_reset(const char *module, void __iomem *reg)
1190 {
1191         unsigned long timeout = jiffies + HZ;
1192
1193         writel_relaxed(1, reg);
1194         do {
1195                 cpu_relax();
1196         } while ((readl_relaxed(reg) & 1) && time_after(timeout, jiffies));
1197
1198         WARN(readl_relaxed(reg) & 1, "failed to soft-reset %s\n", module);
1199 }
1200
1201 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
1202                                struct cpsw_priv *priv)
1203 {
1204         slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
1205         slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
1206 }
1207
1208 static bool cpsw_shp_is_off(struct cpsw_priv *priv)
1209 {
1210         struct cpsw_common *cpsw = priv->cpsw;
1211         struct cpsw_slave *slave;
1212         u32 shift, mask, val;
1213
1214         val = readl_relaxed(&cpsw->regs->ptype);
1215
1216         slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
1217         shift = CPSW_FIFO_SHAPE_EN_SHIFT + 3 * slave->slave_num;
1218         mask = 7 << shift;
1219         val = val & mask;
1220
1221         return !val;
1222 }
1223
1224 static void cpsw_fifo_shp_on(struct cpsw_priv *priv, int fifo, int on)
1225 {
1226         struct cpsw_common *cpsw = priv->cpsw;
1227         struct cpsw_slave *slave;
1228         u32 shift, mask, val;
1229
1230         val = readl_relaxed(&cpsw->regs->ptype);
1231
1232         slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
1233         shift = CPSW_FIFO_SHAPE_EN_SHIFT + 3 * slave->slave_num;
1234         mask = (1 << --fifo) << shift;
1235         val = on ? val | mask : val & ~mask;
1236
1237         writel_relaxed(val, &cpsw->regs->ptype);
1238 }
1239
1240 static void _cpsw_adjust_link(struct cpsw_slave *slave,
1241                               struct cpsw_priv *priv, bool *link)
1242 {
1243         struct phy_device       *phy = slave->phy;
1244         u32                     mac_control = 0;
1245         u32                     slave_port;
1246         struct cpsw_common *cpsw = priv->cpsw;
1247
1248         if (!phy)
1249                 return;
1250
1251         slave_port = cpsw_get_slave_port(slave->slave_num);
1252
1253         if (phy->link) {
1254                 mac_control = cpsw->data.mac_control;
1255
1256                 /* enable forwarding */
1257                 cpsw_ale_control_set(cpsw->ale, slave_port,
1258                                      ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1259
1260                 if (phy->speed == 1000)
1261                         mac_control |= BIT(7);  /* GIGABITEN    */
1262                 if (phy->duplex)
1263                         mac_control |= BIT(0);  /* FULLDUPLEXEN */
1264
1265                 /* set speed_in input in case RMII mode is used in 100Mbps */
1266                 if (phy->speed == 100)
1267                         mac_control |= BIT(15);
1268                 /* in band mode only works in 10Mbps RGMII mode */
1269                 else if ((phy->speed == 10) && phy_interface_is_rgmii(phy))
1270                         mac_control |= BIT(18); /* In Band mode */
1271
1272                 if (priv->rx_pause)
1273                         mac_control |= BIT(3);
1274
1275                 if (priv->tx_pause)
1276                         mac_control |= BIT(4);
1277
1278                 *link = true;
1279
1280                 if (priv->shp_cfg_speed &&
1281                     priv->shp_cfg_speed != slave->phy->speed &&
1282                     !cpsw_shp_is_off(priv))
1283                         dev_warn(priv->dev,
1284                                  "Speed was changed, CBS shaper speeds are changed!");
1285         } else {
1286                 mac_control = 0;
1287                 /* disable forwarding */
1288                 cpsw_ale_control_set(cpsw->ale, slave_port,
1289                                      ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1290         }
1291
1292         if (mac_control != slave->mac_control) {
1293                 phy_print_status(phy);
1294                 writel_relaxed(mac_control, &slave->sliver->mac_control);
1295         }
1296
1297         slave->mac_control = mac_control;
1298 }
1299
1300 static int cpsw_get_common_speed(struct cpsw_common *cpsw)
1301 {
1302         int i, speed;
1303
1304         for (i = 0, speed = 0; i < cpsw->data.slaves; i++)
1305                 if (cpsw->slaves[i].phy && cpsw->slaves[i].phy->link)
1306                         speed += cpsw->slaves[i].phy->speed;
1307
1308         return speed;
1309 }
1310
1311 static int cpsw_need_resplit(struct cpsw_common *cpsw)
1312 {
1313         int i, rlim_ch_num;
1314         int speed, ch_rate;
1315
1316         /* re-split resources only in case speed was changed */
1317         speed = cpsw_get_common_speed(cpsw);
1318         if (speed == cpsw->speed || !speed)
1319                 return 0;
1320
1321         cpsw->speed = speed;
1322
1323         for (i = 0, rlim_ch_num = 0; i < cpsw->tx_ch_num; i++) {
1324                 ch_rate = cpdma_chan_get_rate(cpsw->txv[i].ch);
1325                 if (!ch_rate)
1326                         break;
1327
1328                 rlim_ch_num++;
1329         }
1330
1331         /* cases not dependent on speed */
1332         if (!rlim_ch_num || rlim_ch_num == cpsw->tx_ch_num)
1333                 return 0;
1334
1335         return 1;
1336 }
1337
1338 static void cpsw_adjust_link(struct net_device *ndev)
1339 {
1340         struct cpsw_priv        *priv = netdev_priv(ndev);
1341         struct cpsw_common      *cpsw = priv->cpsw;
1342         bool                    link = false;
1343
1344         for_each_slave(priv, _cpsw_adjust_link, priv, &link);
1345
1346         if (link) {
1347                 if (cpsw_need_resplit(cpsw))
1348                         cpsw_split_res(cpsw);
1349
1350                 netif_carrier_on(ndev);
1351                 if (netif_running(ndev))
1352                         netif_tx_wake_all_queues(ndev);
1353         } else {
1354                 netif_carrier_off(ndev);
1355                 netif_tx_stop_all_queues(ndev);
1356         }
1357 }
1358
1359 static int cpsw_get_coalesce(struct net_device *ndev,
1360                                 struct ethtool_coalesce *coal)
1361 {
1362         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1363
1364         coal->rx_coalesce_usecs = cpsw->coal_intvl;
1365         return 0;
1366 }
1367
1368 static int cpsw_set_coalesce(struct net_device *ndev,
1369                                 struct ethtool_coalesce *coal)
1370 {
1371         struct cpsw_priv *priv = netdev_priv(ndev);
1372         u32 int_ctrl;
1373         u32 num_interrupts = 0;
1374         u32 prescale = 0;
1375         u32 addnl_dvdr = 1;
1376         u32 coal_intvl = 0;
1377         struct cpsw_common *cpsw = priv->cpsw;
1378
1379         coal_intvl = coal->rx_coalesce_usecs;
1380
1381         int_ctrl =  readl(&cpsw->wr_regs->int_control);
1382         prescale = cpsw->bus_freq_mhz * 4;
1383
1384         if (!coal->rx_coalesce_usecs) {
1385                 int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN);
1386                 goto update_return;
1387         }
1388
1389         if (coal_intvl < CPSW_CMINTMIN_INTVL)
1390                 coal_intvl = CPSW_CMINTMIN_INTVL;
1391
1392         if (coal_intvl > CPSW_CMINTMAX_INTVL) {
1393                 /* Interrupt pacer works with 4us Pulse, we can
1394                  * throttle further by dilating the 4us pulse.
1395                  */
1396                 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
1397
1398                 if (addnl_dvdr > 1) {
1399                         prescale *= addnl_dvdr;
1400                         if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
1401                                 coal_intvl = (CPSW_CMINTMAX_INTVL
1402                                                 * addnl_dvdr);
1403                 } else {
1404                         addnl_dvdr = 1;
1405                         coal_intvl = CPSW_CMINTMAX_INTVL;
1406                 }
1407         }
1408
1409         num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
1410         writel(num_interrupts, &cpsw->wr_regs->rx_imax);
1411         writel(num_interrupts, &cpsw->wr_regs->tx_imax);
1412
1413         int_ctrl |= CPSW_INTPACEEN;
1414         int_ctrl &= (~CPSW_INTPRESCALE_MASK);
1415         int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
1416
1417 update_return:
1418         writel(int_ctrl, &cpsw->wr_regs->int_control);
1419
1420         cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
1421         cpsw->coal_intvl = coal_intvl;
1422
1423         return 0;
1424 }
1425
1426 static int cpsw_get_sset_count(struct net_device *ndev, int sset)
1427 {
1428         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1429
1430         switch (sset) {
1431         case ETH_SS_STATS:
1432                 return (CPSW_STATS_COMMON_LEN +
1433                        (cpsw->rx_ch_num + cpsw->tx_ch_num) *
1434                        CPSW_STATS_CH_LEN);
1435         default:
1436                 return -EOPNOTSUPP;
1437         }
1438 }
1439
1440 static void cpsw_add_ch_strings(u8 **p, int ch_num, int rx_dir)
1441 {
1442         int ch_stats_len;
1443         int line;
1444         int i;
1445
1446         ch_stats_len = CPSW_STATS_CH_LEN * ch_num;
1447         for (i = 0; i < ch_stats_len; i++) {
1448                 line = i % CPSW_STATS_CH_LEN;
1449                 snprintf(*p, ETH_GSTRING_LEN,
1450                          "%s DMA chan %ld: %s", rx_dir ? "Rx" : "Tx",
1451                          (long)(i / CPSW_STATS_CH_LEN),
1452                          cpsw_gstrings_ch_stats[line].stat_string);
1453                 *p += ETH_GSTRING_LEN;
1454         }
1455 }
1456
1457 static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1458 {
1459         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1460         u8 *p = data;
1461         int i;
1462
1463         switch (stringset) {
1464         case ETH_SS_STATS:
1465                 for (i = 0; i < CPSW_STATS_COMMON_LEN; i++) {
1466                         memcpy(p, cpsw_gstrings_stats[i].stat_string,
1467                                ETH_GSTRING_LEN);
1468                         p += ETH_GSTRING_LEN;
1469                 }
1470
1471                 cpsw_add_ch_strings(&p, cpsw->rx_ch_num, 1);
1472                 cpsw_add_ch_strings(&p, cpsw->tx_ch_num, 0);
1473                 break;
1474         }
1475 }
1476
1477 static void cpsw_get_ethtool_stats(struct net_device *ndev,
1478                                     struct ethtool_stats *stats, u64 *data)
1479 {
1480         u8 *p;
1481         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1482         struct cpdma_chan_stats ch_stats;
1483         int i, l, ch;
1484
1485         /* Collect Davinci CPDMA stats for Rx and Tx Channel */
1486         for (l = 0; l < CPSW_STATS_COMMON_LEN; l++)
1487                 data[l] = readl(cpsw->hw_stats +
1488                                 cpsw_gstrings_stats[l].stat_offset);
1489
1490         for (ch = 0; ch < cpsw->rx_ch_num; ch++) {
1491                 cpdma_chan_get_stats(cpsw->rxv[ch].ch, &ch_stats);
1492                 for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) {
1493                         p = (u8 *)&ch_stats +
1494                                 cpsw_gstrings_ch_stats[i].stat_offset;
1495                         data[l] = *(u32 *)p;
1496                 }
1497         }
1498
1499         for (ch = 0; ch < cpsw->tx_ch_num; ch++) {
1500                 cpdma_chan_get_stats(cpsw->txv[ch].ch, &ch_stats);
1501                 for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) {
1502                         p = (u8 *)&ch_stats +
1503                                 cpsw_gstrings_ch_stats[i].stat_offset;
1504                         data[l] = *(u32 *)p;
1505                 }
1506         }
1507 }
1508
1509 static inline void cpsw_add_dual_emac_def_ale_entries(
1510                 struct cpsw_priv *priv, struct cpsw_slave *slave,
1511                 u32 slave_port)
1512 {
1513         struct cpsw_common *cpsw = priv->cpsw;
1514         u32 port_mask = 1 << slave_port | ALE_PORT_HOST;
1515
1516         if (cpsw->version == CPSW_VERSION_1)
1517                 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
1518         else
1519                 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
1520         cpsw_ale_add_vlan(cpsw->ale, slave->port_vlan, port_mask,
1521                           port_mask, port_mask, 0);
1522         cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1523                            ALE_PORT_HOST, ALE_VLAN, slave->port_vlan, 0);
1524         cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr,
1525                            HOST_PORT_NUM, ALE_VLAN |
1526                            ALE_SECURE, slave->port_vlan);
1527         cpsw_ale_control_set(cpsw->ale, slave_port,
1528                              ALE_PORT_DROP_UNKNOWN_VLAN, 1);
1529 }
1530
1531 static void soft_reset_slave(struct cpsw_slave *slave)
1532 {
1533         char name[32];
1534
1535         snprintf(name, sizeof(name), "slave-%d", slave->slave_num);
1536         soft_reset(name, &slave->sliver->soft_reset);
1537 }
1538
1539 static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
1540 {
1541         u32 slave_port;
1542         struct phy_device *phy;
1543         struct cpsw_common *cpsw = priv->cpsw;
1544
1545         soft_reset_slave(slave);
1546
1547         /* setup priority mapping */
1548         writel_relaxed(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
1549
1550         switch (cpsw->version) {
1551         case CPSW_VERSION_1:
1552                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
1553                 /* Increase RX FIFO size to 5 for supporting fullduplex
1554                  * flow control mode
1555                  */
1556                 slave_write(slave,
1557                             (CPSW_MAX_BLKS_TX << CPSW_MAX_BLKS_TX_SHIFT) |
1558                             CPSW_MAX_BLKS_RX, CPSW1_MAX_BLKS);
1559                 break;
1560         case CPSW_VERSION_2:
1561         case CPSW_VERSION_3:
1562         case CPSW_VERSION_4:
1563                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
1564                 /* Increase RX FIFO size to 5 for supporting fullduplex
1565                  * flow control mode
1566                  */
1567                 slave_write(slave,
1568                             (CPSW_MAX_BLKS_TX << CPSW_MAX_BLKS_TX_SHIFT) |
1569                             CPSW_MAX_BLKS_RX, CPSW2_MAX_BLKS);
1570                 break;
1571         }
1572
1573         /* setup max packet size, and mac address */
1574         writel_relaxed(cpsw->rx_packet_max, &slave->sliver->rx_maxlen);
1575         cpsw_set_slave_mac(slave, priv);
1576
1577         slave->mac_control = 0; /* no link yet */
1578
1579         slave_port = cpsw_get_slave_port(slave->slave_num);
1580
1581         if (cpsw->data.dual_emac)
1582                 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
1583         else
1584                 cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1585                                    1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
1586
1587         if (slave->data->phy_node) {
1588                 phy = of_phy_connect(priv->ndev, slave->data->phy_node,
1589                                  &cpsw_adjust_link, 0, slave->data->phy_if);
1590                 if (!phy) {
1591                         dev_err(priv->dev, "phy \"%pOF\" not found on slave %d\n",
1592                                 slave->data->phy_node,
1593                                 slave->slave_num);
1594                         return;
1595                 }
1596         } else {
1597                 phy = phy_connect(priv->ndev, slave->data->phy_id,
1598                                  &cpsw_adjust_link, slave->data->phy_if);
1599                 if (IS_ERR(phy)) {
1600                         dev_err(priv->dev,
1601                                 "phy \"%s\" not found on slave %d, err %ld\n",
1602                                 slave->data->phy_id, slave->slave_num,
1603                                 PTR_ERR(phy));
1604                         return;
1605                 }
1606         }
1607
1608         slave->phy = phy;
1609
1610         phy_attached_info(slave->phy);
1611
1612         phy_start(slave->phy);
1613
1614         /* Configure GMII_SEL register */
1615         if (!IS_ERR(slave->data->ifphy))
1616                 phy_set_mode_ext(slave->data->ifphy, PHY_MODE_ETHERNET,
1617                                  slave->data->phy_if);
1618         else
1619                 cpsw_phy_sel(cpsw->dev, slave->phy->interface,
1620                              slave->slave_num);
1621 }
1622
1623 static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
1624 {
1625         struct cpsw_common *cpsw = priv->cpsw;
1626         const int vlan = cpsw->data.default_vlan;
1627         u32 reg;
1628         int i;
1629         int unreg_mcast_mask;
1630
1631         reg = (cpsw->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
1632                CPSW2_PORT_VLAN;
1633
1634         writel(vlan, &cpsw->host_port_regs->port_vlan);
1635
1636         for (i = 0; i < cpsw->data.slaves; i++)
1637                 slave_write(cpsw->slaves + i, vlan, reg);
1638
1639         if (priv->ndev->flags & IFF_ALLMULTI)
1640                 unreg_mcast_mask = ALE_ALL_PORTS;
1641         else
1642                 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1643
1644         cpsw_ale_add_vlan(cpsw->ale, vlan, ALE_ALL_PORTS,
1645                           ALE_ALL_PORTS, ALE_ALL_PORTS,
1646                           unreg_mcast_mask);
1647 }
1648
1649 static void cpsw_init_host_port(struct cpsw_priv *priv)
1650 {
1651         u32 fifo_mode;
1652         u32 control_reg;
1653         struct cpsw_common *cpsw = priv->cpsw;
1654
1655         /* soft reset the controller and initialize ale */
1656         soft_reset("cpsw", &cpsw->regs->soft_reset);
1657         cpsw_ale_start(cpsw->ale);
1658
1659         /* switch to vlan unaware mode */
1660         cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_VLAN_AWARE,
1661                              CPSW_ALE_VLAN_AWARE);
1662         control_reg = readl(&cpsw->regs->control);
1663         control_reg |= CPSW_VLAN_AWARE | CPSW_RX_VLAN_ENCAP;
1664         writel(control_reg, &cpsw->regs->control);
1665         fifo_mode = (cpsw->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
1666                      CPSW_FIFO_NORMAL_MODE;
1667         writel(fifo_mode, &cpsw->host_port_regs->tx_in_ctl);
1668
1669         /* setup host port priority mapping */
1670         writel_relaxed(CPDMA_TX_PRIORITY_MAP,
1671                        &cpsw->host_port_regs->cpdma_tx_pri_map);
1672         writel_relaxed(0, &cpsw->host_port_regs->cpdma_rx_chan_map);
1673
1674         cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM,
1675                              ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1676
1677         if (!cpsw->data.dual_emac) {
1678                 cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM,
1679                                    0, 0);
1680                 cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1681                                    ALE_PORT_HOST, 0, 0, ALE_MCAST_FWD_2);
1682         }
1683 }
1684
1685 static int cpsw_fill_rx_channels(struct cpsw_priv *priv)
1686 {
1687         struct cpsw_common *cpsw = priv->cpsw;
1688         struct sk_buff *skb;
1689         int ch_buf_num;
1690         int ch, i, ret;
1691
1692         for (ch = 0; ch < cpsw->rx_ch_num; ch++) {
1693                 ch_buf_num = cpdma_chan_get_rx_buf_num(cpsw->rxv[ch].ch);
1694                 for (i = 0; i < ch_buf_num; i++) {
1695                         skb = __netdev_alloc_skb_ip_align(priv->ndev,
1696                                                           cpsw->rx_packet_max,
1697                                                           GFP_KERNEL);
1698                         if (!skb) {
1699                                 cpsw_err(priv, ifup, "cannot allocate skb\n");
1700                                 return -ENOMEM;
1701                         }
1702
1703                         skb_set_queue_mapping(skb, ch);
1704                         ret = cpdma_chan_submit(cpsw->rxv[ch].ch, skb,
1705                                                 skb->data, skb_tailroom(skb),
1706                                                 0);
1707                         if (ret < 0) {
1708                                 cpsw_err(priv, ifup,
1709                                          "cannot submit skb to channel %d rx, error %d\n",
1710                                          ch, ret);
1711                                 kfree_skb(skb);
1712                                 return ret;
1713                         }
1714                         kmemleak_not_leak(skb);
1715                 }
1716
1717                 cpsw_info(priv, ifup, "ch %d rx, submitted %d descriptors\n",
1718                           ch, ch_buf_num);
1719         }
1720
1721         return 0;
1722 }
1723
1724 static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_common *cpsw)
1725 {
1726         u32 slave_port;
1727
1728         slave_port = cpsw_get_slave_port(slave->slave_num);
1729
1730         if (!slave->phy)
1731                 return;
1732         phy_stop(slave->phy);
1733         phy_disconnect(slave->phy);
1734         slave->phy = NULL;
1735         cpsw_ale_control_set(cpsw->ale, slave_port,
1736                              ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1737         soft_reset_slave(slave);
1738 }
1739
1740 static int cpsw_tc_to_fifo(int tc, int num_tc)
1741 {
1742         if (tc == num_tc - 1)
1743                 return 0;
1744
1745         return CPSW_FIFO_SHAPERS_NUM - tc;
1746 }
1747
1748 static int cpsw_set_fifo_bw(struct cpsw_priv *priv, int fifo, int bw)
1749 {
1750         struct cpsw_common *cpsw = priv->cpsw;
1751         u32 val = 0, send_pct, shift;
1752         struct cpsw_slave *slave;
1753         int pct = 0, i;
1754
1755         if (bw > priv->shp_cfg_speed * 1000)
1756                 goto err;
1757
1758         /* shaping has to stay enabled for highest fifos linearly
1759          * and fifo bw no more then interface can allow
1760          */
1761         slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
1762         send_pct = slave_read(slave, SEND_PERCENT);
1763         for (i = CPSW_FIFO_SHAPERS_NUM; i > 0; i--) {
1764                 if (!bw) {
1765                         if (i >= fifo || !priv->fifo_bw[i])
1766                                 continue;
1767
1768                         dev_warn(priv->dev, "Prev FIFO%d is shaped", i);
1769                         continue;
1770                 }
1771
1772                 if (!priv->fifo_bw[i] && i > fifo) {
1773                         dev_err(priv->dev, "Upper FIFO%d is not shaped", i);
1774                         return -EINVAL;
1775                 }
1776
1777                 shift = (i - 1) * 8;
1778                 if (i == fifo) {
1779                         send_pct &= ~(CPSW_PCT_MASK << shift);
1780                         val = DIV_ROUND_UP(bw, priv->shp_cfg_speed * 10);
1781                         if (!val)
1782                                 val = 1;
1783
1784                         send_pct |= val << shift;
1785                         pct += val;
1786                         continue;
1787                 }
1788
1789                 if (priv->fifo_bw[i])
1790                         pct += (send_pct >> shift) & CPSW_PCT_MASK;
1791         }
1792
1793         if (pct >= 100)
1794                 goto err;
1795
1796         slave_write(slave, send_pct, SEND_PERCENT);
1797         priv->fifo_bw[fifo] = bw;
1798
1799         dev_warn(priv->dev, "set FIFO%d bw = %d\n", fifo,
1800                  DIV_ROUND_CLOSEST(val * priv->shp_cfg_speed, 100));
1801
1802         return 0;
1803 err:
1804         dev_err(priv->dev, "Bandwidth doesn't fit in tc configuration");
1805         return -EINVAL;
1806 }
1807
1808 static int cpsw_set_fifo_rlimit(struct cpsw_priv *priv, int fifo, int bw)
1809 {
1810         struct cpsw_common *cpsw = priv->cpsw;
1811         struct cpsw_slave *slave;
1812         u32 tx_in_ctl_rg, val;
1813         int ret;
1814
1815         ret = cpsw_set_fifo_bw(priv, fifo, bw);
1816         if (ret)
1817                 return ret;
1818
1819         slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
1820         tx_in_ctl_rg = cpsw->version == CPSW_VERSION_1 ?
1821                        CPSW1_TX_IN_CTL : CPSW2_TX_IN_CTL;
1822
1823         if (!bw)
1824                 cpsw_fifo_shp_on(priv, fifo, bw);
1825
1826         val = slave_read(slave, tx_in_ctl_rg);
1827         if (cpsw_shp_is_off(priv)) {
1828                 /* disable FIFOs rate limited queues */
1829                 val &= ~(0xf << CPSW_FIFO_RATE_EN_SHIFT);
1830
1831                 /* set type of FIFO queues to normal priority mode */
1832                 val &= ~(3 << CPSW_FIFO_QUEUE_TYPE_SHIFT);
1833
1834                 /* set type of FIFO queues to be rate limited */
1835                 if (bw)
1836                         val |= 2 << CPSW_FIFO_QUEUE_TYPE_SHIFT;
1837                 else
1838                         priv->shp_cfg_speed = 0;
1839         }
1840
1841         /* toggle a FIFO rate limited queue */
1842         if (bw)
1843                 val |= BIT(fifo + CPSW_FIFO_RATE_EN_SHIFT);
1844         else
1845                 val &= ~BIT(fifo + CPSW_FIFO_RATE_EN_SHIFT);
1846         slave_write(slave, val, tx_in_ctl_rg);
1847
1848         /* FIFO transmit shape enable */
1849         cpsw_fifo_shp_on(priv, fifo, bw);
1850         return 0;
1851 }
1852
1853 /* Defaults:
1854  * class A - prio 3
1855  * class B - prio 2
1856  * shaping for class A should be set first
1857  */
1858 static int cpsw_set_cbs(struct net_device *ndev,
1859                         struct tc_cbs_qopt_offload *qopt)
1860 {
1861         struct cpsw_priv *priv = netdev_priv(ndev);
1862         struct cpsw_common *cpsw = priv->cpsw;
1863         struct cpsw_slave *slave;
1864         int prev_speed = 0;
1865         int tc, ret, fifo;
1866         u32 bw = 0;
1867
1868         tc = netdev_txq_to_tc(priv->ndev, qopt->queue);
1869
1870         /* enable channels in backward order, as highest FIFOs must be rate
1871          * limited first and for compliance with CPDMA rate limited channels
1872          * that also used in bacward order. FIFO0 cannot be rate limited.
1873          */
1874         fifo = cpsw_tc_to_fifo(tc, ndev->num_tc);
1875         if (!fifo) {
1876                 dev_err(priv->dev, "Last tc%d can't be rate limited", tc);
1877                 return -EINVAL;
1878         }
1879
1880         /* do nothing, it's disabled anyway */
1881         if (!qopt->enable && !priv->fifo_bw[fifo])
1882                 return 0;
1883
1884         /* shapers can be set if link speed is known */
1885         slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
1886         if (slave->phy && slave->phy->link) {
1887                 if (priv->shp_cfg_speed &&
1888                     priv->shp_cfg_speed != slave->phy->speed)
1889                         prev_speed = priv->shp_cfg_speed;
1890
1891                 priv->shp_cfg_speed = slave->phy->speed;
1892         }
1893
1894         if (!priv->shp_cfg_speed) {
1895                 dev_err(priv->dev, "Link speed is not known");
1896                 return -1;
1897         }
1898
1899         ret = pm_runtime_get_sync(cpsw->dev);
1900         if (ret < 0) {
1901                 pm_runtime_put_noidle(cpsw->dev);
1902                 return ret;
1903         }
1904
1905         bw = qopt->enable ? qopt->idleslope : 0;
1906         ret = cpsw_set_fifo_rlimit(priv, fifo, bw);
1907         if (ret) {
1908                 priv->shp_cfg_speed = prev_speed;
1909                 prev_speed = 0;
1910         }
1911
1912         if (bw && prev_speed)
1913                 dev_warn(priv->dev,
1914                          "Speed was changed, CBS shaper speeds are changed!");
1915
1916         pm_runtime_put_sync(cpsw->dev);
1917         return ret;
1918 }
1919
1920 static void cpsw_cbs_resume(struct cpsw_slave *slave, struct cpsw_priv *priv)
1921 {
1922         int fifo, bw;
1923
1924         for (fifo = CPSW_FIFO_SHAPERS_NUM; fifo > 0; fifo--) {
1925                 bw = priv->fifo_bw[fifo];
1926                 if (!bw)
1927                         continue;
1928
1929                 cpsw_set_fifo_rlimit(priv, fifo, bw);
1930         }
1931 }
1932
1933 static void cpsw_mqprio_resume(struct cpsw_slave *slave, struct cpsw_priv *priv)
1934 {
1935         struct cpsw_common *cpsw = priv->cpsw;
1936         u32 tx_prio_map = 0;
1937         int i, tc, fifo;
1938         u32 tx_prio_rg;
1939
1940         if (!priv->mqprio_hw)
1941                 return;
1942
1943         for (i = 0; i < 8; i++) {
1944                 tc = netdev_get_prio_tc_map(priv->ndev, i);
1945                 fifo = CPSW_FIFO_SHAPERS_NUM - tc;
1946                 tx_prio_map |= fifo << (4 * i);
1947         }
1948
1949         tx_prio_rg = cpsw->version == CPSW_VERSION_1 ?
1950                      CPSW1_TX_PRI_MAP : CPSW2_TX_PRI_MAP;
1951
1952         slave_write(slave, tx_prio_map, tx_prio_rg);
1953 }
1954
1955 static int cpsw_restore_vlans(struct net_device *vdev, int vid, void *arg)
1956 {
1957         struct cpsw_priv *priv = arg;
1958
1959         if (!vdev)
1960                 return 0;
1961
1962         cpsw_ndo_vlan_rx_add_vid(priv->ndev, 0, vid);
1963         return 0;
1964 }
1965
1966 /* restore resources after port reset */
1967 static void cpsw_restore(struct cpsw_priv *priv)
1968 {
1969         /* restore vlan configurations */
1970         vlan_for_each(priv->ndev, cpsw_restore_vlans, priv);
1971
1972         /* restore MQPRIO offload */
1973         for_each_slave(priv, cpsw_mqprio_resume, priv);
1974
1975         /* restore CBS offload */
1976         for_each_slave(priv, cpsw_cbs_resume, priv);
1977 }
1978
1979 static int cpsw_ndo_open(struct net_device *ndev)
1980 {
1981         struct cpsw_priv *priv = netdev_priv(ndev);
1982         struct cpsw_common *cpsw = priv->cpsw;
1983         int ret;
1984         u32 reg;
1985
1986         ret = pm_runtime_get_sync(cpsw->dev);
1987         if (ret < 0) {
1988                 pm_runtime_put_noidle(cpsw->dev);
1989                 return ret;
1990         }
1991
1992         netif_carrier_off(ndev);
1993
1994         /* Notify the stack of the actual queue counts. */
1995         ret = netif_set_real_num_tx_queues(ndev, cpsw->tx_ch_num);
1996         if (ret) {
1997                 dev_err(priv->dev, "cannot set real number of tx queues\n");
1998                 goto err_cleanup;
1999         }
2000
2001         ret = netif_set_real_num_rx_queues(ndev, cpsw->rx_ch_num);
2002         if (ret) {
2003                 dev_err(priv->dev, "cannot set real number of rx queues\n");
2004                 goto err_cleanup;
2005         }
2006
2007         reg = cpsw->version;
2008
2009         dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
2010                  CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
2011                  CPSW_RTL_VERSION(reg));
2012
2013         /* Initialize host and slave ports */
2014         if (!cpsw->usage_count)
2015                 cpsw_init_host_port(priv);
2016         for_each_slave(priv, cpsw_slave_open, priv);
2017
2018         /* Add default VLAN */
2019         if (!cpsw->data.dual_emac)
2020                 cpsw_add_default_vlan(priv);
2021         else
2022                 cpsw_ale_add_vlan(cpsw->ale, cpsw->data.default_vlan,
2023                                   ALE_ALL_PORTS, ALE_ALL_PORTS, 0, 0);
2024
2025         /* initialize shared resources for every ndev */
2026         if (!cpsw->usage_count) {
2027                 /* disable priority elevation */
2028                 writel_relaxed(0, &cpsw->regs->ptype);
2029
2030                 /* enable statistics collection only on all ports */
2031                 writel_relaxed(0x7, &cpsw->regs->stat_port_en);
2032
2033                 /* Enable internal fifo flow control */
2034                 writel(0x7, &cpsw->regs->flow_control);
2035
2036                 napi_enable(&cpsw->napi_rx);
2037                 napi_enable(&cpsw->napi_tx);
2038
2039                 if (cpsw->tx_irq_disabled) {
2040                         cpsw->tx_irq_disabled = false;
2041                         enable_irq(cpsw->irqs_table[1]);
2042                 }
2043
2044                 if (cpsw->rx_irq_disabled) {
2045                         cpsw->rx_irq_disabled = false;
2046                         enable_irq(cpsw->irqs_table[0]);
2047                 }
2048
2049                 ret = cpsw_fill_rx_channels(priv);
2050                 if (ret < 0)
2051                         goto err_cleanup;
2052
2053                 if (cpts_register(cpsw->cpts))
2054                         dev_err(priv->dev, "error registering cpts device\n");
2055
2056         }
2057
2058         cpsw_restore(priv);
2059
2060         /* Enable Interrupt pacing if configured */
2061         if (cpsw->coal_intvl != 0) {
2062                 struct ethtool_coalesce coal;
2063
2064                 coal.rx_coalesce_usecs = cpsw->coal_intvl;
2065                 cpsw_set_coalesce(ndev, &coal);
2066         }
2067
2068         cpdma_ctlr_start(cpsw->dma);
2069         cpsw_intr_enable(cpsw);
2070         cpsw->usage_count++;
2071
2072         return 0;
2073
2074 err_cleanup:
2075         cpdma_ctlr_stop(cpsw->dma);
2076         for_each_slave(priv, cpsw_slave_stop, cpsw);
2077         pm_runtime_put_sync(cpsw->dev);
2078         netif_carrier_off(priv->ndev);
2079         return ret;
2080 }
2081
2082 static int cpsw_ndo_stop(struct net_device *ndev)
2083 {
2084         struct cpsw_priv *priv = netdev_priv(ndev);
2085         struct cpsw_common *cpsw = priv->cpsw;
2086
2087         cpsw_info(priv, ifdown, "shutting down cpsw device\n");
2088         __hw_addr_ref_unsync_dev(&ndev->mc, ndev, cpsw_purge_all_mc);
2089         netif_tx_stop_all_queues(priv->ndev);
2090         netif_carrier_off(priv->ndev);
2091
2092         if (cpsw->usage_count <= 1) {
2093                 napi_disable(&cpsw->napi_rx);
2094                 napi_disable(&cpsw->napi_tx);
2095                 cpts_unregister(cpsw->cpts);
2096                 cpsw_intr_disable(cpsw);
2097                 cpdma_ctlr_stop(cpsw->dma);
2098                 cpsw_ale_stop(cpsw->ale);
2099         }
2100         for_each_slave(priv, cpsw_slave_stop, cpsw);
2101
2102         if (cpsw_need_resplit(cpsw))
2103                 cpsw_split_res(cpsw);
2104
2105         cpsw->usage_count--;
2106         pm_runtime_put_sync(cpsw->dev);
2107         return 0;
2108 }
2109
2110 static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
2111                                        struct net_device *ndev)
2112 {
2113         struct cpsw_priv *priv = netdev_priv(ndev);
2114         struct cpsw_common *cpsw = priv->cpsw;
2115         struct cpts *cpts = cpsw->cpts;
2116         struct netdev_queue *txq;
2117         struct cpdma_chan *txch;
2118         int ret, q_idx;
2119
2120         if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
2121                 cpsw_err(priv, tx_err, "packet pad failed\n");
2122                 ndev->stats.tx_dropped++;
2123                 return NET_XMIT_DROP;
2124         }
2125
2126         if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
2127             priv->tx_ts_enabled && cpts_can_timestamp(cpts, skb))
2128                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2129
2130         q_idx = skb_get_queue_mapping(skb);
2131         if (q_idx >= cpsw->tx_ch_num)
2132                 q_idx = q_idx % cpsw->tx_ch_num;
2133
2134         txch = cpsw->txv[q_idx].ch;
2135         txq = netdev_get_tx_queue(ndev, q_idx);
2136         skb_tx_timestamp(skb);
2137         ret = cpdma_chan_submit(txch, skb, skb->data, skb->len,
2138                                 priv->emac_port + cpsw->data.dual_emac);
2139         if (unlikely(ret != 0)) {
2140                 cpsw_err(priv, tx_err, "desc submit failed\n");
2141                 goto fail;
2142         }
2143
2144         /* If there is no more tx desc left free then we need to
2145          * tell the kernel to stop sending us tx frames.
2146          */
2147         if (unlikely(!cpdma_check_free_tx_desc(txch))) {
2148                 netif_tx_stop_queue(txq);
2149
2150                 /* Barrier, so that stop_queue visible to other cpus */
2151                 smp_mb__after_atomic();
2152
2153                 if (cpdma_check_free_tx_desc(txch))
2154                         netif_tx_wake_queue(txq);
2155         }
2156
2157         return NETDEV_TX_OK;
2158 fail:
2159         ndev->stats.tx_dropped++;
2160         netif_tx_stop_queue(txq);
2161
2162         /* Barrier, so that stop_queue visible to other cpus */
2163         smp_mb__after_atomic();
2164
2165         if (cpdma_check_free_tx_desc(txch))
2166                 netif_tx_wake_queue(txq);
2167
2168         return NETDEV_TX_BUSY;
2169 }
2170
2171 #if IS_ENABLED(CONFIG_TI_CPTS)
2172
2173 static void cpsw_hwtstamp_v1(struct cpsw_priv *priv)
2174 {
2175         struct cpsw_common *cpsw = priv->cpsw;
2176         struct cpsw_slave *slave = &cpsw->slaves[cpsw->data.active_slave];
2177         u32 ts_en, seq_id;
2178
2179         if (!priv->tx_ts_enabled && !priv->rx_ts_enabled) {
2180                 slave_write(slave, 0, CPSW1_TS_CTL);
2181                 return;
2182         }
2183
2184         seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
2185         ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
2186
2187         if (priv->tx_ts_enabled)
2188                 ts_en |= CPSW_V1_TS_TX_EN;
2189
2190         if (priv->rx_ts_enabled)
2191                 ts_en |= CPSW_V1_TS_RX_EN;
2192
2193         slave_write(slave, ts_en, CPSW1_TS_CTL);
2194         slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
2195 }
2196
2197 static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
2198 {
2199         struct cpsw_slave *slave;
2200         struct cpsw_common *cpsw = priv->cpsw;
2201         u32 ctrl, mtype;
2202
2203         slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
2204
2205         ctrl = slave_read(slave, CPSW2_CONTROL);
2206         switch (cpsw->version) {
2207         case CPSW_VERSION_2:
2208                 ctrl &= ~CTRL_V2_ALL_TS_MASK;
2209
2210                 if (priv->tx_ts_enabled)
2211                         ctrl |= CTRL_V2_TX_TS_BITS;
2212
2213                 if (priv->rx_ts_enabled)
2214                         ctrl |= CTRL_V2_RX_TS_BITS;
2215                 break;
2216         case CPSW_VERSION_3:
2217         default:
2218                 ctrl &= ~CTRL_V3_ALL_TS_MASK;
2219
2220                 if (priv->tx_ts_enabled)
2221                         ctrl |= CTRL_V3_TX_TS_BITS;
2222
2223                 if (priv->rx_ts_enabled)
2224                         ctrl |= CTRL_V3_RX_TS_BITS;
2225                 break;
2226         }
2227
2228         mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
2229
2230         slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
2231         slave_write(slave, ctrl, CPSW2_CONTROL);
2232         writel_relaxed(ETH_P_1588, &cpsw->regs->ts_ltype);
2233         writel_relaxed(ETH_P_8021Q, &cpsw->regs->vlan_ltype);
2234 }
2235
2236 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
2237 {
2238         struct cpsw_priv *priv = netdev_priv(dev);
2239         struct hwtstamp_config cfg;
2240         struct cpsw_common *cpsw = priv->cpsw;
2241
2242         if (cpsw->version != CPSW_VERSION_1 &&
2243             cpsw->version != CPSW_VERSION_2 &&
2244             cpsw->version != CPSW_VERSION_3)
2245                 return -EOPNOTSUPP;
2246
2247         if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
2248                 return -EFAULT;
2249
2250         /* reserved for future extensions */
2251         if (cfg.flags)
2252                 return -EINVAL;
2253
2254         if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
2255                 return -ERANGE;
2256
2257         switch (cfg.rx_filter) {
2258         case HWTSTAMP_FILTER_NONE:
2259                 priv->rx_ts_enabled = 0;
2260                 break;
2261         case HWTSTAMP_FILTER_ALL:
2262         case HWTSTAMP_FILTER_NTP_ALL:
2263                 return -ERANGE;
2264         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
2265         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
2266         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
2267                 priv->rx_ts_enabled = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
2268                 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
2269                 break;
2270         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2271         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2272         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2273         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
2274         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
2275         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
2276         case HWTSTAMP_FILTER_PTP_V2_EVENT:
2277         case HWTSTAMP_FILTER_PTP_V2_SYNC:
2278         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
2279                 priv->rx_ts_enabled = HWTSTAMP_FILTER_PTP_V2_EVENT;
2280                 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
2281                 break;
2282         default:
2283                 return -ERANGE;
2284         }
2285
2286         priv->tx_ts_enabled = cfg.tx_type == HWTSTAMP_TX_ON;
2287
2288         switch (cpsw->version) {
2289         case CPSW_VERSION_1:
2290                 cpsw_hwtstamp_v1(priv);
2291                 break;
2292         case CPSW_VERSION_2:
2293         case CPSW_VERSION_3:
2294                 cpsw_hwtstamp_v2(priv);
2295                 break;
2296         default:
2297                 WARN_ON(1);
2298         }
2299
2300         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
2301 }
2302
2303 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
2304 {
2305         struct cpsw_common *cpsw = ndev_to_cpsw(dev);
2306         struct cpsw_priv *priv = netdev_priv(dev);
2307         struct hwtstamp_config cfg;
2308
2309         if (cpsw->version != CPSW_VERSION_1 &&
2310             cpsw->version != CPSW_VERSION_2 &&
2311             cpsw->version != CPSW_VERSION_3)
2312                 return -EOPNOTSUPP;
2313
2314         cfg.flags = 0;
2315         cfg.tx_type = priv->tx_ts_enabled ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
2316         cfg.rx_filter = priv->rx_ts_enabled;
2317
2318         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
2319 }
2320 #else
2321 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
2322 {
2323         return -EOPNOTSUPP;
2324 }
2325
2326 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
2327 {
2328         return -EOPNOTSUPP;
2329 }
2330 #endif /*CONFIG_TI_CPTS*/
2331
2332 static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
2333 {
2334         struct cpsw_priv *priv = netdev_priv(dev);
2335         struct cpsw_common *cpsw = priv->cpsw;
2336         int slave_no = cpsw_slave_index(cpsw, priv);
2337
2338         if (!netif_running(dev))
2339                 return -EINVAL;
2340
2341         switch (cmd) {
2342         case SIOCSHWTSTAMP:
2343                 return cpsw_hwtstamp_set(dev, req);
2344         case SIOCGHWTSTAMP:
2345                 return cpsw_hwtstamp_get(dev, req);
2346         }
2347
2348         if (!cpsw->slaves[slave_no].phy)
2349                 return -EOPNOTSUPP;
2350         return phy_mii_ioctl(cpsw->slaves[slave_no].phy, req, cmd);
2351 }
2352
2353 static void cpsw_ndo_tx_timeout(struct net_device *ndev)
2354 {
2355         struct cpsw_priv *priv = netdev_priv(ndev);
2356         struct cpsw_common *cpsw = priv->cpsw;
2357         int ch;
2358
2359         cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
2360         ndev->stats.tx_errors++;
2361         cpsw_intr_disable(cpsw);
2362         for (ch = 0; ch < cpsw->tx_ch_num; ch++) {
2363                 cpdma_chan_stop(cpsw->txv[ch].ch);
2364                 cpdma_chan_start(cpsw->txv[ch].ch);
2365         }
2366
2367         cpsw_intr_enable(cpsw);
2368         netif_trans_update(ndev);
2369         netif_tx_wake_all_queues(ndev);
2370 }
2371
2372 static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
2373 {
2374         struct cpsw_priv *priv = netdev_priv(ndev);
2375         struct sockaddr *addr = (struct sockaddr *)p;
2376         struct cpsw_common *cpsw = priv->cpsw;
2377         int flags = 0;
2378         u16 vid = 0;
2379         int ret;
2380
2381         if (!is_valid_ether_addr(addr->sa_data))
2382                 return -EADDRNOTAVAIL;
2383
2384         ret = pm_runtime_get_sync(cpsw->dev);
2385         if (ret < 0) {
2386                 pm_runtime_put_noidle(cpsw->dev);
2387                 return ret;
2388         }
2389
2390         if (cpsw->data.dual_emac) {
2391                 vid = cpsw->slaves[priv->emac_port].port_vlan;
2392                 flags = ALE_VLAN;
2393         }
2394
2395         cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM,
2396                            flags, vid);
2397         cpsw_ale_add_ucast(cpsw->ale, addr->sa_data, HOST_PORT_NUM,
2398                            flags, vid);
2399
2400         memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
2401         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
2402         for_each_slave(priv, cpsw_set_slave_mac, priv);
2403
2404         pm_runtime_put(cpsw->dev);
2405
2406         return 0;
2407 }
2408
2409 #ifdef CONFIG_NET_POLL_CONTROLLER
2410 static void cpsw_ndo_poll_controller(struct net_device *ndev)
2411 {
2412         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2413
2414         cpsw_intr_disable(cpsw);
2415         cpsw_rx_interrupt(cpsw->irqs_table[0], cpsw);
2416         cpsw_tx_interrupt(cpsw->irqs_table[1], cpsw);
2417         cpsw_intr_enable(cpsw);
2418 }
2419 #endif
2420
2421 static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
2422                                 unsigned short vid)
2423 {
2424         int ret;
2425         int unreg_mcast_mask = 0;
2426         int mcast_mask;
2427         u32 port_mask;
2428         struct cpsw_common *cpsw = priv->cpsw;
2429
2430         if (cpsw->data.dual_emac) {
2431                 port_mask = (1 << (priv->emac_port + 1)) | ALE_PORT_HOST;
2432
2433                 mcast_mask = ALE_PORT_HOST;
2434                 if (priv->ndev->flags & IFF_ALLMULTI)
2435                         unreg_mcast_mask = mcast_mask;
2436         } else {
2437                 port_mask = ALE_ALL_PORTS;
2438                 mcast_mask = port_mask;
2439
2440                 if (priv->ndev->flags & IFF_ALLMULTI)
2441                         unreg_mcast_mask = ALE_ALL_PORTS;
2442                 else
2443                         unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
2444         }
2445
2446         ret = cpsw_ale_add_vlan(cpsw->ale, vid, port_mask, 0, port_mask,
2447                                 unreg_mcast_mask);
2448         if (ret != 0)
2449                 return ret;
2450
2451         ret = cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr,
2452                                  HOST_PORT_NUM, ALE_VLAN, vid);
2453         if (ret != 0)
2454                 goto clean_vid;
2455
2456         ret = cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
2457                                  mcast_mask, ALE_VLAN, vid, 0);
2458         if (ret != 0)
2459                 goto clean_vlan_ucast;
2460         return 0;
2461
2462 clean_vlan_ucast:
2463         cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr,
2464                            HOST_PORT_NUM, ALE_VLAN, vid);
2465 clean_vid:
2466         cpsw_ale_del_vlan(cpsw->ale, vid, 0);
2467         return ret;
2468 }
2469
2470 static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
2471                                     __be16 proto, u16 vid)
2472 {
2473         struct cpsw_priv *priv = netdev_priv(ndev);
2474         struct cpsw_common *cpsw = priv->cpsw;
2475         int ret;
2476
2477         if (vid == cpsw->data.default_vlan)
2478                 return 0;
2479
2480         ret = pm_runtime_get_sync(cpsw->dev);
2481         if (ret < 0) {
2482                 pm_runtime_put_noidle(cpsw->dev);
2483                 return ret;
2484         }
2485
2486         if (cpsw->data.dual_emac) {
2487                 /* In dual EMAC, reserved VLAN id should not be used for
2488                  * creating VLAN interfaces as this can break the dual
2489                  * EMAC port separation
2490                  */
2491                 int i;
2492
2493                 for (i = 0; i < cpsw->data.slaves; i++) {
2494                         if (vid == cpsw->slaves[i].port_vlan) {
2495                                 ret = -EINVAL;
2496                                 goto err;
2497                         }
2498                 }
2499         }
2500
2501         dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
2502         ret = cpsw_add_vlan_ale_entry(priv, vid);
2503 err:
2504         pm_runtime_put(cpsw->dev);
2505         return ret;
2506 }
2507
2508 static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
2509                                      __be16 proto, u16 vid)
2510 {
2511         struct cpsw_priv *priv = netdev_priv(ndev);
2512         struct cpsw_common *cpsw = priv->cpsw;
2513         int ret;
2514
2515         if (vid == cpsw->data.default_vlan)
2516                 return 0;
2517
2518         ret = pm_runtime_get_sync(cpsw->dev);
2519         if (ret < 0) {
2520                 pm_runtime_put_noidle(cpsw->dev);
2521                 return ret;
2522         }
2523
2524         if (cpsw->data.dual_emac) {
2525                 int i;
2526
2527                 for (i = 0; i < cpsw->data.slaves; i++) {
2528                         if (vid == cpsw->slaves[i].port_vlan)
2529                                 goto err;
2530                 }
2531         }
2532
2533         dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
2534         ret = cpsw_ale_del_vlan(cpsw->ale, vid, 0);
2535         ret |= cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr,
2536                                   HOST_PORT_NUM, ALE_VLAN, vid);
2537         ret |= cpsw_ale_del_mcast(cpsw->ale, priv->ndev->broadcast,
2538                                   0, ALE_VLAN, vid);
2539         ret |= cpsw_ale_flush_multicast(cpsw->ale, 0, vid);
2540 err:
2541         pm_runtime_put(cpsw->dev);
2542         return ret;
2543 }
2544
2545 static int cpsw_ndo_set_tx_maxrate(struct net_device *ndev, int queue, u32 rate)
2546 {
2547         struct cpsw_priv *priv = netdev_priv(ndev);
2548         struct cpsw_common *cpsw = priv->cpsw;
2549         struct cpsw_slave *slave;
2550         u32 min_rate;
2551         u32 ch_rate;
2552         int i, ret;
2553
2554         ch_rate = netdev_get_tx_queue(ndev, queue)->tx_maxrate;
2555         if (ch_rate == rate)
2556                 return 0;
2557
2558         ch_rate = rate * 1000;
2559         min_rate = cpdma_chan_get_min_rate(cpsw->dma);
2560         if ((ch_rate < min_rate && ch_rate)) {
2561                 dev_err(priv->dev, "The channel rate cannot be less than %dMbps",
2562                         min_rate);
2563                 return -EINVAL;
2564         }
2565
2566         if (rate > cpsw->speed) {
2567                 dev_err(priv->dev, "The channel rate cannot be more than 2Gbps");
2568                 return -EINVAL;
2569         }
2570
2571         ret = pm_runtime_get_sync(cpsw->dev);
2572         if (ret < 0) {
2573                 pm_runtime_put_noidle(cpsw->dev);
2574                 return ret;
2575         }
2576
2577         ret = cpdma_chan_set_rate(cpsw->txv[queue].ch, ch_rate);
2578         pm_runtime_put(cpsw->dev);
2579
2580         if (ret)
2581                 return ret;
2582
2583         /* update rates for slaves tx queues */
2584         for (i = 0; i < cpsw->data.slaves; i++) {
2585                 slave = &cpsw->slaves[i];
2586                 if (!slave->ndev)
2587                         continue;
2588
2589                 netdev_get_tx_queue(slave->ndev, queue)->tx_maxrate = rate;
2590         }
2591
2592         cpsw_split_res(cpsw);
2593         return ret;
2594 }
2595
2596 static int cpsw_set_mqprio(struct net_device *ndev, void *type_data)
2597 {
2598         struct tc_mqprio_qopt_offload *mqprio = type_data;
2599         struct cpsw_priv *priv = netdev_priv(ndev);
2600         struct cpsw_common *cpsw = priv->cpsw;
2601         int fifo, num_tc, count, offset;
2602         struct cpsw_slave *slave;
2603         u32 tx_prio_map = 0;
2604         int i, tc, ret;
2605
2606         num_tc = mqprio->qopt.num_tc;
2607         if (num_tc > CPSW_TC_NUM)
2608                 return -EINVAL;
2609
2610         if (mqprio->mode != TC_MQPRIO_MODE_DCB)
2611                 return -EINVAL;
2612
2613         ret = pm_runtime_get_sync(cpsw->dev);
2614         if (ret < 0) {
2615                 pm_runtime_put_noidle(cpsw->dev);
2616                 return ret;
2617         }
2618
2619         if (num_tc) {
2620                 for (i = 0; i < 8; i++) {
2621                         tc = mqprio->qopt.prio_tc_map[i];
2622                         fifo = cpsw_tc_to_fifo(tc, num_tc);
2623                         tx_prio_map |= fifo << (4 * i);
2624                 }
2625
2626                 netdev_set_num_tc(ndev, num_tc);
2627                 for (i = 0; i < num_tc; i++) {
2628                         count = mqprio->qopt.count[i];
2629                         offset = mqprio->qopt.offset[i];
2630                         netdev_set_tc_queue(ndev, i, count, offset);
2631                 }
2632         }
2633
2634         if (!mqprio->qopt.hw) {
2635                 /* restore default configuration */
2636                 netdev_reset_tc(ndev);
2637                 tx_prio_map = TX_PRIORITY_MAPPING;
2638         }
2639
2640         priv->mqprio_hw = mqprio->qopt.hw;
2641
2642         offset = cpsw->version == CPSW_VERSION_1 ?
2643                  CPSW1_TX_PRI_MAP : CPSW2_TX_PRI_MAP;
2644
2645         slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
2646         slave_write(slave, tx_prio_map, offset);
2647
2648         pm_runtime_put_sync(cpsw->dev);
2649
2650         return 0;
2651 }
2652
2653 static int cpsw_ndo_setup_tc(struct net_device *ndev, enum tc_setup_type type,
2654                              void *type_data)
2655 {
2656         switch (type) {
2657         case TC_SETUP_QDISC_CBS:
2658                 return cpsw_set_cbs(ndev, type_data);
2659
2660         case TC_SETUP_QDISC_MQPRIO:
2661                 return cpsw_set_mqprio(ndev, type_data);
2662
2663         default:
2664                 return -EOPNOTSUPP;
2665         }
2666 }
2667
2668 static const struct net_device_ops cpsw_netdev_ops = {
2669         .ndo_open               = cpsw_ndo_open,
2670         .ndo_stop               = cpsw_ndo_stop,
2671         .ndo_start_xmit         = cpsw_ndo_start_xmit,
2672         .ndo_set_mac_address    = cpsw_ndo_set_mac_address,
2673         .ndo_do_ioctl           = cpsw_ndo_ioctl,
2674         .ndo_validate_addr      = eth_validate_addr,
2675         .ndo_tx_timeout         = cpsw_ndo_tx_timeout,
2676         .ndo_set_rx_mode        = cpsw_ndo_set_rx_mode,
2677         .ndo_set_tx_maxrate     = cpsw_ndo_set_tx_maxrate,
2678 #ifdef CONFIG_NET_POLL_CONTROLLER
2679         .ndo_poll_controller    = cpsw_ndo_poll_controller,
2680 #endif
2681         .ndo_vlan_rx_add_vid    = cpsw_ndo_vlan_rx_add_vid,
2682         .ndo_vlan_rx_kill_vid   = cpsw_ndo_vlan_rx_kill_vid,
2683         .ndo_setup_tc           = cpsw_ndo_setup_tc,
2684 };
2685
2686 static int cpsw_get_regs_len(struct net_device *ndev)
2687 {
2688         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2689
2690         return cpsw->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32);
2691 }
2692
2693 static void cpsw_get_regs(struct net_device *ndev,
2694                           struct ethtool_regs *regs, void *p)
2695 {
2696         u32 *reg = p;
2697         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2698
2699         /* update CPSW IP version */
2700         regs->version = cpsw->version;
2701
2702         cpsw_ale_dump(cpsw->ale, reg);
2703 }
2704
2705 static void cpsw_get_drvinfo(struct net_device *ndev,
2706                              struct ethtool_drvinfo *info)
2707 {
2708         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2709         struct platform_device  *pdev = to_platform_device(cpsw->dev);
2710
2711         strlcpy(info->driver, "cpsw", sizeof(info->driver));
2712         strlcpy(info->version, "1.0", sizeof(info->version));
2713         strlcpy(info->bus_info, pdev->name, sizeof(info->bus_info));
2714 }
2715
2716 static u32 cpsw_get_msglevel(struct net_device *ndev)
2717 {
2718         struct cpsw_priv *priv = netdev_priv(ndev);
2719         return priv->msg_enable;
2720 }
2721
2722 static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
2723 {
2724         struct cpsw_priv *priv = netdev_priv(ndev);
2725         priv->msg_enable = value;
2726 }
2727
2728 #if IS_ENABLED(CONFIG_TI_CPTS)
2729 static int cpsw_get_ts_info(struct net_device *ndev,
2730                             struct ethtool_ts_info *info)
2731 {
2732         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2733
2734         info->so_timestamping =
2735                 SOF_TIMESTAMPING_TX_HARDWARE |
2736                 SOF_TIMESTAMPING_TX_SOFTWARE |
2737                 SOF_TIMESTAMPING_RX_HARDWARE |
2738                 SOF_TIMESTAMPING_RX_SOFTWARE |
2739                 SOF_TIMESTAMPING_SOFTWARE |
2740                 SOF_TIMESTAMPING_RAW_HARDWARE;
2741         info->phc_index = cpsw->cpts->phc_index;
2742         info->tx_types =
2743                 (1 << HWTSTAMP_TX_OFF) |
2744                 (1 << HWTSTAMP_TX_ON);
2745         info->rx_filters =
2746                 (1 << HWTSTAMP_FILTER_NONE) |
2747                 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
2748                 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
2749         return 0;
2750 }
2751 #else
2752 static int cpsw_get_ts_info(struct net_device *ndev,
2753                             struct ethtool_ts_info *info)
2754 {
2755         info->so_timestamping =
2756                 SOF_TIMESTAMPING_TX_SOFTWARE |
2757                 SOF_TIMESTAMPING_RX_SOFTWARE |
2758                 SOF_TIMESTAMPING_SOFTWARE;
2759         info->phc_index = -1;
2760         info->tx_types = 0;
2761         info->rx_filters = 0;
2762         return 0;
2763 }
2764 #endif
2765
2766 static int cpsw_get_link_ksettings(struct net_device *ndev,
2767                                    struct ethtool_link_ksettings *ecmd)
2768 {
2769         struct cpsw_priv *priv = netdev_priv(ndev);
2770         struct cpsw_common *cpsw = priv->cpsw;
2771         int slave_no = cpsw_slave_index(cpsw, priv);
2772
2773         if (!cpsw->slaves[slave_no].phy)
2774                 return -EOPNOTSUPP;
2775
2776         phy_ethtool_ksettings_get(cpsw->slaves[slave_no].phy, ecmd);
2777         return 0;
2778 }
2779
2780 static int cpsw_set_link_ksettings(struct net_device *ndev,
2781                                    const struct ethtool_link_ksettings *ecmd)
2782 {
2783         struct cpsw_priv *priv = netdev_priv(ndev);
2784         struct cpsw_common *cpsw = priv->cpsw;
2785         int slave_no = cpsw_slave_index(cpsw, priv);
2786
2787         if (cpsw->slaves[slave_no].phy)
2788                 return phy_ethtool_ksettings_set(cpsw->slaves[slave_no].phy,
2789                                                  ecmd);
2790         else
2791                 return -EOPNOTSUPP;
2792 }
2793
2794 static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2795 {
2796         struct cpsw_priv *priv = netdev_priv(ndev);
2797         struct cpsw_common *cpsw = priv->cpsw;
2798         int slave_no = cpsw_slave_index(cpsw, priv);
2799
2800         wol->supported = 0;
2801         wol->wolopts = 0;
2802
2803         if (cpsw->slaves[slave_no].phy)
2804                 phy_ethtool_get_wol(cpsw->slaves[slave_no].phy, wol);
2805 }
2806
2807 static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2808 {
2809         struct cpsw_priv *priv = netdev_priv(ndev);
2810         struct cpsw_common *cpsw = priv->cpsw;
2811         int slave_no = cpsw_slave_index(cpsw, priv);
2812
2813         if (cpsw->slaves[slave_no].phy)
2814                 return phy_ethtool_set_wol(cpsw->slaves[slave_no].phy, wol);
2815         else
2816                 return -EOPNOTSUPP;
2817 }
2818
2819 static void cpsw_get_pauseparam(struct net_device *ndev,
2820                                 struct ethtool_pauseparam *pause)
2821 {
2822         struct cpsw_priv *priv = netdev_priv(ndev);
2823
2824         pause->autoneg = AUTONEG_DISABLE;
2825         pause->rx_pause = priv->rx_pause ? true : false;
2826         pause->tx_pause = priv->tx_pause ? true : false;
2827 }
2828
2829 static int cpsw_set_pauseparam(struct net_device *ndev,
2830                                struct ethtool_pauseparam *pause)
2831 {
2832         struct cpsw_priv *priv = netdev_priv(ndev);
2833         bool link;
2834
2835         priv->rx_pause = pause->rx_pause ? true : false;
2836         priv->tx_pause = pause->tx_pause ? true : false;
2837
2838         for_each_slave(priv, _cpsw_adjust_link, priv, &link);
2839         return 0;
2840 }
2841
2842 static int cpsw_ethtool_op_begin(struct net_device *ndev)
2843 {
2844         struct cpsw_priv *priv = netdev_priv(ndev);
2845         struct cpsw_common *cpsw = priv->cpsw;
2846         int ret;
2847
2848         ret = pm_runtime_get_sync(cpsw->dev);
2849         if (ret < 0) {
2850                 cpsw_err(priv, drv, "ethtool begin failed %d\n", ret);
2851                 pm_runtime_put_noidle(cpsw->dev);
2852         }
2853
2854         return ret;
2855 }
2856
2857 static void cpsw_ethtool_op_complete(struct net_device *ndev)
2858 {
2859         struct cpsw_priv *priv = netdev_priv(ndev);
2860         int ret;
2861
2862         ret = pm_runtime_put(priv->cpsw->dev);
2863         if (ret < 0)
2864                 cpsw_err(priv, drv, "ethtool complete failed %d\n", ret);
2865 }
2866
2867 static void cpsw_get_channels(struct net_device *ndev,
2868                               struct ethtool_channels *ch)
2869 {
2870         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2871
2872         ch->max_rx = cpsw->quirk_irq ? 1 : CPSW_MAX_QUEUES;
2873         ch->max_tx = cpsw->quirk_irq ? 1 : CPSW_MAX_QUEUES;
2874         ch->max_combined = 0;
2875         ch->max_other = 0;
2876         ch->other_count = 0;
2877         ch->rx_count = cpsw->rx_ch_num;
2878         ch->tx_count = cpsw->tx_ch_num;
2879         ch->combined_count = 0;
2880 }
2881
2882 static int cpsw_check_ch_settings(struct cpsw_common *cpsw,
2883                                   struct ethtool_channels *ch)
2884 {
2885         if (cpsw->quirk_irq) {
2886                 dev_err(cpsw->dev, "Maximum one tx/rx queue is allowed");
2887                 return -EOPNOTSUPP;
2888         }
2889
2890         if (ch->combined_count)
2891                 return -EINVAL;
2892
2893         /* verify we have at least one channel in each direction */
2894         if (!ch->rx_count || !ch->tx_count)
2895                 return -EINVAL;
2896
2897         if (ch->rx_count > cpsw->data.channels ||
2898             ch->tx_count > cpsw->data.channels)
2899                 return -EINVAL;
2900
2901         return 0;
2902 }
2903
2904 static int cpsw_update_channels_res(struct cpsw_priv *priv, int ch_num, int rx)
2905 {
2906         struct cpsw_common *cpsw = priv->cpsw;
2907         void (*handler)(void *, int, int);
2908         struct netdev_queue *queue;
2909         struct cpsw_vector *vec;
2910         int ret, *ch, vch;
2911
2912         if (rx) {
2913                 ch = &cpsw->rx_ch_num;
2914                 vec = cpsw->rxv;
2915                 handler = cpsw_rx_handler;
2916         } else {
2917                 ch = &cpsw->tx_ch_num;
2918                 vec = cpsw->txv;
2919                 handler = cpsw_tx_handler;
2920         }
2921
2922         while (*ch < ch_num) {
2923                 vch = rx ? *ch : 7 - *ch;
2924                 vec[*ch].ch = cpdma_chan_create(cpsw->dma, vch, handler, rx);
2925                 queue = netdev_get_tx_queue(priv->ndev, *ch);
2926                 queue->tx_maxrate = 0;
2927
2928                 if (IS_ERR(vec[*ch].ch))
2929                         return PTR_ERR(vec[*ch].ch);
2930
2931                 if (!vec[*ch].ch)
2932                         return -EINVAL;
2933
2934                 cpsw_info(priv, ifup, "created new %d %s channel\n", *ch,
2935                           (rx ? "rx" : "tx"));
2936                 (*ch)++;
2937         }
2938
2939         while (*ch > ch_num) {
2940                 (*ch)--;
2941
2942                 ret = cpdma_chan_destroy(vec[*ch].ch);
2943                 if (ret)
2944                         return ret;
2945
2946                 cpsw_info(priv, ifup, "destroyed %d %s channel\n", *ch,
2947                           (rx ? "rx" : "tx"));
2948         }
2949
2950         return 0;
2951 }
2952
2953 static int cpsw_update_channels(struct cpsw_priv *priv,
2954                                 struct ethtool_channels *ch)
2955 {
2956         int ret;
2957
2958         ret = cpsw_update_channels_res(priv, ch->rx_count, 1);
2959         if (ret)
2960                 return ret;
2961
2962         ret = cpsw_update_channels_res(priv, ch->tx_count, 0);
2963         if (ret)
2964                 return ret;
2965
2966         return 0;
2967 }
2968
2969 static void cpsw_suspend_data_pass(struct net_device *ndev)
2970 {
2971         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2972         struct cpsw_slave *slave;
2973         int i;
2974
2975         /* Disable NAPI scheduling */
2976         cpsw_intr_disable(cpsw);
2977
2978         /* Stop all transmit queues for every network device.
2979          * Disable re-using rx descriptors with dormant_on.
2980          */
2981         for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) {
2982                 if (!(slave->ndev && netif_running(slave->ndev)))
2983                         continue;
2984
2985                 netif_tx_stop_all_queues(slave->ndev);
2986                 netif_dormant_on(slave->ndev);
2987         }
2988
2989         /* Handle rest of tx packets and stop cpdma channels */
2990         cpdma_ctlr_stop(cpsw->dma);
2991 }
2992
2993 static int cpsw_resume_data_pass(struct net_device *ndev)
2994 {
2995         struct cpsw_priv *priv = netdev_priv(ndev);
2996         struct cpsw_common *cpsw = priv->cpsw;
2997         struct cpsw_slave *slave;
2998         int i, ret;
2999
3000         /* Allow rx packets handling */
3001         for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++)
3002                 if (slave->ndev && netif_running(slave->ndev))
3003                         netif_dormant_off(slave->ndev);
3004
3005         /* After this receive is started */
3006         if (cpsw->usage_count) {
3007                 ret = cpsw_fill_rx_channels(priv);
3008                 if (ret)
3009                         return ret;
3010
3011                 cpdma_ctlr_start(cpsw->dma);
3012                 cpsw_intr_enable(cpsw);
3013         }
3014
3015         /* Resume transmit for every affected interface */
3016         for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++)
3017                 if (slave->ndev && netif_running(slave->ndev))
3018                         netif_tx_start_all_queues(slave->ndev);
3019
3020         return 0;
3021 }
3022
3023 static int cpsw_set_channels(struct net_device *ndev,
3024                              struct ethtool_channels *chs)
3025 {
3026         struct cpsw_priv *priv = netdev_priv(ndev);
3027         struct cpsw_common *cpsw = priv->cpsw;
3028         struct cpsw_slave *slave;
3029         int i, ret;
3030
3031         ret = cpsw_check_ch_settings(cpsw, chs);
3032         if (ret < 0)
3033                 return ret;
3034
3035         cpsw_suspend_data_pass(ndev);
3036         ret = cpsw_update_channels(priv, chs);
3037         if (ret)
3038                 goto err;
3039
3040         for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) {
3041                 if (!(slave->ndev && netif_running(slave->ndev)))
3042                         continue;
3043
3044                 /* Inform stack about new count of queues */
3045                 ret = netif_set_real_num_tx_queues(slave->ndev,
3046                                                    cpsw->tx_ch_num);
3047                 if (ret) {
3048                         dev_err(priv->dev, "cannot set real number of tx queues\n");
3049                         goto err;
3050                 }
3051
3052                 ret = netif_set_real_num_rx_queues(slave->ndev,
3053                                                    cpsw->rx_ch_num);
3054                 if (ret) {
3055                         dev_err(priv->dev, "cannot set real number of rx queues\n");
3056                         goto err;
3057                 }
3058         }
3059
3060         if (cpsw->usage_count)
3061                 cpsw_split_res(cpsw);
3062
3063         ret = cpsw_resume_data_pass(ndev);
3064         if (!ret)
3065                 return 0;
3066 err:
3067         dev_err(priv->dev, "cannot update channels number, closing device\n");
3068         dev_close(ndev);
3069         return ret;
3070 }
3071
3072 static int cpsw_get_eee(struct net_device *ndev, struct ethtool_eee *edata)
3073 {
3074         struct cpsw_priv *priv = netdev_priv(ndev);
3075         struct cpsw_common *cpsw = priv->cpsw;
3076         int slave_no = cpsw_slave_index(cpsw, priv);
3077
3078         if (cpsw->slaves[slave_no].phy)
3079                 return phy_ethtool_get_eee(cpsw->slaves[slave_no].phy, edata);
3080         else
3081                 return -EOPNOTSUPP;
3082 }
3083
3084 static int cpsw_set_eee(struct net_device *ndev, struct ethtool_eee *edata)
3085 {
3086         struct cpsw_priv *priv = netdev_priv(ndev);
3087         struct cpsw_common *cpsw = priv->cpsw;
3088         int slave_no = cpsw_slave_index(cpsw, priv);
3089
3090         if (cpsw->slaves[slave_no].phy)
3091                 return phy_ethtool_set_eee(cpsw->slaves[slave_no].phy, edata);
3092         else
3093                 return -EOPNOTSUPP;
3094 }
3095
3096 static int cpsw_nway_reset(struct net_device *ndev)
3097 {
3098         struct cpsw_priv *priv = netdev_priv(ndev);
3099         struct cpsw_common *cpsw = priv->cpsw;
3100         int slave_no = cpsw_slave_index(cpsw, priv);
3101
3102         if (cpsw->slaves[slave_no].phy)
3103                 return genphy_restart_aneg(cpsw->slaves[slave_no].phy);
3104         else
3105                 return -EOPNOTSUPP;
3106 }
3107
3108 static void cpsw_get_ringparam(struct net_device *ndev,
3109                                struct ethtool_ringparam *ering)
3110 {
3111         struct cpsw_priv *priv = netdev_priv(ndev);
3112         struct cpsw_common *cpsw = priv->cpsw;
3113
3114         /* not supported */
3115         ering->tx_max_pending = 0;
3116         ering->tx_pending = cpdma_get_num_tx_descs(cpsw->dma);
3117         ering->rx_max_pending = descs_pool_size - CPSW_MAX_QUEUES;
3118         ering->rx_pending = cpdma_get_num_rx_descs(cpsw->dma);
3119 }
3120
3121 static int cpsw_set_ringparam(struct net_device *ndev,
3122                               struct ethtool_ringparam *ering)
3123 {
3124         struct cpsw_priv *priv = netdev_priv(ndev);
3125         struct cpsw_common *cpsw = priv->cpsw;
3126         int ret;
3127
3128         /* ignore ering->tx_pending - only rx_pending adjustment is supported */
3129
3130         if (ering->rx_mini_pending || ering->rx_jumbo_pending ||
3131             ering->rx_pending < CPSW_MAX_QUEUES ||
3132             ering->rx_pending > (descs_pool_size - CPSW_MAX_QUEUES))
3133                 return -EINVAL;
3134
3135         if (ering->rx_pending == cpdma_get_num_rx_descs(cpsw->dma))
3136                 return 0;
3137
3138         cpsw_suspend_data_pass(ndev);
3139
3140         cpdma_set_num_rx_descs(cpsw->dma, ering->rx_pending);
3141
3142         if (cpsw->usage_count)
3143                 cpdma_chan_split_pool(cpsw->dma);
3144
3145         ret = cpsw_resume_data_pass(ndev);
3146         if (!ret)
3147                 return 0;
3148
3149         dev_err(&ndev->dev, "cannot set ring params, closing device\n");
3150         dev_close(ndev);
3151         return ret;
3152 }
3153
3154 static const struct ethtool_ops cpsw_ethtool_ops = {
3155         .get_drvinfo    = cpsw_get_drvinfo,
3156         .get_msglevel   = cpsw_get_msglevel,
3157         .set_msglevel   = cpsw_set_msglevel,
3158         .get_link       = ethtool_op_get_link,
3159         .get_ts_info    = cpsw_get_ts_info,
3160         .get_coalesce   = cpsw_get_coalesce,
3161         .set_coalesce   = cpsw_set_coalesce,
3162         .get_sset_count         = cpsw_get_sset_count,
3163         .get_strings            = cpsw_get_strings,
3164         .get_ethtool_stats      = cpsw_get_ethtool_stats,
3165         .get_pauseparam         = cpsw_get_pauseparam,
3166         .set_pauseparam         = cpsw_set_pauseparam,
3167         .get_wol        = cpsw_get_wol,
3168         .set_wol        = cpsw_set_wol,
3169         .get_regs_len   = cpsw_get_regs_len,
3170         .get_regs       = cpsw_get_regs,
3171         .begin          = cpsw_ethtool_op_begin,
3172         .complete       = cpsw_ethtool_op_complete,
3173         .get_channels   = cpsw_get_channels,
3174         .set_channels   = cpsw_set_channels,
3175         .get_link_ksettings     = cpsw_get_link_ksettings,
3176         .set_link_ksettings     = cpsw_set_link_ksettings,
3177         .get_eee        = cpsw_get_eee,
3178         .set_eee        = cpsw_set_eee,
3179         .nway_reset     = cpsw_nway_reset,
3180         .get_ringparam = cpsw_get_ringparam,
3181         .set_ringparam = cpsw_set_ringparam,
3182 };
3183
3184 static int cpsw_probe_dt(struct cpsw_platform_data *data,
3185                          struct platform_device *pdev)
3186 {
3187         struct device_node *node = pdev->dev.of_node;
3188         struct device_node *slave_node;
3189         int i = 0, ret;
3190         u32 prop;
3191
3192         if (!node)
3193                 return -EINVAL;
3194
3195         if (of_property_read_u32(node, "slaves", &prop)) {
3196                 dev_err(&pdev->dev, "Missing slaves property in the DT.\n");
3197                 return -EINVAL;
3198         }
3199         data->slaves = prop;
3200
3201         if (of_property_read_u32(node, "active_slave", &prop)) {
3202                 dev_err(&pdev->dev, "Missing active_slave property in the DT.\n");
3203                 return -EINVAL;
3204         }
3205         data->active_slave = prop;
3206
3207         data->slave_data = devm_kcalloc(&pdev->dev,
3208                                         data->slaves,
3209                                         sizeof(struct cpsw_slave_data),
3210                                         GFP_KERNEL);
3211         if (!data->slave_data)
3212                 return -ENOMEM;
3213
3214         if (of_property_read_u32(node, "cpdma_channels", &prop)) {
3215                 dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n");
3216                 return -EINVAL;
3217         }
3218         data->channels = prop;
3219
3220         if (of_property_read_u32(node, "ale_entries", &prop)) {
3221                 dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n");
3222                 return -EINVAL;
3223         }
3224         data->ale_entries = prop;
3225
3226         if (of_property_read_u32(node, "bd_ram_size", &prop)) {
3227                 dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n");
3228                 return -EINVAL;
3229         }
3230         data->bd_ram_size = prop;
3231
3232         if (of_property_read_u32(node, "mac_control", &prop)) {
3233                 dev_err(&pdev->dev, "Missing mac_control property in the DT.\n");
3234                 return -EINVAL;
3235         }
3236         data->mac_control = prop;
3237
3238         if (of_property_read_bool(node, "dual_emac"))
3239                 data->dual_emac = 1;
3240
3241         /*
3242          * Populate all the child nodes here...
3243          */
3244         ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
3245         /* We do not want to force this, as in some cases may not have child */
3246         if (ret)
3247                 dev_warn(&pdev->dev, "Doesn't have any child node\n");
3248
3249         for_each_available_child_of_node(node, slave_node) {
3250                 struct cpsw_slave_data *slave_data = data->slave_data + i;
3251                 const void *mac_addr = NULL;
3252                 int lenp;
3253                 const __be32 *parp;
3254
3255                 /* This is no slave child node, continue */
3256                 if (!of_node_name_eq(slave_node, "slave"))
3257                         continue;
3258
3259                 slave_data->ifphy = devm_of_phy_get(&pdev->dev, slave_node,
3260                                                     NULL);
3261                 if (!IS_ENABLED(CONFIG_TI_CPSW_PHY_SEL) &&
3262                     IS_ERR(slave_data->ifphy)) {
3263                         ret = PTR_ERR(slave_data->ifphy);
3264                         dev_err(&pdev->dev,
3265                                 "%d: Error retrieving port phy: %d\n", i, ret);
3266                         return ret;
3267                 }
3268
3269                 slave_data->phy_node = of_parse_phandle(slave_node,
3270                                                         "phy-handle", 0);
3271                 parp = of_get_property(slave_node, "phy_id", &lenp);
3272                 if (slave_data->phy_node) {
3273                         dev_dbg(&pdev->dev,
3274                                 "slave[%d] using phy-handle=\"%pOF\"\n",
3275                                 i, slave_data->phy_node);
3276                 } else if (of_phy_is_fixed_link(slave_node)) {
3277                         /* In the case of a fixed PHY, the DT node associated
3278                          * to the PHY is the Ethernet MAC DT node.
3279                          */
3280                         ret = of_phy_register_fixed_link(slave_node);
3281                         if (ret) {
3282                                 if (ret != -EPROBE_DEFER)
3283                                         dev_err(&pdev->dev, "failed to register fixed-link phy: %d\n", ret);
3284                                 return ret;
3285                         }
3286                         slave_data->phy_node = of_node_get(slave_node);
3287                 } else if (parp) {
3288                         u32 phyid;
3289                         struct device_node *mdio_node;
3290                         struct platform_device *mdio;
3291
3292                         if (lenp != (sizeof(__be32) * 2)) {
3293                                 dev_err(&pdev->dev, "Invalid slave[%d] phy_id property\n", i);
3294                                 goto no_phy_slave;
3295                         }
3296                         mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
3297                         phyid = be32_to_cpup(parp+1);
3298                         mdio = of_find_device_by_node(mdio_node);
3299                         of_node_put(mdio_node);
3300                         if (!mdio) {
3301                                 dev_err(&pdev->dev, "Missing mdio platform device\n");
3302                                 return -EINVAL;
3303                         }
3304                         snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
3305                                  PHY_ID_FMT, mdio->name, phyid);
3306                         put_device(&mdio->dev);
3307                 } else {
3308                         dev_err(&pdev->dev,
3309                                 "No slave[%d] phy_id, phy-handle, or fixed-link property\n",
3310                                 i);
3311                         goto no_phy_slave;
3312                 }
3313                 slave_data->phy_if = of_get_phy_mode(slave_node);
3314                 if (slave_data->phy_if < 0) {
3315                         dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n",
3316                                 i);
3317                         return slave_data->phy_if;
3318                 }
3319
3320 no_phy_slave:
3321                 mac_addr = of_get_mac_address(slave_node);
3322                 if (mac_addr) {
3323                         memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
3324                 } else {
3325                         ret = ti_cm_get_macid(&pdev->dev, i,
3326                                               slave_data->mac_addr);
3327                         if (ret)
3328                                 return ret;
3329                 }
3330                 if (data->dual_emac) {
3331                         if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
3332                                                  &prop)) {
3333                                 dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n");
3334                                 slave_data->dual_emac_res_vlan = i+1;
3335                                 dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n",
3336                                         slave_data->dual_emac_res_vlan, i);
3337                         } else {
3338                                 slave_data->dual_emac_res_vlan = prop;
3339                         }
3340                 }
3341
3342                 i++;
3343                 if (i == data->slaves)
3344                         break;
3345         }
3346
3347         return 0;
3348 }
3349
3350 static void cpsw_remove_dt(struct platform_device *pdev)
3351 {
3352         struct net_device *ndev = platform_get_drvdata(pdev);
3353         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
3354         struct cpsw_platform_data *data = &cpsw->data;
3355         struct device_node *node = pdev->dev.of_node;
3356         struct device_node *slave_node;
3357         int i = 0;
3358
3359         for_each_available_child_of_node(node, slave_node) {
3360                 struct cpsw_slave_data *slave_data = &data->slave_data[i];
3361
3362                 if (!of_node_name_eq(slave_node, "slave"))
3363                         continue;
3364
3365                 if (of_phy_is_fixed_link(slave_node))
3366                         of_phy_deregister_fixed_link(slave_node);
3367
3368                 of_node_put(slave_data->phy_node);
3369
3370                 i++;
3371                 if (i == data->slaves)
3372                         break;
3373         }
3374
3375         of_platform_depopulate(&pdev->dev);
3376 }
3377
3378 static int cpsw_probe_dual_emac(struct cpsw_priv *priv)
3379 {
3380         struct cpsw_common              *cpsw = priv->cpsw;
3381         struct cpsw_platform_data       *data = &cpsw->data;
3382         struct net_device               *ndev;
3383         struct cpsw_priv                *priv_sl2;
3384         int ret = 0;
3385
3386         ndev = devm_alloc_etherdev_mqs(cpsw->dev, sizeof(struct cpsw_priv),
3387                                        CPSW_MAX_QUEUES, CPSW_MAX_QUEUES);
3388         if (!ndev) {
3389                 dev_err(cpsw->dev, "cpsw: error allocating net_device\n");
3390                 return -ENOMEM;
3391         }
3392
3393         priv_sl2 = netdev_priv(ndev);
3394         priv_sl2->cpsw = cpsw;
3395         priv_sl2->ndev = ndev;
3396         priv_sl2->dev  = &ndev->dev;
3397         priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
3398
3399         if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
3400                 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
3401                         ETH_ALEN);
3402                 dev_info(cpsw->dev, "cpsw: Detected MACID = %pM\n",
3403                          priv_sl2->mac_addr);
3404         } else {
3405                 eth_random_addr(priv_sl2->mac_addr);
3406                 dev_info(cpsw->dev, "cpsw: Random MACID = %pM\n",
3407                          priv_sl2->mac_addr);
3408         }
3409         memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
3410
3411         priv_sl2->emac_port = 1;
3412         cpsw->slaves[1].ndev = ndev;
3413         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_CTAG_RX;
3414
3415         ndev->netdev_ops = &cpsw_netdev_ops;
3416         ndev->ethtool_ops = &cpsw_ethtool_ops;
3417
3418         /* register the network device */
3419         SET_NETDEV_DEV(ndev, cpsw->dev);
3420         ret = register_netdev(ndev);
3421         if (ret)
3422                 dev_err(cpsw->dev, "cpsw: error registering net device\n");
3423
3424         return ret;
3425 }
3426
3427 static const struct of_device_id cpsw_of_mtable[] = {
3428         { .compatible = "ti,cpsw"},
3429         { .compatible = "ti,am335x-cpsw"},
3430         { .compatible = "ti,am4372-cpsw"},
3431         { .compatible = "ti,dra7-cpsw"},
3432         { /* sentinel */ },
3433 };
3434 MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
3435
3436 static const struct soc_device_attribute cpsw_soc_devices[] = {
3437         { .family = "AM33xx", .revision = "ES1.0"},
3438         { /* sentinel */ }
3439 };
3440
3441 static int cpsw_probe(struct platform_device *pdev)
3442 {
3443         struct device                   *dev = &pdev->dev;
3444         struct clk                      *clk;
3445         struct cpsw_platform_data       *data;
3446         struct net_device               *ndev;
3447         struct cpsw_priv                *priv;
3448         struct cpdma_params             dma_params;
3449         struct cpsw_ale_params          ale_params;
3450         void __iomem                    *ss_regs;
3451         void __iomem                    *cpts_regs;
3452         struct resource                 *res, *ss_res;
3453         struct gpio_descs               *mode;
3454         u32 slave_offset, sliver_offset, slave_size;
3455         const struct soc_device_attribute *soc;
3456         struct cpsw_common              *cpsw;
3457         int ret = 0, i, ch;
3458         int irq;
3459
3460         cpsw = devm_kzalloc(dev, sizeof(struct cpsw_common), GFP_KERNEL);
3461         if (!cpsw)
3462                 return -ENOMEM;
3463
3464         cpsw->dev = dev;
3465
3466         mode = devm_gpiod_get_array_optional(dev, "mode", GPIOD_OUT_LOW);
3467         if (IS_ERR(mode)) {
3468                 ret = PTR_ERR(mode);
3469                 dev_err(dev, "gpio request failed, ret %d\n", ret);
3470                 return ret;
3471         }
3472
3473         clk = devm_clk_get(dev, "fck");
3474         if (IS_ERR(clk)) {
3475                 ret = PTR_ERR(mode);
3476                 dev_err(dev, "fck is not found %d\n", ret);
3477                 return ret;
3478         }
3479         cpsw->bus_freq_mhz = clk_get_rate(clk) / 1000000;
3480
3481         ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3482         ss_regs = devm_ioremap_resource(dev, ss_res);
3483         if (IS_ERR(ss_regs))
3484                 return PTR_ERR(ss_regs);
3485         cpsw->regs = ss_regs;
3486
3487         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3488         cpsw->wr_regs = devm_ioremap_resource(dev, res);
3489         if (IS_ERR(cpsw->wr_regs))
3490                 return PTR_ERR(cpsw->wr_regs);
3491
3492         /* RX IRQ */
3493         irq = platform_get_irq(pdev, 1);
3494         if (irq < 0)
3495                 return irq;
3496         cpsw->irqs_table[0] = irq;
3497
3498         /* TX IRQ */
3499         irq = platform_get_irq(pdev, 2);
3500         if (irq < 0)
3501                 return irq;
3502         cpsw->irqs_table[1] = irq;
3503
3504         /*
3505          * This may be required here for child devices.
3506          */
3507         pm_runtime_enable(dev);
3508
3509         /* Need to enable clocks with runtime PM api to access module
3510          * registers
3511          */
3512         ret = pm_runtime_get_sync(dev);
3513         if (ret < 0) {
3514                 pm_runtime_put_noidle(dev);
3515                 goto clean_runtime_disable_ret;
3516         }
3517
3518         ret = cpsw_probe_dt(&cpsw->data, pdev);
3519         if (ret)
3520                 goto clean_dt_ret;
3521
3522         soc = soc_device_match(cpsw_soc_devices);
3523         if (soc)
3524                 cpsw->quirk_irq = 1;
3525
3526         data = &cpsw->data;
3527         cpsw->slaves = devm_kcalloc(dev,
3528                                     data->slaves, sizeof(struct cpsw_slave),
3529                                     GFP_KERNEL);
3530         if (!cpsw->slaves) {
3531                 ret = -ENOMEM;
3532                 goto clean_dt_ret;
3533         }
3534
3535         cpsw->rx_packet_max = max(rx_packet_max, CPSW_MAX_PACKET_SIZE);
3536
3537         cpsw->rx_ch_num = 1;
3538         cpsw->tx_ch_num = 1;
3539
3540         cpsw->version = readl(&cpsw->regs->id_ver);
3541
3542         memset(&dma_params, 0, sizeof(dma_params));
3543         memset(&ale_params, 0, sizeof(ale_params));
3544
3545         switch (cpsw->version) {
3546         case CPSW_VERSION_1:
3547                 cpsw->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
3548                 cpts_regs               = ss_regs + CPSW1_CPTS_OFFSET;
3549                 cpsw->hw_stats       = ss_regs + CPSW1_HW_STATS;
3550                 dma_params.dmaregs   = ss_regs + CPSW1_CPDMA_OFFSET;
3551                 dma_params.txhdp     = ss_regs + CPSW1_STATERAM_OFFSET;
3552                 ale_params.ale_regs  = ss_regs + CPSW1_ALE_OFFSET;
3553                 slave_offset         = CPSW1_SLAVE_OFFSET;
3554                 slave_size           = CPSW1_SLAVE_SIZE;
3555                 sliver_offset        = CPSW1_SLIVER_OFFSET;
3556                 dma_params.desc_mem_phys = 0;
3557                 break;
3558         case CPSW_VERSION_2:
3559         case CPSW_VERSION_3:
3560         case CPSW_VERSION_4:
3561                 cpsw->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
3562                 cpts_regs               = ss_regs + CPSW2_CPTS_OFFSET;
3563                 cpsw->hw_stats       = ss_regs + CPSW2_HW_STATS;
3564                 dma_params.dmaregs   = ss_regs + CPSW2_CPDMA_OFFSET;
3565                 dma_params.txhdp     = ss_regs + CPSW2_STATERAM_OFFSET;
3566                 ale_params.ale_regs  = ss_regs + CPSW2_ALE_OFFSET;
3567                 slave_offset         = CPSW2_SLAVE_OFFSET;
3568                 slave_size           = CPSW2_SLAVE_SIZE;
3569                 sliver_offset        = CPSW2_SLIVER_OFFSET;
3570                 dma_params.desc_mem_phys =
3571                         (u32 __force) ss_res->start + CPSW2_BD_OFFSET;
3572                 break;
3573         default:
3574                 dev_err(dev, "unknown version 0x%08x\n", cpsw->version);
3575                 ret = -ENODEV;
3576                 goto clean_dt_ret;
3577         }
3578
3579         for (i = 0; i < cpsw->data.slaves; i++) {
3580                 struct cpsw_slave *slave = &cpsw->slaves[i];
3581                 void __iomem            *regs = cpsw->regs;
3582
3583                 slave->slave_num = i;
3584                 slave->data     = &cpsw->data.slave_data[i];
3585                 slave->regs     = regs + slave_offset;
3586                 slave->sliver   = regs + sliver_offset;
3587                 slave->port_vlan = slave->data->dual_emac_res_vlan;
3588
3589                 slave_offset  += slave_size;
3590                 sliver_offset += SLIVER_SIZE;
3591         }
3592
3593         ale_params.dev                  = dev;
3594         ale_params.ale_ageout           = ale_ageout;
3595         ale_params.ale_entries          = data->ale_entries;
3596         ale_params.ale_ports            = CPSW_ALE_PORTS_NUM;
3597
3598         cpsw->ale = cpsw_ale_create(&ale_params);
3599         if (!cpsw->ale) {
3600                 dev_err(dev, "error initializing ale engine\n");
3601                 ret = -ENODEV;
3602                 goto clean_dt_ret;
3603         }
3604
3605         dma_params.dev          = dev;
3606         dma_params.rxthresh     = dma_params.dmaregs + CPDMA_RXTHRESH;
3607         dma_params.rxfree       = dma_params.dmaregs + CPDMA_RXFREE;
3608         dma_params.rxhdp        = dma_params.txhdp + CPDMA_RXHDP;
3609         dma_params.txcp         = dma_params.txhdp + CPDMA_TXCP;
3610         dma_params.rxcp         = dma_params.txhdp + CPDMA_RXCP;
3611
3612         dma_params.num_chan             = data->channels;
3613         dma_params.has_soft_reset       = true;
3614         dma_params.min_packet_size      = CPSW_MIN_PACKET_SIZE;
3615         dma_params.desc_mem_size        = data->bd_ram_size;
3616         dma_params.desc_align           = 16;
3617         dma_params.has_ext_regs         = true;
3618         dma_params.desc_hw_addr         = dma_params.desc_mem_phys;
3619         dma_params.bus_freq_mhz         = cpsw->bus_freq_mhz;
3620         dma_params.descs_pool_size      = descs_pool_size;
3621
3622         cpsw->dma = cpdma_ctlr_create(&dma_params);
3623         if (!cpsw->dma) {
3624                 dev_err(dev, "error initializing dma\n");
3625                 ret = -ENOMEM;
3626                 goto clean_dt_ret;
3627         }
3628
3629         cpsw->cpts = cpts_create(cpsw->dev, cpts_regs, cpsw->dev->of_node);
3630         if (IS_ERR(cpsw->cpts)) {
3631                 ret = PTR_ERR(cpsw->cpts);
3632                 goto clean_dma_ret;
3633         }
3634
3635         ch = cpsw->quirk_irq ? 0 : 7;
3636         cpsw->txv[0].ch = cpdma_chan_create(cpsw->dma, ch, cpsw_tx_handler, 0);
3637         if (IS_ERR(cpsw->txv[0].ch)) {
3638                 dev_err(dev, "error initializing tx dma channel\n");
3639                 ret = PTR_ERR(cpsw->txv[0].ch);
3640                 goto clean_cpts;
3641         }
3642
3643         cpsw->rxv[0].ch = cpdma_chan_create(cpsw->dma, 0, cpsw_rx_handler, 1);
3644         if (IS_ERR(cpsw->rxv[0].ch)) {
3645                 dev_err(dev, "error initializing rx dma channel\n");
3646                 ret = PTR_ERR(cpsw->rxv[0].ch);
3647                 goto clean_cpts;
3648         }
3649         cpsw_split_res(cpsw);
3650
3651         /* setup netdev */
3652         ndev = devm_alloc_etherdev_mqs(dev, sizeof(struct cpsw_priv),
3653                                        CPSW_MAX_QUEUES, CPSW_MAX_QUEUES);
3654         if (!ndev) {
3655                 dev_err(dev, "error allocating net_device\n");
3656                 goto clean_cpts;
3657         }
3658
3659         platform_set_drvdata(pdev, ndev);
3660         priv = netdev_priv(ndev);
3661         priv->cpsw = cpsw;
3662         priv->ndev = ndev;
3663         priv->dev  = dev;
3664         priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
3665         priv->emac_port = 0;
3666
3667         if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
3668                 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
3669                 dev_info(dev, "Detected MACID = %pM\n", priv->mac_addr);
3670         } else {
3671                 eth_random_addr(priv->mac_addr);
3672                 dev_info(dev, "Random MACID = %pM\n", priv->mac_addr);
3673         }
3674
3675         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
3676
3677         cpsw->slaves[0].ndev = ndev;
3678
3679         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_CTAG_RX;
3680
3681         ndev->netdev_ops = &cpsw_netdev_ops;
3682         ndev->ethtool_ops = &cpsw_ethtool_ops;
3683         netif_napi_add(ndev, &cpsw->napi_rx,
3684                        cpsw->quirk_irq ? cpsw_rx_poll : cpsw_rx_mq_poll,
3685                        CPSW_POLL_WEIGHT);
3686         netif_tx_napi_add(ndev, &cpsw->napi_tx,
3687                           cpsw->quirk_irq ? cpsw_tx_poll : cpsw_tx_mq_poll,
3688                           CPSW_POLL_WEIGHT);
3689
3690         /* register the network device */
3691         SET_NETDEV_DEV(ndev, dev);
3692         ret = register_netdev(ndev);
3693         if (ret) {
3694                 dev_err(dev, "error registering net device\n");
3695                 ret = -ENODEV;
3696                 goto clean_cpts;
3697         }
3698
3699         if (cpsw->data.dual_emac) {
3700                 ret = cpsw_probe_dual_emac(priv);
3701                 if (ret) {
3702                         cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
3703                         goto clean_unregister_netdev_ret;
3704                 }
3705         }
3706
3707         /* Grab RX and TX IRQs. Note that we also have RX_THRESHOLD and
3708          * MISC IRQs which are always kept disabled with this driver so
3709          * we will not request them.
3710          *
3711          * If anyone wants to implement support for those, make sure to
3712          * first request and append them to irqs_table array.
3713          */
3714         ret = devm_request_irq(dev, cpsw->irqs_table[0], cpsw_rx_interrupt,
3715                                0, dev_name(dev), cpsw);
3716         if (ret < 0) {
3717                 dev_err(dev, "error attaching irq (%d)\n", ret);
3718                 goto clean_unregister_netdev_ret;
3719         }
3720
3721
3722         ret = devm_request_irq(dev, cpsw->irqs_table[1], cpsw_tx_interrupt,
3723                                0, dev_name(&pdev->dev), cpsw);
3724         if (ret < 0) {
3725                 dev_err(dev, "error attaching irq (%d)\n", ret);
3726                 goto clean_unregister_netdev_ret;
3727         }
3728
3729         cpsw_notice(priv, probe,
3730                     "initialized device (regs %pa, irq %d, pool size %d)\n",
3731                     &ss_res->start, cpsw->irqs_table[0], descs_pool_size);
3732
3733         pm_runtime_put(&pdev->dev);
3734
3735         return 0;
3736
3737 clean_unregister_netdev_ret:
3738         unregister_netdev(ndev);
3739 clean_cpts:
3740         cpts_release(cpsw->cpts);
3741 clean_dma_ret:
3742         cpdma_ctlr_destroy(cpsw->dma);
3743 clean_dt_ret:
3744         cpsw_remove_dt(pdev);
3745         pm_runtime_put_sync(&pdev->dev);
3746 clean_runtime_disable_ret:
3747         pm_runtime_disable(&pdev->dev);
3748         return ret;
3749 }
3750
3751 static int cpsw_remove(struct platform_device *pdev)
3752 {
3753         struct net_device *ndev = platform_get_drvdata(pdev);
3754         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
3755         int ret;
3756
3757         ret = pm_runtime_get_sync(&pdev->dev);
3758         if (ret < 0) {
3759                 pm_runtime_put_noidle(&pdev->dev);
3760                 return ret;
3761         }
3762
3763         if (cpsw->data.dual_emac)
3764                 unregister_netdev(cpsw->slaves[1].ndev);
3765         unregister_netdev(ndev);
3766
3767         cpts_release(cpsw->cpts);
3768         cpdma_ctlr_destroy(cpsw->dma);
3769         cpsw_remove_dt(pdev);
3770         pm_runtime_put_sync(&pdev->dev);
3771         pm_runtime_disable(&pdev->dev);
3772         return 0;
3773 }
3774
3775 #ifdef CONFIG_PM_SLEEP
3776 static int cpsw_suspend(struct device *dev)
3777 {
3778         struct net_device       *ndev = dev_get_drvdata(dev);
3779         struct cpsw_common      *cpsw = ndev_to_cpsw(ndev);
3780
3781         if (cpsw->data.dual_emac) {
3782                 int i;
3783
3784                 for (i = 0; i < cpsw->data.slaves; i++) {
3785                         if (netif_running(cpsw->slaves[i].ndev))
3786                                 cpsw_ndo_stop(cpsw->slaves[i].ndev);
3787                 }
3788         } else {
3789                 if (netif_running(ndev))
3790                         cpsw_ndo_stop(ndev);
3791         }
3792
3793         /* Select sleep pin state */
3794         pinctrl_pm_select_sleep_state(dev);
3795
3796         return 0;
3797 }
3798
3799 static int cpsw_resume(struct device *dev)
3800 {
3801         struct net_device       *ndev = dev_get_drvdata(dev);
3802         struct cpsw_common      *cpsw = ndev_to_cpsw(ndev);
3803
3804         /* Select default pin state */
3805         pinctrl_pm_select_default_state(dev);
3806
3807         /* shut up ASSERT_RTNL() warning in netif_set_real_num_tx/rx_queues */
3808         rtnl_lock();
3809         if (cpsw->data.dual_emac) {
3810                 int i;
3811
3812                 for (i = 0; i < cpsw->data.slaves; i++) {
3813                         if (netif_running(cpsw->slaves[i].ndev))
3814                                 cpsw_ndo_open(cpsw->slaves[i].ndev);
3815                 }
3816         } else {
3817                 if (netif_running(ndev))
3818                         cpsw_ndo_open(ndev);
3819         }
3820         rtnl_unlock();
3821
3822         return 0;
3823 }
3824 #endif
3825
3826 static SIMPLE_DEV_PM_OPS(cpsw_pm_ops, cpsw_suspend, cpsw_resume);
3827
3828 static struct platform_driver cpsw_driver = {
3829         .driver = {
3830                 .name    = "cpsw",
3831                 .pm      = &cpsw_pm_ops,
3832                 .of_match_table = cpsw_of_mtable,
3833         },
3834         .probe = cpsw_probe,
3835         .remove = cpsw_remove,
3836 };
3837
3838 module_platform_driver(cpsw_driver);
3839
3840 MODULE_LICENSE("GPL");
3841 MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
3842 MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
3843 MODULE_DESCRIPTION("TI CPSW Ethernet driver");