1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * DWMAC4 DMA Header file.
5 * Copyright (C) 2007-2015 STMicroelectronics Ltd
7 * Author: Alexandre Torgue <alexandre.torgue@st.com>
10 #ifndef __DWMAC4_DMA_H__
11 #define __DWMAC4_DMA_H__
13 /* Define the max channel number used for tx (also rx).
14 * dwmac4 accepts up to 8 channels for TX (and also 8 channels for RX
16 #define DMA_CHANNEL_NB_MAX 1
18 #define DMA_BUS_MODE 0x00001000
19 #define DMA_SYS_BUS_MODE 0x00001004
20 #define DMA_STATUS 0x00001008
21 #define DMA_DEBUG_STATUS_0 0x0000100c
22 #define DMA_DEBUG_STATUS_1 0x00001010
23 #define DMA_DEBUG_STATUS_2 0x00001014
24 #define DMA_AXI_BUS_MODE 0x00001028
26 /* DMA Bus Mode bitmap */
27 #define DMA_BUS_MODE_SFT_RESET BIT(0)
29 /* DMA SYS Bus Mode bitmap */
30 #define DMA_BUS_MODE_SPH BIT(24)
31 #define DMA_BUS_MODE_PBL BIT(16)
32 #define DMA_BUS_MODE_PBL_SHIFT 16
33 #define DMA_BUS_MODE_RPBL_SHIFT 16
34 #define DMA_BUS_MODE_MB BIT(14)
35 #define DMA_BUS_MODE_FB BIT(0)
37 /* DMA Interrupt top status */
38 #define DMA_STATUS_MAC BIT(17)
39 #define DMA_STATUS_MTL BIT(16)
40 #define DMA_STATUS_CHAN7 BIT(7)
41 #define DMA_STATUS_CHAN6 BIT(6)
42 #define DMA_STATUS_CHAN5 BIT(5)
43 #define DMA_STATUS_CHAN4 BIT(4)
44 #define DMA_STATUS_CHAN3 BIT(3)
45 #define DMA_STATUS_CHAN2 BIT(2)
46 #define DMA_STATUS_CHAN1 BIT(1)
47 #define DMA_STATUS_CHAN0 BIT(0)
49 /* DMA debug status bitmap */
50 #define DMA_DEBUG_STATUS_TS_MASK 0xf
51 #define DMA_DEBUG_STATUS_RS_MASK 0xf
54 #define DMA_AXI_EN_LPI BIT(31)
55 #define DMA_AXI_LPI_XIT_FRM BIT(30)
56 #define DMA_AXI_WR_OSR_LMT GENMASK(27, 24)
57 #define DMA_AXI_WR_OSR_LMT_SHIFT 24
58 #define DMA_AXI_RD_OSR_LMT GENMASK(19, 16)
59 #define DMA_AXI_RD_OSR_LMT_SHIFT 16
61 #define DMA_AXI_OSR_MAX 0xf
62 #define DMA_AXI_MAX_OSR_LIMIT ((DMA_AXI_OSR_MAX << DMA_AXI_WR_OSR_LMT_SHIFT) | \
63 (DMA_AXI_OSR_MAX << DMA_AXI_RD_OSR_LMT_SHIFT))
65 #define DMA_SYS_BUS_MB BIT(14)
66 #define DMA_AXI_1KBBE BIT(13)
67 #define DMA_SYS_BUS_AAL BIT(12)
68 #define DMA_SYS_BUS_EAME BIT(11)
69 #define DMA_AXI_BLEN256 BIT(7)
70 #define DMA_AXI_BLEN128 BIT(6)
71 #define DMA_AXI_BLEN64 BIT(5)
72 #define DMA_AXI_BLEN32 BIT(4)
73 #define DMA_AXI_BLEN16 BIT(3)
74 #define DMA_AXI_BLEN8 BIT(2)
75 #define DMA_AXI_BLEN4 BIT(1)
76 #define DMA_SYS_BUS_FB BIT(0)
78 #define DMA_BURST_LEN_DEFAULT (DMA_AXI_BLEN256 | DMA_AXI_BLEN128 | \
79 DMA_AXI_BLEN64 | DMA_AXI_BLEN32 | \
80 DMA_AXI_BLEN16 | DMA_AXI_BLEN8 | \
83 #define DMA_AXI_BURST_LEN_MASK 0x000000FE
85 /* Following DMA defines are chanels oriented */
86 #define DMA_CHAN_BASE_ADDR 0x00001100
87 #define DMA_CHAN_BASE_OFFSET 0x80
88 #define DMA_CHANX_BASE_ADDR(x) (DMA_CHAN_BASE_ADDR + \
89 (x * DMA_CHAN_BASE_OFFSET))
90 #define DMA_CHAN_REG_NUMBER 17
92 #define DMA_CHAN_CONTROL(x) DMA_CHANX_BASE_ADDR(x)
93 #define DMA_CHAN_TX_CONTROL(x) (DMA_CHANX_BASE_ADDR(x) + 0x4)
94 #define DMA_CHAN_RX_CONTROL(x) (DMA_CHANX_BASE_ADDR(x) + 0x8)
95 #define DMA_CHAN_TX_BASE_ADDR_HI(x) (DMA_CHANX_BASE_ADDR(x) + 0x10)
96 #define DMA_CHAN_TX_BASE_ADDR(x) (DMA_CHANX_BASE_ADDR(x) + 0x14)
97 #define DMA_CHAN_RX_BASE_ADDR_HI(x) (DMA_CHANX_BASE_ADDR(x) + 0x18)
98 #define DMA_CHAN_RX_BASE_ADDR(x) (DMA_CHANX_BASE_ADDR(x) + 0x1c)
99 #define DMA_CHAN_TX_END_ADDR(x) (DMA_CHANX_BASE_ADDR(x) + 0x20)
100 #define DMA_CHAN_RX_END_ADDR(x) (DMA_CHANX_BASE_ADDR(x) + 0x28)
101 #define DMA_CHAN_TX_RING_LEN(x) (DMA_CHANX_BASE_ADDR(x) + 0x2c)
102 #define DMA_CHAN_RX_RING_LEN(x) (DMA_CHANX_BASE_ADDR(x) + 0x30)
103 #define DMA_CHAN_INTR_ENA(x) (DMA_CHANX_BASE_ADDR(x) + 0x34)
104 #define DMA_CHAN_RX_WATCHDOG(x) (DMA_CHANX_BASE_ADDR(x) + 0x38)
105 #define DMA_CHAN_SLOT_CTRL_STATUS(x) (DMA_CHANX_BASE_ADDR(x) + 0x3c)
106 #define DMA_CHAN_CUR_TX_DESC(x) (DMA_CHANX_BASE_ADDR(x) + 0x44)
107 #define DMA_CHAN_CUR_RX_DESC(x) (DMA_CHANX_BASE_ADDR(x) + 0x4c)
108 #define DMA_CHAN_CUR_TX_BUF_ADDR(x) (DMA_CHANX_BASE_ADDR(x) + 0x54)
109 #define DMA_CHAN_CUR_RX_BUF_ADDR(x) (DMA_CHANX_BASE_ADDR(x) + 0x5c)
110 #define DMA_CHAN_STATUS(x) (DMA_CHANX_BASE_ADDR(x) + 0x60)
113 #define DMA_CONTROL_MSS_MASK GENMASK(13, 0)
115 /* DMA Tx Channel X Control register defines */
116 #define DMA_CONTROL_TSE BIT(12)
117 #define DMA_CONTROL_OSP BIT(4)
118 #define DMA_CONTROL_ST BIT(0)
120 /* DMA Rx Channel X Control register defines */
121 #define DMA_CONTROL_SR BIT(0)
122 #define DMA_RBSZ_MASK GENMASK(14, 1)
123 #define DMA_RBSZ_SHIFT 1
125 /* Interrupt status per channel */
126 #define DMA_CHAN_STATUS_REB GENMASK(21, 19)
127 #define DMA_CHAN_STATUS_REB_SHIFT 19
128 #define DMA_CHAN_STATUS_TEB GENMASK(18, 16)
129 #define DMA_CHAN_STATUS_TEB_SHIFT 16
130 #define DMA_CHAN_STATUS_NIS BIT(15)
131 #define DMA_CHAN_STATUS_AIS BIT(14)
132 #define DMA_CHAN_STATUS_CDE BIT(13)
133 #define DMA_CHAN_STATUS_FBE BIT(12)
134 #define DMA_CHAN_STATUS_ERI BIT(11)
135 #define DMA_CHAN_STATUS_ETI BIT(10)
136 #define DMA_CHAN_STATUS_RWT BIT(9)
137 #define DMA_CHAN_STATUS_RPS BIT(8)
138 #define DMA_CHAN_STATUS_RBU BIT(7)
139 #define DMA_CHAN_STATUS_RI BIT(6)
140 #define DMA_CHAN_STATUS_TBU BIT(2)
141 #define DMA_CHAN_STATUS_TPS BIT(1)
142 #define DMA_CHAN_STATUS_TI BIT(0)
144 /* Interrupt enable bits per channel */
145 #define DMA_CHAN_INTR_ENA_NIE BIT(16)
146 #define DMA_CHAN_INTR_ENA_AIE BIT(15)
147 #define DMA_CHAN_INTR_ENA_NIE_4_10 BIT(15)
148 #define DMA_CHAN_INTR_ENA_AIE_4_10 BIT(14)
149 #define DMA_CHAN_INTR_ENA_CDE BIT(13)
150 #define DMA_CHAN_INTR_ENA_FBE BIT(12)
151 #define DMA_CHAN_INTR_ENA_ERE BIT(11)
152 #define DMA_CHAN_INTR_ENA_ETE BIT(10)
153 #define DMA_CHAN_INTR_ENA_RWE BIT(9)
154 #define DMA_CHAN_INTR_ENA_RSE BIT(8)
155 #define DMA_CHAN_INTR_ENA_RBUE BIT(7)
156 #define DMA_CHAN_INTR_ENA_RIE BIT(6)
157 #define DMA_CHAN_INTR_ENA_TBUE BIT(2)
158 #define DMA_CHAN_INTR_ENA_TSE BIT(1)
159 #define DMA_CHAN_INTR_ENA_TIE BIT(0)
161 #define DMA_CHAN_INTR_NORMAL (DMA_CHAN_INTR_ENA_NIE | \
162 DMA_CHAN_INTR_ENA_RIE | \
163 DMA_CHAN_INTR_ENA_TIE)
165 #define DMA_CHAN_INTR_ABNORMAL (DMA_CHAN_INTR_ENA_AIE | \
166 DMA_CHAN_INTR_ENA_FBE)
167 /* DMA default interrupt mask for 4.00 */
168 #define DMA_CHAN_INTR_DEFAULT_MASK (DMA_CHAN_INTR_NORMAL | \
169 DMA_CHAN_INTR_ABNORMAL)
171 #define DMA_CHAN_INTR_NORMAL_4_10 (DMA_CHAN_INTR_ENA_NIE_4_10 | \
172 DMA_CHAN_INTR_ENA_RIE | \
173 DMA_CHAN_INTR_ENA_TIE)
175 #define DMA_CHAN_INTR_ABNORMAL_4_10 (DMA_CHAN_INTR_ENA_AIE_4_10 | \
176 DMA_CHAN_INTR_ENA_FBE)
177 /* DMA default interrupt mask for 4.10a */
178 #define DMA_CHAN_INTR_DEFAULT_MASK_4_10 (DMA_CHAN_INTR_NORMAL_4_10 | \
179 DMA_CHAN_INTR_ABNORMAL_4_10)
181 /* channel 0 specific fields */
182 #define DMA_CHAN0_DBG_STAT_TPS GENMASK(15, 12)
183 #define DMA_CHAN0_DBG_STAT_TPS_SHIFT 12
184 #define DMA_CHAN0_DBG_STAT_RPS GENMASK(11, 8)
185 #define DMA_CHAN0_DBG_STAT_RPS_SHIFT 8
187 int dwmac4_dma_reset(void __iomem *ioaddr);
188 void dwmac4_enable_dma_irq(void __iomem *ioaddr, u32 chan);
189 void dwmac410_enable_dma_irq(void __iomem *ioaddr, u32 chan);
190 void dwmac4_disable_dma_irq(void __iomem *ioaddr, u32 chan);
191 void dwmac4_dma_start_tx(void __iomem *ioaddr, u32 chan);
192 void dwmac4_dma_stop_tx(void __iomem *ioaddr, u32 chan);
193 void dwmac4_dma_start_rx(void __iomem *ioaddr, u32 chan);
194 void dwmac4_dma_stop_rx(void __iomem *ioaddr, u32 chan);
195 int dwmac4_dma_interrupt(void __iomem *ioaddr,
196 struct stmmac_extra_stats *x, u32 chan);
197 void dwmac4_set_rx_ring_len(void __iomem *ioaddr, u32 len, u32 chan);
198 void dwmac4_set_tx_ring_len(void __iomem *ioaddr, u32 len, u32 chan);
199 void dwmac4_set_rx_tail_ptr(void __iomem *ioaddr, u32 tail_ptr, u32 chan);
200 void dwmac4_set_tx_tail_ptr(void __iomem *ioaddr, u32 tail_ptr, u32 chan);
202 #endif /* __DWMAC4_DMA_H__ */