2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <asm-generic/kmap_types.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/io-mapping.h>
41 #include <linux/interrupt.h>
42 #include <linux/mlx5/driver.h>
43 #include <linux/mlx5/cq.h>
44 #include <linux/mlx5/qp.h>
45 #include <linux/mlx5/srq.h>
46 #include <linux/debugfs.h>
47 #include <linux/kmod.h>
48 #include <linux/mlx5/mlx5_ifc.h>
49 #include "mlx5_core.h"
51 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
52 MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver");
53 MODULE_LICENSE("Dual BSD/GPL");
54 MODULE_VERSION(DRIVER_VERSION);
56 int mlx5_core_debug_mask;
57 module_param_named(debug_mask, mlx5_core_debug_mask, int, 0644);
58 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
60 #define MLX5_DEFAULT_PROF 2
61 static int prof_sel = MLX5_DEFAULT_PROF;
62 module_param_named(prof_sel, prof_sel, int, 0444);
63 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
65 struct workqueue_struct *mlx5_core_wq;
66 static LIST_HEAD(intf_list);
67 static LIST_HEAD(dev_list);
68 static DEFINE_MUTEX(intf_mutex);
70 struct mlx5_device_context {
71 struct list_head list;
72 struct mlx5_interface *intf;
76 static struct mlx5_profile profile[] = {
81 .mask = MLX5_PROF_MASK_QP_SIZE,
85 .mask = MLX5_PROF_MASK_QP_SIZE |
86 MLX5_PROF_MASK_MR_CACHE,
155 static int set_dma_caps(struct pci_dev *pdev)
159 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
161 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
162 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
164 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
169 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
172 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
173 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
176 "Can't set consistent PCI DMA mask, aborting\n");
181 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
185 static int request_bar(struct pci_dev *pdev)
189 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
190 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
194 err = pci_request_regions(pdev, DRIVER_NAME);
196 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
201 static void release_bar(struct pci_dev *pdev)
203 pci_release_regions(pdev);
206 static int mlx5_enable_msix(struct mlx5_core_dev *dev)
208 struct mlx5_priv *priv = &dev->priv;
209 struct mlx5_eq_table *table = &priv->eq_table;
210 int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq);
214 nvec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() +
215 MLX5_EQ_VEC_COMP_BASE;
216 nvec = min_t(int, nvec, num_eqs);
217 if (nvec <= MLX5_EQ_VEC_COMP_BASE)
220 priv->msix_arr = kcalloc(nvec, sizeof(*priv->msix_arr), GFP_KERNEL);
222 priv->irq_info = kcalloc(nvec, sizeof(*priv->irq_info), GFP_KERNEL);
223 if (!priv->msix_arr || !priv->irq_info)
226 for (i = 0; i < nvec; i++)
227 priv->msix_arr[i].entry = i;
229 nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr,
230 MLX5_EQ_VEC_COMP_BASE + 1, nvec);
234 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
239 kfree(priv->irq_info);
240 kfree(priv->msix_arr);
244 static void mlx5_disable_msix(struct mlx5_core_dev *dev)
246 struct mlx5_priv *priv = &dev->priv;
248 pci_disable_msix(dev->pdev);
249 kfree(priv->irq_info);
250 kfree(priv->msix_arr);
253 struct mlx5_reg_host_endianess {
259 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
262 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
263 MLX5_DEV_CAP_FLAG_DCT,
266 static u16 to_fw_pkey_sz(u32 size)
282 pr_warn("invalid pkey table size %d\n", size);
287 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type,
288 enum mlx5_cap_mode cap_mode)
290 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
291 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
292 void *out, *hca_caps;
293 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
296 memset(in, 0, sizeof(in));
297 out = kzalloc(out_sz, GFP_KERNEL);
301 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
302 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
303 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
307 err = mlx5_cmd_status_to_err_v2(out);
310 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
311 cap_type, cap_mode, err);
315 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
318 case HCA_CAP_OPMOD_GET_MAX:
319 memcpy(dev->hca_caps_max[cap_type], hca_caps,
320 MLX5_UN_SZ_BYTES(hca_cap_union));
322 case HCA_CAP_OPMOD_GET_CUR:
323 memcpy(dev->hca_caps_cur[cap_type], hca_caps,
324 MLX5_UN_SZ_BYTES(hca_cap_union));
328 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
338 static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz)
340 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)];
343 memset(out, 0, sizeof(out));
345 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
346 err = mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
350 err = mlx5_cmd_status_to_err_v2(out);
355 static int handle_hca_cap(struct mlx5_core_dev *dev)
357 void *set_ctx = NULL;
358 struct mlx5_profile *prof = dev->profile;
360 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
363 set_ctx = kzalloc(set_sz, GFP_KERNEL);
367 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL, HCA_CAP_OPMOD_GET_MAX);
371 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL, HCA_CAP_OPMOD_GET_CUR);
375 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
377 memcpy(set_hca_cap, dev->hca_caps_cur[MLX5_CAP_GENERAL],
378 MLX5_ST_SZ_BYTES(cmd_hca_cap));
380 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
381 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
383 /* we limit the size of the pkey table to 128 entries for now */
384 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
387 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
388 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
391 /* disable cmdif checksum */
392 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
394 err = set_caps(dev, set_ctx, set_sz);
401 static int set_hca_ctrl(struct mlx5_core_dev *dev)
403 struct mlx5_reg_host_endianess he_in;
404 struct mlx5_reg_host_endianess he_out;
407 memset(&he_in, 0, sizeof(he_in));
408 he_in.he = MLX5_SET_HOST_ENDIANNESS;
409 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
410 &he_out, sizeof(he_out),
411 MLX5_REG_HOST_ENDIANNESS, 0, 1);
415 static int mlx5_core_enable_hca(struct mlx5_core_dev *dev)
418 struct mlx5_enable_hca_mbox_in in;
419 struct mlx5_enable_hca_mbox_out out;
421 memset(&in, 0, sizeof(in));
422 memset(&out, 0, sizeof(out));
423 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_ENABLE_HCA);
424 err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
429 return mlx5_cmd_status_to_err(&out.hdr);
434 static int mlx5_core_disable_hca(struct mlx5_core_dev *dev)
437 struct mlx5_disable_hca_mbox_in in;
438 struct mlx5_disable_hca_mbox_out out;
440 memset(&in, 0, sizeof(in));
441 memset(&out, 0, sizeof(out));
442 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_DISABLE_HCA);
443 err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
448 return mlx5_cmd_status_to_err(&out.hdr);
453 static int mlx5_irq_set_affinity_hint(struct mlx5_core_dev *mdev, int i)
455 struct mlx5_priv *priv = &mdev->priv;
456 struct msix_entry *msix = priv->msix_arr;
457 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
458 int numa_node = dev_to_node(&mdev->pdev->dev);
461 if (!zalloc_cpumask_var(&priv->irq_info[i].mask, GFP_KERNEL)) {
462 mlx5_core_warn(mdev, "zalloc_cpumask_var failed");
466 cpumask_set_cpu(cpumask_local_spread(i, numa_node),
467 priv->irq_info[i].mask);
469 err = irq_set_affinity_hint(irq, priv->irq_info[i].mask);
471 mlx5_core_warn(mdev, "irq_set_affinity_hint failed,irq 0x%.4x",
479 free_cpumask_var(priv->irq_info[i].mask);
483 static void mlx5_irq_clear_affinity_hint(struct mlx5_core_dev *mdev, int i)
485 struct mlx5_priv *priv = &mdev->priv;
486 struct msix_entry *msix = priv->msix_arr;
487 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
489 irq_set_affinity_hint(irq, NULL);
490 free_cpumask_var(priv->irq_info[i].mask);
493 static int mlx5_irq_set_affinity_hints(struct mlx5_core_dev *mdev)
498 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++) {
499 err = mlx5_irq_set_affinity_hint(mdev, i);
507 for (i--; i >= 0; i--)
508 mlx5_irq_clear_affinity_hint(mdev, i);
513 static void mlx5_irq_clear_affinity_hints(struct mlx5_core_dev *mdev)
517 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++)
518 mlx5_irq_clear_affinity_hint(mdev, i);
521 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn)
523 struct mlx5_eq_table *table = &dev->priv.eq_table;
524 struct mlx5_eq *eq, *n;
527 spin_lock(&table->lock);
528 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
529 if (eq->index == vector) {
536 spin_unlock(&table->lock);
540 EXPORT_SYMBOL(mlx5_vector2eqn);
542 static void free_comp_eqs(struct mlx5_core_dev *dev)
544 struct mlx5_eq_table *table = &dev->priv.eq_table;
545 struct mlx5_eq *eq, *n;
547 spin_lock(&table->lock);
548 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
550 spin_unlock(&table->lock);
551 if (mlx5_destroy_unmap_eq(dev, eq))
552 mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n",
555 spin_lock(&table->lock);
557 spin_unlock(&table->lock);
560 static int alloc_comp_eqs(struct mlx5_core_dev *dev)
562 struct mlx5_eq_table *table = &dev->priv.eq_table;
563 char name[MLX5_MAX_IRQ_NAME];
570 INIT_LIST_HEAD(&table->comp_eqs_list);
571 ncomp_vec = table->num_comp_vectors;
572 nent = MLX5_COMP_EQ_SIZE;
573 for (i = 0; i < ncomp_vec; i++) {
574 eq = kzalloc(sizeof(*eq), GFP_KERNEL);
580 snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i);
581 err = mlx5_create_map_eq(dev, eq,
582 i + MLX5_EQ_VEC_COMP_BASE, nent, 0,
583 name, &dev->priv.uuari.uars[0]);
588 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn);
590 spin_lock(&table->lock);
591 list_add_tail(&eq->list, &table->comp_eqs_list);
592 spin_unlock(&table->lock);
602 #ifdef CONFIG_MLX5_CORE_EN
603 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
605 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)];
606 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)];
607 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)];
608 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)];
612 memset(query_in, 0, sizeof(query_in));
613 memset(query_out, 0, sizeof(query_out));
615 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
617 err = mlx5_cmd_exec_check_status(dev, query_in, sizeof(query_in),
618 query_out, sizeof(query_out));
620 if (((struct mlx5_outbox_hdr *)query_out)->status ==
621 MLX5_CMD_STAT_BAD_OP_ERR) {
622 pr_debug("Only ISSI 0 is supported\n");
626 pr_err("failed to query ISSI\n");
630 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
632 if (sup_issi & (1 << 1)) {
633 memset(set_in, 0, sizeof(set_in));
634 memset(set_out, 0, sizeof(set_out));
636 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
637 MLX5_SET(set_issi_in, set_in, current_issi, 1);
639 err = mlx5_cmd_exec_check_status(dev, set_in, sizeof(set_in),
640 set_out, sizeof(set_out));
642 pr_err("failed to set ISSI=1\n");
649 } else if (sup_issi & (1 << 0) || !sup_issi) {
657 static int mlx5_dev_init(struct mlx5_core_dev *dev, struct pci_dev *pdev)
659 struct mlx5_priv *priv = &dev->priv;
663 pci_set_drvdata(dev->pdev, dev);
664 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
665 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
667 mutex_init(&priv->pgdir_mutex);
668 INIT_LIST_HEAD(&priv->pgdir_list);
669 spin_lock_init(&priv->mkey_lock);
671 priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root);
675 err = pci_enable_device(pdev);
677 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
681 err = request_bar(pdev);
683 dev_err(&pdev->dev, "error requesting BARs, aborting\n");
687 pci_set_master(pdev);
689 err = set_dma_caps(pdev);
691 dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n");
695 dev->iseg_base = pci_resource_start(dev->pdev, 0);
696 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
699 dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n");
702 dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
703 fw_rev_min(dev), fw_rev_sub(dev));
705 err = mlx5_cmd_init(dev);
707 dev_err(&pdev->dev, "Failed initializing command interface, aborting\n");
711 mlx5_pagealloc_init(dev);
713 err = mlx5_core_enable_hca(dev);
715 dev_err(&pdev->dev, "enable hca failed\n");
716 goto err_pagealloc_cleanup;
719 #ifdef CONFIG_MLX5_CORE_EN
720 err = mlx5_core_set_issi(dev);
722 dev_err(&pdev->dev, "failed to set issi\n");
723 goto err_disable_hca;
727 err = mlx5_satisfy_startup_pages(dev, 1);
729 dev_err(&pdev->dev, "failed to allocate boot pages\n");
730 goto err_disable_hca;
733 err = set_hca_ctrl(dev);
735 dev_err(&pdev->dev, "set_hca_ctrl failed\n");
736 goto reclaim_boot_pages;
739 err = handle_hca_cap(dev);
741 dev_err(&pdev->dev, "handle_hca_cap failed\n");
742 goto reclaim_boot_pages;
745 err = mlx5_satisfy_startup_pages(dev, 0);
747 dev_err(&pdev->dev, "failed to allocate init pages\n");
748 goto reclaim_boot_pages;
751 err = mlx5_pagealloc_start(dev);
753 dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n");
754 goto reclaim_boot_pages;
757 err = mlx5_cmd_init_hca(dev);
759 dev_err(&pdev->dev, "init hca failed\n");
760 goto err_pagealloc_stop;
763 mlx5_start_health_poll(dev);
765 err = mlx5_query_hca_caps(dev);
767 dev_err(&pdev->dev, "query hca failed\n");
771 err = mlx5_query_board_id(dev);
773 dev_err(&pdev->dev, "query board id failed\n");
777 err = mlx5_enable_msix(dev);
779 dev_err(&pdev->dev, "enable msix failed\n");
783 err = mlx5_eq_init(dev);
785 dev_err(&pdev->dev, "failed to initialize eq\n");
789 err = mlx5_alloc_uuars(dev, &priv->uuari);
791 dev_err(&pdev->dev, "Failed allocating uar, aborting\n");
795 err = mlx5_start_eqs(dev);
797 dev_err(&pdev->dev, "Failed to start pages and async EQs\n");
801 err = alloc_comp_eqs(dev);
803 dev_err(&pdev->dev, "Failed to alloc completion EQs\n");
807 err = mlx5_irq_set_affinity_hints(dev);
809 dev_err(&pdev->dev, "Failed to alloc affinity hint cpumask\n");
810 goto err_free_comp_eqs;
813 MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock);
815 mlx5_init_cq_table(dev);
816 mlx5_init_qp_table(dev);
817 mlx5_init_srq_table(dev);
818 mlx5_init_mr_table(dev);
829 mlx5_free_uuars(dev, &priv->uuari);
832 mlx5_eq_cleanup(dev);
835 mlx5_disable_msix(dev);
838 mlx5_stop_health_poll(dev);
839 if (mlx5_cmd_teardown_hca(dev)) {
840 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
845 mlx5_pagealloc_stop(dev);
848 mlx5_reclaim_startup_pages(dev);
851 mlx5_core_disable_hca(dev);
853 err_pagealloc_cleanup:
854 mlx5_pagealloc_cleanup(dev);
855 mlx5_cmd_cleanup(dev);
861 pci_clear_master(dev->pdev);
862 release_bar(dev->pdev);
865 pci_disable_device(dev->pdev);
868 debugfs_remove(priv->dbg_root);
872 static void mlx5_dev_cleanup(struct mlx5_core_dev *dev)
874 struct mlx5_priv *priv = &dev->priv;
876 mlx5_cleanup_srq_table(dev);
877 mlx5_cleanup_qp_table(dev);
878 mlx5_cleanup_cq_table(dev);
879 mlx5_irq_clear_affinity_hints(dev);
882 mlx5_free_uuars(dev, &priv->uuari);
883 mlx5_eq_cleanup(dev);
884 mlx5_disable_msix(dev);
885 mlx5_stop_health_poll(dev);
886 if (mlx5_cmd_teardown_hca(dev)) {
887 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
890 mlx5_pagealloc_stop(dev);
891 mlx5_reclaim_startup_pages(dev);
892 mlx5_core_disable_hca(dev);
893 mlx5_pagealloc_cleanup(dev);
894 mlx5_cmd_cleanup(dev);
896 pci_clear_master(dev->pdev);
897 release_bar(dev->pdev);
898 pci_disable_device(dev->pdev);
899 debugfs_remove(priv->dbg_root);
902 static void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
904 struct mlx5_device_context *dev_ctx;
905 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
907 dev_ctx = kmalloc(sizeof(*dev_ctx), GFP_KERNEL);
909 pr_warn("mlx5_add_device: alloc context failed\n");
913 dev_ctx->intf = intf;
914 dev_ctx->context = intf->add(dev);
916 if (dev_ctx->context) {
917 spin_lock_irq(&priv->ctx_lock);
918 list_add_tail(&dev_ctx->list, &priv->ctx_list);
919 spin_unlock_irq(&priv->ctx_lock);
925 static void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
927 struct mlx5_device_context *dev_ctx;
928 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
930 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
931 if (dev_ctx->intf == intf) {
932 spin_lock_irq(&priv->ctx_lock);
933 list_del(&dev_ctx->list);
934 spin_unlock_irq(&priv->ctx_lock);
936 intf->remove(dev, dev_ctx->context);
941 static int mlx5_register_device(struct mlx5_core_dev *dev)
943 struct mlx5_priv *priv = &dev->priv;
944 struct mlx5_interface *intf;
946 mutex_lock(&intf_mutex);
947 list_add_tail(&priv->dev_list, &dev_list);
948 list_for_each_entry(intf, &intf_list, list)
949 mlx5_add_device(intf, priv);
950 mutex_unlock(&intf_mutex);
954 static void mlx5_unregister_device(struct mlx5_core_dev *dev)
956 struct mlx5_priv *priv = &dev->priv;
957 struct mlx5_interface *intf;
959 mutex_lock(&intf_mutex);
960 list_for_each_entry(intf, &intf_list, list)
961 mlx5_remove_device(intf, priv);
962 list_del(&priv->dev_list);
963 mutex_unlock(&intf_mutex);
966 int mlx5_register_interface(struct mlx5_interface *intf)
968 struct mlx5_priv *priv;
970 if (!intf->add || !intf->remove)
973 mutex_lock(&intf_mutex);
974 list_add_tail(&intf->list, &intf_list);
975 list_for_each_entry(priv, &dev_list, dev_list)
976 mlx5_add_device(intf, priv);
977 mutex_unlock(&intf_mutex);
981 EXPORT_SYMBOL(mlx5_register_interface);
983 void mlx5_unregister_interface(struct mlx5_interface *intf)
985 struct mlx5_priv *priv;
987 mutex_lock(&intf_mutex);
988 list_for_each_entry(priv, &dev_list, dev_list)
989 mlx5_remove_device(intf, priv);
990 list_del(&intf->list);
991 mutex_unlock(&intf_mutex);
993 EXPORT_SYMBOL(mlx5_unregister_interface);
995 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol)
997 struct mlx5_priv *priv = &mdev->priv;
998 struct mlx5_device_context *dev_ctx;
1000 void *result = NULL;
1002 spin_lock_irqsave(&priv->ctx_lock, flags);
1004 list_for_each_entry(dev_ctx, &mdev->priv.ctx_list, list)
1005 if ((dev_ctx->intf->protocol == protocol) &&
1006 dev_ctx->intf->get_dev) {
1007 result = dev_ctx->intf->get_dev(dev_ctx->context);
1011 spin_unlock_irqrestore(&priv->ctx_lock, flags);
1015 EXPORT_SYMBOL(mlx5_get_protocol_dev);
1017 static void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event,
1018 unsigned long param)
1020 struct mlx5_priv *priv = &dev->priv;
1021 struct mlx5_device_context *dev_ctx;
1022 unsigned long flags;
1024 spin_lock_irqsave(&priv->ctx_lock, flags);
1026 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
1027 if (dev_ctx->intf->event)
1028 dev_ctx->intf->event(dev, dev_ctx->context, event, param);
1030 spin_unlock_irqrestore(&priv->ctx_lock, flags);
1033 struct mlx5_core_event_handler {
1034 void (*event)(struct mlx5_core_dev *dev,
1035 enum mlx5_dev_event event,
1039 #define MLX5_IB_MOD "mlx5_ib"
1041 static int init_one(struct pci_dev *pdev,
1042 const struct pci_device_id *id)
1044 struct mlx5_core_dev *dev;
1045 struct mlx5_priv *priv;
1048 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1050 dev_err(&pdev->dev, "kzalloc failed\n");
1055 pci_set_drvdata(pdev, dev);
1057 if (prof_sel < 0 || prof_sel >= ARRAY_SIZE(profile)) {
1058 pr_warn("selected profile out of range, selecting default (%d)\n",
1060 prof_sel = MLX5_DEFAULT_PROF;
1062 dev->profile = &profile[prof_sel];
1063 dev->event = mlx5_core_event;
1065 INIT_LIST_HEAD(&priv->ctx_list);
1066 spin_lock_init(&priv->ctx_lock);
1067 err = mlx5_dev_init(dev, pdev);
1069 dev_err(&pdev->dev, "mlx5_dev_init failed %d\n", err);
1073 err = mlx5_register_device(dev);
1075 dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err);
1079 err = request_module_nowait(MLX5_IB_MOD);
1081 pr_info("failed request module on %s\n", MLX5_IB_MOD);
1086 mlx5_dev_cleanup(dev);
1091 static void remove_one(struct pci_dev *pdev)
1093 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1095 mlx5_unregister_device(dev);
1096 mlx5_dev_cleanup(dev);
1100 static const struct pci_device_id mlx5_core_pci_table[] = {
1101 { PCI_VDEVICE(MELLANOX, 0x1011) }, /* Connect-IB */
1102 { PCI_VDEVICE(MELLANOX, 0x1012) }, /* Connect-IB VF */
1103 { PCI_VDEVICE(MELLANOX, 0x1013) }, /* ConnectX-4 */
1104 { PCI_VDEVICE(MELLANOX, 0x1014) }, /* ConnectX-4 VF */
1105 { PCI_VDEVICE(MELLANOX, 0x1015) }, /* ConnectX-4LX */
1106 { PCI_VDEVICE(MELLANOX, 0x1016) }, /* ConnectX-4LX VF */
1110 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1112 static struct pci_driver mlx5_core_driver = {
1113 .name = DRIVER_NAME,
1114 .id_table = mlx5_core_pci_table,
1116 .remove = remove_one
1119 static int __init init(void)
1123 mlx5_register_debugfs();
1124 mlx5_core_wq = create_singlethread_workqueue("mlx5_core_wq");
1125 if (!mlx5_core_wq) {
1131 err = pci_register_driver(&mlx5_core_driver);
1135 #ifdef CONFIG_MLX5_CORE_EN
1142 mlx5_health_cleanup();
1143 destroy_workqueue(mlx5_core_wq);
1145 mlx5_unregister_debugfs();
1149 static void __exit cleanup(void)
1151 #ifdef CONFIG_MLX5_CORE_EN
1154 pci_unregister_driver(&mlx5_core_driver);
1155 mlx5_health_cleanup();
1156 destroy_workqueue(mlx5_core_wq);
1157 mlx5_unregister_debugfs();
1161 module_exit(cleanup);