drivers/net/ethernet/mellanox/mlx4/qp.c

   1 /*
   2  * Copyright (c) 2004 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
   4  * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
   5  * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
   6  *
   7  * This software is available to you under a choice of one of two
   8  * licenses.  You may choose to be licensed under the terms of the GNU
   9  * General Public License (GPL) Version 2, available from the file
  10  * COPYING in the main directory of this source tree, or the
  11  * OpenIB.org BSD license below:
  12  *
  13  *     Redistribution and use in source and binary forms, with or
  14  *     without modification, are permitted provided that the following
  15  *     conditions are met:
  16  *
  17  *      - Redistributions of source code must retain the above
  18  *        copyright notice, this list of conditions and the following
  19  *        disclaimer.
  20  *
  21  *      - Redistributions in binary form must reproduce the above
  22  *        copyright notice, this list of conditions and the following
  23  *        disclaimer in the documentation and/or other materials
  24  *        provided with the distribution.
  25  *
  26  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  27  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  28  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  29  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  30  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  31  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  32  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  33  * SOFTWARE.
  34  */
  35
  36 #include <linux/gfp.h>
  37 #include <linux/export.h>
  38
  39 #include <linux/mlx4/cmd.h>
  40 #include <linux/mlx4/qp.h>
  41
  42 #include "mlx4.h"
  43 #include "icm.h"
  44
  45 /* QP to support BF should have bits 6,7 cleared */
  46 #define MLX4_BF_QP_SKIP_MASK    0xc0
  47 #define MLX4_MAX_BF_QP_RANGE    0x40
  48
  49 void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type)
  50 {
  51         struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table;
  52         struct mlx4_qp *qp;
  53
  54         spin_lock(&qp_table->lock);
  55
  56         qp = __mlx4_qp_lookup(dev, qpn);
  57         if (qp)
  58                 refcount_inc(&qp->refcount);
  59
  60         spin_unlock(&qp_table->lock);
  61
  62         if (!qp) {
  63                 mlx4_dbg(dev, "Async event for none existent QP %08x\n", qpn);
  64                 return;
  65         }
  66
  67         qp->event(qp, event_type);
  68
  69         if (refcount_dec_and_test(&qp->refcount))
  70                 complete(&qp->free);
  71 }
  72
  73 /* used for INIT/CLOSE port logic */
  74 static int is_master_qp0(struct mlx4_dev *dev, struct mlx4_qp *qp, int *real_qp0, int *proxy_qp0)
  75 {
  76         /* this procedure is called after we already know we are on the master */
  77         /* qp0 is either the proxy qp0, or the real qp0 */
  78         u32 pf_proxy_offset = dev->phys_caps.base_proxy_sqpn + 8 * mlx4_master_func_num(dev);
  79         *proxy_qp0 = qp->qpn >= pf_proxy_offset && qp->qpn <= pf_proxy_offset + 1;
  80
  81         *real_qp0 = qp->qpn >= dev->phys_caps.base_sqpn &&
  82                 qp->qpn <= dev->phys_caps.base_sqpn + 1;
  83
  84         return *real_qp0 || *proxy_qp0;
  85 }
  86
  87 static int __mlx4_qp_modify(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
  88                      enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state,
  89                      struct mlx4_qp_context *context,
  90                      enum mlx4_qp_optpar optpar,
  91                      int sqd_event, struct mlx4_qp *qp, int native)
  92 {
  93         static const u16 op[MLX4_QP_NUM_STATE][MLX4_QP_NUM_STATE] = {
  94                 [MLX4_QP_STATE_RST] = {
  95                         [MLX4_QP_STATE_RST]     = MLX4_CMD_2RST_QP,
  96                         [MLX4_QP_STATE_ERR]     = MLX4_CMD_2ERR_QP,
  97                         [MLX4_QP_STATE_INIT]    = MLX4_CMD_RST2INIT_QP,
  98                 },
  99                 [MLX4_QP_STATE_INIT]  = {
 100                         [MLX4_QP_STATE_RST]     = MLX4_CMD_2RST_QP,
 101                         [MLX4_QP_STATE_ERR]     = MLX4_CMD_2ERR_QP,
 102                         [MLX4_QP_STATE_INIT]    = MLX4_CMD_INIT2INIT_QP,
 103                         [MLX4_QP_STATE_RTR]     = MLX4_CMD_INIT2RTR_QP,
 104                 },
 105                 [MLX4_QP_STATE_RTR]   = {
 106                         [MLX4_QP_STATE_RST]     = MLX4_CMD_2RST_QP,
 107                         [MLX4_QP_STATE_ERR]     = MLX4_CMD_2ERR_QP,
 108                         [MLX4_QP_STATE_RTS]     = MLX4_CMD_RTR2RTS_QP,
 109                 },
 110                 [MLX4_QP_STATE_RTS]   = {
 111                         [MLX4_QP_STATE_RST]     = MLX4_CMD_2RST_QP,
 112                         [MLX4_QP_STATE_ERR]     = MLX4_CMD_2ERR_QP,
 113                         [MLX4_QP_STATE_RTS]     = MLX4_CMD_RTS2RTS_QP,
 114                         [MLX4_QP_STATE_SQD]     = MLX4_CMD_RTS2SQD_QP,
 115                 },
 116                 [MLX4_QP_STATE_SQD] = {
 117                         [MLX4_QP_STATE_RST]     = MLX4_CMD_2RST_QP,
 118                         [MLX4_QP_STATE_ERR]     = MLX4_CMD_2ERR_QP,
 119                         [MLX4_QP_STATE_RTS]     = MLX4_CMD_SQD2RTS_QP,
 120                         [MLX4_QP_STATE_SQD]     = MLX4_CMD_SQD2SQD_QP,
 121                 },
 122                 [MLX4_QP_STATE_SQER] = {
 123                         [MLX4_QP_STATE_RST]     = MLX4_CMD_2RST_QP,
 124                         [MLX4_QP_STATE_ERR]     = MLX4_CMD_2ERR_QP,
 125                         [MLX4_QP_STATE_RTS]     = MLX4_CMD_SQERR2RTS_QP,
 126                 },
 127                 [MLX4_QP_STATE_ERR] = {
 128                         [MLX4_QP_STATE_RST]     = MLX4_CMD_2RST_QP,
 129                         [MLX4_QP_STATE_ERR]     = MLX4_CMD_2ERR_QP,
 130                 }
 131         };
 132
 133         struct mlx4_priv *priv = mlx4_priv(dev);
 134         struct mlx4_cmd_mailbox *mailbox;
 135         int ret = 0;
 136         int real_qp0 = 0;
 137         int proxy_qp0 = 0;
 138         u8 port;
 139
 140         if (cur_state >= MLX4_QP_NUM_STATE || new_state >= MLX4_QP_NUM_STATE ||
 141             !op[cur_state][new_state])
 142                 return -EINVAL;
 143
 144         if (op[cur_state][new_state] == MLX4_CMD_2RST_QP) {
 145                 ret = mlx4_cmd(dev, 0, qp->qpn, 2,
 146                         MLX4_CMD_2RST_QP, MLX4_CMD_TIME_CLASS_A, native);
 147                 if (mlx4_is_master(dev) && cur_state != MLX4_QP_STATE_ERR &&
 148                     cur_state != MLX4_QP_STATE_RST &&
 149                     is_master_qp0(dev, qp, &real_qp0, &proxy_qp0)) {
 150                         port = (qp->qpn & 1) + 1;
 151                         if (proxy_qp0)
 152                                 priv->mfunc.master.qp0_state[port].proxy_qp0_active = 0;
 153                         else
 154                                 priv->mfunc.master.qp0_state[port].qp0_active = 0;
 155                 }
 156                 return ret;
 157         }
 158
 159         mailbox = mlx4_alloc_cmd_mailbox(dev);
 160         if (IS_ERR(mailbox))
 161                 return PTR_ERR(mailbox);
 162
 163         if (cur_state == MLX4_QP_STATE_RST && new_state == MLX4_QP_STATE_INIT) {
 164                 u64 mtt_addr = mlx4_mtt_addr(dev, mtt);
 165                 context->mtt_base_addr_h = mtt_addr >> 32;
 166                 context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff);
 167                 context->log_page_size   = mtt->page_shift - MLX4_ICM_PAGE_SHIFT;
 168         }
 169
 170         if ((cur_state == MLX4_QP_STATE_RTR) &&
 171             (new_state == MLX4_QP_STATE_RTS) &&
 172             dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2)
 173                 context->roce_entropy =
 174                         cpu_to_be16(mlx4_qp_roce_entropy(dev, qp->qpn));
 175
 176         *(__be32 *) mailbox->buf = cpu_to_be32(optpar);
 177         memcpy(mailbox->buf + 8, context, sizeof(*context));
 178
 179         ((struct mlx4_qp_context *) (mailbox->buf + 8))->local_qpn =
 180                 cpu_to_be32(qp->qpn);
 181
 182         ret = mlx4_cmd(dev, mailbox->dma,
 183                        qp->qpn | (!!sqd_event << 31),
 184                        new_state == MLX4_QP_STATE_RST ? 2 : 0,
 185                        op[cur_state][new_state], MLX4_CMD_TIME_CLASS_C, native);
 186
 187         if (mlx4_is_master(dev) && is_master_qp0(dev, qp, &real_qp0, &proxy_qp0)) {
 188                 port = (qp->qpn & 1) + 1;
 189                 if (cur_state != MLX4_QP_STATE_ERR &&
 190                     cur_state != MLX4_QP_STATE_RST &&
 191                     new_state == MLX4_QP_STATE_ERR) {
 192                         if (proxy_qp0)
 193                                 priv->mfunc.master.qp0_state[port].proxy_qp0_active = 0;
 194                         else
 195                                 priv->mfunc.master.qp0_state[port].qp0_active = 0;
 196                 } else if (new_state == MLX4_QP_STATE_RTR) {
 197                         if (proxy_qp0)
 198                                 priv->mfunc.master.qp0_state[port].proxy_qp0_active = 1;
 199                         else
 200                                 priv->mfunc.master.qp0_state[port].qp0_active = 1;
 201                 }
 202         }
 203
 204         mlx4_free_cmd_mailbox(dev, mailbox);
 205         return ret;
 206 }
 207
 208 int mlx4_qp_modify(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
 209                    enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state,
 210                    struct mlx4_qp_context *context,
 211                    enum mlx4_qp_optpar optpar,
 212                    int sqd_event, struct mlx4_qp *qp)
 213 {
 214         return __mlx4_qp_modify(dev, mtt, cur_state, new_state, context,
 215                                 optpar, sqd_event, qp, 0);
 216 }
 217 EXPORT_SYMBOL_GPL(mlx4_qp_modify);
 218
 219 int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
 220                             int *base, u8 flags)
 221 {
 222         u32 uid;
 223         int bf_qp = !!(flags & (u8)MLX4_RESERVE_ETH_BF_QP);
 224
 225         struct mlx4_priv *priv = mlx4_priv(dev);
 226         struct mlx4_qp_table *qp_table = &priv->qp_table;
 227
 228         if (cnt > MLX4_MAX_BF_QP_RANGE && bf_qp)
 229                 return -ENOMEM;
 230
 231         uid = MLX4_QP_TABLE_ZONE_GENERAL;
 232         if (flags & (u8)MLX4_RESERVE_A0_QP) {
 233                 if (bf_qp)
 234                         uid = MLX4_QP_TABLE_ZONE_RAW_ETH;
 235                 else
 236                         uid = MLX4_QP_TABLE_ZONE_RSS;
 237         }
 238
 239         *base = mlx4_zone_alloc_entries(qp_table->zones, uid, cnt, align,
 240                                         bf_qp ? MLX4_BF_QP_SKIP_MASK : 0, NULL);
 241         if (*base == -1)
 242                 return -ENOMEM;
 243
 244         return 0;
 245 }
 246
 247 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
 248                           int *base, u8 flags, u8 usage)
 249 {
 250         u32 in_modifier = RES_QP | (((u32)usage & 3) << 30);
 251         u64 in_param = 0;
 252         u64 out_param;
 253         int err;
 254
 255         /* Turn off all unsupported QP allocation flags */
 256         flags &= dev->caps.alloc_res_qp_mask;
 257
 258         if (mlx4_is_mfunc(dev)) {
 259                 set_param_l(&in_param, (((u32)flags) << 24) | (u32)cnt);
 260                 set_param_h(&in_param, align);
 261                 err = mlx4_cmd_imm(dev, in_param, &out_param,
 262                                    in_modifier, RES_OP_RESERVE,
 263                                    MLX4_CMD_ALLOC_RES,
 264                                    MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
 265                 if (err)
 266                         return err;
 267
 268                 *base = get_param_l(&out_param);
 269                 return 0;
 270         }
 271         return __mlx4_qp_reserve_range(dev, cnt, align, base, flags);
 272 }
 273 EXPORT_SYMBOL_GPL(mlx4_qp_reserve_range);
 274
 275 void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt)
 276 {
 277         struct mlx4_priv *priv = mlx4_priv(dev);
 278         struct mlx4_qp_table *qp_table = &priv->qp_table;
 279
 280         if (mlx4_is_qp_reserved(dev, (u32) base_qpn))
 281                 return;
 282         mlx4_zone_free_entries_unique(qp_table->zones, base_qpn, cnt);
 283 }
 284
 285 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt)
 286 {
 287         u64 in_param = 0;
 288         int err;
 289
 290         if (mlx4_is_mfunc(dev)) {
 291                 set_param_l(&in_param, base_qpn);
 292                 set_param_h(&in_param, cnt);
 293                 err = mlx4_cmd(dev, in_param, RES_QP, RES_OP_RESERVE,
 294                                MLX4_CMD_FREE_RES,
 295                                MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
 296                 if (err) {
 297                         mlx4_warn(dev, "Failed to release qp range base:%d cnt:%d\n",
 298                                   base_qpn, cnt);
 299                 }
 300         } else
 301                  __mlx4_qp_release_range(dev, base_qpn, cnt);
 302 }
 303 EXPORT_SYMBOL_GPL(mlx4_qp_release_range);
 304
 305 int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn)
 306 {
 307         struct mlx4_priv *priv = mlx4_priv(dev);
 308         struct mlx4_qp_table *qp_table = &priv->qp_table;
 309         int err;
 310
 311         err = mlx4_table_get(dev, &qp_table->qp_table, qpn);
 312         if (err)
 313                 goto err_out;
 314
 315         err = mlx4_table_get(dev, &qp_table->auxc_table, qpn);
 316         if (err)
 317                 goto err_put_qp;
 318
 319         err = mlx4_table_get(dev, &qp_table->altc_table, qpn);
 320         if (err)
 321                 goto err_put_auxc;
 322
 323         err = mlx4_table_get(dev, &qp_table->rdmarc_table, qpn);
 324         if (err)
 325                 goto err_put_altc;
 326
 327         err = mlx4_table_get(dev, &qp_table->cmpt_table, qpn);
 328         if (err)
 329                 goto err_put_rdmarc;
 330
 331         return 0;
 332
 333 err_put_rdmarc:
 334         mlx4_table_put(dev, &qp_table->rdmarc_table, qpn);
 335
 336 err_put_altc:
 337         mlx4_table_put(dev, &qp_table->altc_table, qpn);
 338
 339 err_put_auxc:
 340         mlx4_table_put(dev, &qp_table->auxc_table, qpn);
 341
 342 err_put_qp:
 343         mlx4_table_put(dev, &qp_table->qp_table, qpn);
 344
 345 err_out:
 346         return err;
 347 }
 348
 349 static int mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn)
 350 {
 351         u64 param = 0;
 352
 353         if (mlx4_is_mfunc(dev)) {
 354                 set_param_l(&param, qpn);
 355                 return mlx4_cmd_imm(dev, param, &param, RES_QP, RES_OP_MAP_ICM,
 356                                     MLX4_CMD_ALLOC_RES, MLX4_CMD_TIME_CLASS_A,
 357                                     MLX4_CMD_WRAPPED);
 358         }
 359         return __mlx4_qp_alloc_icm(dev, qpn);
 360 }
 361
 362 void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn)
 363 {
 364         struct mlx4_priv *priv = mlx4_priv(dev);
 365         struct mlx4_qp_table *qp_table = &priv->qp_table;
 366
 367         mlx4_table_put(dev, &qp_table->cmpt_table, qpn);
 368         mlx4_table_put(dev, &qp_table->rdmarc_table, qpn);
 369         mlx4_table_put(dev, &qp_table->altc_table, qpn);
 370         mlx4_table_put(dev, &qp_table->auxc_table, qpn);
 371         mlx4_table_put(dev, &qp_table->qp_table, qpn);
 372 }
 373
 374 static void mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn)
 375 {
 376         u64 in_param = 0;
 377
 378         if (mlx4_is_mfunc(dev)) {
 379                 set_param_l(&in_param, qpn);
 380                 if (mlx4_cmd(dev, in_param, RES_QP, RES_OP_MAP_ICM,
 381                              MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
 382                              MLX4_CMD_WRAPPED))
 383                         mlx4_warn(dev, "Failed to free icm of qp:%d\n", qpn);
 384         } else
 385                 __mlx4_qp_free_icm(dev, qpn);
 386 }
 387
 388 struct mlx4_qp *mlx4_qp_lookup(struct mlx4_dev *dev, u32 qpn)
 389 {
 390         struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table;
 391         struct mlx4_qp *qp;
 392
 393         spin_lock(&qp_table->lock);
 394
 395         qp = __mlx4_qp_lookup(dev, qpn);
 396
 397         spin_unlock(&qp_table->lock);
 398         return qp;
 399 }
 400
 401 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp)
 402 {
 403         struct mlx4_priv *priv = mlx4_priv(dev);
 404         struct mlx4_qp_table *qp_table = &priv->qp_table;
 405         int err;
 406
 407         if (!qpn)
 408                 return -EINVAL;
 409
 410         qp->qpn = qpn;
 411
 412         err = mlx4_qp_alloc_icm(dev, qpn);
 413         if (err)
 414                 return err;
 415
 416         spin_lock_irq(&qp_table->lock);
 417         err = radix_tree_insert(&dev->qp_table_tree, qp->qpn &
 418                                 (dev->caps.num_qps - 1), qp);
 419         spin_unlock_irq(&qp_table->lock);
 420         if (err)
 421                 goto err_icm;
 422
 423         refcount_set(&qp->refcount, 1);
 424         init_completion(&qp->free);
 425
 426         return 0;
 427
 428 err_icm:
 429         mlx4_qp_free_icm(dev, qpn);
 430         return err;
 431 }
 432
 433 EXPORT_SYMBOL_GPL(mlx4_qp_alloc);
 434
 435 int mlx4_update_qp(struct mlx4_dev *dev, u32 qpn,
 436                    enum mlx4_update_qp_attr attr,
 437                    struct mlx4_update_qp_params *params)
 438 {
 439         struct mlx4_cmd_mailbox *mailbox;
 440         struct mlx4_update_qp_context *cmd;
 441         u64 pri_addr_path_mask = 0;
 442         u64 qp_mask = 0;
 443         int err = 0;
 444
 445         if (!attr || (attr & ~MLX4_UPDATE_QP_SUPPORTED_ATTRS))
 446                 return -EINVAL;
 447
 448         mailbox = mlx4_alloc_cmd_mailbox(dev);
 449         if (IS_ERR(mailbox))
 450                 return PTR_ERR(mailbox);
 451
 452         cmd = (struct mlx4_update_qp_context *)mailbox->buf;
 453
 454         if (attr & MLX4_UPDATE_QP_SMAC) {
 455                 pri_addr_path_mask |= 1ULL << MLX4_UPD_QP_PATH_MASK_MAC_INDEX;
 456                 cmd->qp_context.pri_path.grh_mylmc = params->smac_index;
 457         }
 458
 459         if (attr & MLX4_UPDATE_QP_ETH_SRC_CHECK_MC_LB) {
 460                 if (!(dev->caps.flags2
 461                       & MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB)) {
 462                         mlx4_warn(dev,
 463                                   "Trying to set src check LB, but it isn't supported\n");
 464                         err = -EOPNOTSUPP;
 465                         goto out;
 466                 }
 467                 pri_addr_path_mask |=
 468                         1ULL << MLX4_UPD_QP_PATH_MASK_ETH_SRC_CHECK_MC_LB;
 469                 if (params->flags &
 470                     MLX4_UPDATE_QP_PARAMS_FLAGS_ETH_CHECK_MC_LB) {
 471                         cmd->qp_context.pri_path.fl |=
 472                                 MLX4_FL_ETH_SRC_CHECK_MC_LB;
 473                 }
 474         }
 475
 476         if (attr & MLX4_UPDATE_QP_VSD) {
 477                 qp_mask |= 1ULL << MLX4_UPD_QP_MASK_VSD;
 478                 if (params->flags & MLX4_UPDATE_QP_PARAMS_FLAGS_VSD_ENABLE)
 479                         cmd->qp_context.param3 |= cpu_to_be32(MLX4_STRIP_VLAN);
 480         }
 481
 482         if (attr & MLX4_UPDATE_QP_RATE_LIMIT) {
 483                 qp_mask |= 1ULL << MLX4_UPD_QP_MASK_RATE_LIMIT;
 484                 cmd->qp_context.rate_limit_params = cpu_to_be16((params->rate_unit << 14) | params->rate_val);
 485         }
 486
 487         if (attr & MLX4_UPDATE_QP_QOS_VPORT) {
 488                 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_QOS_VPP)) {
 489                         mlx4_warn(dev, "Granular QoS per VF is not enabled\n");
 490                         err = -EOPNOTSUPP;
 491                         goto out;
 492                 }
 493
 494                 qp_mask |= 1ULL << MLX4_UPD_QP_MASK_QOS_VPP;
 495                 cmd->qp_context.qos_vport = params->qos_vport;
 496         }
 497
 498         cmd->primary_addr_path_mask = cpu_to_be64(pri_addr_path_mask);
 499         cmd->qp_mask = cpu_to_be64(qp_mask);
 500
 501         err = mlx4_cmd(dev, mailbox->dma, qpn & 0xffffff, 0,
 502                        MLX4_CMD_UPDATE_QP, MLX4_CMD_TIME_CLASS_A,
 503                        MLX4_CMD_NATIVE);
 504 out:
 505         mlx4_free_cmd_mailbox(dev, mailbox);
 506         return err;
 507 }
 508 EXPORT_SYMBOL_GPL(mlx4_update_qp);
 509
 510 void mlx4_qp_remove(struct mlx4_dev *dev, struct mlx4_qp *qp)
 511 {
 512         struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table;
 513         unsigned long flags;
 514
 515         spin_lock_irqsave(&qp_table->lock, flags);
 516         radix_tree_delete(&dev->qp_table_tree, qp->qpn & (dev->caps.num_qps - 1));
 517         spin_unlock_irqrestore(&qp_table->lock, flags);
 518 }
 519 EXPORT_SYMBOL_GPL(mlx4_qp_remove);
 520
 521 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp)
 522 {
 523         if (refcount_dec_and_test(&qp->refcount))
 524                 complete(&qp->free);
 525         wait_for_completion(&qp->free);
 526
 527         mlx4_qp_free_icm(dev, qp->qpn);
 528 }
 529 EXPORT_SYMBOL_GPL(mlx4_qp_free);
 530
 531 static int mlx4_CONF_SPECIAL_QP(struct mlx4_dev *dev, u32 base_qpn)
 532 {
 533         return mlx4_cmd(dev, 0, base_qpn, 0, MLX4_CMD_CONF_SPECIAL_QP,
 534                         MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
 535 }
 536
 537 #define MLX4_QP_TABLE_RSS_ETH_PRIORITY 2
 538 #define MLX4_QP_TABLE_RAW_ETH_PRIORITY 1
 539 #define MLX4_QP_TABLE_RAW_ETH_SIZE     256
 540
 541 static int mlx4_create_zones(struct mlx4_dev *dev,
 542                              u32 reserved_bottom_general,
 543                              u32 reserved_top_general,
 544                              u32 reserved_bottom_rss,
 545                              u32 start_offset_rss,
 546                              u32 max_table_offset)
 547 {
 548         struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table;
 549         struct mlx4_bitmap (*bitmap)[MLX4_QP_TABLE_ZONE_NUM] = NULL;
 550         int bitmap_initialized = 0;
 551         u32 last_offset;
 552         int k;
 553         int err;
 554
 555         qp_table->zones = mlx4_zone_allocator_create(MLX4_ZONE_ALLOC_FLAGS_NO_OVERLAP);
 556
 557         if (NULL == qp_table->zones)
 558                 return -ENOMEM;
 559
 560         bitmap = kmalloc(sizeof(*bitmap), GFP_KERNEL);
 561
 562         if (NULL == bitmap) {
 563                 err = -ENOMEM;
 564                 goto free_zone;
 565         }
 566
 567         err = mlx4_bitmap_init(*bitmap + MLX4_QP_TABLE_ZONE_GENERAL, dev->caps.num_qps,
 568                                (1 << 23) - 1, reserved_bottom_general,
 569                                reserved_top_general);
 570
 571         if (err)
 572                 goto free_bitmap;
 573
 574         ++bitmap_initialized;
 575
 576         err = mlx4_zone_add_one(qp_table->zones, *bitmap + MLX4_QP_TABLE_ZONE_GENERAL,
 577                                 MLX4_ZONE_FALLBACK_TO_HIGHER_PRIO |
 578                                 MLX4_ZONE_USE_RR, 0,
 579                                 0, qp_table->zones_uids + MLX4_QP_TABLE_ZONE_GENERAL);
 580
 581         if (err)
 582                 goto free_bitmap;
 583
 584         err = mlx4_bitmap_init(*bitmap + MLX4_QP_TABLE_ZONE_RSS,
 585                                reserved_bottom_rss,
 586                                reserved_bottom_rss - 1,
 587                                dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
 588                                reserved_bottom_rss - start_offset_rss);
 589
 590         if (err)
 591                 goto free_bitmap;
 592
 593         ++bitmap_initialized;
 594
 595         err = mlx4_zone_add_one(qp_table->zones, *bitmap + MLX4_QP_TABLE_ZONE_RSS,
 596                                 MLX4_ZONE_ALLOW_ALLOC_FROM_LOWER_PRIO |
 597                                 MLX4_ZONE_ALLOW_ALLOC_FROM_EQ_PRIO |
 598                                 MLX4_ZONE_USE_RR, MLX4_QP_TABLE_RSS_ETH_PRIORITY,
 599                                 0, qp_table->zones_uids + MLX4_QP_TABLE_ZONE_RSS);
 600
 601         if (err)
 602                 goto free_bitmap;
 603
 604         last_offset = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
 605         /*  We have a single zone for the A0 steering QPs area of the FW. This area
 606          *  needs to be split into subareas. One set of subareas is for RSS QPs
 607          *  (in which qp number bits 6 and/or 7 are set); the other set of subareas
 608          *  is for RAW_ETH QPs, which require that both bits 6 and 7 are zero.
 609          *  Currently, the values returned by the FW (A0 steering area starting qp number
 610          *  and A0 steering area size) are such that there are only two subareas -- one
 611          *  for RSS and one for RAW_ETH.
 612          */
 613         for (k = MLX4_QP_TABLE_ZONE_RSS + 1; k < sizeof(*bitmap)/sizeof((*bitmap)[0]);
 614              k++) {
 615                 int size;
 616                 u32 offset = start_offset_rss;
 617                 u32 bf_mask;
 618                 u32 requested_size;
 619
 620                 /* Assuming MLX4_BF_QP_SKIP_MASK is consecutive ones, this calculates
 621                  * a mask of all LSB bits set until (and not including) the first
 622                  * set bit of  MLX4_BF_QP_SKIP_MASK. For example, if MLX4_BF_QP_SKIP_MASK
 623                  * is 0xc0, bf_mask will be 0x3f.
 624                  */
 625                 bf_mask = (MLX4_BF_QP_SKIP_MASK & ~(MLX4_BF_QP_SKIP_MASK - 1)) - 1;
 626                 requested_size = min((u32)MLX4_QP_TABLE_RAW_ETH_SIZE, bf_mask + 1);
 627
 628                 if (((last_offset & MLX4_BF_QP_SKIP_MASK) &&
 629                      ((int)(max_table_offset - last_offset)) >=
 630                      roundup_pow_of_two(MLX4_BF_QP_SKIP_MASK)) ||
 631                     (!(last_offset & MLX4_BF_QP_SKIP_MASK) &&
 632                      !((last_offset + requested_size - 1) &
 633                        MLX4_BF_QP_SKIP_MASK)))
 634                         size = requested_size;
 635                 else {
 636                         u32 candidate_offset =
 637                                 (last_offset | MLX4_BF_QP_SKIP_MASK | bf_mask) + 1;
 638
 639                         if (last_offset & MLX4_BF_QP_SKIP_MASK)
 640                                 last_offset = candidate_offset;
 641
 642                         /* From this point, the BF bits are 0 */
 643
 644                         if (last_offset > max_table_offset) {
 645                                 /* need to skip */
 646                                 size = -1;
 647                         } else {
 648                                 size = min3(max_table_offset - last_offset,
 649                                             bf_mask - (last_offset & bf_mask),
 650                                             requested_size);
 651                                 if (size < requested_size) {
 652                                         int candidate_size;
 653
 654                                         candidate_size = min3(
 655                                                 max_table_offset - candidate_offset,
 656                                                 bf_mask - (last_offset & bf_mask),
 657                                                 requested_size);
 658
 659                                         /*  We will not take this path if last_offset was
 660                                          *  already set above to candidate_offset
 661                                          */
 662                                         if (candidate_size > size) {
 663                                                 last_offset = candidate_offset;
 664                                                 size = candidate_size;
 665                                         }
 666                                 }
 667                         }
 668                 }
 669
 670                 if (size > 0) {
 671                         /* mlx4_bitmap_alloc_range will find a contiguous range of "size"
 672                          * QPs in which both bits 6 and 7 are zero, because we pass it the
 673                          * MLX4_BF_SKIP_MASK).
 674                          */
 675                         offset = mlx4_bitmap_alloc_range(
 676                                         *bitmap + MLX4_QP_TABLE_ZONE_RSS,
 677                                         size, 1,
 678                                         MLX4_BF_QP_SKIP_MASK);
 679
 680                         if (offset == (u32)-1) {
 681                                 err = -ENOMEM;
 682                                 break;
 683                         }
 684
 685                         last_offset = offset + size;
 686
 687                         err = mlx4_bitmap_init(*bitmap + k, roundup_pow_of_two(size),
 688                                                roundup_pow_of_two(size) - 1, 0,
 689                                                roundup_pow_of_two(size) - size);
 690                 } else {
 691                         /* Add an empty bitmap, we'll allocate from different zones (since
 692                          * at least one is reserved)
 693                          */
 694                         err = mlx4_bitmap_init(*bitmap + k, 1,
 695                                                MLX4_QP_TABLE_RAW_ETH_SIZE - 1, 0,
 696                                                0);
 697                         mlx4_bitmap_alloc_range(*bitmap + k, 1, 1, 0);
 698                 }
 699
 700                 if (err)
 701                         break;
 702
 703                 ++bitmap_initialized;
 704
 705                 err = mlx4_zone_add_one(qp_table->zones, *bitmap + k,
 706                                         MLX4_ZONE_ALLOW_ALLOC_FROM_LOWER_PRIO |
 707                                         MLX4_ZONE_ALLOW_ALLOC_FROM_EQ_PRIO |
 708                                         MLX4_ZONE_USE_RR, MLX4_QP_TABLE_RAW_ETH_PRIORITY,
 709                                         offset, qp_table->zones_uids + k);
 710
 711                 if (err)
 712                         break;
 713         }
 714
 715         if (err)
 716                 goto free_bitmap;
 717
 718         qp_table->bitmap_gen = *bitmap;
 719
 720         return err;
 721
 722 free_bitmap:
 723         for (k = 0; k < bitmap_initialized; k++)
 724                 mlx4_bitmap_cleanup(*bitmap + k);
 725         kfree(bitmap);
 726 free_zone:
 727         mlx4_zone_allocator_destroy(qp_table->zones);
 728         return err;
 729 }
 730
 731 static void mlx4_cleanup_qp_zones(struct mlx4_dev *dev)
 732 {
 733         struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table;
 734
 735         if (qp_table->zones) {
 736                 int i;
 737
 738                 for (i = 0;
 739                      i < sizeof(qp_table->zones_uids)/sizeof(qp_table->zones_uids[0]);
 740                      i++) {
 741                         struct mlx4_bitmap *bitmap =
 742                                 mlx4_zone_get_bitmap(qp_table->zones,
 743                                                      qp_table->zones_uids[i]);
 744
 745                         mlx4_zone_remove_one(qp_table->zones, qp_table->zones_uids[i]);
 746                         if (NULL == bitmap)
 747                                 continue;
 748
 749                         mlx4_bitmap_cleanup(bitmap);
 750                 }
 751                 mlx4_zone_allocator_destroy(qp_table->zones);
 752                 kfree(qp_table->bitmap_gen);
 753                 qp_table->bitmap_gen = NULL;
 754                 qp_table->zones = NULL;
 755         }
 756 }
 757
 758 int mlx4_init_qp_table(struct mlx4_dev *dev)
 759 {
 760         struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table;
 761         int err;
 762         int reserved_from_top = 0;
 763         int reserved_from_bot;
 764         int k;
 765         int fixed_reserved_from_bot_rv = 0;
 766         int bottom_reserved_for_rss_bitmap;
 767         u32 max_table_offset = dev->caps.dmfs_high_rate_qpn_base +
 768                         dev->caps.dmfs_high_rate_qpn_range;
 769
 770         spin_lock_init(&qp_table->lock);
 771         INIT_RADIX_TREE(&dev->qp_table_tree, GFP_ATOMIC);
 772         if (mlx4_is_slave(dev))
 773                 return 0;
 774
 775         /* We reserve 2 extra QPs per port for the special QPs.  The
 776          * block of special QPs must be aligned to a multiple of 8, so
 777          * round up.
 778          *
 779          * We also reserve the MSB of the 24-bit QP number to indicate
 780          * that a QP is an XRC QP.
 781          */
 782         for (k = 0; k <= MLX4_QP_REGION_BOTTOM; k++)
 783                 fixed_reserved_from_bot_rv += dev->caps.reserved_qps_cnt[k];
 784
 785         if (fixed_reserved_from_bot_rv < max_table_offset)
 786                 fixed_reserved_from_bot_rv = max_table_offset;
 787
 788         /* We reserve at least 1 extra for bitmaps that we don't have enough space for*/
 789         bottom_reserved_for_rss_bitmap =
 790                 roundup_pow_of_two(fixed_reserved_from_bot_rv + 1);
 791         dev->phys_caps.base_sqpn = ALIGN(bottom_reserved_for_rss_bitmap, 8);
 792
 793         {
 794                 int sort[MLX4_NUM_QP_REGION];
 795                 int i, j;
 796                 int last_base = dev->caps.num_qps;
 797
 798                 for (i = 1; i < MLX4_NUM_QP_REGION; ++i)
 799                         sort[i] = i;
 800
 801                 for (i = MLX4_NUM_QP_REGION; i > MLX4_QP_REGION_BOTTOM; --i) {
 802                         for (j = MLX4_QP_REGION_BOTTOM + 2; j < i; ++j) {
 803                                 if (dev->caps.reserved_qps_cnt[sort[j]] >
 804                                     dev->caps.reserved_qps_cnt[sort[j - 1]])
 805                                         swap(sort[j], sort[j - 1]);
 806                         }
 807                 }
 808
 809                 for (i = MLX4_QP_REGION_BOTTOM + 1; i < MLX4_NUM_QP_REGION; ++i) {
 810                         last_base -= dev->caps.reserved_qps_cnt[sort[i]];
 811                         dev->caps.reserved_qps_base[sort[i]] = last_base;
 812                         reserved_from_top +=
 813                                 dev->caps.reserved_qps_cnt[sort[i]];
 814                 }
 815         }
 816
 817        /* Reserve 8 real SQPs in both native and SRIOV modes.
 818         * In addition, in SRIOV mode, reserve 8 proxy SQPs per function
 819         * (for all PFs and VFs), and 8 corresponding tunnel QPs.
 820         * Each proxy SQP works opposite its own tunnel QP.
 821         *
 822         * The QPs are arranged as follows:
 823         * a. 8 real SQPs
 824         * b. All the proxy SQPs (8 per function)
 825         * c. All the tunnel QPs (8 per function)
 826         */
 827         reserved_from_bot = mlx4_num_reserved_sqps(dev);
 828         if (reserved_from_bot + reserved_from_top > dev->caps.num_qps) {
 829                 mlx4_err(dev, "Number of reserved QPs is higher than number of QPs\n");
 830                 return -EINVAL;
 831         }
 832
 833         err = mlx4_create_zones(dev, reserved_from_bot, reserved_from_bot,
 834                                 bottom_reserved_for_rss_bitmap,
 835                                 fixed_reserved_from_bot_rv,
 836                                 max_table_offset);
 837
 838         if (err)
 839                 return err;
 840
 841         if (mlx4_is_mfunc(dev)) {
 842                 /* for PPF use */
 843                 dev->phys_caps.base_proxy_sqpn = dev->phys_caps.base_sqpn + 8;
 844                 dev->phys_caps.base_tunnel_sqpn = dev->phys_caps.base_sqpn + 8 + 8 * MLX4_MFUNC_MAX;
 845
 846                 /* In mfunc, calculate proxy and tunnel qp offsets for the PF here,
 847                  * since the PF does not call mlx4_slave_caps */
 848                 dev->caps.spec_qps = kcalloc(dev->caps.num_ports,
 849                                              sizeof(*dev->caps.spec_qps),
 850                                              GFP_KERNEL);
 851                 if (!dev->caps.spec_qps) {
 852                         err = -ENOMEM;
 853                         goto err_mem;
 854                 }
 855
 856                 for (k = 0; k < dev->caps.num_ports; k++) {
 857                         dev->caps.spec_qps[k].qp0_proxy = dev->phys_caps.base_proxy_sqpn +
 858                                 8 * mlx4_master_func_num(dev) + k;
 859                         dev->caps.spec_qps[k].qp0_tunnel = dev->caps.spec_qps[k].qp0_proxy + 8 * MLX4_MFUNC_MAX;
 860                         dev->caps.spec_qps[k].qp1_proxy = dev->phys_caps.base_proxy_sqpn +
 861                                 8 * mlx4_master_func_num(dev) + MLX4_MAX_PORTS + k;
 862                         dev->caps.spec_qps[k].qp1_tunnel = dev->caps.spec_qps[k].qp1_proxy + 8 * MLX4_MFUNC_MAX;
 863                 }
 864         }
 865
 866
 867         err = mlx4_CONF_SPECIAL_QP(dev, dev->phys_caps.base_sqpn);
 868         if (err)
 869                 goto err_mem;
 870
 871         return err;
 872
 873 err_mem:
 874         kfree(dev->caps.spec_qps);
 875         dev->caps.spec_qps = NULL;
 876         mlx4_cleanup_qp_zones(dev);
 877         return err;
 878 }
 879
 880 void mlx4_cleanup_qp_table(struct mlx4_dev *dev)
 881 {
 882         if (mlx4_is_slave(dev))
 883                 return;
 884
 885         mlx4_CONF_SPECIAL_QP(dev, 0);
 886
 887         mlx4_cleanup_qp_zones(dev);
 888 }
 889
 890 int mlx4_qp_query(struct mlx4_dev *dev, struct mlx4_qp *qp,
 891                   struct mlx4_qp_context *context)
 892 {
 893         struct mlx4_cmd_mailbox *mailbox;
 894         int err;
 895
 896         mailbox = mlx4_alloc_cmd_mailbox(dev);
 897         if (IS_ERR(mailbox))
 898                 return PTR_ERR(mailbox);
 899
 900         err = mlx4_cmd_box(dev, 0, mailbox->dma, qp->qpn, 0,
 901                            MLX4_CMD_QUERY_QP, MLX4_CMD_TIME_CLASS_A,
 902                            MLX4_CMD_WRAPPED);
 903         if (!err)
 904                 memcpy(context, mailbox->buf + 8, sizeof(*context));
 905
 906         mlx4_free_cmd_mailbox(dev, mailbox);
 907         return err;
 908 }
 909 EXPORT_SYMBOL_GPL(mlx4_qp_query);
 910
 911 int mlx4_qp_to_ready(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
 912                      struct mlx4_qp_context *context,
 913                      struct mlx4_qp *qp, enum mlx4_qp_state *qp_state)
 914 {
 915         int err;
 916         int i;
 917         enum mlx4_qp_state states[] = {
 918                 MLX4_QP_STATE_RST,
 919                 MLX4_QP_STATE_INIT,
 920                 MLX4_QP_STATE_RTR,
 921                 MLX4_QP_STATE_RTS
 922         };
 923
 924         for (i = 0; i < ARRAY_SIZE(states) - 1; i++) {
 925                 context->flags &= cpu_to_be32(~(0xf << 28));
 926                 context->flags |= cpu_to_be32(states[i + 1] << 28);
 927                 if (states[i + 1] != MLX4_QP_STATE_RTR)
 928                         context->params2 &= ~cpu_to_be32(MLX4_QP_BIT_FPP);
 929                 err = mlx4_qp_modify(dev, mtt, states[i], states[i + 1],
 930                                      context, 0, 0, qp);
 931                 if (err) {
 932                         mlx4_err(dev, "Failed to bring QP to state: %d with error: %d\n",
 933                                  states[i + 1], err);
 934                         return err;
 935                 }
 936
 937                 *qp_state = states[i + 1];
 938         }
 939
 940         return 0;
 941 }
 942 EXPORT_SYMBOL_GPL(mlx4_qp_to_ready);
 943
 944 u16 mlx4_qp_roce_entropy(struct mlx4_dev *dev, u32 qpn)
 945 {
 946         struct mlx4_qp_context context;
 947         struct mlx4_qp qp;
 948         int err;
 949
 950         qp.qpn = qpn;
 951         err = mlx4_qp_query(dev, &qp, &context);
 952         if (!err) {
 953                 u32 dest_qpn = be32_to_cpu(context.remote_qpn) & 0xffffff;
 954                 u16 folded_dst = folded_qp(dest_qpn);
 955                 u16 folded_src = folded_qp(qpn);
 956
 957                 return (dest_qpn != qpn) ?
 958                         ((folded_dst ^ folded_src) | 0xC000) :
 959                         folded_src | 0xC000;
 960         }
 961         return 0xdead;
 962 }