drivers/net/ethernet/mellanox/mlx4/main.c

   1 /*
   2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
   4  * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
   5  * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
   6  *
   7  * This software is available to you under a choice of one of two
   8  * licenses.  You may choose to be licensed under the terms of the GNU
   9  * General Public License (GPL) Version 2, available from the file
  10  * COPYING in the main directory of this source tree, or the
  11  * OpenIB.org BSD license below:
  12  *
  13  *     Redistribution and use in source and binary forms, with or
  14  *     without modification, are permitted provided that the following
  15  *     conditions are met:
  16  *
  17  *      - Redistributions of source code must retain the above
  18  *        copyright notice, this list of conditions and the following
  19  *        disclaimer.
  20  *
  21  *      - Redistributions in binary form must reproduce the above
  22  *        copyright notice, this list of conditions and the following
  23  *        disclaimer in the documentation and/or other materials
  24  *        provided with the distribution.
  25  *
  26  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  27  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  28  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  29  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  30  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  31  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  32  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  33  * SOFTWARE.
  34  */
  35
  36 #include <linux/module.h>
  37 #include <linux/init.h>
  38 #include <linux/errno.h>
  39 #include <linux/pci.h>
  40 #include <linux/dma-mapping.h>
  41 #include <linux/slab.h>
  42 #include <linux/io-mapping.h>
  43 #include <linux/delay.h>
  44 #include <linux/kmod.h>
  45
  46 #include <linux/mlx4/device.h>
  47 #include <linux/mlx4/doorbell.h>
  48
  49 #include "mlx4.h"
  50 #include "fw.h"
  51 #include "icm.h"
  52
  53 MODULE_AUTHOR("Roland Dreier");
  54 MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
  55 MODULE_LICENSE("Dual BSD/GPL");
  56 MODULE_VERSION(DRV_VERSION);
  57
  58 struct workqueue_struct *mlx4_wq;
  59
  60 #ifdef CONFIG_MLX4_DEBUG
  61
  62 int mlx4_debug_level = 0;
  63 module_param_named(debug_level, mlx4_debug_level, int, 0644);
  64 MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
  65
  66 #endif /* CONFIG_MLX4_DEBUG */
  67
  68 #ifdef CONFIG_PCI_MSI
  69
  70 static int msi_x = 1;
  71 module_param(msi_x, int, 0444);
  72 MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
  73
  74 #else /* CONFIG_PCI_MSI */
  75
  76 #define msi_x (0)
  77
  78 #endif /* CONFIG_PCI_MSI */
  79
  80 static uint8_t num_vfs[3] = {0, 0, 0};
  81 static int num_vfs_argc;
  82 module_param_array(num_vfs, byte , &num_vfs_argc, 0444);
  83 MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0\n"
  84                           "num_vfs=port1,port2,port1+2");
  85
  86 static uint8_t probe_vf[3] = {0, 0, 0};
  87 static int probe_vfs_argc;
  88 module_param_array(probe_vf, byte, &probe_vfs_argc, 0444);
  89 MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)\n"
  90                            "probe_vf=port1,port2,port1+2");
  91
  92 int mlx4_log_num_mgm_entry_size = MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
  93 module_param_named(log_num_mgm_entry_size,
  94                         mlx4_log_num_mgm_entry_size, int, 0444);
  95 MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num"
  96                                          " of qp per mcg, for example:"
  97                                          " 10 gives 248.range: 7 <="
  98                                          " log_num_mgm_entry_size <= 12."
  99                                          " To activate device managed"
 100                                          " flow steering when available, set to -1");
 101
 102 static bool enable_64b_cqe_eqe = true;
 103 module_param(enable_64b_cqe_eqe, bool, 0444);
 104 MODULE_PARM_DESC(enable_64b_cqe_eqe,
 105                  "Enable 64 byte CQEs/EQEs when the FW supports this (default: True)");
 106
 107 #define PF_CONTEXT_BEHAVIOUR_MASK       (MLX4_FUNC_CAP_64B_EQE_CQE | \
 108                                          MLX4_FUNC_CAP_EQE_CQE_STRIDE | \
 109                                          MLX4_FUNC_CAP_DMFS_A0_STATIC)
 110
 111 #define RESET_PERSIST_MASK_FLAGS        (MLX4_FLAG_SRIOV)
 112
 113 static char mlx4_version[] =
 114         DRV_NAME ": Mellanox ConnectX core driver v"
 115         DRV_VERSION " (" DRV_RELDATE ")\n";
 116
 117 static struct mlx4_profile default_profile = {
 118         .num_qp         = 1 << 18,
 119         .num_srq        = 1 << 16,
 120         .rdmarc_per_qp  = 1 << 4,
 121         .num_cq         = 1 << 16,
 122         .num_mcg        = 1 << 13,
 123         .num_mpt        = 1 << 19,
 124         .num_mtt        = 1 << 20, /* It is really num mtt segements */
 125 };
 126
 127 static struct mlx4_profile low_mem_profile = {
 128         .num_qp         = 1 << 17,
 129         .num_srq        = 1 << 6,
 130         .rdmarc_per_qp  = 1 << 4,
 131         .num_cq         = 1 << 8,
 132         .num_mcg        = 1 << 8,
 133         .num_mpt        = 1 << 9,
 134         .num_mtt        = 1 << 7,
 135 };
 136
 137 static int log_num_mac = 7;
 138 module_param_named(log_num_mac, log_num_mac, int, 0444);
 139 MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
 140
 141 static int log_num_vlan;
 142 module_param_named(log_num_vlan, log_num_vlan, int, 0444);
 143 MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
 144 /* Log2 max number of VLANs per ETH port (0-7) */
 145 #define MLX4_LOG_NUM_VLANS 7
 146 #define MLX4_MIN_LOG_NUM_VLANS 0
 147 #define MLX4_MIN_LOG_NUM_MAC 1
 148
 149 static bool use_prio;
 150 module_param_named(use_prio, use_prio, bool, 0444);
 151 MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports (deprecated)");
 152
 153 int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG);
 154 module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
 155 MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)");
 156
 157 static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE};
 158 static int arr_argc = 2;
 159 module_param_array(port_type_array, int, &arr_argc, 0444);
 160 MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default "
 161                                 "1 for IB, 2 for Ethernet");
 162
 163 struct mlx4_port_config {
 164         struct list_head list;
 165         enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
 166         struct pci_dev *pdev;
 167 };
 168
 169 static atomic_t pf_loading = ATOMIC_INIT(0);
 170
 171 int mlx4_check_port_params(struct mlx4_dev *dev,
 172                            enum mlx4_port_type *port_type)
 173 {
 174         int i;
 175
 176         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
 177                 for (i = 0; i < dev->caps.num_ports - 1; i++) {
 178                         if (port_type[i] != port_type[i + 1]) {
 179                                 mlx4_err(dev, "Only same port types supported on this HCA, aborting\n");
 180                                 return -EINVAL;
 181                         }
 182                 }
 183         }
 184
 185         for (i = 0; i < dev->caps.num_ports; i++) {
 186                 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
 187                         mlx4_err(dev, "Requested port type for port %d is not supported on this HCA\n",
 188                                  i + 1);
 189                         return -EINVAL;
 190                 }
 191         }
 192         return 0;
 193 }
 194
 195 static void mlx4_set_port_mask(struct mlx4_dev *dev)
 196 {
 197         int i;
 198
 199         for (i = 1; i <= dev->caps.num_ports; ++i)
 200                 dev->caps.port_mask[i] = dev->caps.port_type[i];
 201 }
 202
 203 enum {
 204         MLX4_QUERY_FUNC_NUM_SYS_EQS = 1 << 0,
 205 };
 206
 207 static int mlx4_query_func(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
 208 {
 209         int err = 0;
 210         struct mlx4_func func;
 211
 212         if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) {
 213                 err = mlx4_QUERY_FUNC(dev, &func, 0);
 214                 if (err) {
 215                         mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
 216                         return err;
 217                 }
 218                 dev_cap->max_eqs = func.max_eq;
 219                 dev_cap->reserved_eqs = func.rsvd_eqs;
 220                 dev_cap->reserved_uars = func.rsvd_uars;
 221                 err |= MLX4_QUERY_FUNC_NUM_SYS_EQS;
 222         }
 223         return err;
 224 }
 225
 226 static void mlx4_enable_cqe_eqe_stride(struct mlx4_dev *dev)
 227 {
 228         struct mlx4_caps *dev_cap = &dev->caps;
 229
 230         /* FW not supporting or cancelled by user */
 231         if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) ||
 232             !(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE))
 233                 return;
 234
 235         /* Must have 64B CQE_EQE enabled by FW to use bigger stride
 236          * When FW has NCSI it may decide not to report 64B CQE/EQEs
 237          */
 238         if (!(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_EQE) ||
 239             !(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_CQE)) {
 240                 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
 241                 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
 242                 return;
 243         }
 244
 245         if (cache_line_size() == 128 || cache_line_size() == 256) {
 246                 mlx4_dbg(dev, "Enabling CQE stride cacheLine supported\n");
 247                 /* Changing the real data inside CQE size to 32B */
 248                 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
 249                 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
 250
 251                 if (mlx4_is_master(dev))
 252                         dev_cap->function_caps |= MLX4_FUNC_CAP_EQE_CQE_STRIDE;
 253         } else {
 254                 if (cache_line_size() != 32  && cache_line_size() != 64)
 255                         mlx4_dbg(dev, "Disabling CQE stride, cacheLine size unsupported\n");
 256                 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
 257                 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
 258         }
 259 }
 260
 261 static int _mlx4_dev_port(struct mlx4_dev *dev, int port,
 262                           struct mlx4_port_cap *port_cap)
 263 {
 264         dev->caps.vl_cap[port]      = port_cap->max_vl;
 265         dev->caps.ib_mtu_cap[port]          = port_cap->ib_mtu;
 266         dev->phys_caps.gid_phys_table_len[port]  = port_cap->max_gids;
 267         dev->phys_caps.pkey_phys_table_len[port] = port_cap->max_pkeys;
 268         /* set gid and pkey table operating lengths by default
 269          * to non-sriov values
 270          */
 271         dev->caps.gid_table_len[port]  = port_cap->max_gids;
 272         dev->caps.pkey_table_len[port] = port_cap->max_pkeys;
 273         dev->caps.port_width_cap[port] = port_cap->max_port_width;
 274         dev->caps.eth_mtu_cap[port]    = port_cap->eth_mtu;
 275         dev->caps.def_mac[port]        = port_cap->def_mac;
 276         dev->caps.supported_type[port] = port_cap->supported_port_types;
 277         dev->caps.suggested_type[port] = port_cap->suggested_type;
 278         dev->caps.default_sense[port] = port_cap->default_sense;
 279         dev->caps.trans_type[port]          = port_cap->trans_type;
 280         dev->caps.vendor_oui[port]     = port_cap->vendor_oui;
 281         dev->caps.wavelength[port]     = port_cap->wavelength;
 282         dev->caps.trans_code[port]     = port_cap->trans_code;
 283
 284         return 0;
 285 }
 286
 287 static int mlx4_dev_port(struct mlx4_dev *dev, int port,
 288                          struct mlx4_port_cap *port_cap)
 289 {
 290         int err = 0;
 291
 292         err = mlx4_QUERY_PORT(dev, port, port_cap);
 293
 294         if (err)
 295                 mlx4_err(dev, "QUERY_PORT command failed.\n");
 296
 297         return err;
 298 }
 299
 300 static inline void mlx4_enable_ignore_fcs(struct mlx4_dev *dev)
 301 {
 302         if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_IGNORE_FCS))
 303                 return;
 304
 305         if (mlx4_is_mfunc(dev)) {
 306                 mlx4_dbg(dev, "SRIOV mode - Disabling Ignore FCS");
 307                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_IGNORE_FCS;
 308                 return;
 309         }
 310
 311         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP)) {
 312                 mlx4_dbg(dev,
 313                          "Keep FCS is not supported - Disabling Ignore FCS");
 314                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_IGNORE_FCS;
 315                 return;
 316         }
 317 }
 318
 319 #define MLX4_A0_STEERING_TABLE_SIZE     256
 320 static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
 321 {
 322         int err;
 323         int i;
 324
 325         err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
 326         if (err) {
 327                 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
 328                 return err;
 329         }
 330         mlx4_dev_cap_dump(dev, dev_cap);
 331
 332         if (dev_cap->min_page_sz > PAGE_SIZE) {
 333                 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n",
 334                          dev_cap->min_page_sz, PAGE_SIZE);
 335                 return -ENODEV;
 336         }
 337         if (dev_cap->num_ports > MLX4_MAX_PORTS) {
 338                 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n",
 339                          dev_cap->num_ports, MLX4_MAX_PORTS);
 340                 return -ENODEV;
 341         }
 342
 343         if (dev_cap->uar_size > pci_resource_len(dev->persist->pdev, 2)) {
 344                 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n",
 345                          dev_cap->uar_size,
 346                          (unsigned long long)
 347                          pci_resource_len(dev->persist->pdev, 2));
 348                 return -ENODEV;
 349         }
 350
 351         dev->caps.num_ports          = dev_cap->num_ports;
 352         dev->caps.num_sys_eqs = dev_cap->num_sys_eqs;
 353         dev->phys_caps.num_phys_eqs = dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS ?
 354                                       dev->caps.num_sys_eqs :
 355                                       MLX4_MAX_EQ_NUM;
 356         for (i = 1; i <= dev->caps.num_ports; ++i) {
 357                 err = _mlx4_dev_port(dev, i, dev_cap->port_cap + i);
 358                 if (err) {
 359                         mlx4_err(dev, "QUERY_PORT command failed, aborting\n");
 360                         return err;
 361                 }
 362         }
 363
 364         dev->caps.uar_page_size      = PAGE_SIZE;
 365         dev->caps.num_uars           = dev_cap->uar_size / PAGE_SIZE;
 366         dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
 367         dev->caps.bf_reg_size        = dev_cap->bf_reg_size;
 368         dev->caps.bf_regs_per_page   = dev_cap->bf_regs_per_page;
 369         dev->caps.max_sq_sg          = dev_cap->max_sq_sg;
 370         dev->caps.max_rq_sg          = dev_cap->max_rq_sg;
 371         dev->caps.max_wqes           = dev_cap->max_qp_sz;
 372         dev->caps.max_qp_init_rdma   = dev_cap->max_requester_per_qp;
 373         dev->caps.max_srq_wqes       = dev_cap->max_srq_sz;
 374         dev->caps.max_srq_sge        = dev_cap->max_rq_sg - 1;
 375         dev->caps.reserved_srqs      = dev_cap->reserved_srqs;
 376         dev->caps.max_sq_desc_sz     = dev_cap->max_sq_desc_sz;
 377         dev->caps.max_rq_desc_sz     = dev_cap->max_rq_desc_sz;
 378         /*
 379          * Subtract 1 from the limit because we need to allocate a
 380          * spare CQE so the HCA HW can tell the difference between an
 381          * empty CQ and a full CQ.
 382          */
 383         dev->caps.max_cqes           = dev_cap->max_cq_sz - 1;
 384         dev->caps.reserved_cqs       = dev_cap->reserved_cqs;
 385         dev->caps.reserved_eqs       = dev_cap->reserved_eqs;
 386         dev->caps.reserved_mtts      = dev_cap->reserved_mtts;
 387         dev->caps.reserved_mrws      = dev_cap->reserved_mrws;
 388
 389         /* The first 128 UARs are used for EQ doorbells */
 390         dev->caps.reserved_uars      = max_t(int, 128, dev_cap->reserved_uars);
 391         dev->caps.reserved_pds       = dev_cap->reserved_pds;
 392         dev->caps.reserved_xrcds     = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
 393                                         dev_cap->reserved_xrcds : 0;
 394         dev->caps.max_xrcds          = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
 395                                         dev_cap->max_xrcds : 0;
 396         dev->caps.mtt_entry_sz       = dev_cap->mtt_entry_sz;
 397
 398         dev->caps.max_msg_sz         = dev_cap->max_msg_sz;
 399         dev->caps.page_size_cap      = ~(u32) (dev_cap->min_page_sz - 1);
 400         dev->caps.flags              = dev_cap->flags;
 401         dev->caps.flags2             = dev_cap->flags2;
 402         dev->caps.bmme_flags         = dev_cap->bmme_flags;
 403         dev->caps.reserved_lkey      = dev_cap->reserved_lkey;
 404         dev->caps.stat_rate_support  = dev_cap->stat_rate_support;
 405         dev->caps.max_gso_sz         = dev_cap->max_gso_sz;
 406         dev->caps.max_rss_tbl_sz     = dev_cap->max_rss_tbl_sz;
 407
 408         /* Sense port always allowed on supported devices for ConnectX-1 and -2 */
 409         if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT)
 410                 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
 411         /* Don't do sense port on multifunction devices (for now at least) */
 412         if (mlx4_is_mfunc(dev))
 413                 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
 414
 415         if (mlx4_low_memory_profile()) {
 416                 dev->caps.log_num_macs  = MLX4_MIN_LOG_NUM_MAC;
 417                 dev->caps.log_num_vlans = MLX4_MIN_LOG_NUM_VLANS;
 418         } else {
 419                 dev->caps.log_num_macs  = log_num_mac;
 420                 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS;
 421         }
 422
 423         for (i = 1; i <= dev->caps.num_ports; ++i) {
 424                 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE;
 425                 if (dev->caps.supported_type[i]) {
 426                         /* if only ETH is supported - assign ETH */
 427                         if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH)
 428                                 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
 429                         /* if only IB is supported, assign IB */
 430                         else if (dev->caps.supported_type[i] ==
 431                                  MLX4_PORT_TYPE_IB)
 432                                 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB;
 433                         else {
 434                                 /* if IB and ETH are supported, we set the port
 435                                  * type according to user selection of port type;
 436                                  * if user selected none, take the FW hint */
 437                                 if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE)
 438                                         dev->caps.port_type[i] = dev->caps.suggested_type[i] ?
 439                                                 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB;
 440                                 else
 441                                         dev->caps.port_type[i] = port_type_array[i - 1];
 442                         }
 443                 }
 444                 /*
 445                  * Link sensing is allowed on the port if 3 conditions are true:
 446                  * 1. Both protocols are supported on the port.
 447                  * 2. Different types are supported on the port
 448                  * 3. FW declared that it supports link sensing
 449                  */
 450                 mlx4_priv(dev)->sense.sense_allowed[i] =
 451                         ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) &&
 452                          (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
 453                          (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT));
 454
 455                 /*
 456                  * If "default_sense" bit is set, we move the port to "AUTO" mode
 457                  * and perform sense_port FW command to try and set the correct
 458                  * port type from beginning
 459                  */
 460                 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) {
 461                         enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE;
 462                         dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO;
 463                         mlx4_SENSE_PORT(dev, i, &sensed_port);
 464                         if (sensed_port != MLX4_PORT_TYPE_NONE)
 465                                 dev->caps.port_type[i] = sensed_port;
 466                 } else {
 467                         dev->caps.possible_type[i] = dev->caps.port_type[i];
 468                 }
 469
 470                 if (dev->caps.log_num_macs > dev_cap->port_cap[i].log_max_macs) {
 471                         dev->caps.log_num_macs = dev_cap->port_cap[i].log_max_macs;
 472                         mlx4_warn(dev, "Requested number of MACs is too much for port %d, reducing to %d\n",
 473                                   i, 1 << dev->caps.log_num_macs);
 474                 }
 475                 if (dev->caps.log_num_vlans > dev_cap->port_cap[i].log_max_vlans) {
 476                         dev->caps.log_num_vlans = dev_cap->port_cap[i].log_max_vlans;
 477                         mlx4_warn(dev, "Requested number of VLANs is too much for port %d, reducing to %d\n",
 478                                   i, 1 << dev->caps.log_num_vlans);
 479                 }
 480         }
 481
 482         if (mlx4_is_master(dev) && (dev->caps.num_ports == 2) &&
 483             (port_type_array[0] == MLX4_PORT_TYPE_IB) &&
 484             (port_type_array[1] == MLX4_PORT_TYPE_ETH)) {
 485                 mlx4_warn(dev,
 486                           "Granular QoS per VF not supported with IB/Eth configuration\n");
 487                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_QOS_VPP;
 488         }
 489
 490         dev->caps.max_counters = dev_cap->max_counters;
 491
 492         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
 493         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
 494                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
 495                 (1 << dev->caps.log_num_macs) *
 496                 (1 << dev->caps.log_num_vlans) *
 497                 dev->caps.num_ports;
 498         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
 499
 500         if (dev_cap->dmfs_high_rate_qpn_base > 0 &&
 501             dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN)
 502                 dev->caps.dmfs_high_rate_qpn_base = dev_cap->dmfs_high_rate_qpn_base;
 503         else
 504                 dev->caps.dmfs_high_rate_qpn_base =
 505                         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
 506
 507         if (dev_cap->dmfs_high_rate_qpn_range > 0 &&
 508             dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN) {
 509                 dev->caps.dmfs_high_rate_qpn_range = dev_cap->dmfs_high_rate_qpn_range;
 510                 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DEFAULT;
 511                 dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_FS_A0;
 512         } else {
 513                 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_NOT_SUPPORTED;
 514                 dev->caps.dmfs_high_rate_qpn_base =
 515                         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
 516                 dev->caps.dmfs_high_rate_qpn_range = MLX4_A0_STEERING_TABLE_SIZE;
 517         }
 518
 519         dev->caps.rl_caps = dev_cap->rl_caps;
 520
 521         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_RSS_RAW_ETH] =
 522                 dev->caps.dmfs_high_rate_qpn_range;
 523
 524         dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
 525                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
 526                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
 527                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
 528
 529         dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0;
 530
 531         if (!enable_64b_cqe_eqe && !mlx4_is_slave(dev)) {
 532                 if (dev_cap->flags &
 533                     (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) {
 534                         mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n");
 535                         dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
 536                         dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
 537                 }
 538
 539                 if (dev_cap->flags2 &
 540                     (MLX4_DEV_CAP_FLAG2_CQE_STRIDE |
 541                      MLX4_DEV_CAP_FLAG2_EQE_STRIDE)) {
 542                         mlx4_warn(dev, "Disabling EQE/CQE stride per user request\n");
 543                         dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
 544                         dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
 545                 }
 546         }
 547
 548         if ((dev->caps.flags &
 549             (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) &&
 550             mlx4_is_master(dev))
 551                 dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE;
 552
 553         if (!mlx4_is_slave(dev)) {
 554                 mlx4_enable_cqe_eqe_stride(dev);
 555                 dev->caps.alloc_res_qp_mask =
 556                         (dev->caps.bf_reg_size ? MLX4_RESERVE_ETH_BF_QP : 0) |
 557                         MLX4_RESERVE_A0_QP;
 558
 559                 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETS_CFG) &&
 560                     dev->caps.flags & MLX4_DEV_CAP_FLAG_SET_ETH_SCHED) {
 561                         mlx4_warn(dev, "Old device ETS support detected\n");
 562                         mlx4_warn(dev, "Consider upgrading device FW.\n");
 563                         dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_ETS_CFG;
 564                 }
 565
 566         } else {
 567                 dev->caps.alloc_res_qp_mask = 0;
 568         }
 569
 570         mlx4_enable_ignore_fcs(dev);
 571
 572         return 0;
 573 }
 574
 575 static int mlx4_get_pcie_dev_link_caps(struct mlx4_dev *dev,
 576                                        enum pci_bus_speed *speed,
 577                                        enum pcie_link_width *width)
 578 {
 579         u32 lnkcap1, lnkcap2;
 580         int err1, err2;
 581
 582 #define  PCIE_MLW_CAP_SHIFT 4   /* start of MLW mask in link capabilities */
 583
 584         *speed = PCI_SPEED_UNKNOWN;
 585         *width = PCIE_LNK_WIDTH_UNKNOWN;
 586
 587         err1 = pcie_capability_read_dword(dev->persist->pdev, PCI_EXP_LNKCAP,
 588                                           &lnkcap1);
 589         err2 = pcie_capability_read_dword(dev->persist->pdev, PCI_EXP_LNKCAP2,
 590                                           &lnkcap2);
 591         if (!err2 && lnkcap2) { /* PCIe r3.0-compliant */
 592                 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
 593                         *speed = PCIE_SPEED_8_0GT;
 594                 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
 595                         *speed = PCIE_SPEED_5_0GT;
 596                 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
 597                         *speed = PCIE_SPEED_2_5GT;
 598         }
 599         if (!err1) {
 600                 *width = (lnkcap1 & PCI_EXP_LNKCAP_MLW) >> PCIE_MLW_CAP_SHIFT;
 601                 if (!lnkcap2) { /* pre-r3.0 */
 602                         if (lnkcap1 & PCI_EXP_LNKCAP_SLS_5_0GB)
 603                                 *speed = PCIE_SPEED_5_0GT;
 604                         else if (lnkcap1 & PCI_EXP_LNKCAP_SLS_2_5GB)
 605                                 *speed = PCIE_SPEED_2_5GT;
 606                 }
 607         }
 608
 609         if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN) {
 610                 return err1 ? err1 :
 611                         err2 ? err2 : -EINVAL;
 612         }
 613         return 0;
 614 }
 615
 616 static void mlx4_check_pcie_caps(struct mlx4_dev *dev)
 617 {
 618         enum pcie_link_width width, width_cap;
 619         enum pci_bus_speed speed, speed_cap;
 620         int err;
 621
 622 #define PCIE_SPEED_STR(speed) \
 623         (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \
 624          speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \
 625          speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \
 626          "Unknown")
 627
 628         err = mlx4_get_pcie_dev_link_caps(dev, &speed_cap, &width_cap);
 629         if (err) {
 630                 mlx4_warn(dev,
 631                           "Unable to determine PCIe device BW capabilities\n");
 632                 return;
 633         }
 634
 635         err = pcie_get_minimum_link(dev->persist->pdev, &speed, &width);
 636         if (err || speed == PCI_SPEED_UNKNOWN ||
 637             width == PCIE_LNK_WIDTH_UNKNOWN) {
 638                 mlx4_warn(dev,
 639                           "Unable to determine PCI device chain minimum BW\n");
 640                 return;
 641         }
 642
 643         if (width != width_cap || speed != speed_cap)
 644                 mlx4_warn(dev,
 645                           "PCIe BW is different than device's capability\n");
 646
 647         mlx4_info(dev, "PCIe link speed is %s, device supports %s\n",
 648                   PCIE_SPEED_STR(speed), PCIE_SPEED_STR(speed_cap));
 649         mlx4_info(dev, "PCIe link width is x%d, device supports x%d\n",
 650                   width, width_cap);
 651         return;
 652 }
 653
 654 /*The function checks if there are live vf, return the num of them*/
 655 static int mlx4_how_many_lives_vf(struct mlx4_dev *dev)
 656 {
 657         struct mlx4_priv *priv = mlx4_priv(dev);
 658         struct mlx4_slave_state *s_state;
 659         int i;
 660         int ret = 0;
 661
 662         for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) {
 663                 s_state = &priv->mfunc.master.slave_state[i];
 664                 if (s_state->active && s_state->last_cmd !=
 665                     MLX4_COMM_CMD_RESET) {
 666                         mlx4_warn(dev, "%s: slave: %d is still active\n",
 667                                   __func__, i);
 668                         ret++;
 669                 }
 670         }
 671         return ret;
 672 }
 673
 674 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey)
 675 {
 676         u32 qk = MLX4_RESERVED_QKEY_BASE;
 677
 678         if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX ||
 679             qpn < dev->phys_caps.base_proxy_sqpn)
 680                 return -EINVAL;
 681
 682         if (qpn >= dev->phys_caps.base_tunnel_sqpn)
 683                 /* tunnel qp */
 684                 qk += qpn - dev->phys_caps.base_tunnel_sqpn;
 685         else
 686                 qk += qpn - dev->phys_caps.base_proxy_sqpn;
 687         *qkey = qk;
 688         return 0;
 689 }
 690 EXPORT_SYMBOL(mlx4_get_parav_qkey);
 691
 692 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val)
 693 {
 694         struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
 695
 696         if (!mlx4_is_master(dev))
 697                 return;
 698
 699         priv->virt2phys_pkey[slave][port - 1][i] = val;
 700 }
 701 EXPORT_SYMBOL(mlx4_sync_pkey_table);
 702
 703 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid)
 704 {
 705         struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
 706
 707         if (!mlx4_is_master(dev))
 708                 return;
 709
 710         priv->slave_node_guids[slave] = guid;
 711 }
 712 EXPORT_SYMBOL(mlx4_put_slave_node_guid);
 713
 714 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave)
 715 {
 716         struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
 717
 718         if (!mlx4_is_master(dev))
 719                 return 0;
 720
 721         return priv->slave_node_guids[slave];
 722 }
 723 EXPORT_SYMBOL(mlx4_get_slave_node_guid);
 724
 725 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave)
 726 {
 727         struct mlx4_priv *priv = mlx4_priv(dev);
 728         struct mlx4_slave_state *s_slave;
 729
 730         if (!mlx4_is_master(dev))
 731                 return 0;
 732
 733         s_slave = &priv->mfunc.master.slave_state[slave];
 734         return !!s_slave->active;
 735 }
 736 EXPORT_SYMBOL(mlx4_is_slave_active);
 737
 738 static void slave_adjust_steering_mode(struct mlx4_dev *dev,
 739                                        struct mlx4_dev_cap *dev_cap,
 740                                        struct mlx4_init_hca_param *hca_param)
 741 {
 742         dev->caps.steering_mode = hca_param->steering_mode;
 743         if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
 744                 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
 745                 dev->caps.fs_log_max_ucast_qp_range_size =
 746                         dev_cap->fs_log_max_ucast_qp_range_size;
 747         } else
 748                 dev->caps.num_qp_per_mgm =
 749                         4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2);
 750
 751         mlx4_dbg(dev, "Steering mode is: %s\n",
 752                  mlx4_steering_mode_str(dev->caps.steering_mode));
 753 }
 754
 755 static int mlx4_slave_cap(struct mlx4_dev *dev)
 756 {
 757         int                        err;
 758         u32                        page_size;
 759         struct mlx4_dev_cap        dev_cap;
 760         struct mlx4_func_cap       func_cap;
 761         struct mlx4_init_hca_param hca_param;
 762         u8                         i;
 763
 764         memset(&hca_param, 0, sizeof(hca_param));
 765         err = mlx4_QUERY_HCA(dev, &hca_param);
 766         if (err) {
 767                 mlx4_err(dev, "QUERY_HCA command failed, aborting\n");
 768                 return err;
 769         }
 770
 771         /* fail if the hca has an unknown global capability
 772          * at this time global_caps should be always zeroed
 773          */
 774         if (hca_param.global_caps) {
 775                 mlx4_err(dev, "Unknown hca global capabilities\n");
 776                 return -ENOSYS;
 777         }
 778
 779         mlx4_log_num_mgm_entry_size = hca_param.log_mc_entry_sz;
 780
 781         dev->caps.hca_core_clock = hca_param.hca_core_clock;
 782
 783         memset(&dev_cap, 0, sizeof(dev_cap));
 784         dev->caps.max_qp_dest_rdma = 1 << hca_param.log_rd_per_qp;
 785         err = mlx4_dev_cap(dev, &dev_cap);
 786         if (err) {
 787                 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
 788                 return err;
 789         }
 790
 791         err = mlx4_QUERY_FW(dev);
 792         if (err)
 793                 mlx4_err(dev, "QUERY_FW command failed: could not get FW version\n");
 794
 795         page_size = ~dev->caps.page_size_cap + 1;
 796         mlx4_warn(dev, "HCA minimum page size:%d\n", page_size);
 797         if (page_size > PAGE_SIZE) {
 798                 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n",
 799                          page_size, PAGE_SIZE);
 800                 return -ENODEV;
 801         }
 802
 803         /* slave gets uar page size from QUERY_HCA fw command */
 804         dev->caps.uar_page_size = 1 << (hca_param.uar_page_sz + 12);
 805
 806         /* TODO: relax this assumption */
 807         if (dev->caps.uar_page_size != PAGE_SIZE) {
 808                 mlx4_err(dev, "UAR size:%d != kernel PAGE_SIZE of %ld\n",
 809                          dev->caps.uar_page_size, PAGE_SIZE);
 810                 return -ENODEV;
 811         }
 812
 813         memset(&func_cap, 0, sizeof(func_cap));
 814         err = mlx4_QUERY_FUNC_CAP(dev, 0, &func_cap);
 815         if (err) {
 816                 mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d)\n",
 817                          err);
 818                 return err;
 819         }
 820
 821         if ((func_cap.pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) !=
 822             PF_CONTEXT_BEHAVIOUR_MASK) {
 823                 mlx4_err(dev, "Unknown pf context behaviour %x known flags %x\n",
 824                          func_cap.pf_context_behaviour, PF_CONTEXT_BEHAVIOUR_MASK);
 825                 return -ENOSYS;
 826         }
 827
 828         dev->caps.num_ports             = func_cap.num_ports;
 829         dev->quotas.qp                  = func_cap.qp_quota;
 830         dev->quotas.srq                 = func_cap.srq_quota;
 831         dev->quotas.cq                  = func_cap.cq_quota;
 832         dev->quotas.mpt                 = func_cap.mpt_quota;
 833         dev->quotas.mtt                 = func_cap.mtt_quota;
 834         dev->caps.num_qps               = 1 << hca_param.log_num_qps;
 835         dev->caps.num_srqs              = 1 << hca_param.log_num_srqs;
 836         dev->caps.num_cqs               = 1 << hca_param.log_num_cqs;
 837         dev->caps.num_mpts              = 1 << hca_param.log_mpt_sz;
 838         dev->caps.num_eqs               = func_cap.max_eq;
 839         dev->caps.reserved_eqs          = func_cap.reserved_eq;
 840         dev->caps.reserved_lkey         = func_cap.reserved_lkey;
 841         dev->caps.num_pds               = MLX4_NUM_PDS;
 842         dev->caps.num_mgms              = 0;
 843         dev->caps.num_amgms             = 0;
 844
 845         if (dev->caps.num_ports > MLX4_MAX_PORTS) {
 846                 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n",
 847                          dev->caps.num_ports, MLX4_MAX_PORTS);
 848                 return -ENODEV;
 849         }
 850
 851         dev->caps.qp0_qkey = kcalloc(dev->caps.num_ports, sizeof(u32), GFP_KERNEL);
 852         dev->caps.qp0_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
 853         dev->caps.qp0_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
 854         dev->caps.qp1_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
 855         dev->caps.qp1_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
 856
 857         if (!dev->caps.qp0_tunnel || !dev->caps.qp0_proxy ||
 858             !dev->caps.qp1_tunnel || !dev->caps.qp1_proxy ||
 859             !dev->caps.qp0_qkey) {
 860                 err = -ENOMEM;
 861                 goto err_mem;
 862         }
 863
 864         for (i = 1; i <= dev->caps.num_ports; ++i) {
 865                 err = mlx4_QUERY_FUNC_CAP(dev, i, &func_cap);
 866                 if (err) {
 867                         mlx4_err(dev, "QUERY_FUNC_CAP port command failed for port %d, aborting (%d)\n",
 868                                  i, err);
 869                         goto err_mem;
 870                 }
 871                 dev->caps.qp0_qkey[i - 1] = func_cap.qp0_qkey;
 872                 dev->caps.qp0_tunnel[i - 1] = func_cap.qp0_tunnel_qpn;
 873                 dev->caps.qp0_proxy[i - 1] = func_cap.qp0_proxy_qpn;
 874                 dev->caps.qp1_tunnel[i - 1] = func_cap.qp1_tunnel_qpn;
 875                 dev->caps.qp1_proxy[i - 1] = func_cap.qp1_proxy_qpn;
 876                 dev->caps.port_mask[i] = dev->caps.port_type[i];
 877                 dev->caps.phys_port_id[i] = func_cap.phys_port_id;
 878                 if (mlx4_get_slave_pkey_gid_tbl_len(dev, i,
 879                                                     &dev->caps.gid_table_len[i],
 880                                                     &dev->caps.pkey_table_len[i]))
 881                         goto err_mem;
 882         }
 883
 884         if (dev->caps.uar_page_size * (dev->caps.num_uars -
 885                                        dev->caps.reserved_uars) >
 886                                        pci_resource_len(dev->persist->pdev,
 887                                                         2)) {
 888                 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n",
 889                          dev->caps.uar_page_size * dev->caps.num_uars,
 890                          (unsigned long long)
 891                          pci_resource_len(dev->persist->pdev, 2));
 892                 goto err_mem;
 893         }
 894
 895         if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) {
 896                 dev->caps.eqe_size   = 64;
 897                 dev->caps.eqe_factor = 1;
 898         } else {
 899                 dev->caps.eqe_size   = 32;
 900                 dev->caps.eqe_factor = 0;
 901         }
 902
 903         if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) {
 904                 dev->caps.cqe_size   = 64;
 905                 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
 906         } else {
 907                 dev->caps.cqe_size   = 32;
 908         }
 909
 910         if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_EQE_STRIDE_ENABLED) {
 911                 dev->caps.eqe_size = hca_param.eqe_size;
 912                 dev->caps.eqe_factor = 0;
 913         }
 914
 915         if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_CQE_STRIDE_ENABLED) {
 916                 dev->caps.cqe_size = hca_param.cqe_size;
 917                 /* User still need to know when CQE > 32B */
 918                 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
 919         }
 920
 921         dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
 922         mlx4_warn(dev, "Timestamping is not supported in slave mode\n");
 923
 924         slave_adjust_steering_mode(dev, &dev_cap, &hca_param);
 925         mlx4_dbg(dev, "RSS support for IP fragments is %s\n",
 926                  hca_param.rss_ip_frags ? "on" : "off");
 927
 928         if (func_cap.extra_flags & MLX4_QUERY_FUNC_FLAGS_BF_RES_QP &&
 929             dev->caps.bf_reg_size)
 930                 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_ETH_BF_QP;
 931
 932         if (func_cap.extra_flags & MLX4_QUERY_FUNC_FLAGS_A0_RES_QP)
 933                 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_A0_QP;
 934
 935         return 0;
 936
 937 err_mem:
 938         kfree(dev->caps.qp0_qkey);
 939         kfree(dev->caps.qp0_tunnel);
 940         kfree(dev->caps.qp0_proxy);
 941         kfree(dev->caps.qp1_tunnel);
 942         kfree(dev->caps.qp1_proxy);
 943         dev->caps.qp0_qkey = NULL;
 944         dev->caps.qp0_tunnel = NULL;
 945         dev->caps.qp0_proxy = NULL;
 946         dev->caps.qp1_tunnel = NULL;
 947         dev->caps.qp1_proxy = NULL;
 948
 949         return err;
 950 }
 951
 952 static void mlx4_request_modules(struct mlx4_dev *dev)
 953 {
 954         int port;
 955         int has_ib_port = false;
 956         int has_eth_port = false;
 957 #define EN_DRV_NAME     "mlx4_en"
 958 #define IB_DRV_NAME     "mlx4_ib"
 959
 960         for (port = 1; port <= dev->caps.num_ports; port++) {
 961                 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_IB)
 962                         has_ib_port = true;
 963                 else if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
 964                         has_eth_port = true;
 965         }
 966
 967         if (has_eth_port)
 968                 request_module_nowait(EN_DRV_NAME);
 969         if (has_ib_port || (dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
 970                 request_module_nowait(IB_DRV_NAME);
 971 }
 972
 973 /*
 974  * Change the port configuration of the device.
 975  * Every user of this function must hold the port mutex.
 976  */
 977 int mlx4_change_port_types(struct mlx4_dev *dev,
 978                            enum mlx4_port_type *port_types)
 979 {
 980         int err = 0;
 981         int change = 0;
 982         int port;
 983
 984         for (port = 0; port <  dev->caps.num_ports; port++) {
 985                 /* Change the port type only if the new type is different
 986                  * from the current, and not set to Auto */
 987                 if (port_types[port] != dev->caps.port_type[port + 1])
 988                         change = 1;
 989         }
 990         if (change) {
 991                 mlx4_unregister_device(dev);
 992                 for (port = 1; port <= dev->caps.num_ports; port++) {
 993                         mlx4_CLOSE_PORT(dev, port);
 994                         dev->caps.port_type[port] = port_types[port - 1];
 995                         err = mlx4_SET_PORT(dev, port, -1);
 996                         if (err) {
 997                                 mlx4_err(dev, "Failed to set port %d, aborting\n",
 998                                          port);
 999                                 goto out;
1000                         }
1001                 }
1002                 mlx4_set_port_mask(dev);
1003                 err = mlx4_register_device(dev);
1004                 if (err) {
1005                         mlx4_err(dev, "Failed to register device\n");
1006                         goto out;
1007                 }
1008                 mlx4_request_modules(dev);
1009         }
1010
1011 out:
1012         return err;
1013 }
1014
1015 static ssize_t show_port_type(struct device *dev,
1016                               struct device_attribute *attr,
1017                               char *buf)
1018 {
1019         struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1020                                                    port_attr);
1021         struct mlx4_dev *mdev = info->dev;
1022         char type[8];
1023
1024         sprintf(type, "%s",
1025                 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
1026                 "ib" : "eth");
1027         if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
1028                 sprintf(buf, "auto (%s)\n", type);
1029         else
1030                 sprintf(buf, "%s\n", type);
1031
1032         return strlen(buf);
1033 }
1034
1035 static ssize_t set_port_type(struct device *dev,
1036                              struct device_attribute *attr,
1037                              const char *buf, size_t count)
1038 {
1039         struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1040                                                    port_attr);
1041         struct mlx4_dev *mdev = info->dev;
1042         struct mlx4_priv *priv = mlx4_priv(mdev);
1043         enum mlx4_port_type types[MLX4_MAX_PORTS];
1044         enum mlx4_port_type new_types[MLX4_MAX_PORTS];
1045         static DEFINE_MUTEX(set_port_type_mutex);
1046         int i;
1047         int err = 0;
1048
1049         mutex_lock(&set_port_type_mutex);
1050
1051         if (!strcmp(buf, "ib\n"))
1052                 info->tmp_type = MLX4_PORT_TYPE_IB;
1053         else if (!strcmp(buf, "eth\n"))
1054                 info->tmp_type = MLX4_PORT_TYPE_ETH;
1055         else if (!strcmp(buf, "auto\n"))
1056                 info->tmp_type = MLX4_PORT_TYPE_AUTO;
1057         else {
1058                 mlx4_err(mdev, "%s is not supported port type\n", buf);
1059                 err = -EINVAL;
1060                 goto err_out;
1061         }
1062
1063         mlx4_stop_sense(mdev);
1064         mutex_lock(&priv->port_mutex);
1065         /* Possible type is always the one that was delivered */
1066         mdev->caps.possible_type[info->port] = info->tmp_type;
1067
1068         for (i = 0; i < mdev->caps.num_ports; i++) {
1069                 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
1070                                         mdev->caps.possible_type[i+1];
1071                 if (types[i] == MLX4_PORT_TYPE_AUTO)
1072                         types[i] = mdev->caps.port_type[i+1];
1073         }
1074
1075         if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
1076             !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) {
1077                 for (i = 1; i <= mdev->caps.num_ports; i++) {
1078                         if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
1079                                 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
1080                                 err = -EINVAL;
1081                         }
1082                 }
1083         }
1084         if (err) {
1085                 mlx4_err(mdev, "Auto sensing is not supported on this HCA. Set only 'eth' or 'ib' for both ports (should be the same)\n");
1086                 goto out;
1087         }
1088
1089         mlx4_do_sense_ports(mdev, new_types, types);
1090
1091         err = mlx4_check_port_params(mdev, new_types);
1092         if (err)
1093                 goto out;
1094
1095         /* We are about to apply the changes after the configuration
1096          * was verified, no need to remember the temporary types
1097          * any more */
1098         for (i = 0; i < mdev->caps.num_ports; i++)
1099                 priv->port[i + 1].tmp_type = 0;
1100
1101         err = mlx4_change_port_types(mdev, new_types);
1102
1103 out:
1104         mlx4_start_sense(mdev);
1105         mutex_unlock(&priv->port_mutex);
1106 err_out:
1107         mutex_unlock(&set_port_type_mutex);
1108
1109         return err ? err : count;
1110 }
1111
1112 enum ibta_mtu {
1113         IB_MTU_256  = 1,
1114         IB_MTU_512  = 2,
1115         IB_MTU_1024 = 3,
1116         IB_MTU_2048 = 4,
1117         IB_MTU_4096 = 5
1118 };
1119
1120 static inline int int_to_ibta_mtu(int mtu)
1121 {
1122         switch (mtu) {
1123         case 256:  return IB_MTU_256;
1124         case 512:  return IB_MTU_512;
1125         case 1024: return IB_MTU_1024;
1126         case 2048: return IB_MTU_2048;
1127         case 4096: return IB_MTU_4096;
1128         default: return -1;
1129         }
1130 }
1131
1132 static inline int ibta_mtu_to_int(enum ibta_mtu mtu)
1133 {
1134         switch (mtu) {
1135         case IB_MTU_256:  return  256;
1136         case IB_MTU_512:  return  512;
1137         case IB_MTU_1024: return 1024;
1138         case IB_MTU_2048: return 2048;
1139         case IB_MTU_4096: return 4096;
1140         default: return -1;
1141         }
1142 }
1143
1144 static ssize_t show_port_ib_mtu(struct device *dev,
1145                              struct device_attribute *attr,
1146                              char *buf)
1147 {
1148         struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1149                                                    port_mtu_attr);
1150         struct mlx4_dev *mdev = info->dev;
1151
1152         if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH)
1153                 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
1154
1155         sprintf(buf, "%d\n",
1156                         ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port]));
1157         return strlen(buf);
1158 }
1159
1160 static ssize_t set_port_ib_mtu(struct device *dev,
1161                              struct device_attribute *attr,
1162                              const char *buf, size_t count)
1163 {
1164         struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1165                                                    port_mtu_attr);
1166         struct mlx4_dev *mdev = info->dev;
1167         struct mlx4_priv *priv = mlx4_priv(mdev);
1168         int err, port, mtu, ibta_mtu = -1;
1169
1170         if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) {
1171                 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
1172                 return -EINVAL;
1173         }
1174
1175         err = kstrtoint(buf, 0, &mtu);
1176         if (!err)
1177                 ibta_mtu = int_to_ibta_mtu(mtu);
1178
1179         if (err || ibta_mtu < 0) {
1180                 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf);
1181                 return -EINVAL;
1182         }
1183
1184         mdev->caps.port_ib_mtu[info->port] = ibta_mtu;
1185
1186         mlx4_stop_sense(mdev);
1187         mutex_lock(&priv->port_mutex);
1188         mlx4_unregister_device(mdev);
1189         for (port = 1; port <= mdev->caps.num_ports; port++) {
1190                 mlx4_CLOSE_PORT(mdev, port);
1191                 err = mlx4_SET_PORT(mdev, port, -1);
1192                 if (err) {
1193                         mlx4_err(mdev, "Failed to set port %d, aborting\n",
1194                                  port);
1195                         goto err_set_port;
1196                 }
1197         }
1198         err = mlx4_register_device(mdev);
1199 err_set_port:
1200         mutex_unlock(&priv->port_mutex);
1201         mlx4_start_sense(mdev);
1202         return err ? err : count;
1203 }
1204
1205 int mlx4_bond(struct mlx4_dev *dev)
1206 {
1207         int ret = 0;
1208         struct mlx4_priv *priv = mlx4_priv(dev);
1209
1210         mutex_lock(&priv->bond_mutex);
1211
1212         if (!mlx4_is_bonded(dev))
1213                 ret = mlx4_do_bond(dev, true);
1214         else
1215                 ret = 0;
1216
1217         mutex_unlock(&priv->bond_mutex);
1218         if (ret)
1219                 mlx4_err(dev, "Failed to bond device: %d\n", ret);
1220         else
1221                 mlx4_dbg(dev, "Device is bonded\n");
1222         return ret;
1223 }
1224 EXPORT_SYMBOL_GPL(mlx4_bond);
1225
1226 int mlx4_unbond(struct mlx4_dev *dev)
1227 {
1228         int ret = 0;
1229         struct mlx4_priv *priv = mlx4_priv(dev);
1230
1231         mutex_lock(&priv->bond_mutex);
1232
1233         if (mlx4_is_bonded(dev))
1234                 ret = mlx4_do_bond(dev, false);
1235
1236         mutex_unlock(&priv->bond_mutex);
1237         if (ret)
1238                 mlx4_err(dev, "Failed to unbond device: %d\n", ret);
1239         else
1240                 mlx4_dbg(dev, "Device is unbonded\n");
1241         return ret;
1242 }
1243 EXPORT_SYMBOL_GPL(mlx4_unbond);
1244
1245
1246 int mlx4_port_map_set(struct mlx4_dev *dev, struct mlx4_port_map *v2p)
1247 {
1248         u8 port1 = v2p->port1;
1249         u8 port2 = v2p->port2;
1250         struct mlx4_priv *priv = mlx4_priv(dev);
1251         int err;
1252
1253         if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PORT_REMAP))
1254                 return -ENOTSUPP;
1255
1256         mutex_lock(&priv->bond_mutex);
1257
1258         /* zero means keep current mapping for this port */
1259         if (port1 == 0)
1260                 port1 = priv->v2p.port1;
1261         if (port2 == 0)
1262                 port2 = priv->v2p.port2;
1263
1264         if ((port1 < 1) || (port1 > MLX4_MAX_PORTS) ||
1265             (port2 < 1) || (port2 > MLX4_MAX_PORTS) ||
1266             (port1 == 2 && port2 == 1)) {
1267                 /* besides boundary checks cross mapping makes
1268                  * no sense and therefore not allowed */
1269                 err = -EINVAL;
1270         } else if ((port1 == priv->v2p.port1) &&
1271                  (port2 == priv->v2p.port2)) {
1272                 err = 0;
1273         } else {
1274                 err = mlx4_virt2phy_port_map(dev, port1, port2);
1275                 if (!err) {
1276                         mlx4_dbg(dev, "port map changed: [%d][%d]\n",
1277                                  port1, port2);
1278                         priv->v2p.port1 = port1;
1279                         priv->v2p.port2 = port2;
1280                 } else {
1281                         mlx4_err(dev, "Failed to change port mape: %d\n", err);
1282                 }
1283         }
1284
1285         mutex_unlock(&priv->bond_mutex);
1286         return err;
1287 }
1288 EXPORT_SYMBOL_GPL(mlx4_port_map_set);
1289
1290 static int mlx4_load_fw(struct mlx4_dev *dev)
1291 {
1292         struct mlx4_priv *priv = mlx4_priv(dev);
1293         int err;
1294
1295         priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
1296                                          GFP_HIGHUSER | __GFP_NOWARN, 0);
1297         if (!priv->fw.fw_icm) {
1298                 mlx4_err(dev, "Couldn't allocate FW area, aborting\n");
1299                 return -ENOMEM;
1300         }
1301
1302         err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
1303         if (err) {
1304                 mlx4_err(dev, "MAP_FA command failed, aborting\n");
1305                 goto err_free;
1306         }
1307
1308         err = mlx4_RUN_FW(dev);
1309         if (err) {
1310                 mlx4_err(dev, "RUN_FW command failed, aborting\n");
1311                 goto err_unmap_fa;
1312         }
1313
1314         return 0;
1315
1316 err_unmap_fa:
1317         mlx4_UNMAP_FA(dev);
1318
1319 err_free:
1320         mlx4_free_icm(dev, priv->fw.fw_icm, 0);
1321         return err;
1322 }
1323
1324 static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
1325                                 int cmpt_entry_sz)
1326 {
1327         struct mlx4_priv *priv = mlx4_priv(dev);
1328         int err;
1329         int num_eqs;
1330
1331         err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
1332                                   cmpt_base +
1333                                   ((u64) (MLX4_CMPT_TYPE_QP *
1334                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1335                                   cmpt_entry_sz, dev->caps.num_qps,
1336                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1337                                   0, 0);
1338         if (err)
1339                 goto err;
1340
1341         err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
1342                                   cmpt_base +
1343                                   ((u64) (MLX4_CMPT_TYPE_SRQ *
1344                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1345                                   cmpt_entry_sz, dev->caps.num_srqs,
1346                                   dev->caps.reserved_srqs, 0, 0);
1347         if (err)
1348                 goto err_qp;
1349
1350         err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
1351                                   cmpt_base +
1352                                   ((u64) (MLX4_CMPT_TYPE_CQ *
1353                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1354                                   cmpt_entry_sz, dev->caps.num_cqs,
1355                                   dev->caps.reserved_cqs, 0, 0);
1356         if (err)
1357                 goto err_srq;
1358
1359         num_eqs = dev->phys_caps.num_phys_eqs;
1360         err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
1361                                   cmpt_base +
1362                                   ((u64) (MLX4_CMPT_TYPE_EQ *
1363                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1364                                   cmpt_entry_sz, num_eqs, num_eqs, 0, 0);
1365         if (err)
1366                 goto err_cq;
1367
1368         return 0;
1369
1370 err_cq:
1371         mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1372
1373 err_srq:
1374         mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1375
1376 err_qp:
1377         mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1378
1379 err:
1380         return err;
1381 }
1382
1383 static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
1384                          struct mlx4_init_hca_param *init_hca, u64 icm_size)
1385 {
1386         struct mlx4_priv *priv = mlx4_priv(dev);
1387         u64 aux_pages;
1388         int num_eqs;
1389         int err;
1390
1391         err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
1392         if (err) {
1393                 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting\n");
1394                 return err;
1395         }
1396
1397         mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory\n",
1398                  (unsigned long long) icm_size >> 10,
1399                  (unsigned long long) aux_pages << 2);
1400
1401         priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
1402                                           GFP_HIGHUSER | __GFP_NOWARN, 0);
1403         if (!priv->fw.aux_icm) {
1404                 mlx4_err(dev, "Couldn't allocate aux memory, aborting\n");
1405                 return -ENOMEM;
1406         }
1407
1408         err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
1409         if (err) {
1410                 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting\n");
1411                 goto err_free_aux;
1412         }
1413
1414         err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
1415         if (err) {
1416                 mlx4_err(dev, "Failed to map cMPT context memory, aborting\n");
1417                 goto err_unmap_aux;
1418         }
1419
1420
1421         num_eqs = dev->phys_caps.num_phys_eqs;
1422         err = mlx4_init_icm_table(dev, &priv->eq_table.table,
1423                                   init_hca->eqc_base, dev_cap->eqc_entry_sz,
1424                                   num_eqs, num_eqs, 0, 0);
1425         if (err) {
1426                 mlx4_err(dev, "Failed to map EQ context memory, aborting\n");
1427                 goto err_unmap_cmpt;
1428         }
1429
1430         /*
1431          * Reserved MTT entries must be aligned up to a cacheline
1432          * boundary, since the FW will write to them, while the driver
1433          * writes to all other MTT entries. (The variable
1434          * dev->caps.mtt_entry_sz below is really the MTT segment
1435          * size, not the raw entry size)
1436          */
1437         dev->caps.reserved_mtts =
1438                 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
1439                       dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
1440
1441         err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
1442                                   init_hca->mtt_base,
1443                                   dev->caps.mtt_entry_sz,
1444                                   dev->caps.num_mtts,
1445                                   dev->caps.reserved_mtts, 1, 0);
1446         if (err) {
1447                 mlx4_err(dev, "Failed to map MTT context memory, aborting\n");
1448                 goto err_unmap_eq;
1449         }
1450
1451         err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
1452                                   init_hca->dmpt_base,
1453                                   dev_cap->dmpt_entry_sz,
1454                                   dev->caps.num_mpts,
1455                                   dev->caps.reserved_mrws, 1, 1);
1456         if (err) {
1457                 mlx4_err(dev, "Failed to map dMPT context memory, aborting\n");
1458                 goto err_unmap_mtt;
1459         }
1460
1461         err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
1462                                   init_hca->qpc_base,
1463                                   dev_cap->qpc_entry_sz,
1464                                   dev->caps.num_qps,
1465                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1466                                   0, 0);
1467         if (err) {
1468                 mlx4_err(dev, "Failed to map QP context memory, aborting\n");
1469                 goto err_unmap_dmpt;
1470         }
1471
1472         err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
1473                                   init_hca->auxc_base,
1474                                   dev_cap->aux_entry_sz,
1475                                   dev->caps.num_qps,
1476                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1477                                   0, 0);
1478         if (err) {
1479                 mlx4_err(dev, "Failed to map AUXC context memory, aborting\n");
1480                 goto err_unmap_qp;
1481         }
1482
1483         err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
1484                                   init_hca->altc_base,
1485                                   dev_cap->altc_entry_sz,
1486                                   dev->caps.num_qps,
1487                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1488                                   0, 0);
1489         if (err) {
1490                 mlx4_err(dev, "Failed to map ALTC context memory, aborting\n");
1491                 goto err_unmap_auxc;
1492         }
1493
1494         err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
1495                                   init_hca->rdmarc_base,
1496                                   dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
1497                                   dev->caps.num_qps,
1498                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1499                                   0, 0);
1500         if (err) {
1501                 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
1502                 goto err_unmap_altc;
1503         }
1504
1505         err = mlx4_init_icm_table(dev, &priv->cq_table.table,
1506                                   init_hca->cqc_base,
1507                                   dev_cap->cqc_entry_sz,
1508                                   dev->caps.num_cqs,
1509                                   dev->caps.reserved_cqs, 0, 0);
1510         if (err) {
1511                 mlx4_err(dev, "Failed to map CQ context memory, aborting\n");
1512                 goto err_unmap_rdmarc;
1513         }
1514
1515         err = mlx4_init_icm_table(dev, &priv->srq_table.table,
1516                                   init_hca->srqc_base,
1517                                   dev_cap->srq_entry_sz,
1518                                   dev->caps.num_srqs,
1519                                   dev->caps.reserved_srqs, 0, 0);
1520         if (err) {
1521                 mlx4_err(dev, "Failed to map SRQ context memory, aborting\n");
1522                 goto err_unmap_cq;
1523         }
1524
1525         /*
1526          * For flow steering device managed mode it is required to use
1527          * mlx4_init_icm_table. For B0 steering mode it's not strictly
1528          * required, but for simplicity just map the whole multicast
1529          * group table now.  The table isn't very big and it's a lot
1530          * easier than trying to track ref counts.
1531          */
1532         err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
1533                                   init_hca->mc_base,
1534                                   mlx4_get_mgm_entry_size(dev),
1535                                   dev->caps.num_mgms + dev->caps.num_amgms,
1536                                   dev->caps.num_mgms + dev->caps.num_amgms,
1537                                   0, 0);
1538         if (err) {
1539                 mlx4_err(dev, "Failed to map MCG context memory, aborting\n");
1540                 goto err_unmap_srq;
1541         }
1542
1543         return 0;
1544
1545 err_unmap_srq:
1546         mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1547
1548 err_unmap_cq:
1549         mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1550
1551 err_unmap_rdmarc:
1552         mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1553
1554 err_unmap_altc:
1555         mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1556
1557 err_unmap_auxc:
1558         mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1559
1560 err_unmap_qp:
1561         mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1562
1563 err_unmap_dmpt:
1564         mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1565
1566 err_unmap_mtt:
1567         mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1568
1569 err_unmap_eq:
1570         mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
1571
1572 err_unmap_cmpt:
1573         mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1574         mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1575         mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1576         mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1577
1578 err_unmap_aux:
1579         mlx4_UNMAP_ICM_AUX(dev);
1580
1581 err_free_aux:
1582         mlx4_free_icm(dev, priv->fw.aux_icm, 0);
1583
1584         return err;
1585 }
1586
1587 static void mlx4_free_icms(struct mlx4_dev *dev)
1588 {
1589         struct mlx4_priv *priv = mlx4_priv(dev);
1590
1591         mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
1592         mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1593         mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1594         mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1595         mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1596         mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1597         mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1598         mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1599         mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1600         mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
1601         mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1602         mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1603         mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1604         mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1605
1606         mlx4_UNMAP_ICM_AUX(dev);
1607         mlx4_free_icm(dev, priv->fw.aux_icm, 0);
1608 }
1609
1610 static void mlx4_slave_exit(struct mlx4_dev *dev)
1611 {
1612         struct mlx4_priv *priv = mlx4_priv(dev);
1613
1614         mutex_lock(&priv->cmd.slave_cmd_mutex);
1615         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_CMD_NA_OP,
1616                           MLX4_COMM_TIME))
1617                 mlx4_warn(dev, "Failed to close slave function\n");
1618         mutex_unlock(&priv->cmd.slave_cmd_mutex);
1619 }
1620
1621 static int map_bf_area(struct mlx4_dev *dev)
1622 {
1623         struct mlx4_priv *priv = mlx4_priv(dev);
1624         resource_size_t bf_start;
1625         resource_size_t bf_len;
1626         int err = 0;
1627
1628         if (!dev->caps.bf_reg_size)
1629                 return -ENXIO;
1630
1631         bf_start = pci_resource_start(dev->persist->pdev, 2) +
1632                         (dev->caps.num_uars << PAGE_SHIFT);
1633         bf_len = pci_resource_len(dev->persist->pdev, 2) -
1634                         (dev->caps.num_uars << PAGE_SHIFT);
1635         priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len);
1636         if (!priv->bf_mapping)
1637                 err = -ENOMEM;
1638
1639         return err;
1640 }
1641
1642 static void unmap_bf_area(struct mlx4_dev *dev)
1643 {
1644         if (mlx4_priv(dev)->bf_mapping)
1645                 io_mapping_free(mlx4_priv(dev)->bf_mapping);
1646 }
1647
1648 cycle_t mlx4_read_clock(struct mlx4_dev *dev)
1649 {
1650         u32 clockhi, clocklo, clockhi1;
1651         cycle_t cycles;
1652         int i;
1653         struct mlx4_priv *priv = mlx4_priv(dev);
1654
1655         for (i = 0; i < 10; i++) {
1656                 clockhi = swab32(readl(priv->clock_mapping));
1657                 clocklo = swab32(readl(priv->clock_mapping + 4));
1658                 clockhi1 = swab32(readl(priv->clock_mapping));
1659                 if (clockhi == clockhi1)
1660                         break;
1661         }
1662
1663         cycles = (u64) clockhi << 32 | (u64) clocklo;
1664
1665         return cycles;
1666 }
1667 EXPORT_SYMBOL_GPL(mlx4_read_clock);
1668
1669
1670 static int map_internal_clock(struct mlx4_dev *dev)
1671 {
1672         struct mlx4_priv *priv = mlx4_priv(dev);
1673
1674         priv->clock_mapping =
1675                 ioremap(pci_resource_start(dev->persist->pdev,
1676                                            priv->fw.clock_bar) +
1677                         priv->fw.clock_offset, MLX4_CLOCK_SIZE);
1678
1679         if (!priv->clock_mapping)
1680                 return -ENOMEM;
1681
1682         return 0;
1683 }
1684
1685 int mlx4_get_internal_clock_params(struct mlx4_dev *dev,
1686                                    struct mlx4_clock_params *params)
1687 {
1688         struct mlx4_priv *priv = mlx4_priv(dev);
1689
1690         if (mlx4_is_slave(dev))
1691                 return -ENOTSUPP;
1692
1693         if (!params)
1694                 return -EINVAL;
1695
1696         params->bar = priv->fw.clock_bar;
1697         params->offset = priv->fw.clock_offset;
1698         params->size = MLX4_CLOCK_SIZE;
1699
1700         return 0;
1701 }
1702 EXPORT_SYMBOL_GPL(mlx4_get_internal_clock_params);
1703
1704 static void unmap_internal_clock(struct mlx4_dev *dev)
1705 {
1706         struct mlx4_priv *priv = mlx4_priv(dev);
1707
1708         if (priv->clock_mapping)
1709                 iounmap(priv->clock_mapping);
1710 }
1711
1712 static void mlx4_close_hca(struct mlx4_dev *dev)
1713 {
1714         unmap_internal_clock(dev);
1715         unmap_bf_area(dev);
1716         if (mlx4_is_slave(dev))
1717                 mlx4_slave_exit(dev);
1718         else {
1719                 mlx4_CLOSE_HCA(dev, 0);
1720                 mlx4_free_icms(dev);
1721         }
1722 }
1723
1724 static void mlx4_close_fw(struct mlx4_dev *dev)
1725 {
1726         if (!mlx4_is_slave(dev)) {
1727                 mlx4_UNMAP_FA(dev);
1728                 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
1729         }
1730 }
1731
1732 static int mlx4_comm_check_offline(struct mlx4_dev *dev)
1733 {
1734 #define COMM_CHAN_OFFLINE_OFFSET 0x09
1735
1736         u32 comm_flags;
1737         u32 offline_bit;
1738         unsigned long end;
1739         struct mlx4_priv *priv = mlx4_priv(dev);
1740
1741         end = msecs_to_jiffies(MLX4_COMM_OFFLINE_TIME_OUT) + jiffies;
1742         while (time_before(jiffies, end)) {
1743                 comm_flags = swab32(readl((__iomem char *)priv->mfunc.comm +
1744                                           MLX4_COMM_CHAN_FLAGS));
1745                 offline_bit = (comm_flags &
1746                                (u32)(1 << COMM_CHAN_OFFLINE_OFFSET));
1747                 if (!offline_bit)
1748                         return 0;
1749                 /* There are cases as part of AER/Reset flow that PF needs
1750                  * around 100 msec to load. We therefore sleep for 100 msec
1751                  * to allow other tasks to make use of that CPU during this
1752                  * time interval.
1753                  */
1754                 msleep(100);
1755         }
1756         mlx4_err(dev, "Communication channel is offline.\n");
1757         return -EIO;
1758 }
1759
1760 static void mlx4_reset_vf_support(struct mlx4_dev *dev)
1761 {
1762 #define COMM_CHAN_RST_OFFSET 0x1e
1763
1764         struct mlx4_priv *priv = mlx4_priv(dev);
1765         u32 comm_rst;
1766         u32 comm_caps;
1767
1768         comm_caps = swab32(readl((__iomem char *)priv->mfunc.comm +
1769                                  MLX4_COMM_CHAN_CAPS));
1770         comm_rst = (comm_caps & (u32)(1 << COMM_CHAN_RST_OFFSET));
1771
1772         if (comm_rst)
1773                 dev->caps.vf_caps |= MLX4_VF_CAP_FLAG_RESET;
1774 }
1775
1776 static int mlx4_init_slave(struct mlx4_dev *dev)
1777 {
1778         struct mlx4_priv *priv = mlx4_priv(dev);
1779         u64 dma = (u64) priv->mfunc.vhcr_dma;
1780         int ret_from_reset = 0;
1781         u32 slave_read;
1782         u32 cmd_channel_ver;
1783
1784         if (atomic_read(&pf_loading)) {
1785                 mlx4_warn(dev, "PF is not ready - Deferring probe\n");
1786                 return -EPROBE_DEFER;
1787         }
1788
1789         mutex_lock(&priv->cmd.slave_cmd_mutex);
1790         priv->cmd.max_cmds = 1;
1791         if (mlx4_comm_check_offline(dev)) {
1792                 mlx4_err(dev, "PF is not responsive, skipping initialization\n");
1793                 goto err_offline;
1794         }
1795
1796         mlx4_reset_vf_support(dev);
1797         mlx4_warn(dev, "Sending reset\n");
1798         ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0,
1799                                        MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME);
1800         /* if we are in the middle of flr the slave will try
1801          * NUM_OF_RESET_RETRIES times before leaving.*/
1802         if (ret_from_reset) {
1803                 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) {
1804                         mlx4_warn(dev, "slave is currently in the middle of FLR - Deferring probe\n");
1805                         mutex_unlock(&priv->cmd.slave_cmd_mutex);
1806                         return -EPROBE_DEFER;
1807                 } else
1808                         goto err;
1809         }
1810
1811         /* check the driver version - the slave I/F revision
1812          * must match the master's */
1813         slave_read = swab32(readl(&priv->mfunc.comm->slave_read));
1814         cmd_channel_ver = mlx4_comm_get_version();
1815
1816         if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) !=
1817                 MLX4_COMM_GET_IF_REV(slave_read)) {
1818                 mlx4_err(dev, "slave driver version is not supported by the master\n");
1819                 goto err;
1820         }
1821
1822         mlx4_warn(dev, "Sending vhcr0\n");
1823         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48,
1824                              MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
1825                 goto err;
1826         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32,
1827                              MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
1828                 goto err;
1829         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16,
1830                              MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
1831                 goto err;
1832         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma,
1833                           MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
1834                 goto err;
1835
1836         mutex_unlock(&priv->cmd.slave_cmd_mutex);
1837         return 0;
1838
1839 err:
1840         mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_CMD_NA_OP, 0);
1841 err_offline:
1842         mutex_unlock(&priv->cmd.slave_cmd_mutex);
1843         return -EIO;
1844 }
1845
1846 static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev)
1847 {
1848         int i;
1849
1850         for (i = 1; i <= dev->caps.num_ports; i++) {
1851                 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH)
1852                         dev->caps.gid_table_len[i] =
1853                                 mlx4_get_slave_num_gids(dev, 0, i);
1854                 else
1855                         dev->caps.gid_table_len[i] = 1;
1856                 dev->caps.pkey_table_len[i] =
1857                         dev->phys_caps.pkey_phys_table_len[i] - 1;
1858         }
1859 }
1860
1861 static int choose_log_fs_mgm_entry_size(int qp_per_entry)
1862 {
1863         int i = MLX4_MIN_MGM_LOG_ENTRY_SIZE;
1864
1865         for (i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE;
1866               i++) {
1867                 if (qp_per_entry <= 4 * ((1 << i) / 16 - 2))
1868                         break;
1869         }
1870
1871         return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1;
1872 }
1873
1874 static const char *dmfs_high_rate_steering_mode_str(int dmfs_high_steer_mode)
1875 {
1876         switch (dmfs_high_steer_mode) {
1877         case MLX4_STEERING_DMFS_A0_DEFAULT:
1878                 return "default performance";
1879
1880         case MLX4_STEERING_DMFS_A0_DYNAMIC:
1881                 return "dynamic hybrid mode";
1882
1883         case MLX4_STEERING_DMFS_A0_STATIC:
1884                 return "performance optimized for limited rule configuration (static)";
1885
1886         case MLX4_STEERING_DMFS_A0_DISABLE:
1887                 return "disabled performance optimized steering";
1888
1889         case MLX4_STEERING_DMFS_A0_NOT_SUPPORTED:
1890                 return "performance optimized steering not supported";
1891
1892         default:
1893                 return "Unrecognized mode";
1894         }
1895 }
1896
1897 #define MLX4_DMFS_A0_STEERING                   (1UL << 2)
1898
1899 static void choose_steering_mode(struct mlx4_dev *dev,
1900                                  struct mlx4_dev_cap *dev_cap)
1901 {
1902         if (mlx4_log_num_mgm_entry_size <= 0) {
1903                 if ((-mlx4_log_num_mgm_entry_size) & MLX4_DMFS_A0_STEERING) {
1904                         if (dev->caps.dmfs_high_steer_mode ==
1905                             MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
1906                                 mlx4_err(dev, "DMFS high rate mode not supported\n");
1907                         else
1908                                 dev->caps.dmfs_high_steer_mode =
1909                                         MLX4_STEERING_DMFS_A0_STATIC;
1910                 }
1911         }
1912
1913         if (mlx4_log_num_mgm_entry_size <= 0 &&
1914             dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN &&
1915             (!mlx4_is_mfunc(dev) ||
1916              (dev_cap->fs_max_num_qp_per_entry >=
1917              (dev->persist->num_vfs + 1))) &&
1918             choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >=
1919                 MLX4_MIN_MGM_LOG_ENTRY_SIZE) {
1920                 dev->oper_log_mgm_entry_size =
1921                         choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry);
1922                 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
1923                 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
1924                 dev->caps.fs_log_max_ucast_qp_range_size =
1925                         dev_cap->fs_log_max_ucast_qp_range_size;
1926         } else {
1927                 if (dev->caps.dmfs_high_steer_mode !=
1928                     MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
1929                         dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DISABLE;
1930                 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER &&
1931                     dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1932                         dev->caps.steering_mode = MLX4_STEERING_MODE_B0;
1933                 else {
1934                         dev->caps.steering_mode = MLX4_STEERING_MODE_A0;
1935
1936                         if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER ||
1937                             dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1938                                 mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags set to use B0 steering - falling back to A0 steering mode\n");
1939                 }
1940                 dev->oper_log_mgm_entry_size =
1941                         mlx4_log_num_mgm_entry_size > 0 ?
1942                         mlx4_log_num_mgm_entry_size :
1943                         MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
1944                 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev);
1945         }
1946         mlx4_dbg(dev, "Steering mode is: %s, oper_log_mgm_entry_size = %d, modparam log_num_mgm_entry_size = %d\n",
1947                  mlx4_steering_mode_str(dev->caps.steering_mode),
1948                  dev->oper_log_mgm_entry_size,
1949                  mlx4_log_num_mgm_entry_size);
1950 }
1951
1952 static void choose_tunnel_offload_mode(struct mlx4_dev *dev,
1953                                        struct mlx4_dev_cap *dev_cap)
1954 {
1955         if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED &&
1956             dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS)
1957                 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_VXLAN;
1958         else
1959                 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_NONE;
1960
1961         mlx4_dbg(dev, "Tunneling offload mode is: %s\n",  (dev->caps.tunnel_offload_mode
1962                  == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) ? "vxlan" : "none");
1963 }
1964
1965 static int mlx4_validate_optimized_steering(struct mlx4_dev *dev)
1966 {
1967         int i;
1968         struct mlx4_port_cap port_cap;
1969
1970         if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
1971                 return -EINVAL;
1972
1973         for (i = 1; i <= dev->caps.num_ports; i++) {
1974                 if (mlx4_dev_port(dev, i, &port_cap)) {
1975                         mlx4_err(dev,
1976                                  "QUERY_DEV_CAP command failed, can't veify DMFS high rate steering.\n");
1977                 } else if ((dev->caps.dmfs_high_steer_mode !=
1978                             MLX4_STEERING_DMFS_A0_DEFAULT) &&
1979                            (port_cap.dmfs_optimized_state ==
1980                             !!(dev->caps.dmfs_high_steer_mode ==
1981                             MLX4_STEERING_DMFS_A0_DISABLE))) {
1982                         mlx4_err(dev,
1983                                  "DMFS high rate steer mode differ, driver requested %s but %s in FW.\n",
1984                                  dmfs_high_rate_steering_mode_str(
1985                                         dev->caps.dmfs_high_steer_mode),
1986                                  (port_cap.dmfs_optimized_state ?
1987                                         "enabled" : "disabled"));
1988                 }
1989         }
1990
1991         return 0;
1992 }
1993
1994 static int mlx4_init_fw(struct mlx4_dev *dev)
1995 {
1996         struct mlx4_mod_stat_cfg   mlx4_cfg;
1997         int err = 0;
1998
1999         if (!mlx4_is_slave(dev)) {
2000                 err = mlx4_QUERY_FW(dev);
2001                 if (err) {
2002                         if (err == -EACCES)
2003                                 mlx4_info(dev, "non-primary physical function, skipping\n");
2004                         else
2005                                 mlx4_err(dev, "QUERY_FW command failed, aborting\n");
2006                         return err;
2007                 }
2008
2009                 err = mlx4_load_fw(dev);
2010                 if (err) {
2011                         mlx4_err(dev, "Failed to start FW, aborting\n");
2012                         return err;
2013                 }
2014
2015                 mlx4_cfg.log_pg_sz_m = 1;
2016                 mlx4_cfg.log_pg_sz = 0;
2017                 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
2018                 if (err)
2019                         mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
2020         }
2021
2022         return err;
2023 }
2024
2025 static int mlx4_init_hca(struct mlx4_dev *dev)
2026 {
2027         struct mlx4_priv          *priv = mlx4_priv(dev);
2028         struct mlx4_adapter        adapter;
2029         struct mlx4_dev_cap        dev_cap;
2030         struct mlx4_profile        profile;
2031         struct mlx4_init_hca_param init_hca;
2032         u64 icm_size;
2033         struct mlx4_config_dev_params params;
2034         int err;
2035
2036         if (!mlx4_is_slave(dev)) {
2037                 err = mlx4_dev_cap(dev, &dev_cap);
2038                 if (err) {
2039                         mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
2040                         return err;
2041                 }
2042
2043                 choose_steering_mode(dev, &dev_cap);
2044                 choose_tunnel_offload_mode(dev, &dev_cap);
2045
2046                 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC &&
2047                     mlx4_is_master(dev))
2048                         dev->caps.function_caps |= MLX4_FUNC_CAP_DMFS_A0_STATIC;
2049
2050                 err = mlx4_get_phys_port_id(dev);
2051                 if (err)
2052                         mlx4_err(dev, "Fail to get physical port id\n");
2053
2054                 if (mlx4_is_master(dev))
2055                         mlx4_parav_master_pf_caps(dev);
2056
2057                 if (mlx4_low_memory_profile()) {
2058                         mlx4_info(dev, "Running from within kdump kernel. Using low memory profile\n");
2059                         profile = low_mem_profile;
2060                 } else {
2061                         profile = default_profile;
2062                 }
2063                 if (dev->caps.steering_mode ==
2064                     MLX4_STEERING_MODE_DEVICE_MANAGED)
2065                         profile.num_mcg = MLX4_FS_NUM_MCG;
2066
2067                 icm_size = mlx4_make_profile(dev, &profile, &dev_cap,
2068                                              &init_hca);
2069                 if ((long long) icm_size < 0) {
2070                         err = icm_size;
2071                         return err;
2072                 }
2073
2074                 dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1;
2075
2076                 init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
2077                 init_hca.uar_page_sz = PAGE_SHIFT - 12;
2078                 init_hca.mw_enabled = 0;
2079                 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW ||
2080                     dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN)
2081                         init_hca.mw_enabled = INIT_HCA_TPT_MW_ENABLE;
2082
2083                 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
2084                 if (err)
2085                         return err;
2086
2087                 err = mlx4_INIT_HCA(dev, &init_hca);
2088                 if (err) {
2089                         mlx4_err(dev, "INIT_HCA command failed, aborting\n");
2090                         goto err_free_icm;
2091                 }
2092
2093                 if (dev_cap.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) {
2094                         err = mlx4_query_func(dev, &dev_cap);
2095                         if (err < 0) {
2096                                 mlx4_err(dev, "QUERY_FUNC command failed, aborting.\n");
2097                                 goto err_close;
2098                         } else if (err & MLX4_QUERY_FUNC_NUM_SYS_EQS) {
2099                                 dev->caps.num_eqs = dev_cap.max_eqs;
2100                                 dev->caps.reserved_eqs = dev_cap.reserved_eqs;
2101                                 dev->caps.reserved_uars = dev_cap.reserved_uars;
2102                         }
2103                 }
2104
2105                 /*
2106                  * If TS is supported by FW
2107                  * read HCA frequency by QUERY_HCA command
2108                  */
2109                 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) {
2110                         memset(&init_hca, 0, sizeof(init_hca));
2111                         err = mlx4_QUERY_HCA(dev, &init_hca);
2112                         if (err) {
2113                                 mlx4_err(dev, "QUERY_HCA command failed, disable timestamp\n");
2114                                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
2115                         } else {
2116                                 dev->caps.hca_core_clock =
2117                                         init_hca.hca_core_clock;
2118                         }
2119
2120                         /* In case we got HCA frequency 0 - disable timestamping
2121                          * to avoid dividing by zero
2122                          */
2123                         if (!dev->caps.hca_core_clock) {
2124                                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
2125                                 mlx4_err(dev,
2126                                          "HCA frequency is 0 - timestamping is not supported\n");
2127                         } else if (map_internal_clock(dev)) {
2128                                 /*
2129                                  * Map internal clock,
2130                                  * in case of failure disable timestamping
2131                                  */
2132                                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
2133                                 mlx4_err(dev, "Failed to map internal clock. Timestamping is not supported\n");
2134                         }
2135                 }
2136
2137                 if (dev->caps.dmfs_high_steer_mode !=
2138                     MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) {
2139                         if (mlx4_validate_optimized_steering(dev))
2140                                 mlx4_warn(dev, "Optimized steering validation failed\n");
2141
2142                         if (dev->caps.dmfs_high_steer_mode ==
2143                             MLX4_STEERING_DMFS_A0_DISABLE) {
2144                                 dev->caps.dmfs_high_rate_qpn_base =
2145                                         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
2146                                 dev->caps.dmfs_high_rate_qpn_range =
2147                                         MLX4_A0_STEERING_TABLE_SIZE;
2148                         }
2149
2150                         mlx4_dbg(dev, "DMFS high rate steer mode is: %s\n",
2151                                  dmfs_high_rate_steering_mode_str(
2152                                         dev->caps.dmfs_high_steer_mode));
2153                 }
2154         } else {
2155                 err = mlx4_init_slave(dev);
2156                 if (err) {
2157                         if (err != -EPROBE_DEFER)
2158                                 mlx4_err(dev, "Failed to initialize slave\n");
2159                         return err;
2160                 }
2161
2162                 err = mlx4_slave_cap(dev);
2163                 if (err) {
2164                         mlx4_err(dev, "Failed to obtain slave caps\n");
2165                         goto err_close;
2166                 }
2167         }
2168
2169         if (map_bf_area(dev))
2170                 mlx4_dbg(dev, "Failed to map blue flame area\n");
2171
2172         /*Only the master set the ports, all the rest got it from it.*/
2173         if (!mlx4_is_slave(dev))
2174                 mlx4_set_port_mask(dev);
2175
2176         err = mlx4_QUERY_ADAPTER(dev, &adapter);
2177         if (err) {
2178                 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting\n");
2179                 goto unmap_bf;
2180         }
2181
2182         /* Query CONFIG_DEV parameters */
2183         err = mlx4_config_dev_retrieval(dev, &params);
2184         if (err && err != -ENOTSUPP) {
2185                 mlx4_err(dev, "Failed to query CONFIG_DEV parameters\n");
2186         } else if (!err) {
2187                 dev->caps.rx_checksum_flags_port[1] = params.rx_csum_flags_port_1;
2188                 dev->caps.rx_checksum_flags_port[2] = params.rx_csum_flags_port_2;
2189         }
2190         priv->eq_table.inta_pin = adapter.inta_pin;
2191         memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
2192
2193         return 0;
2194
2195 unmap_bf:
2196         unmap_internal_clock(dev);
2197         unmap_bf_area(dev);
2198
2199         if (mlx4_is_slave(dev)) {
2200                 kfree(dev->caps.qp0_qkey);
2201                 kfree(dev->caps.qp0_tunnel);
2202                 kfree(dev->caps.qp0_proxy);
2203                 kfree(dev->caps.qp1_tunnel);
2204                 kfree(dev->caps.qp1_proxy);
2205         }
2206
2207 err_close:
2208         if (mlx4_is_slave(dev))
2209                 mlx4_slave_exit(dev);
2210         else
2211                 mlx4_CLOSE_HCA(dev, 0);
2212
2213 err_free_icm:
2214         if (!mlx4_is_slave(dev))
2215                 mlx4_free_icms(dev);
2216
2217         return err;
2218 }
2219
2220 static int mlx4_init_counters_table(struct mlx4_dev *dev)
2221 {
2222         struct mlx4_priv *priv = mlx4_priv(dev);
2223         int nent_pow2;
2224
2225         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2226                 return -ENOENT;
2227
2228         if (!dev->caps.max_counters)
2229                 return -ENOSPC;
2230
2231         nent_pow2 = roundup_pow_of_two(dev->caps.max_counters);
2232         /* reserve last counter index for sink counter */
2233         return mlx4_bitmap_init(&priv->counters_bitmap, nent_pow2,
2234                                 nent_pow2 - 1, 0,
2235                                 nent_pow2 - dev->caps.max_counters + 1);
2236 }
2237
2238 static void mlx4_cleanup_counters_table(struct mlx4_dev *dev)
2239 {
2240         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2241                 return;
2242
2243         if (!dev->caps.max_counters)
2244                 return;
2245
2246         mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap);
2247 }
2248
2249 static void mlx4_cleanup_default_counters(struct mlx4_dev *dev)
2250 {
2251         struct mlx4_priv *priv = mlx4_priv(dev);
2252         int port;
2253
2254         for (port = 0; port < dev->caps.num_ports; port++)
2255                 if (priv->def_counter[port] != -1)
2256                         mlx4_counter_free(dev,  priv->def_counter[port]);
2257 }
2258
2259 static int mlx4_allocate_default_counters(struct mlx4_dev *dev)
2260 {
2261         struct mlx4_priv *priv = mlx4_priv(dev);
2262         int port, err = 0;
2263         u32 idx;
2264
2265         for (port = 0; port < dev->caps.num_ports; port++)
2266                 priv->def_counter[port] = -1;
2267
2268         for (port = 0; port < dev->caps.num_ports; port++) {
2269                 err = mlx4_counter_alloc(dev, &idx);
2270
2271                 if (!err || err == -ENOSPC) {
2272                         priv->def_counter[port] = idx;
2273                 } else if (err == -ENOENT) {
2274                         err = 0;
2275                         continue;
2276                 } else {
2277                         mlx4_err(dev, "%s: failed to allocate default counter port %d err %d\n",
2278                                  __func__, port + 1, err);
2279                         mlx4_cleanup_default_counters(dev);
2280                         return err;
2281                 }
2282
2283                 mlx4_dbg(dev, "%s: default counter index %d for port %d\n",
2284                          __func__, priv->def_counter[port], port + 1);
2285         }
2286
2287         return err;
2288 }
2289
2290 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
2291 {
2292         struct mlx4_priv *priv = mlx4_priv(dev);
2293
2294         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2295                 return -ENOENT;
2296
2297         *idx = mlx4_bitmap_alloc(&priv->counters_bitmap);
2298         if (*idx == -1) {
2299                 *idx = MLX4_SINK_COUNTER_INDEX(dev);
2300                 return -ENOSPC;
2301         }
2302
2303         return 0;
2304 }
2305
2306 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
2307 {
2308         u64 out_param;
2309         int err;
2310
2311         if (mlx4_is_mfunc(dev)) {
2312                 err = mlx4_cmd_imm(dev, 0, &out_param, RES_COUNTER,
2313                                    RES_OP_RESERVE, MLX4_CMD_ALLOC_RES,
2314                                    MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
2315                 if (!err)
2316                         *idx = get_param_l(&out_param);
2317
2318                 return err;
2319         }
2320         return __mlx4_counter_alloc(dev, idx);
2321 }
2322 EXPORT_SYMBOL_GPL(mlx4_counter_alloc);
2323
2324 static int __mlx4_clear_if_stat(struct mlx4_dev *dev,
2325                                 u8 counter_index)
2326 {
2327         struct mlx4_cmd_mailbox *if_stat_mailbox;
2328         int err;
2329         u32 if_stat_in_mod = (counter_index & 0xff) | MLX4_QUERY_IF_STAT_RESET;
2330
2331         if_stat_mailbox = mlx4_alloc_cmd_mailbox(dev);
2332         if (IS_ERR(if_stat_mailbox))
2333                 return PTR_ERR(if_stat_mailbox);
2334
2335         err = mlx4_cmd_box(dev, 0, if_stat_mailbox->dma, if_stat_in_mod, 0,
2336                            MLX4_CMD_QUERY_IF_STAT, MLX4_CMD_TIME_CLASS_C,
2337                            MLX4_CMD_NATIVE);
2338
2339         mlx4_free_cmd_mailbox(dev, if_stat_mailbox);
2340         return err;
2341 }
2342
2343 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
2344 {
2345         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2346                 return;
2347
2348         if (idx == MLX4_SINK_COUNTER_INDEX(dev))
2349                 return;
2350
2351         __mlx4_clear_if_stat(dev, idx);
2352
2353         mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx, MLX4_USE_RR);
2354         return;
2355 }
2356
2357 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
2358 {
2359         u64 in_param = 0;
2360
2361         if (mlx4_is_mfunc(dev)) {
2362                 set_param_l(&in_param, idx);
2363                 mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE,
2364                          MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
2365                          MLX4_CMD_WRAPPED);
2366                 return;
2367         }
2368         __mlx4_counter_free(dev, idx);
2369 }
2370 EXPORT_SYMBOL_GPL(mlx4_counter_free);
2371
2372 int mlx4_get_default_counter_index(struct mlx4_dev *dev, int port)
2373 {
2374         struct mlx4_priv *priv = mlx4_priv(dev);
2375
2376         return priv->def_counter[port - 1];
2377 }
2378 EXPORT_SYMBOL_GPL(mlx4_get_default_counter_index);
2379
2380 void mlx4_set_admin_guid(struct mlx4_dev *dev, __be64 guid, int entry, int port)
2381 {
2382         struct mlx4_priv *priv = mlx4_priv(dev);
2383
2384         priv->mfunc.master.vf_admin[entry].vport[port].guid = guid;
2385 }
2386 EXPORT_SYMBOL_GPL(mlx4_set_admin_guid);
2387
2388 __be64 mlx4_get_admin_guid(struct mlx4_dev *dev, int entry, int port)
2389 {
2390         struct mlx4_priv *priv = mlx4_priv(dev);
2391
2392         return priv->mfunc.master.vf_admin[entry].vport[port].guid;
2393 }
2394 EXPORT_SYMBOL_GPL(mlx4_get_admin_guid);
2395
2396 void mlx4_set_random_admin_guid(struct mlx4_dev *dev, int entry, int port)
2397 {
2398         struct mlx4_priv *priv = mlx4_priv(dev);
2399         __be64 guid;
2400
2401         /* hw GUID */
2402         if (entry == 0)
2403                 return;
2404
2405         get_random_bytes((char *)&guid, sizeof(guid));
2406         guid &= ~(cpu_to_be64(1ULL << 56));
2407         guid |= cpu_to_be64(1ULL << 57);
2408         priv->mfunc.master.vf_admin[entry].vport[port].guid = guid;
2409 }
2410
2411 static int mlx4_setup_hca(struct mlx4_dev *dev)
2412 {
2413         struct mlx4_priv *priv = mlx4_priv(dev);
2414         int err;
2415         int port;
2416         __be32 ib_port_default_caps;
2417
2418         err = mlx4_init_uar_table(dev);
2419         if (err) {
2420                 mlx4_err(dev, "Failed to initialize user access region table, aborting\n");
2421                  return err;
2422         }
2423
2424         err = mlx4_uar_alloc(dev, &priv->driver_uar);
2425         if (err) {
2426                 mlx4_err(dev, "Failed to allocate driver access region, aborting\n");
2427                 goto err_uar_table_free;
2428         }
2429
2430         priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
2431         if (!priv->kar) {
2432                 mlx4_err(dev, "Couldn't map kernel access region, aborting\n");
2433                 err = -ENOMEM;
2434                 goto err_uar_free;
2435         }
2436
2437         err = mlx4_init_pd_table(dev);
2438         if (err) {
2439                 mlx4_err(dev, "Failed to initialize protection domain table, aborting\n");
2440                 goto err_kar_unmap;
2441         }
2442
2443         err = mlx4_init_xrcd_table(dev);
2444         if (err) {
2445                 mlx4_err(dev, "Failed to initialize reliable connection domain table, aborting\n");
2446                 goto err_pd_table_free;
2447         }
2448
2449         err = mlx4_init_mr_table(dev);
2450         if (err) {
2451                 mlx4_err(dev, "Failed to initialize memory region table, aborting\n");
2452                 goto err_xrcd_table_free;
2453         }
2454
2455         if (!mlx4_is_slave(dev)) {
2456                 err = mlx4_init_mcg_table(dev);
2457                 if (err) {
2458                         mlx4_err(dev, "Failed to initialize multicast group table, aborting\n");
2459                         goto err_mr_table_free;
2460                 }
2461                 err = mlx4_config_mad_demux(dev);
2462                 if (err) {
2463                         mlx4_err(dev, "Failed in config_mad_demux, aborting\n");
2464                         goto err_mcg_table_free;
2465                 }
2466         }
2467
2468         err = mlx4_init_eq_table(dev);
2469         if (err) {
2470                 mlx4_err(dev, "Failed to initialize event queue table, aborting\n");
2471                 goto err_mcg_table_free;
2472         }
2473
2474         err = mlx4_cmd_use_events(dev);
2475         if (err) {
2476                 mlx4_err(dev, "Failed to switch to event-driven firmware commands, aborting\n");
2477                 goto err_eq_table_free;
2478         }
2479
2480         err = mlx4_NOP(dev);
2481         if (err) {
2482                 if (dev->flags & MLX4_FLAG_MSI_X) {
2483                         mlx4_warn(dev, "NOP command failed to generate MSI-X interrupt IRQ %d)\n",
2484                                   priv->eq_table.eq[MLX4_EQ_ASYNC].irq);
2485                         mlx4_warn(dev, "Trying again without MSI-X\n");
2486                 } else {
2487                         mlx4_err(dev, "NOP command failed to generate interrupt (IRQ %d), aborting\n",
2488                                  priv->eq_table.eq[MLX4_EQ_ASYNC].irq);
2489                         mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
2490                 }
2491
2492                 goto err_cmd_poll;
2493         }
2494
2495         mlx4_dbg(dev, "NOP command IRQ test passed\n");
2496
2497         err = mlx4_init_cq_table(dev);
2498         if (err) {
2499                 mlx4_err(dev, "Failed to initialize completion queue table, aborting\n");
2500                 goto err_cmd_poll;
2501         }
2502
2503         err = mlx4_init_srq_table(dev);
2504         if (err) {
2505                 mlx4_err(dev, "Failed to initialize shared receive queue table, aborting\n");
2506                 goto err_cq_table_free;
2507         }
2508
2509         err = mlx4_init_qp_table(dev);
2510         if (err) {
2511                 mlx4_err(dev, "Failed to initialize queue pair table, aborting\n");
2512                 goto err_srq_table_free;
2513         }
2514
2515         if (!mlx4_is_slave(dev)) {
2516                 err = mlx4_init_counters_table(dev);
2517                 if (err && err != -ENOENT) {
2518                         mlx4_err(dev, "Failed to initialize counters table, aborting\n");
2519                         goto err_qp_table_free;
2520                 }
2521         }
2522
2523         err = mlx4_allocate_default_counters(dev);
2524         if (err) {
2525                 mlx4_err(dev, "Failed to allocate default counters, aborting\n");
2526                 goto err_counters_table_free;
2527         }
2528
2529         if (!mlx4_is_slave(dev)) {
2530                 for (port = 1; port <= dev->caps.num_ports; port++) {
2531                         ib_port_default_caps = 0;
2532                         err = mlx4_get_port_ib_caps(dev, port,
2533                                                     &ib_port_default_caps);
2534                         if (err)
2535                                 mlx4_warn(dev, "failed to get port %d default ib capabilities (%d). Continuing with caps = 0\n",
2536                                           port, err);
2537                         dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
2538
2539                         /* initialize per-slave default ib port capabilities */
2540                         if (mlx4_is_master(dev)) {
2541                                 int i;
2542                                 for (i = 0; i < dev->num_slaves; i++) {
2543                                         if (i == mlx4_master_func_num(dev))
2544                                                 continue;
2545                                         priv->mfunc.master.slave_state[i].ib_cap_mask[port] =
2546                                                 ib_port_default_caps;
2547                                 }
2548                         }
2549
2550                         if (mlx4_is_mfunc(dev))
2551                                 dev->caps.port_ib_mtu[port] = IB_MTU_2048;
2552                         else
2553                                 dev->caps.port_ib_mtu[port] = IB_MTU_4096;
2554
2555                         err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ?
2556                                             dev->caps.pkey_table_len[port] : -1);
2557                         if (err) {
2558                                 mlx4_err(dev, "Failed to set port %d, aborting\n",
2559                                          port);
2560                                 goto err_default_countes_free;
2561                         }
2562                 }
2563         }
2564
2565         return 0;
2566
2567 err_default_countes_free:
2568         mlx4_cleanup_default_counters(dev);
2569
2570 err_counters_table_free:
2571         if (!mlx4_is_slave(dev))
2572                 mlx4_cleanup_counters_table(dev);
2573
2574 err_qp_table_free:
2575         mlx4_cleanup_qp_table(dev);
2576
2577 err_srq_table_free:
2578         mlx4_cleanup_srq_table(dev);
2579
2580 err_cq_table_free:
2581         mlx4_cleanup_cq_table(dev);
2582
2583 err_cmd_poll:
2584         mlx4_cmd_use_polling(dev);
2585
2586 err_eq_table_free:
2587         mlx4_cleanup_eq_table(dev);
2588
2589 err_mcg_table_free:
2590         if (!mlx4_is_slave(dev))
2591                 mlx4_cleanup_mcg_table(dev);
2592
2593 err_mr_table_free:
2594         mlx4_cleanup_mr_table(dev);
2595
2596 err_xrcd_table_free:
2597         mlx4_cleanup_xrcd_table(dev);
2598
2599 err_pd_table_free:
2600         mlx4_cleanup_pd_table(dev);
2601
2602 err_kar_unmap:
2603         iounmap(priv->kar);
2604
2605 err_uar_free:
2606         mlx4_uar_free(dev, &priv->driver_uar);
2607
2608 err_uar_table_free:
2609         mlx4_cleanup_uar_table(dev);
2610         return err;
2611 }
2612
2613 static int mlx4_init_affinity_hint(struct mlx4_dev *dev, int port, int eqn)
2614 {
2615         int requested_cpu = 0;
2616         struct mlx4_priv *priv = mlx4_priv(dev);
2617         struct mlx4_eq *eq;
2618         int off = 0;
2619         int i;
2620
2621         if (eqn > dev->caps.num_comp_vectors)
2622                 return -EINVAL;
2623
2624         for (i = 1; i < port; i++)
2625                 off += mlx4_get_eqs_per_port(dev, i);
2626
2627         requested_cpu = eqn - off - !!(eqn > MLX4_EQ_ASYNC);
2628
2629         /* Meaning EQs are shared, and this call comes from the second port */
2630         if (requested_cpu < 0)
2631                 return 0;
2632
2633         eq = &priv->eq_table.eq[eqn];
2634
2635         if (!zalloc_cpumask_var(&eq->affinity_mask, GFP_KERNEL))
2636                 return -ENOMEM;
2637
2638         cpumask_set_cpu(requested_cpu, eq->affinity_mask);
2639
2640         return 0;
2641 }
2642
2643 static void mlx4_enable_msi_x(struct mlx4_dev *dev)
2644 {
2645         struct mlx4_priv *priv = mlx4_priv(dev);
2646         struct msix_entry *entries;
2647         int i;
2648         int port = 0;
2649
2650         if (msi_x) {
2651                 int nreq = dev->caps.num_ports * num_online_cpus() + 1;
2652
2653                 nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs,
2654                              nreq);
2655
2656                 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL);
2657                 if (!entries)
2658                         goto no_msi;
2659
2660                 for (i = 0; i < nreq; ++i)
2661                         entries[i].entry = i;
2662
2663                 nreq = pci_enable_msix_range(dev->persist->pdev, entries, 2,
2664                                              nreq);
2665
2666                 if (nreq < 0 || nreq < MLX4_EQ_ASYNC) {
2667                         kfree(entries);
2668                         goto no_msi;
2669                 }
2670                 /* 1 is reserved for events (asyncrounous EQ) */
2671                 dev->caps.num_comp_vectors = nreq - 1;
2672
2673                 priv->eq_table.eq[MLX4_EQ_ASYNC].irq = entries[0].vector;
2674                 bitmap_zero(priv->eq_table.eq[MLX4_EQ_ASYNC].actv_ports.ports,
2675                             dev->caps.num_ports);
2676
2677                 for (i = 0; i < dev->caps.num_comp_vectors + 1; i++) {
2678                         if (i == MLX4_EQ_ASYNC)
2679                                 continue;
2680
2681                         priv->eq_table.eq[i].irq =
2682                                 entries[i + 1 - !!(i > MLX4_EQ_ASYNC)].vector;
2683
2684                         if (MLX4_IS_LEGACY_EQ_MODE(dev->caps)) {
2685                                 bitmap_fill(priv->eq_table.eq[i].actv_ports.ports,
2686                                             dev->caps.num_ports);
2687                                 /* We don't set affinity hint when there
2688                                  * aren't enough EQs
2689                                  */
2690                         } else {
2691                                 set_bit(port,
2692                                         priv->eq_table.eq[i].actv_ports.ports);
2693                                 if (mlx4_init_affinity_hint(dev, port + 1, i))
2694                                         mlx4_warn(dev, "Couldn't init hint cpumask for EQ %d\n",
2695                                                   i);
2696                         }
2697                         /* We divide the Eqs evenly between the two ports.
2698                          * (dev->caps.num_comp_vectors / dev->caps.num_ports)
2699                          * refers to the number of Eqs per port
2700                          * (i.e eqs_per_port). Theoretically, we would like to
2701                          * write something like (i + 1) % eqs_per_port == 0.
2702                          * However, since there's an asynchronous Eq, we have
2703                          * to skip over it by comparing this condition to
2704                          * !!((i + 1) > MLX4_EQ_ASYNC).
2705                          */
2706                         if ((dev->caps.num_comp_vectors > dev->caps.num_ports) &&
2707                             ((i + 1) %
2708                              (dev->caps.num_comp_vectors / dev->caps.num_ports)) ==
2709                             !!((i + 1) > MLX4_EQ_ASYNC))
2710                                 /* If dev->caps.num_comp_vectors < dev->caps.num_ports,
2711                                  * everything is shared anyway.
2712                                  */
2713                                 port++;
2714                 }
2715
2716                 dev->flags |= MLX4_FLAG_MSI_X;
2717
2718                 kfree(entries);
2719                 return;
2720         }
2721
2722 no_msi:
2723         dev->caps.num_comp_vectors = 1;
2724
2725         BUG_ON(MLX4_EQ_ASYNC >= 2);
2726         for (i = 0; i < 2; ++i) {
2727                 priv->eq_table.eq[i].irq = dev->persist->pdev->irq;
2728                 if (i != MLX4_EQ_ASYNC) {
2729                         bitmap_fill(priv->eq_table.eq[i].actv_ports.ports,
2730                                     dev->caps.num_ports);
2731                 }
2732         }
2733 }
2734
2735 static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
2736 {
2737         struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
2738         int err = 0;
2739
2740         info->dev = dev;
2741         info->port = port;
2742         if (!mlx4_is_slave(dev)) {
2743                 mlx4_init_mac_table(dev, &info->mac_table);
2744                 mlx4_init_vlan_table(dev, &info->vlan_table);
2745                 mlx4_init_roce_gid_table(dev, &info->gid_table);
2746                 info->base_qpn = mlx4_get_base_qpn(dev, port);
2747         }
2748
2749         sprintf(info->dev_name, "mlx4_port%d", port);
2750         info->port_attr.attr.name = info->dev_name;
2751         if (mlx4_is_mfunc(dev))
2752                 info->port_attr.attr.mode = S_IRUGO;
2753         else {
2754                 info->port_attr.attr.mode = S_IRUGO | S_IWUSR;
2755                 info->port_attr.store     = set_port_type;
2756         }
2757         info->port_attr.show      = show_port_type;
2758         sysfs_attr_init(&info->port_attr.attr);
2759
2760         err = device_create_file(&dev->persist->pdev->dev, &info->port_attr);
2761         if (err) {
2762                 mlx4_err(dev, "Failed to create file for port %d\n", port);
2763                 info->port = -1;
2764         }
2765
2766         sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port);
2767         info->port_mtu_attr.attr.name = info->dev_mtu_name;
2768         if (mlx4_is_mfunc(dev))
2769                 info->port_mtu_attr.attr.mode = S_IRUGO;
2770         else {
2771                 info->port_mtu_attr.attr.mode = S_IRUGO | S_IWUSR;
2772                 info->port_mtu_attr.store     = set_port_ib_mtu;
2773         }
2774         info->port_mtu_attr.show      = show_port_ib_mtu;
2775         sysfs_attr_init(&info->port_mtu_attr.attr);
2776
2777         err = device_create_file(&dev->persist->pdev->dev,
2778                                  &info->port_mtu_attr);
2779         if (err) {
2780                 mlx4_err(dev, "Failed to create mtu file for port %d\n", port);
2781                 device_remove_file(&info->dev->persist->pdev->dev,
2782                                    &info->port_attr);
2783                 info->port = -1;
2784         }
2785
2786         return err;
2787 }
2788
2789 static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
2790 {
2791         if (info->port < 0)
2792                 return;
2793
2794         device_remove_file(&info->dev->persist->pdev->dev, &info->port_attr);
2795         device_remove_file(&info->dev->persist->pdev->dev,
2796                            &info->port_mtu_attr);
2797 #ifdef CONFIG_RFS_ACCEL
2798         free_irq_cpu_rmap(info->rmap);
2799         info->rmap = NULL;
2800 #endif
2801 }
2802
2803 static int mlx4_init_steering(struct mlx4_dev *dev)
2804 {
2805         struct mlx4_priv *priv = mlx4_priv(dev);
2806         int num_entries = dev->caps.num_ports;
2807         int i, j;
2808
2809         priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL);
2810         if (!priv->steer)
2811                 return -ENOMEM;
2812
2813         for (i = 0; i < num_entries; i++)
2814                 for (j = 0; j < MLX4_NUM_STEERS; j++) {
2815                         INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]);
2816                         INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]);
2817                 }
2818         return 0;
2819 }
2820
2821 static void mlx4_clear_steering(struct mlx4_dev *dev)
2822 {
2823         struct mlx4_priv *priv = mlx4_priv(dev);
2824         struct mlx4_steer_index *entry, *tmp_entry;
2825         struct mlx4_promisc_qp *pqp, *tmp_pqp;
2826         int num_entries = dev->caps.num_ports;
2827         int i, j;
2828
2829         for (i = 0; i < num_entries; i++) {
2830                 for (j = 0; j < MLX4_NUM_STEERS; j++) {
2831                         list_for_each_entry_safe(pqp, tmp_pqp,
2832                                                  &priv->steer[i].promisc_qps[j],
2833                                                  list) {
2834                                 list_del(&pqp->list);
2835                                 kfree(pqp);
2836                         }
2837                         list_for_each_entry_safe(entry, tmp_entry,
2838                                                  &priv->steer[i].steer_entries[j],
2839                                                  list) {
2840                                 list_del(&entry->list);
2841                                 list_for_each_entry_safe(pqp, tmp_pqp,
2842                                                          &entry->duplicates,
2843                                                          list) {
2844                                         list_del(&pqp->list);
2845                                         kfree(pqp);
2846                                 }
2847                                 kfree(entry);
2848                         }
2849                 }
2850         }
2851         kfree(priv->steer);
2852 }
2853
2854 static int extended_func_num(struct pci_dev *pdev)
2855 {
2856         return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn);
2857 }
2858
2859 #define MLX4_OWNER_BASE 0x8069c
2860 #define MLX4_OWNER_SIZE 4
2861
2862 static int mlx4_get_ownership(struct mlx4_dev *dev)
2863 {
2864         void __iomem *owner;
2865         u32 ret;
2866
2867         if (pci_channel_offline(dev->persist->pdev))
2868                 return -EIO;
2869
2870         owner = ioremap(pci_resource_start(dev->persist->pdev, 0) +
2871                         MLX4_OWNER_BASE,
2872                         MLX4_OWNER_SIZE);
2873         if (!owner) {
2874                 mlx4_err(dev, "Failed to obtain ownership bit\n");
2875                 return -ENOMEM;
2876         }
2877
2878         ret = readl(owner);
2879         iounmap(owner);
2880         return (int) !!ret;
2881 }
2882
2883 static void mlx4_free_ownership(struct mlx4_dev *dev)
2884 {
2885         void __iomem *owner;
2886
2887         if (pci_channel_offline(dev->persist->pdev))
2888                 return;
2889
2890         owner = ioremap(pci_resource_start(dev->persist->pdev, 0) +
2891                         MLX4_OWNER_BASE,
2892                         MLX4_OWNER_SIZE);
2893         if (!owner) {
2894                 mlx4_err(dev, "Failed to obtain ownership bit\n");
2895                 return;
2896         }
2897         writel(0, owner);
2898         msleep(1000);
2899         iounmap(owner);
2900 }
2901
2902 #define SRIOV_VALID_STATE(flags) (!!((flags) & MLX4_FLAG_SRIOV) ==\
2903                                   !!((flags) & MLX4_FLAG_MASTER))
2904
2905 static u64 mlx4_enable_sriov(struct mlx4_dev *dev, struct pci_dev *pdev,
2906                              u8 total_vfs, int existing_vfs, int reset_flow)
2907 {
2908         u64 dev_flags = dev->flags;
2909         int err = 0;
2910
2911         if (reset_flow) {
2912                 dev->dev_vfs = kcalloc(total_vfs, sizeof(*dev->dev_vfs),
2913                                        GFP_KERNEL);
2914                 if (!dev->dev_vfs)
2915                         goto free_mem;
2916                 return dev_flags;
2917         }
2918
2919         atomic_inc(&pf_loading);
2920         if (dev->flags &  MLX4_FLAG_SRIOV) {
2921                 if (existing_vfs != total_vfs) {
2922                         mlx4_err(dev, "SR-IOV was already enabled, but with num_vfs (%d) different than requested (%d)\n",
2923                                  existing_vfs, total_vfs);
2924                         total_vfs = existing_vfs;
2925                 }
2926         }
2927
2928         dev->dev_vfs = kzalloc(total_vfs * sizeof(*dev->dev_vfs), GFP_KERNEL);
2929         if (NULL == dev->dev_vfs) {
2930                 mlx4_err(dev, "Failed to allocate memory for VFs\n");
2931                 goto disable_sriov;
2932         }
2933
2934         if (!(dev->flags &  MLX4_FLAG_SRIOV)) {
2935                 mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n", total_vfs);
2936                 err = pci_enable_sriov(pdev, total_vfs);
2937         }
2938         if (err) {
2939                 mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d)\n",
2940                          err);
2941                 goto disable_sriov;
2942         } else {
2943                 mlx4_warn(dev, "Running in master mode\n");
2944                 dev_flags |= MLX4_FLAG_SRIOV |
2945                         MLX4_FLAG_MASTER;
2946                 dev_flags &= ~MLX4_FLAG_SLAVE;
2947                 dev->persist->num_vfs = total_vfs;
2948         }
2949         return dev_flags;
2950
2951 disable_sriov:
2952         atomic_dec(&pf_loading);
2953 free_mem:
2954         dev->persist->num_vfs = 0;
2955         kfree(dev->dev_vfs);
2956         dev->dev_vfs = NULL;
2957         return dev_flags & ~MLX4_FLAG_MASTER;
2958 }
2959
2960 enum {
2961         MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64 = -1,
2962 };
2963
2964 static int mlx4_check_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
2965                               int *nvfs)
2966 {
2967         int requested_vfs = nvfs[0] + nvfs[1] + nvfs[2];
2968         /* Checking for 64 VFs as a limitation of CX2 */
2969         if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_80_VFS) &&
2970             requested_vfs >= 64) {
2971                 mlx4_err(dev, "Requested %d VFs, but FW does not support more than 64\n",
2972                          requested_vfs);
2973                 return MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64;
2974         }
2975         return 0;
2976 }
2977
2978 static int mlx4_load_one(struct pci_dev *pdev, int pci_dev_data,
2979                          int total_vfs, int *nvfs, struct mlx4_priv *priv,
2980                          int reset_flow)
2981 {
2982         struct mlx4_dev *dev;
2983         unsigned sum = 0;
2984         int err;
2985         int port;
2986         int i;
2987         struct mlx4_dev_cap *dev_cap = NULL;
2988         int existing_vfs = 0;
2989
2990         dev = &priv->dev;
2991
2992         INIT_LIST_HEAD(&priv->ctx_list);
2993         spin_lock_init(&priv->ctx_lock);
2994
2995         mutex_init(&priv->port_mutex);
2996         mutex_init(&priv->bond_mutex);
2997
2998         INIT_LIST_HEAD(&priv->pgdir_list);
2999         mutex_init(&priv->pgdir_mutex);
3000
3001         INIT_LIST_HEAD(&priv->bf_list);
3002         mutex_init(&priv->bf_mutex);
3003
3004         dev->rev_id = pdev->revision;
3005         dev->numa_node = dev_to_node(&pdev->dev);
3006
3007         /* Detect if this device is a virtual function */
3008         if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
3009                 mlx4_warn(dev, "Detected virtual function - running in slave mode\n");
3010                 dev->flags |= MLX4_FLAG_SLAVE;
3011         } else {
3012                 /* We reset the device and enable SRIOV only for physical
3013                  * devices.  Try to claim ownership on the device;
3014                  * if already taken, skip -- do not allow multiple PFs */
3015                 err = mlx4_get_ownership(dev);
3016                 if (err) {
3017                         if (err < 0)
3018                                 return err;
3019                         else {
3020                                 mlx4_warn(dev, "Multiple PFs not yet supported - Skipping PF\n");
3021                                 return -EINVAL;
3022                         }
3023                 }
3024
3025                 atomic_set(&priv->opreq_count, 0);
3026                 INIT_WORK(&priv->opreq_task, mlx4_opreq_action);
3027
3028                 /*
3029                  * Now reset the HCA before we touch the PCI capabilities or
3030                  * attempt a firmware command, since a boot ROM may have left
3031                  * the HCA in an undefined state.
3032                  */
3033                 err = mlx4_reset(dev);
3034                 if (err) {
3035                         mlx4_err(dev, "Failed to reset HCA, aborting\n");
3036                         goto err_sriov;
3037                 }
3038
3039                 if (total_vfs) {
3040                         dev->flags = MLX4_FLAG_MASTER;
3041                         existing_vfs = pci_num_vf(pdev);
3042                         if (existing_vfs)
3043                                 dev->flags |= MLX4_FLAG_SRIOV;
3044                         dev->persist->num_vfs = total_vfs;
3045                 }
3046         }
3047
3048         /* on load remove any previous indication of internal error,
3049          * device is up.
3050          */
3051         dev->persist->state = MLX4_DEVICE_STATE_UP;
3052
3053 slave_start:
3054         err = mlx4_cmd_init(dev);
3055         if (err) {
3056                 mlx4_err(dev, "Failed to init command interface, aborting\n");
3057                 goto err_sriov;
3058         }
3059
3060         /* In slave functions, the communication channel must be initialized
3061          * before posting commands. Also, init num_slaves before calling
3062          * mlx4_init_hca */
3063         if (mlx4_is_mfunc(dev)) {
3064                 if (mlx4_is_master(dev)) {
3065                         dev->num_slaves = MLX4_MAX_NUM_SLAVES;
3066
3067                 } else {
3068                         dev->num_slaves = 0;
3069                         err = mlx4_multi_func_init(dev);
3070                         if (err) {
3071                                 mlx4_err(dev, "Failed to init slave mfunc interface, aborting\n");
3072                                 goto err_cmd;
3073                         }
3074                 }
3075         }
3076
3077         err = mlx4_init_fw(dev);
3078         if (err) {
3079                 mlx4_err(dev, "Failed to init fw, aborting.\n");
3080                 goto err_mfunc;
3081         }
3082
3083         if (mlx4_is_master(dev)) {
3084                 /* when we hit the goto slave_start below, dev_cap already initialized */
3085                 if (!dev_cap) {
3086                         dev_cap = kzalloc(sizeof(*dev_cap), GFP_KERNEL);
3087
3088                         if (!dev_cap) {
3089                                 err = -ENOMEM;
3090                                 goto err_fw;
3091                         }
3092
3093                         err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
3094                         if (err) {
3095                                 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
3096                                 goto err_fw;
3097                         }
3098
3099                         if (mlx4_check_dev_cap(dev, dev_cap, nvfs))
3100                                 goto err_fw;
3101
3102                         if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) {
3103                                 u64 dev_flags = mlx4_enable_sriov(dev, pdev,
3104                                                                   total_vfs,
3105                                                                   existing_vfs,
3106                                                                   reset_flow);
3107
3108                                 mlx4_close_fw(dev);
3109                                 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
3110                                 dev->flags = dev_flags;
3111                                 if (!SRIOV_VALID_STATE(dev->flags)) {
3112                                         mlx4_err(dev, "Invalid SRIOV state\n");
3113                                         goto err_sriov;
3114                                 }
3115                                 err = mlx4_reset(dev);
3116                                 if (err) {
3117                                         mlx4_err(dev, "Failed to reset HCA, aborting.\n");
3118                                         goto err_sriov;
3119                                 }
3120                                 goto slave_start;
3121                         }
3122                 } else {
3123                         /* Legacy mode FW requires SRIOV to be enabled before
3124                          * doing QUERY_DEV_CAP, since max_eq's value is different if
3125                          * SRIOV is enabled.
3126                          */
3127                         memset(dev_cap, 0, sizeof(*dev_cap));
3128                         err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
3129                         if (err) {
3130                                 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
3131                                 goto err_fw;
3132                         }
3133
3134                         if (mlx4_check_dev_cap(dev, dev_cap, nvfs))
3135                                 goto err_fw;
3136                 }
3137         }
3138
3139         err = mlx4_init_hca(dev);
3140         if (err) {
3141                 if (err == -EACCES) {
3142                         /* Not primary Physical function
3143                          * Running in slave mode */
3144                         mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
3145                         /* We're not a PF */
3146                         if (dev->flags & MLX4_FLAG_SRIOV) {
3147                                 if (!existing_vfs)
3148                                         pci_disable_sriov(pdev);
3149                                 if (mlx4_is_master(dev) && !reset_flow)
3150                                         atomic_dec(&pf_loading);
3151                                 dev->flags &= ~MLX4_FLAG_SRIOV;
3152                         }
3153                         if (!mlx4_is_slave(dev))
3154                                 mlx4_free_ownership(dev);
3155                         dev->flags |= MLX4_FLAG_SLAVE;
3156                         dev->flags &= ~MLX4_FLAG_MASTER;
3157                         goto slave_start;
3158                 } else
3159                         goto err_fw;
3160         }
3161
3162         if (mlx4_is_master(dev) && (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) {
3163                 u64 dev_flags = mlx4_enable_sriov(dev, pdev, total_vfs,
3164                                                   existing_vfs, reset_flow);
3165
3166                 if ((dev->flags ^ dev_flags) & (MLX4_FLAG_MASTER | MLX4_FLAG_SLAVE)) {
3167                         mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_VHCR);
3168                         dev->flags = dev_flags;
3169                         err = mlx4_cmd_init(dev);
3170                         if (err) {
3171                                 /* Only VHCR is cleaned up, so could still
3172                                  * send FW commands
3173                                  */
3174                                 mlx4_err(dev, "Failed to init VHCR command interface, aborting\n");
3175                                 goto err_close;
3176                         }
3177                 } else {
3178                         dev->flags = dev_flags;
3179                 }
3180
3181                 if (!SRIOV_VALID_STATE(dev->flags)) {
3182                         mlx4_err(dev, "Invalid SRIOV state\n");
3183                         goto err_close;
3184                 }
3185         }
3186
3187         /* check if the device is functioning at its maximum possible speed.
3188          * No return code for this call, just warn the user in case of PCI
3189          * express device capabilities are under-satisfied by the bus.
3190          */
3191         if (!mlx4_is_slave(dev))
3192                 mlx4_check_pcie_caps(dev);
3193
3194         /* In master functions, the communication channel must be initialized
3195          * after obtaining its address from fw */
3196         if (mlx4_is_master(dev)) {
3197                 if (dev->caps.num_ports < 2 &&
3198                     num_vfs_argc > 1) {
3199                         err = -EINVAL;
3200                         mlx4_err(dev,
3201                                  "Error: Trying to configure VFs on port 2, but HCA has only %d physical ports\n",
3202                                  dev->caps.num_ports);
3203                         goto err_close;
3204                 }
3205                 memcpy(dev->persist->nvfs, nvfs, sizeof(dev->persist->nvfs));
3206
3207                 for (i = 0;
3208                      i < sizeof(dev->persist->nvfs)/
3209                      sizeof(dev->persist->nvfs[0]); i++) {
3210                         unsigned j;
3211
3212                         for (j = 0; j < dev->persist->nvfs[i]; ++sum, ++j) {
3213                                 dev->dev_vfs[sum].min_port = i < 2 ? i + 1 : 1;
3214                                 dev->dev_vfs[sum].n_ports = i < 2 ? 1 :
3215                                         dev->caps.num_ports;
3216                         }
3217                 }
3218
3219                 /* In master functions, the communication channel
3220                  * must be initialized after obtaining its address from fw
3221                  */
3222                 err = mlx4_multi_func_init(dev);
3223                 if (err) {
3224                         mlx4_err(dev, "Failed to init master mfunc interface, aborting.\n");
3225                         goto err_close;
3226                 }
3227         }
3228
3229         err = mlx4_alloc_eq_table(dev);
3230         if (err)
3231                 goto err_master_mfunc;
3232
3233         bitmap_zero(priv->msix_ctl.pool_bm, MAX_MSIX);
3234         mutex_init(&priv->msix_ctl.pool_lock);
3235
3236         mlx4_enable_msi_x(dev);
3237         if ((mlx4_is_mfunc(dev)) &&
3238             !(dev->flags & MLX4_FLAG_MSI_X)) {
3239                 err = -ENOSYS;
3240                 mlx4_err(dev, "INTx is not supported in multi-function mode, aborting\n");
3241                 goto err_free_eq;
3242         }
3243
3244         if (!mlx4_is_slave(dev)) {
3245                 err = mlx4_init_steering(dev);
3246                 if (err)
3247                         goto err_disable_msix;
3248         }
3249
3250         err = mlx4_setup_hca(dev);
3251         if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) &&
3252             !mlx4_is_mfunc(dev)) {
3253                 dev->flags &= ~MLX4_FLAG_MSI_X;
3254                 dev->caps.num_comp_vectors = 1;
3255                 pci_disable_msix(pdev);
3256                 err = mlx4_setup_hca(dev);
3257         }
3258
3259         if (err)
3260                 goto err_steer;
3261
3262         mlx4_init_quotas(dev);
3263         /* When PF resources are ready arm its comm channel to enable
3264          * getting commands
3265          */
3266         if (mlx4_is_master(dev)) {
3267                 err = mlx4_ARM_COMM_CHANNEL(dev);
3268                 if (err) {
3269                         mlx4_err(dev, " Failed to arm comm channel eq: %x\n",
3270                                  err);
3271                         goto err_steer;
3272                 }
3273         }
3274
3275         for (port = 1; port <= dev->caps.num_ports; port++) {
3276                 err = mlx4_init_port_info(dev, port);
3277                 if (err)
3278                         goto err_port;
3279         }
3280
3281         priv->v2p.port1 = 1;
3282         priv->v2p.port2 = 2;
3283
3284         err = mlx4_register_device(dev);
3285         if (err)
3286                 goto err_port;
3287
3288         mlx4_request_modules(dev);
3289
3290         mlx4_sense_init(dev);
3291         mlx4_start_sense(dev);
3292
3293         priv->removed = 0;
3294
3295         if (mlx4_is_master(dev) && dev->persist->num_vfs && !reset_flow)
3296                 atomic_dec(&pf_loading);
3297
3298         kfree(dev_cap);
3299         return 0;
3300
3301 err_port:
3302         for (--port; port >= 1; --port)
3303                 mlx4_cleanup_port_info(&priv->port[port]);
3304
3305         mlx4_cleanup_default_counters(dev);
3306         if (!mlx4_is_slave(dev))
3307                 mlx4_cleanup_counters_table(dev);
3308         mlx4_cleanup_qp_table(dev);
3309         mlx4_cleanup_srq_table(dev);
3310         mlx4_cleanup_cq_table(dev);
3311         mlx4_cmd_use_polling(dev);
3312         mlx4_cleanup_eq_table(dev);
3313         mlx4_cleanup_mcg_table(dev);
3314         mlx4_cleanup_mr_table(dev);
3315         mlx4_cleanup_xrcd_table(dev);
3316         mlx4_cleanup_pd_table(dev);
3317         mlx4_cleanup_uar_table(dev);
3318
3319 err_steer:
3320         if (!mlx4_is_slave(dev))
3321                 mlx4_clear_steering(dev);
3322
3323 err_disable_msix:
3324         if (dev->flags & MLX4_FLAG_MSI_X)
3325                 pci_disable_msix(pdev);
3326
3327 err_free_eq:
3328         mlx4_free_eq_table(dev);
3329
3330 err_master_mfunc:
3331         if (mlx4_is_master(dev)) {
3332                 mlx4_free_resource_tracker(dev, RES_TR_FREE_STRUCTS_ONLY);
3333                 mlx4_multi_func_cleanup(dev);
3334         }
3335
3336         if (mlx4_is_slave(dev)) {
3337                 kfree(dev->caps.qp0_qkey);
3338                 kfree(dev->caps.qp0_tunnel);
3339                 kfree(dev->caps.qp0_proxy);
3340                 kfree(dev->caps.qp1_tunnel);
3341                 kfree(dev->caps.qp1_proxy);
3342         }
3343
3344 err_close:
3345         mlx4_close_hca(dev);
3346
3347 err_fw:
3348         mlx4_close_fw(dev);
3349
3350 err_mfunc:
3351         if (mlx4_is_slave(dev))
3352                 mlx4_multi_func_cleanup(dev);
3353
3354 err_cmd:
3355         mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
3356
3357 err_sriov:
3358         if (dev->flags & MLX4_FLAG_SRIOV && !existing_vfs) {
3359                 pci_disable_sriov(pdev);
3360                 dev->flags &= ~MLX4_FLAG_SRIOV;
3361         }
3362
3363         if (mlx4_is_master(dev) && dev->persist->num_vfs && !reset_flow)
3364                 atomic_dec(&pf_loading);
3365
3366         kfree(priv->dev.dev_vfs);
3367
3368         if (!mlx4_is_slave(dev))
3369                 mlx4_free_ownership(dev);
3370
3371         kfree(dev_cap);
3372         return err;
3373 }
3374
3375 static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data,
3376                            struct mlx4_priv *priv)
3377 {
3378         int err;
3379         int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
3380         int prb_vf[MLX4_MAX_PORTS + 1] = {0, 0, 0};
3381         const int param_map[MLX4_MAX_PORTS + 1][MLX4_MAX_PORTS + 1] = {
3382                 {2, 0, 0}, {0, 1, 2}, {0, 1, 2} };
3383         unsigned total_vfs = 0;
3384         unsigned int i;
3385
3386         pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev));
3387
3388         err = pci_enable_device(pdev);
3389         if (err) {
3390                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
3391                 return err;
3392         }
3393
3394         /* Due to requirement that all VFs and the PF are *guaranteed* 2 MACS
3395          * per port, we must limit the number of VFs to 63 (since their are
3396          * 128 MACs)
3397          */
3398         for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]) && i < num_vfs_argc;
3399              total_vfs += nvfs[param_map[num_vfs_argc - 1][i]], i++) {
3400                 nvfs[param_map[num_vfs_argc - 1][i]] = num_vfs[i];
3401                 if (nvfs[i] < 0) {
3402                         dev_err(&pdev->dev, "num_vfs module parameter cannot be negative\n");
3403                         err = -EINVAL;
3404                         goto err_disable_pdev;
3405                 }
3406         }
3407         for (i = 0; i < sizeof(prb_vf)/sizeof(prb_vf[0]) && i < probe_vfs_argc;
3408              i++) {
3409                 prb_vf[param_map[probe_vfs_argc - 1][i]] = probe_vf[i];
3410                 if (prb_vf[i] < 0 || prb_vf[i] > nvfs[i]) {
3411                         dev_err(&pdev->dev, "probe_vf module parameter cannot be negative or greater than num_vfs\n");
3412                         err = -EINVAL;
3413                         goto err_disable_pdev;
3414                 }
3415         }
3416         if (total_vfs >= MLX4_MAX_NUM_VF) {
3417                 dev_err(&pdev->dev,
3418                         "Requested more VF's (%d) than allowed (%d)\n",
3419                         total_vfs, MLX4_MAX_NUM_VF - 1);
3420                 err = -EINVAL;
3421                 goto err_disable_pdev;
3422         }
3423
3424         for (i = 0; i < MLX4_MAX_PORTS; i++) {
3425                 if (nvfs[i] + nvfs[2] >= MLX4_MAX_NUM_VF_P_PORT) {
3426                         dev_err(&pdev->dev,
3427                                 "Requested more VF's (%d) for port (%d) than allowed (%d)\n",
3428                                 nvfs[i] + nvfs[2], i + 1,
3429                                 MLX4_MAX_NUM_VF_P_PORT - 1);
3430                         err = -EINVAL;
3431                         goto err_disable_pdev;
3432                 }
3433         }
3434
3435         /* Check for BARs. */
3436         if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) &&
3437             !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
3438                 dev_err(&pdev->dev, "Missing DCS, aborting (driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n",
3439                         pci_dev_data, pci_resource_flags(pdev, 0));
3440                 err = -ENODEV;
3441                 goto err_disable_pdev;
3442         }
3443         if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
3444                 dev_err(&pdev->dev, "Missing UAR, aborting\n");
3445                 err = -ENODEV;
3446                 goto err_disable_pdev;
3447         }
3448
3449         err = pci_request_regions(pdev, DRV_NAME);
3450         if (err) {
3451                 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
3452                 goto err_disable_pdev;
3453         }
3454
3455         pci_set_master(pdev);
3456
3457         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
3458         if (err) {
3459                 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
3460                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3461                 if (err) {
3462                         dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
3463                         goto err_release_regions;
3464                 }
3465         }
3466         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
3467         if (err) {
3468                 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
3469                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3470                 if (err) {
3471                         dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, aborting\n");
3472                         goto err_release_regions;
3473                 }
3474         }
3475
3476         /* Allow large DMA segments, up to the firmware limit of 1 GB */
3477         dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024);
3478         /* Detect if this device is a virtual function */
3479         if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
3480                 /* When acting as pf, we normally skip vfs unless explicitly
3481                  * requested to probe them.
3482                  */
3483                 if (total_vfs) {
3484                         unsigned vfs_offset = 0;
3485
3486                         for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]) &&
3487                              vfs_offset + nvfs[i] < extended_func_num(pdev);
3488                              vfs_offset += nvfs[i], i++)
3489                                 ;
3490                         if (i == sizeof(nvfs)/sizeof(nvfs[0])) {
3491                                 err = -ENODEV;
3492                                 goto err_release_regions;
3493                         }
3494                         if ((extended_func_num(pdev) - vfs_offset)
3495                             > prb_vf[i]) {
3496                                 dev_warn(&pdev->dev, "Skipping virtual function:%d\n",
3497                                          extended_func_num(pdev));
3498                                 err = -ENODEV;
3499                                 goto err_release_regions;
3500                         }
3501                 }
3502         }
3503
3504         err = mlx4_catas_init(&priv->dev);
3505         if (err)
3506                 goto err_release_regions;
3507
3508         err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv, 0);
3509         if (err)
3510                 goto err_catas;
3511
3512         return 0;
3513
3514 err_catas:
3515         mlx4_catas_end(&priv->dev);
3516
3517 err_release_regions:
3518         pci_release_regions(pdev);
3519
3520 err_disable_pdev:
3521         pci_disable_device(pdev);
3522         pci_set_drvdata(pdev, NULL);
3523         return err;
3524 }
3525
3526 static int mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
3527 {
3528         struct mlx4_priv *priv;
3529         struct mlx4_dev *dev;
3530         int ret;
3531
3532         printk_once(KERN_INFO "%s", mlx4_version);
3533
3534         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
3535         if (!priv)
3536                 return -ENOMEM;
3537
3538         dev       = &priv->dev;
3539         dev->persist = kzalloc(sizeof(*dev->persist), GFP_KERNEL);
3540         if (!dev->persist) {
3541                 kfree(priv);
3542                 return -ENOMEM;
3543         }
3544         dev->persist->pdev = pdev;
3545         dev->persist->dev = dev;
3546         pci_set_drvdata(pdev, dev->persist);
3547         priv->pci_dev_data = id->driver_data;
3548         mutex_init(&dev->persist->device_state_mutex);
3549         mutex_init(&dev->persist->interface_state_mutex);
3550
3551         ret =  __mlx4_init_one(pdev, id->driver_data, priv);
3552         if (ret) {
3553                 kfree(dev->persist);
3554                 kfree(priv);
3555         } else {
3556                 pci_save_state(pdev);
3557         }
3558
3559         return ret;
3560 }
3561
3562 static void mlx4_clean_dev(struct mlx4_dev *dev)
3563 {
3564         struct mlx4_dev_persistent *persist = dev->persist;
3565         struct mlx4_priv *priv = mlx4_priv(dev);
3566         unsigned long   flags = (dev->flags & RESET_PERSIST_MASK_FLAGS);
3567
3568         memset(priv, 0, sizeof(*priv));
3569         priv->dev.persist = persist;
3570         priv->dev.flags = flags;
3571 }
3572
3573 static void mlx4_unload_one(struct pci_dev *pdev)
3574 {
3575         struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3576         struct mlx4_dev  *dev  = persist->dev;
3577         struct mlx4_priv *priv = mlx4_priv(dev);
3578         int               pci_dev_data;
3579         int p, i;
3580
3581         if (priv->removed)
3582                 return;
3583
3584         /* saving current ports type for further use */
3585         for (i = 0; i < dev->caps.num_ports; i++) {
3586                 dev->persist->curr_port_type[i] = dev->caps.port_type[i + 1];
3587                 dev->persist->curr_port_poss_type[i] = dev->caps.
3588                                                        possible_type[i + 1];
3589         }
3590
3591         pci_dev_data = priv->pci_dev_data;
3592
3593         mlx4_stop_sense(dev);
3594         mlx4_unregister_device(dev);
3595
3596         for (p = 1; p <= dev->caps.num_ports; p++) {
3597                 mlx4_cleanup_port_info(&priv->port[p]);
3598                 mlx4_CLOSE_PORT(dev, p);
3599         }
3600
3601         if (mlx4_is_master(dev))
3602                 mlx4_free_resource_tracker(dev,
3603                                            RES_TR_FREE_SLAVES_ONLY);
3604
3605         mlx4_cleanup_default_counters(dev);
3606         if (!mlx4_is_slave(dev))
3607                 mlx4_cleanup_counters_table(dev);
3608         mlx4_cleanup_qp_table(dev);
3609         mlx4_cleanup_srq_table(dev);
3610         mlx4_cleanup_cq_table(dev);
3611         mlx4_cmd_use_polling(dev);
3612         mlx4_cleanup_eq_table(dev);
3613         mlx4_cleanup_mcg_table(dev);
3614         mlx4_cleanup_mr_table(dev);
3615         mlx4_cleanup_xrcd_table(dev);
3616         mlx4_cleanup_pd_table(dev);
3617
3618         if (mlx4_is_master(dev))
3619                 mlx4_free_resource_tracker(dev,
3620                                            RES_TR_FREE_STRUCTS_ONLY);
3621
3622         iounmap(priv->kar);
3623         mlx4_uar_free(dev, &priv->driver_uar);
3624         mlx4_cleanup_uar_table(dev);
3625         if (!mlx4_is_slave(dev))
3626                 mlx4_clear_steering(dev);
3627         mlx4_free_eq_table(dev);
3628         if (mlx4_is_master(dev))
3629                 mlx4_multi_func_cleanup(dev);
3630         mlx4_close_hca(dev);
3631         mlx4_close_fw(dev);
3632         if (mlx4_is_slave(dev))
3633                 mlx4_multi_func_cleanup(dev);
3634         mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
3635
3636         if (dev->flags & MLX4_FLAG_MSI_X)
3637                 pci_disable_msix(pdev);
3638
3639         if (!mlx4_is_slave(dev))
3640                 mlx4_free_ownership(dev);
3641
3642         kfree(dev->caps.qp0_qkey);
3643         kfree(dev->caps.qp0_tunnel);
3644         kfree(dev->caps.qp0_proxy);
3645         kfree(dev->caps.qp1_tunnel);
3646         kfree(dev->caps.qp1_proxy);
3647         kfree(dev->dev_vfs);
3648
3649         mlx4_clean_dev(dev);
3650         priv->pci_dev_data = pci_dev_data;
3651         priv->removed = 1;
3652 }
3653
3654 static void mlx4_remove_one(struct pci_dev *pdev)
3655 {
3656         struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3657         struct mlx4_dev  *dev  = persist->dev;
3658         struct mlx4_priv *priv = mlx4_priv(dev);
3659         int active_vfs = 0;
3660
3661         mutex_lock(&persist->interface_state_mutex);
3662         persist->interface_state |= MLX4_INTERFACE_STATE_DELETION;
3663         mutex_unlock(&persist->interface_state_mutex);
3664
3665         /* Disabling SR-IOV is not allowed while there are active vf's */
3666         if (mlx4_is_master(dev) && dev->flags & MLX4_FLAG_SRIOV) {
3667                 active_vfs = mlx4_how_many_lives_vf(dev);
3668                 if (active_vfs) {
3669                         pr_warn("Removing PF when there are active VF's !!\n");
3670                         pr_warn("Will not disable SR-IOV.\n");
3671                 }
3672         }
3673
3674         /* device marked to be under deletion running now without the lock
3675          * letting other tasks to be terminated
3676          */
3677         if (persist->interface_state & MLX4_INTERFACE_STATE_UP)
3678                 mlx4_unload_one(pdev);
3679         else
3680                 mlx4_info(dev, "%s: interface is down\n", __func__);
3681         mlx4_catas_end(dev);
3682         if (dev->flags & MLX4_FLAG_SRIOV && !active_vfs) {
3683                 mlx4_warn(dev, "Disabling SR-IOV\n");
3684                 pci_disable_sriov(pdev);
3685         }
3686
3687         pci_release_regions(pdev);
3688         pci_disable_device(pdev);
3689         kfree(dev->persist);
3690         kfree(priv);
3691         pci_set_drvdata(pdev, NULL);
3692 }
3693
3694 static int restore_current_port_types(struct mlx4_dev *dev,
3695                                       enum mlx4_port_type *types,
3696                                       enum mlx4_port_type *poss_types)
3697 {
3698         struct mlx4_priv *priv = mlx4_priv(dev);
3699         int err, i;
3700
3701         mlx4_stop_sense(dev);
3702
3703         mutex_lock(&priv->port_mutex);
3704         for (i = 0; i < dev->caps.num_ports; i++)
3705                 dev->caps.possible_type[i + 1] = poss_types[i];
3706         err = mlx4_change_port_types(dev, types);
3707         mlx4_start_sense(dev);
3708         mutex_unlock(&priv->port_mutex);
3709
3710         return err;
3711 }
3712
3713 int mlx4_restart_one(struct pci_dev *pdev)
3714 {
3715         struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3716         struct mlx4_dev  *dev  = persist->dev;
3717         struct mlx4_priv *priv = mlx4_priv(dev);
3718         int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
3719         int pci_dev_data, err, total_vfs;
3720
3721         pci_dev_data = priv->pci_dev_data;
3722         total_vfs = dev->persist->num_vfs;
3723         memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs));
3724
3725         mlx4_unload_one(pdev);
3726         err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv, 1);
3727         if (err) {
3728                 mlx4_err(dev, "%s: ERROR: mlx4_load_one failed, pci_name=%s, err=%d\n",
3729                          __func__, pci_name(pdev), err);
3730                 return err;
3731         }
3732
3733         err = restore_current_port_types(dev, dev->persist->curr_port_type,
3734                                          dev->persist->curr_port_poss_type);
3735         if (err)
3736                 mlx4_err(dev, "could not restore original port types (%d)\n",
3737                          err);
3738
3739         return err;
3740 }
3741
3742 static const struct pci_device_id mlx4_pci_table[] = {
3743         /* MT25408 "Hermon" SDR */
3744         { PCI_VDEVICE(MELLANOX, 0x6340), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3745         /* MT25408 "Hermon" DDR */
3746         { PCI_VDEVICE(MELLANOX, 0x634a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3747         /* MT25408 "Hermon" QDR */
3748         { PCI_VDEVICE(MELLANOX, 0x6354), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3749         /* MT25408 "Hermon" DDR PCIe gen2 */
3750         { PCI_VDEVICE(MELLANOX, 0x6732), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3751         /* MT25408 "Hermon" QDR PCIe gen2 */
3752         { PCI_VDEVICE(MELLANOX, 0x673c), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3753         /* MT25408 "Hermon" EN 10GigE */
3754         { PCI_VDEVICE(MELLANOX, 0x6368), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3755         /* MT25408 "Hermon" EN 10GigE PCIe gen2 */
3756         { PCI_VDEVICE(MELLANOX, 0x6750), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3757         /* MT25458 ConnectX EN 10GBASE-T 10GigE */
3758         { PCI_VDEVICE(MELLANOX, 0x6372), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3759         /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */
3760         { PCI_VDEVICE(MELLANOX, 0x675a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3761         /* MT26468 ConnectX EN 10GigE PCIe gen2*/
3762         { PCI_VDEVICE(MELLANOX, 0x6764), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3763         /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */
3764         { PCI_VDEVICE(MELLANOX, 0x6746), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3765         /* MT26478 ConnectX2 40GigE PCIe gen2 */
3766         { PCI_VDEVICE(MELLANOX, 0x676e), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3767         /* MT25400 Family [ConnectX-2 Virtual Function] */
3768         { PCI_VDEVICE(MELLANOX, 0x1002), MLX4_PCI_DEV_IS_VF },
3769         /* MT27500 Family [ConnectX-3] */
3770         { PCI_VDEVICE(MELLANOX, 0x1003), 0 },
3771         /* MT27500 Family [ConnectX-3 Virtual Function] */
3772         { PCI_VDEVICE(MELLANOX, 0x1004), MLX4_PCI_DEV_IS_VF },
3773         { PCI_VDEVICE(MELLANOX, 0x1005), 0 }, /* MT27510 Family */
3774         { PCI_VDEVICE(MELLANOX, 0x1006), 0 }, /* MT27511 Family */
3775         { PCI_VDEVICE(MELLANOX, 0x1007), 0 }, /* MT27520 Family */
3776         { PCI_VDEVICE(MELLANOX, 0x1008), 0 }, /* MT27521 Family */
3777         { PCI_VDEVICE(MELLANOX, 0x1009), 0 }, /* MT27530 Family */
3778         { PCI_VDEVICE(MELLANOX, 0x100a), 0 }, /* MT27531 Family */
3779         { PCI_VDEVICE(MELLANOX, 0x100b), 0 }, /* MT27540 Family */
3780         { PCI_VDEVICE(MELLANOX, 0x100c), 0 }, /* MT27541 Family */
3781         { PCI_VDEVICE(MELLANOX, 0x100d), 0 }, /* MT27550 Family */
3782         { PCI_VDEVICE(MELLANOX, 0x100e), 0 }, /* MT27551 Family */
3783         { PCI_VDEVICE(MELLANOX, 0x100f), 0 }, /* MT27560 Family */
3784         { PCI_VDEVICE(MELLANOX, 0x1010), 0 }, /* MT27561 Family */
3785         { 0, }
3786 };
3787
3788 MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
3789
3790 static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev,
3791                                               pci_channel_state_t state)
3792 {
3793         struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3794
3795         mlx4_err(persist->dev, "mlx4_pci_err_detected was called\n");
3796         mlx4_enter_error_state(persist);
3797
3798         mutex_lock(&persist->interface_state_mutex);
3799         if (persist->interface_state & MLX4_INTERFACE_STATE_UP)
3800                 mlx4_unload_one(pdev);
3801
3802         mutex_unlock(&persist->interface_state_mutex);
3803         if (state == pci_channel_io_perm_failure)
3804                 return PCI_ERS_RESULT_DISCONNECT;
3805
3806         pci_disable_device(pdev);
3807         return PCI_ERS_RESULT_NEED_RESET;
3808 }
3809
3810 static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev)
3811 {
3812         struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3813         struct mlx4_dev  *dev  = persist->dev;
3814         struct mlx4_priv *priv = mlx4_priv(dev);
3815         int               ret;
3816         int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
3817         int total_vfs;
3818
3819         mlx4_err(dev, "mlx4_pci_slot_reset was called\n");
3820         ret = pci_enable_device(pdev);
3821         if (ret) {
3822                 mlx4_err(dev, "Can not re-enable device, ret=%d\n", ret);
3823                 return PCI_ERS_RESULT_DISCONNECT;
3824         }
3825
3826         pci_set_master(pdev);
3827         pci_restore_state(pdev);
3828         pci_save_state(pdev);
3829
3830         total_vfs = dev->persist->num_vfs;
3831         memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs));
3832
3833         mutex_lock(&persist->interface_state_mutex);
3834         if (!(persist->interface_state & MLX4_INTERFACE_STATE_UP)) {
3835                 ret = mlx4_load_one(pdev, priv->pci_dev_data, total_vfs, nvfs,
3836                                     priv, 1);
3837                 if (ret) {
3838                         mlx4_err(dev, "%s: mlx4_load_one failed, ret=%d\n",
3839                                  __func__,  ret);
3840                         goto end;
3841                 }
3842
3843                 ret = restore_current_port_types(dev, dev->persist->
3844                                                  curr_port_type, dev->persist->
3845                                                  curr_port_poss_type);
3846                 if (ret)
3847                         mlx4_err(dev, "could not restore original port types (%d)\n", ret);
3848         }
3849 end:
3850         mutex_unlock(&persist->interface_state_mutex);
3851
3852         return ret ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
3853 }
3854
3855 static void mlx4_shutdown(struct pci_dev *pdev)
3856 {
3857         struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3858
3859         mlx4_info(persist->dev, "mlx4_shutdown was called\n");
3860         mutex_lock(&persist->interface_state_mutex);
3861         if (persist->interface_state & MLX4_INTERFACE_STATE_UP)
3862                 mlx4_unload_one(pdev);
3863         mutex_unlock(&persist->interface_state_mutex);
3864 }
3865
3866 static const struct pci_error_handlers mlx4_err_handler = {
3867         .error_detected = mlx4_pci_err_detected,
3868         .slot_reset     = mlx4_pci_slot_reset,
3869 };
3870
3871 static struct pci_driver mlx4_driver = {
3872         .name           = DRV_NAME,
3873         .id_table       = mlx4_pci_table,
3874         .probe          = mlx4_init_one,
3875         .shutdown       = mlx4_shutdown,
3876         .remove         = mlx4_remove_one,
3877         .err_handler    = &mlx4_err_handler,
3878 };
3879
3880 static int __init mlx4_verify_params(void)
3881 {
3882         if ((log_num_mac < 0) || (log_num_mac > 7)) {
3883                 pr_warn("mlx4_core: bad num_mac: %d\n", log_num_mac);
3884                 return -1;
3885         }
3886
3887         if (log_num_vlan != 0)
3888                 pr_warn("mlx4_core: log_num_vlan - obsolete module param, using %d\n",
3889                         MLX4_LOG_NUM_VLANS);
3890
3891         if (use_prio != 0)
3892                 pr_warn("mlx4_core: use_prio - obsolete module param, ignored\n");
3893
3894         if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) {
3895                 pr_warn("mlx4_core: bad log_mtts_per_seg: %d\n",
3896                         log_mtts_per_seg);
3897                 return -1;
3898         }
3899
3900         /* Check if module param for ports type has legal combination */
3901         if (port_type_array[0] == false && port_type_array[1] == true) {
3902                 pr_warn("Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n");
3903                 port_type_array[0] = true;
3904         }
3905
3906         if (mlx4_log_num_mgm_entry_size < -7 ||
3907             (mlx4_log_num_mgm_entry_size > 0 &&
3908              (mlx4_log_num_mgm_entry_size < MLX4_MIN_MGM_LOG_ENTRY_SIZE ||
3909               mlx4_log_num_mgm_entry_size > MLX4_MAX_MGM_LOG_ENTRY_SIZE))) {
3910                 pr_warn("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not in legal range (-7..0 or %d..%d)\n",
3911                         mlx4_log_num_mgm_entry_size,
3912                         MLX4_MIN_MGM_LOG_ENTRY_SIZE,
3913                         MLX4_MAX_MGM_LOG_ENTRY_SIZE);
3914                 return -1;
3915         }
3916
3917         return 0;
3918 }
3919
3920 static int __init mlx4_init(void)
3921 {
3922         int ret;
3923
3924         if (mlx4_verify_params())
3925                 return -EINVAL;
3926
3927
3928         mlx4_wq = create_singlethread_workqueue("mlx4");
3929         if (!mlx4_wq)
3930                 return -ENOMEM;
3931
3932         ret = pci_register_driver(&mlx4_driver);
3933         if (ret < 0)
3934                 destroy_workqueue(mlx4_wq);
3935         return ret < 0 ? ret : 0;
3936 }
3937
3938 static void __exit mlx4_cleanup(void)
3939 {
3940         pci_unregister_driver(&mlx4_driver);
3941         destroy_workqueue(mlx4_wq);
3942 }
3943
3944 module_init(mlx4_init);
3945 module_exit(mlx4_cleanup);