drivers/iommu/arm-smmu.c

   1 /*
   2  * IOMMU API for ARM architected SMMU implementations.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program; if not, write to the Free Software
  15  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  16  *
  17  * Copyright (C) 2013 ARM Limited
  18  *
  19  * Author: Will Deacon <will.deacon@arm.com>
  20  *
  21  * This driver currently supports:
  22  *      - SMMUv1 and v2 implementations
  23  *      - Stream-matching and stream-indexing
  24  *      - v7/v8 long-descriptor format
  25  *      - Non-secure access to the SMMU
  26  *      - Context fault reporting
  27  */
  28
  29 #define pr_fmt(fmt) "arm-smmu: " fmt
  30
  31 #include <linux/delay.h>
  32 #include <linux/dma-mapping.h>
  33 #include <linux/err.h>
  34 #include <linux/interrupt.h>
  35 #include <linux/io.h>
  36 #include <linux/iommu.h>
  37 #include <linux/iopoll.h>
  38 #include <linux/module.h>
  39 #include <linux/of.h>
  40 #include <linux/of_address.h>
  41 #include <linux/pci.h>
  42 #include <linux/platform_device.h>
  43 #include <linux/slab.h>
  44 #include <linux/spinlock.h>
  45
  46 #include <linux/amba/bus.h>
  47
  48 #include "io-pgtable.h"
  49
  50 /* Maximum number of stream IDs assigned to a single device */
  51 #define MAX_MASTER_STREAMIDS            MAX_PHANDLE_ARGS
  52
  53 /* Maximum number of context banks per SMMU */
  54 #define ARM_SMMU_MAX_CBS                128
  55
  56 /* Maximum number of mapping groups per SMMU */
  57 #define ARM_SMMU_MAX_SMRS               128
  58
  59 /* SMMU global address space */
  60 #define ARM_SMMU_GR0(smmu)              ((smmu)->base)
  61 #define ARM_SMMU_GR1(smmu)              ((smmu)->base + (1 << (smmu)->pgshift))
  62
  63 /*
  64  * SMMU global address space with conditional offset to access secure
  65  * aliases of non-secure registers (e.g. nsCR0: 0x400, nsGFSR: 0x448,
  66  * nsGFSYNR0: 0x450)
  67  */
  68 #define ARM_SMMU_GR0_NS(smmu)                                           \
  69         ((smmu)->base +                                                 \
  70                 ((smmu->options & ARM_SMMU_OPT_SECURE_CFG_ACCESS)       \
  71                         ? 0x400 : 0))
  72
  73 #ifdef CONFIG_64BIT
  74 #define smmu_writeq     writeq_relaxed
  75 #else
  76 #define smmu_writeq(reg64, addr)                                \
  77         do {                                                    \
  78                 u64 __val = (reg64);                            \
  79                 void __iomem *__addr = (addr);                  \
  80                 writel_relaxed(__val >> 32, __addr + 4);        \
  81                 writel_relaxed(__val, __addr);                  \
  82         } while (0)
  83 #endif
  84
  85 /* Configuration registers */
  86 #define ARM_SMMU_GR0_sCR0               0x0
  87 #define sCR0_CLIENTPD                   (1 << 0)
  88 #define sCR0_GFRE                       (1 << 1)
  89 #define sCR0_GFIE                       (1 << 2)
  90 #define sCR0_GCFGFRE                    (1 << 4)
  91 #define sCR0_GCFGFIE                    (1 << 5)
  92 #define sCR0_USFCFG                     (1 << 10)
  93 #define sCR0_VMIDPNE                    (1 << 11)
  94 #define sCR0_PTM                        (1 << 12)
  95 #define sCR0_FB                         (1 << 13)
  96 #define sCR0_BSU_SHIFT                  14
  97 #define sCR0_BSU_MASK                   0x3
  98
  99 /* Identification registers */
 100 #define ARM_SMMU_GR0_ID0                0x20
 101 #define ARM_SMMU_GR0_ID1                0x24
 102 #define ARM_SMMU_GR0_ID2                0x28
 103 #define ARM_SMMU_GR0_ID3                0x2c
 104 #define ARM_SMMU_GR0_ID4                0x30
 105 #define ARM_SMMU_GR0_ID5                0x34
 106 #define ARM_SMMU_GR0_ID6                0x38
 107 #define ARM_SMMU_GR0_ID7                0x3c
 108 #define ARM_SMMU_GR0_sGFSR              0x48
 109 #define ARM_SMMU_GR0_sGFSYNR0           0x50
 110 #define ARM_SMMU_GR0_sGFSYNR1           0x54
 111 #define ARM_SMMU_GR0_sGFSYNR2           0x58
 112
 113 #define ID0_S1TS                        (1 << 30)
 114 #define ID0_S2TS                        (1 << 29)
 115 #define ID0_NTS                         (1 << 28)
 116 #define ID0_SMS                         (1 << 27)
 117 #define ID0_ATOSNS                      (1 << 26)
 118 #define ID0_CTTW                        (1 << 14)
 119 #define ID0_NUMIRPT_SHIFT               16
 120 #define ID0_NUMIRPT_MASK                0xff
 121 #define ID0_NUMSIDB_SHIFT               9
 122 #define ID0_NUMSIDB_MASK                0xf
 123 #define ID0_NUMSMRG_SHIFT               0
 124 #define ID0_NUMSMRG_MASK                0xff
 125
 126 #define ID1_PAGESIZE                    (1 << 31)
 127 #define ID1_NUMPAGENDXB_SHIFT           28
 128 #define ID1_NUMPAGENDXB_MASK            7
 129 #define ID1_NUMS2CB_SHIFT               16
 130 #define ID1_NUMS2CB_MASK                0xff
 131 #define ID1_NUMCB_SHIFT                 0
 132 #define ID1_NUMCB_MASK                  0xff
 133
 134 #define ID2_OAS_SHIFT                   4
 135 #define ID2_OAS_MASK                    0xf
 136 #define ID2_IAS_SHIFT                   0
 137 #define ID2_IAS_MASK                    0xf
 138 #define ID2_UBS_SHIFT                   8
 139 #define ID2_UBS_MASK                    0xf
 140 #define ID2_PTFS_4K                     (1 << 12)
 141 #define ID2_PTFS_16K                    (1 << 13)
 142 #define ID2_PTFS_64K                    (1 << 14)
 143
 144 /* Global TLB invalidation */
 145 #define ARM_SMMU_GR0_TLBIVMID           0x64
 146 #define ARM_SMMU_GR0_TLBIALLNSNH        0x68
 147 #define ARM_SMMU_GR0_TLBIALLH           0x6c
 148 #define ARM_SMMU_GR0_sTLBGSYNC          0x70
 149 #define ARM_SMMU_GR0_sTLBGSTATUS        0x74
 150 #define sTLBGSTATUS_GSACTIVE            (1 << 0)
 151 #define TLB_LOOP_TIMEOUT                1000000 /* 1s! */
 152
 153 /* Stream mapping registers */
 154 #define ARM_SMMU_GR0_SMR(n)             (0x800 + ((n) << 2))
 155 #define SMR_VALID                       (1 << 31)
 156 #define SMR_MASK_SHIFT                  16
 157 #define SMR_MASK_MASK                   0x7fff
 158 #define SMR_ID_SHIFT                    0
 159 #define SMR_ID_MASK                     0x7fff
 160
 161 #define ARM_SMMU_GR0_S2CR(n)            (0xc00 + ((n) << 2))
 162 #define S2CR_CBNDX_SHIFT                0
 163 #define S2CR_CBNDX_MASK                 0xff
 164 #define S2CR_TYPE_SHIFT                 16
 165 #define S2CR_TYPE_MASK                  0x3
 166 #define S2CR_TYPE_TRANS                 (0 << S2CR_TYPE_SHIFT)
 167 #define S2CR_TYPE_BYPASS                (1 << S2CR_TYPE_SHIFT)
 168 #define S2CR_TYPE_FAULT                 (2 << S2CR_TYPE_SHIFT)
 169
 170 /* Context bank attribute registers */
 171 #define ARM_SMMU_GR1_CBAR(n)            (0x0 + ((n) << 2))
 172 #define CBAR_VMID_SHIFT                 0
 173 #define CBAR_VMID_MASK                  0xff
 174 #define CBAR_S1_BPSHCFG_SHIFT           8
 175 #define CBAR_S1_BPSHCFG_MASK            3
 176 #define CBAR_S1_BPSHCFG_NSH             3
 177 #define CBAR_S1_MEMATTR_SHIFT           12
 178 #define CBAR_S1_MEMATTR_MASK            0xf
 179 #define CBAR_S1_MEMATTR_WB              0xf
 180 #define CBAR_TYPE_SHIFT                 16
 181 #define CBAR_TYPE_MASK                  0x3
 182 #define CBAR_TYPE_S2_TRANS              (0 << CBAR_TYPE_SHIFT)
 183 #define CBAR_TYPE_S1_TRANS_S2_BYPASS    (1 << CBAR_TYPE_SHIFT)
 184 #define CBAR_TYPE_S1_TRANS_S2_FAULT     (2 << CBAR_TYPE_SHIFT)
 185 #define CBAR_TYPE_S1_TRANS_S2_TRANS     (3 << CBAR_TYPE_SHIFT)
 186 #define CBAR_IRPTNDX_SHIFT              24
 187 #define CBAR_IRPTNDX_MASK               0xff
 188
 189 #define ARM_SMMU_GR1_CBA2R(n)           (0x800 + ((n) << 2))
 190 #define CBA2R_RW64_32BIT                (0 << 0)
 191 #define CBA2R_RW64_64BIT                (1 << 0)
 192
 193 /* Translation context bank */
 194 #define ARM_SMMU_CB_BASE(smmu)          ((smmu)->base + ((smmu)->size >> 1))
 195 #define ARM_SMMU_CB(smmu, n)            ((n) * (1 << (smmu)->pgshift))
 196
 197 #define ARM_SMMU_CB_SCTLR               0x0
 198 #define ARM_SMMU_CB_RESUME              0x8
 199 #define ARM_SMMU_CB_TTBCR2              0x10
 200 #define ARM_SMMU_CB_TTBR0               0x20
 201 #define ARM_SMMU_CB_TTBR1               0x28
 202 #define ARM_SMMU_CB_TTBCR               0x30
 203 #define ARM_SMMU_CB_S1_MAIR0            0x38
 204 #define ARM_SMMU_CB_S1_MAIR1            0x3c
 205 #define ARM_SMMU_CB_PAR_LO              0x50
 206 #define ARM_SMMU_CB_PAR_HI              0x54
 207 #define ARM_SMMU_CB_FSR                 0x58
 208 #define ARM_SMMU_CB_FAR_LO              0x60
 209 #define ARM_SMMU_CB_FAR_HI              0x64
 210 #define ARM_SMMU_CB_FSYNR0              0x68
 211 #define ARM_SMMU_CB_S1_TLBIVA           0x600
 212 #define ARM_SMMU_CB_S1_TLBIASID         0x610
 213 #define ARM_SMMU_CB_S1_TLBIVAL          0x620
 214 #define ARM_SMMU_CB_S2_TLBIIPAS2        0x630
 215 #define ARM_SMMU_CB_S2_TLBIIPAS2L       0x638
 216 #define ARM_SMMU_CB_ATS1PR              0x800
 217 #define ARM_SMMU_CB_ATSR                0x8f0
 218
 219 #define SCTLR_S1_ASIDPNE                (1 << 12)
 220 #define SCTLR_CFCFG                     (1 << 7)
 221 #define SCTLR_CFIE                      (1 << 6)
 222 #define SCTLR_CFRE                      (1 << 5)
 223 #define SCTLR_E                         (1 << 4)
 224 #define SCTLR_AFE                       (1 << 2)
 225 #define SCTLR_TRE                       (1 << 1)
 226 #define SCTLR_M                         (1 << 0)
 227 #define SCTLR_EAE_SBOP                  (SCTLR_AFE | SCTLR_TRE)
 228
 229 #define CB_PAR_F                        (1 << 0)
 230
 231 #define ATSR_ACTIVE                     (1 << 0)
 232
 233 #define RESUME_RETRY                    (0 << 0)
 234 #define RESUME_TERMINATE                (1 << 0)
 235
 236 #define TTBCR2_SEP_SHIFT                15
 237 #define TTBCR2_SEP_UPSTREAM             (0x7 << TTBCR2_SEP_SHIFT)
 238
 239 #define TTBRn_ASID_SHIFT                48
 240
 241 #define FSR_MULTI                       (1 << 31)
 242 #define FSR_SS                          (1 << 30)
 243 #define FSR_UUT                         (1 << 8)
 244 #define FSR_ASF                         (1 << 7)
 245 #define FSR_TLBLKF                      (1 << 6)
 246 #define FSR_TLBMCF                      (1 << 5)
 247 #define FSR_EF                          (1 << 4)
 248 #define FSR_PF                          (1 << 3)
 249 #define FSR_AFF                         (1 << 2)
 250 #define FSR_TF                          (1 << 1)
 251
 252 #define FSR_IGN                         (FSR_AFF | FSR_ASF | \
 253                                          FSR_TLBMCF | FSR_TLBLKF)
 254 #define FSR_FAULT                       (FSR_MULTI | FSR_SS | FSR_UUT | \
 255                                          FSR_EF | FSR_PF | FSR_TF | FSR_IGN)
 256
 257 #define FSYNR0_WNR                      (1 << 4)
 258
 259 static int force_stage;
 260 module_param_named(force_stage, force_stage, int, S_IRUGO);
 261 MODULE_PARM_DESC(force_stage,
 262         "Force SMMU mappings to be installed at a particular stage of translation. A value of '1' or '2' forces the corresponding stage. All other values are ignored (i.e. no stage is forced). Note that selecting a specific stage will disable support for nested translation.");
 263
 264 enum arm_smmu_arch_version {
 265         ARM_SMMU_V1 = 1,
 266         ARM_SMMU_V2,
 267 };
 268
 269 struct arm_smmu_smr {
 270         u8                              idx;
 271         u16                             mask;
 272         u16                             id;
 273 };
 274
 275 struct arm_smmu_master_cfg {
 276         int                             num_streamids;
 277         u16                             streamids[MAX_MASTER_STREAMIDS];
 278         struct arm_smmu_smr             *smrs;
 279 };
 280
 281 struct arm_smmu_master {
 282         struct device_node              *of_node;
 283         struct rb_node                  node;
 284         struct arm_smmu_master_cfg      cfg;
 285 };
 286
 287 struct arm_smmu_device {
 288         struct device                   *dev;
 289
 290         void __iomem                    *base;
 291         unsigned long                   size;
 292         unsigned long                   pgshift;
 293
 294 #define ARM_SMMU_FEAT_COHERENT_WALK     (1 << 0)
 295 #define ARM_SMMU_FEAT_STREAM_MATCH      (1 << 1)
 296 #define ARM_SMMU_FEAT_TRANS_S1          (1 << 2)
 297 #define ARM_SMMU_FEAT_TRANS_S2          (1 << 3)
 298 #define ARM_SMMU_FEAT_TRANS_NESTED      (1 << 4)
 299 #define ARM_SMMU_FEAT_TRANS_OPS         (1 << 5)
 300         u32                             features;
 301
 302 #define ARM_SMMU_OPT_SECURE_CFG_ACCESS (1 << 0)
 303         u32                             options;
 304         enum arm_smmu_arch_version      version;
 305
 306         u32                             num_context_banks;
 307         u32                             num_s2_context_banks;
 308         DECLARE_BITMAP(context_map, ARM_SMMU_MAX_CBS);
 309         atomic_t                        irptndx;
 310
 311         u32                             num_mapping_groups;
 312         DECLARE_BITMAP(smr_map, ARM_SMMU_MAX_SMRS);
 313
 314         unsigned long                   va_size;
 315         unsigned long                   ipa_size;
 316         unsigned long                   pa_size;
 317
 318         u32                             num_global_irqs;
 319         u32                             num_context_irqs;
 320         unsigned int                    *irqs;
 321
 322         struct list_head                list;
 323         struct rb_root                  masters;
 324 };
 325
 326 struct arm_smmu_cfg {
 327         u8                              cbndx;
 328         u8                              irptndx;
 329         u32                             cbar;
 330 };
 331 #define INVALID_IRPTNDX                 0xff
 332
 333 #define ARM_SMMU_CB_ASID(cfg)           ((cfg)->cbndx)
 334 #define ARM_SMMU_CB_VMID(cfg)           ((cfg)->cbndx + 1)
 335
 336 enum arm_smmu_domain_stage {
 337         ARM_SMMU_DOMAIN_S1 = 0,
 338         ARM_SMMU_DOMAIN_S2,
 339         ARM_SMMU_DOMAIN_NESTED,
 340 };
 341
 342 struct arm_smmu_domain {
 343         struct arm_smmu_device          *smmu;
 344         struct io_pgtable_ops           *pgtbl_ops;
 345         spinlock_t                      pgtbl_lock;
 346         struct arm_smmu_cfg             cfg;
 347         enum arm_smmu_domain_stage      stage;
 348         struct mutex                    init_mutex; /* Protects smmu pointer */
 349         struct iommu_domain             domain;
 350 };
 351
 352 static struct iommu_ops arm_smmu_ops;
 353
 354 static DEFINE_SPINLOCK(arm_smmu_devices_lock);
 355 static LIST_HEAD(arm_smmu_devices);
 356
 357 struct arm_smmu_option_prop {
 358         u32 opt;
 359         const char *prop;
 360 };
 361
 362 static struct arm_smmu_option_prop arm_smmu_options[] = {
 363         { ARM_SMMU_OPT_SECURE_CFG_ACCESS, "calxeda,smmu-secure-config-access" },
 364         { 0, NULL},
 365 };
 366
 367 static struct arm_smmu_domain *to_smmu_domain(struct iommu_domain *dom)
 368 {
 369         return container_of(dom, struct arm_smmu_domain, domain);
 370 }
 371
 372 static void parse_driver_options(struct arm_smmu_device *smmu)
 373 {
 374         int i = 0;
 375
 376         do {
 377                 if (of_property_read_bool(smmu->dev->of_node,
 378                                                 arm_smmu_options[i].prop)) {
 379                         smmu->options |= arm_smmu_options[i].opt;
 380                         dev_notice(smmu->dev, "option %s\n",
 381                                 arm_smmu_options[i].prop);
 382                 }
 383         } while (arm_smmu_options[++i].opt);
 384 }
 385
 386 static struct device_node *dev_get_dev_node(struct device *dev)
 387 {
 388         if (dev_is_pci(dev)) {
 389                 struct pci_bus *bus = to_pci_dev(dev)->bus;
 390
 391                 while (!pci_is_root_bus(bus))
 392                         bus = bus->parent;
 393                 return bus->bridge->parent->of_node;
 394         }
 395
 396         return dev->of_node;
 397 }
 398
 399 static struct arm_smmu_master *find_smmu_master(struct arm_smmu_device *smmu,
 400                                                 struct device_node *dev_node)
 401 {
 402         struct rb_node *node = smmu->masters.rb_node;
 403
 404         while (node) {
 405                 struct arm_smmu_master *master;
 406
 407                 master = container_of(node, struct arm_smmu_master, node);
 408
 409                 if (dev_node < master->of_node)
 410                         node = node->rb_left;
 411                 else if (dev_node > master->of_node)
 412                         node = node->rb_right;
 413                 else
 414                         return master;
 415         }
 416
 417         return NULL;
 418 }
 419
 420 static struct arm_smmu_master_cfg *
 421 find_smmu_master_cfg(struct device *dev)
 422 {
 423         struct arm_smmu_master_cfg *cfg = NULL;
 424         struct iommu_group *group = iommu_group_get(dev);
 425
 426         if (group) {
 427                 cfg = iommu_group_get_iommudata(group);
 428                 iommu_group_put(group);
 429         }
 430
 431         return cfg;
 432 }
 433
 434 static int insert_smmu_master(struct arm_smmu_device *smmu,
 435                               struct arm_smmu_master *master)
 436 {
 437         struct rb_node **new, *parent;
 438
 439         new = &smmu->masters.rb_node;
 440         parent = NULL;
 441         while (*new) {
 442                 struct arm_smmu_master *this
 443                         = container_of(*new, struct arm_smmu_master, node);
 444
 445                 parent = *new;
 446                 if (master->of_node < this->of_node)
 447                         new = &((*new)->rb_left);
 448                 else if (master->of_node > this->of_node)
 449                         new = &((*new)->rb_right);
 450                 else
 451                         return -EEXIST;
 452         }
 453
 454         rb_link_node(&master->node, parent, new);
 455         rb_insert_color(&master->node, &smmu->masters);
 456         return 0;
 457 }
 458
 459 static int register_smmu_master(struct arm_smmu_device *smmu,
 460                                 struct device *dev,
 461                                 struct of_phandle_args *masterspec)
 462 {
 463         int i;
 464         struct arm_smmu_master *master;
 465
 466         master = find_smmu_master(smmu, masterspec->np);
 467         if (master) {
 468                 dev_err(dev,
 469                         "rejecting multiple registrations for master device %s\n",
 470                         masterspec->np->name);
 471                 return -EBUSY;
 472         }
 473
 474         if (masterspec->args_count > MAX_MASTER_STREAMIDS) {
 475                 dev_err(dev,
 476                         "reached maximum number (%d) of stream IDs for master device %s\n",
 477                         MAX_MASTER_STREAMIDS, masterspec->np->name);
 478                 return -ENOSPC;
 479         }
 480
 481         master = devm_kzalloc(dev, sizeof(*master), GFP_KERNEL);
 482         if (!master)
 483                 return -ENOMEM;
 484
 485         master->of_node                 = masterspec->np;
 486         master->cfg.num_streamids       = masterspec->args_count;
 487
 488         for (i = 0; i < master->cfg.num_streamids; ++i) {
 489                 u16 streamid = masterspec->args[i];
 490
 491                 if (!(smmu->features & ARM_SMMU_FEAT_STREAM_MATCH) &&
 492                      (streamid >= smmu->num_mapping_groups)) {
 493                         dev_err(dev,
 494                                 "stream ID for master device %s greater than maximum allowed (%d)\n",
 495                                 masterspec->np->name, smmu->num_mapping_groups);
 496                         return -ERANGE;
 497                 }
 498                 master->cfg.streamids[i] = streamid;
 499         }
 500         return insert_smmu_master(smmu, master);
 501 }
 502
 503 static struct arm_smmu_device *find_smmu_for_device(struct device *dev)
 504 {
 505         struct arm_smmu_device *smmu;
 506         struct arm_smmu_master *master = NULL;
 507         struct device_node *dev_node = dev_get_dev_node(dev);
 508
 509         spin_lock(&arm_smmu_devices_lock);
 510         list_for_each_entry(smmu, &arm_smmu_devices, list) {
 511                 master = find_smmu_master(smmu, dev_node);
 512                 if (master)
 513                         break;
 514         }
 515         spin_unlock(&arm_smmu_devices_lock);
 516
 517         return master ? smmu : NULL;
 518 }
 519
 520 static int __arm_smmu_alloc_bitmap(unsigned long *map, int start, int end)
 521 {
 522         int idx;
 523
 524         do {
 525                 idx = find_next_zero_bit(map, end, start);
 526                 if (idx == end)
 527                         return -ENOSPC;
 528         } while (test_and_set_bit(idx, map));
 529
 530         return idx;
 531 }
 532
 533 static void __arm_smmu_free_bitmap(unsigned long *map, int idx)
 534 {
 535         clear_bit(idx, map);
 536 }
 537
 538 /* Wait for any pending TLB invalidations to complete */
 539 static void __arm_smmu_tlb_sync(struct arm_smmu_device *smmu)
 540 {
 541         int count = 0;
 542         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
 543
 544         writel_relaxed(0, gr0_base + ARM_SMMU_GR0_sTLBGSYNC);
 545         while (readl_relaxed(gr0_base + ARM_SMMU_GR0_sTLBGSTATUS)
 546                & sTLBGSTATUS_GSACTIVE) {
 547                 cpu_relax();
 548                 if (++count == TLB_LOOP_TIMEOUT) {
 549                         dev_err_ratelimited(smmu->dev,
 550                         "TLB sync timed out -- SMMU may be deadlocked\n");
 551                         return;
 552                 }
 553                 udelay(1);
 554         }
 555 }
 556
 557 static void arm_smmu_tlb_sync(void *cookie)
 558 {
 559         struct arm_smmu_domain *smmu_domain = cookie;
 560         __arm_smmu_tlb_sync(smmu_domain->smmu);
 561 }
 562
 563 static void arm_smmu_tlb_inv_context(void *cookie)
 564 {
 565         struct arm_smmu_domain *smmu_domain = cookie;
 566         struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
 567         struct arm_smmu_device *smmu = smmu_domain->smmu;
 568         bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;
 569         void __iomem *base;
 570
 571         if (stage1) {
 572                 base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
 573                 writel_relaxed(ARM_SMMU_CB_ASID(cfg),
 574                                base + ARM_SMMU_CB_S1_TLBIASID);
 575         } else {
 576                 base = ARM_SMMU_GR0(smmu);
 577                 writel_relaxed(ARM_SMMU_CB_VMID(cfg),
 578                                base + ARM_SMMU_GR0_TLBIVMID);
 579         }
 580
 581         __arm_smmu_tlb_sync(smmu);
 582 }
 583
 584 static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size,
 585                                           bool leaf, void *cookie)
 586 {
 587         struct arm_smmu_domain *smmu_domain = cookie;
 588         struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
 589         struct arm_smmu_device *smmu = smmu_domain->smmu;
 590         bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;
 591         void __iomem *reg;
 592
 593         if (stage1) {
 594                 reg = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
 595                 reg += leaf ? ARM_SMMU_CB_S1_TLBIVAL : ARM_SMMU_CB_S1_TLBIVA;
 596
 597                 if (!IS_ENABLED(CONFIG_64BIT) || smmu->version == ARM_SMMU_V1) {
 598                         iova &= ~12UL;
 599                         iova |= ARM_SMMU_CB_ASID(cfg);
 600                         writel_relaxed(iova, reg);
 601 #ifdef CONFIG_64BIT
 602                 } else {
 603                         iova >>= 12;
 604                         iova |= (u64)ARM_SMMU_CB_ASID(cfg) << 48;
 605                         writeq_relaxed(iova, reg);
 606 #endif
 607                 }
 608 #ifdef CONFIG_64BIT
 609         } else if (smmu->version == ARM_SMMU_V2) {
 610                 reg = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
 611                 reg += leaf ? ARM_SMMU_CB_S2_TLBIIPAS2L :
 612                               ARM_SMMU_CB_S2_TLBIIPAS2;
 613                 writeq_relaxed(iova >> 12, reg);
 614 #endif
 615         } else {
 616                 reg = ARM_SMMU_GR0(smmu) + ARM_SMMU_GR0_TLBIVMID;
 617                 writel_relaxed(ARM_SMMU_CB_VMID(cfg), reg);
 618         }
 619 }
 620
 621 static struct iommu_gather_ops arm_smmu_gather_ops = {
 622         .tlb_flush_all  = arm_smmu_tlb_inv_context,
 623         .tlb_add_flush  = arm_smmu_tlb_inv_range_nosync,
 624         .tlb_sync       = arm_smmu_tlb_sync,
 625 };
 626
 627 static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
 628 {
 629         int flags, ret;
 630         u32 fsr, far, fsynr, resume;
 631         unsigned long iova;
 632         struct iommu_domain *domain = dev;
 633         struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
 634         struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
 635         struct arm_smmu_device *smmu = smmu_domain->smmu;
 636         void __iomem *cb_base;
 637
 638         cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
 639         fsr = readl_relaxed(cb_base + ARM_SMMU_CB_FSR);
 640
 641         if (!(fsr & FSR_FAULT))
 642                 return IRQ_NONE;
 643
 644         if (fsr & FSR_IGN)
 645                 dev_err_ratelimited(smmu->dev,
 646                                     "Unexpected context fault (fsr 0x%x)\n",
 647                                     fsr);
 648
 649         fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0);
 650         flags = fsynr & FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ;
 651
 652         far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_LO);
 653         iova = far;
 654 #ifdef CONFIG_64BIT
 655         far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_HI);
 656         iova |= ((unsigned long)far << 32);
 657 #endif
 658
 659         if (!report_iommu_fault(domain, smmu->dev, iova, flags)) {
 660                 ret = IRQ_HANDLED;
 661                 resume = RESUME_RETRY;
 662         } else {
 663                 dev_err_ratelimited(smmu->dev,
 664                     "Unhandled context fault: iova=0x%08lx, fsynr=0x%x, cb=%d\n",
 665                     iova, fsynr, cfg->cbndx);
 666                 ret = IRQ_NONE;
 667                 resume = RESUME_TERMINATE;
 668         }
 669
 670         /* Clear the faulting FSR */
 671         writel(fsr, cb_base + ARM_SMMU_CB_FSR);
 672
 673         /* Retry or terminate any stalled transactions */
 674         if (fsr & FSR_SS)
 675                 writel_relaxed(resume, cb_base + ARM_SMMU_CB_RESUME);
 676
 677         return ret;
 678 }
 679
 680 static irqreturn_t arm_smmu_global_fault(int irq, void *dev)
 681 {
 682         u32 gfsr, gfsynr0, gfsynr1, gfsynr2;
 683         struct arm_smmu_device *smmu = dev;
 684         void __iomem *gr0_base = ARM_SMMU_GR0_NS(smmu);
 685
 686         gfsr = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR);
 687         gfsynr0 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR0);
 688         gfsynr1 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR1);
 689         gfsynr2 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR2);
 690
 691         if (!gfsr)
 692                 return IRQ_NONE;
 693
 694         dev_err_ratelimited(smmu->dev,
 695                 "Unexpected global fault, this could be serious\n");
 696         dev_err_ratelimited(smmu->dev,
 697                 "\tGFSR 0x%08x, GFSYNR0 0x%08x, GFSYNR1 0x%08x, GFSYNR2 0x%08x\n",
 698                 gfsr, gfsynr0, gfsynr1, gfsynr2);
 699
 700         writel(gfsr, gr0_base + ARM_SMMU_GR0_sGFSR);
 701         return IRQ_HANDLED;
 702 }
 703
 704 static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain,
 705                                        struct io_pgtable_cfg *pgtbl_cfg)
 706 {
 707         u32 reg;
 708         u64 reg64;
 709         bool stage1;
 710         struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
 711         struct arm_smmu_device *smmu = smmu_domain->smmu;
 712         void __iomem *cb_base, *gr1_base;
 713
 714         gr1_base = ARM_SMMU_GR1(smmu);
 715         stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;
 716         cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
 717
 718         if (smmu->version > ARM_SMMU_V1) {
 719                 /*
 720                  * CBA2R.
 721                  * *Must* be initialised before CBAR thanks to VMID16
 722                  * architectural oversight affected some implementations.
 723                  */
 724 #ifdef CONFIG_64BIT
 725                 reg = CBA2R_RW64_64BIT;
 726 #else
 727                 reg = CBA2R_RW64_32BIT;
 728 #endif
 729                 writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBA2R(cfg->cbndx));
 730         }
 731
 732         /* CBAR */
 733         reg = cfg->cbar;
 734         if (smmu->version == ARM_SMMU_V1)
 735                 reg |= cfg->irptndx << CBAR_IRPTNDX_SHIFT;
 736
 737         /*
 738          * Use the weakest shareability/memory types, so they are
 739          * overridden by the ttbcr/pte.
 740          */
 741         if (stage1) {
 742                 reg |= (CBAR_S1_BPSHCFG_NSH << CBAR_S1_BPSHCFG_SHIFT) |
 743                         (CBAR_S1_MEMATTR_WB << CBAR_S1_MEMATTR_SHIFT);
 744         } else {
 745                 reg |= ARM_SMMU_CB_VMID(cfg) << CBAR_VMID_SHIFT;
 746         }
 747         writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBAR(cfg->cbndx));
 748
 749         /* TTBRs */
 750         if (stage1) {
 751                 reg64 = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0];
 752
 753                 reg64 |= ((u64)ARM_SMMU_CB_ASID(cfg)) << TTBRn_ASID_SHIFT;
 754                 smmu_writeq(reg64, cb_base + ARM_SMMU_CB_TTBR0);
 755
 756                 reg64 = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[1];
 757                 reg64 |= ((u64)ARM_SMMU_CB_ASID(cfg)) << TTBRn_ASID_SHIFT;
 758                 smmu_writeq(reg64, cb_base + ARM_SMMU_CB_TTBR1);
 759         } else {
 760                 reg64 = pgtbl_cfg->arm_lpae_s2_cfg.vttbr;
 761                 smmu_writeq(reg64, cb_base + ARM_SMMU_CB_TTBR0);
 762         }
 763
 764         /* TTBCR */
 765         if (stage1) {
 766                 reg = pgtbl_cfg->arm_lpae_s1_cfg.tcr;
 767                 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR);
 768                 if (smmu->version > ARM_SMMU_V1) {
 769                         reg = pgtbl_cfg->arm_lpae_s1_cfg.tcr >> 32;
 770                         reg |= TTBCR2_SEP_UPSTREAM;
 771                         writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR2);
 772                 }
 773         } else {
 774                 reg = pgtbl_cfg->arm_lpae_s2_cfg.vtcr;
 775                 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR);
 776         }
 777
 778         /* MAIRs (stage-1 only) */
 779         if (stage1) {
 780                 reg = pgtbl_cfg->arm_lpae_s1_cfg.mair[0];
 781                 writel_relaxed(reg, cb_base + ARM_SMMU_CB_S1_MAIR0);
 782                 reg = pgtbl_cfg->arm_lpae_s1_cfg.mair[1];
 783                 writel_relaxed(reg, cb_base + ARM_SMMU_CB_S1_MAIR1);
 784         }
 785
 786         /* SCTLR */
 787         reg = SCTLR_CFCFG | SCTLR_CFIE | SCTLR_CFRE | SCTLR_M | SCTLR_EAE_SBOP;
 788         if (stage1)
 789                 reg |= SCTLR_S1_ASIDPNE;
 790 #ifdef __BIG_ENDIAN
 791         reg |= SCTLR_E;
 792 #endif
 793         writel_relaxed(reg, cb_base + ARM_SMMU_CB_SCTLR);
 794 }
 795
 796 static int arm_smmu_init_domain_context(struct iommu_domain *domain,
 797                                         struct arm_smmu_device *smmu)
 798 {
 799         int irq, start, ret = 0;
 800         unsigned long ias, oas;
 801         struct io_pgtable_ops *pgtbl_ops;
 802         struct io_pgtable_cfg pgtbl_cfg;
 803         enum io_pgtable_fmt fmt;
 804         struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
 805         struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
 806
 807         mutex_lock(&smmu_domain->init_mutex);
 808         if (smmu_domain->smmu)
 809                 goto out_unlock;
 810
 811         /*
 812          * Mapping the requested stage onto what we support is surprisingly
 813          * complicated, mainly because the spec allows S1+S2 SMMUs without
 814          * support for nested translation. That means we end up with the
 815          * following table:
 816          *
 817          * Requested        Supported        Actual
 818          *     S1               N              S1
 819          *     S1             S1+S2            S1
 820          *     S1               S2             S2
 821          *     S1               S1             S1
 822          *     N                N              N
 823          *     N              S1+S2            S2
 824          *     N                S2             S2
 825          *     N                S1             S1
 826          *
 827          * Note that you can't actually request stage-2 mappings.
 828          */
 829         if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S1))
 830                 smmu_domain->stage = ARM_SMMU_DOMAIN_S2;
 831         if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S2))
 832                 smmu_domain->stage = ARM_SMMU_DOMAIN_S1;
 833
 834         switch (smmu_domain->stage) {
 835         case ARM_SMMU_DOMAIN_S1:
 836                 cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS;
 837                 start = smmu->num_s2_context_banks;
 838                 ias = smmu->va_size;
 839                 oas = smmu->ipa_size;
 840                 if (IS_ENABLED(CONFIG_64BIT))
 841                         fmt = ARM_64_LPAE_S1;
 842                 else
 843                         fmt = ARM_32_LPAE_S1;
 844                 break;
 845         case ARM_SMMU_DOMAIN_NESTED:
 846                 /*
 847                  * We will likely want to change this if/when KVM gets
 848                  * involved.
 849                  */
 850         case ARM_SMMU_DOMAIN_S2:
 851                 cfg->cbar = CBAR_TYPE_S2_TRANS;
 852                 start = 0;
 853                 ias = smmu->ipa_size;
 854                 oas = smmu->pa_size;
 855                 if (IS_ENABLED(CONFIG_64BIT))
 856                         fmt = ARM_64_LPAE_S2;
 857                 else
 858                         fmt = ARM_32_LPAE_S2;
 859                 break;
 860         default:
 861                 ret = -EINVAL;
 862                 goto out_unlock;
 863         }
 864
 865         ret = __arm_smmu_alloc_bitmap(smmu->context_map, start,
 866                                       smmu->num_context_banks);
 867         if (IS_ERR_VALUE(ret))
 868                 goto out_unlock;
 869
 870         cfg->cbndx = ret;
 871         if (smmu->version == ARM_SMMU_V1) {
 872                 cfg->irptndx = atomic_inc_return(&smmu->irptndx);
 873                 cfg->irptndx %= smmu->num_context_irqs;
 874         } else {
 875                 cfg->irptndx = cfg->cbndx;
 876         }
 877
 878         pgtbl_cfg = (struct io_pgtable_cfg) {
 879                 .pgsize_bitmap  = arm_smmu_ops.pgsize_bitmap,
 880                 .ias            = ias,
 881                 .oas            = oas,
 882                 .tlb            = &arm_smmu_gather_ops,
 883                 .iommu_dev      = smmu->dev,
 884         };
 885
 886         smmu_domain->smmu = smmu;
 887         pgtbl_ops = alloc_io_pgtable_ops(fmt, &pgtbl_cfg, smmu_domain);
 888         if (!pgtbl_ops) {
 889                 ret = -ENOMEM;
 890                 goto out_clear_smmu;
 891         }
 892
 893         /* Update our support page sizes to reflect the page table format */
 894         arm_smmu_ops.pgsize_bitmap = pgtbl_cfg.pgsize_bitmap;
 895
 896         /* Initialise the context bank with our page table cfg */
 897         arm_smmu_init_context_bank(smmu_domain, &pgtbl_cfg);
 898
 899         /*
 900          * Request context fault interrupt. Do this last to avoid the
 901          * handler seeing a half-initialised domain state.
 902          */
 903         irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx];
 904         ret = request_irq(irq, arm_smmu_context_fault, IRQF_SHARED,
 905                           "arm-smmu-context-fault", domain);
 906         if (IS_ERR_VALUE(ret)) {
 907                 dev_err(smmu->dev, "failed to request context IRQ %d (%u)\n",
 908                         cfg->irptndx, irq);
 909                 cfg->irptndx = INVALID_IRPTNDX;
 910         }
 911
 912         mutex_unlock(&smmu_domain->init_mutex);
 913
 914         /* Publish page table ops for map/unmap */
 915         smmu_domain->pgtbl_ops = pgtbl_ops;
 916         return 0;
 917
 918 out_clear_smmu:
 919         smmu_domain->smmu = NULL;
 920 out_unlock:
 921         mutex_unlock(&smmu_domain->init_mutex);
 922         return ret;
 923 }
 924
 925 static void arm_smmu_destroy_domain_context(struct iommu_domain *domain)
 926 {
 927         struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
 928         struct arm_smmu_device *smmu = smmu_domain->smmu;
 929         struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
 930         void __iomem *cb_base;
 931         int irq;
 932
 933         if (!smmu)
 934                 return;
 935
 936         /*
 937          * Disable the context bank and free the page tables before freeing
 938          * it.
 939          */
 940         cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
 941         writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR);
 942
 943         if (cfg->irptndx != INVALID_IRPTNDX) {
 944                 irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx];
 945                 free_irq(irq, domain);
 946         }
 947
 948         free_io_pgtable_ops(smmu_domain->pgtbl_ops);
 949         __arm_smmu_free_bitmap(smmu->context_map, cfg->cbndx);
 950 }
 951
 952 static struct iommu_domain *arm_smmu_domain_alloc(unsigned type)
 953 {
 954         struct arm_smmu_domain *smmu_domain;
 955
 956         if (type != IOMMU_DOMAIN_UNMANAGED)
 957                 return NULL;
 958         /*
 959          * Allocate the domain and initialise some of its data structures.
 960          * We can't really do anything meaningful until we've added a
 961          * master.
 962          */
 963         smmu_domain = kzalloc(sizeof(*smmu_domain), GFP_KERNEL);
 964         if (!smmu_domain)
 965                 return NULL;
 966
 967         mutex_init(&smmu_domain->init_mutex);
 968         spin_lock_init(&smmu_domain->pgtbl_lock);
 969
 970         return &smmu_domain->domain;
 971 }
 972
 973 static void arm_smmu_domain_free(struct iommu_domain *domain)
 974 {
 975         struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
 976
 977         /*
 978          * Free the domain resources. We assume that all devices have
 979          * already been detached.
 980          */
 981         arm_smmu_destroy_domain_context(domain);
 982         kfree(smmu_domain);
 983 }
 984
 985 static int arm_smmu_master_configure_smrs(struct arm_smmu_device *smmu,
 986                                           struct arm_smmu_master_cfg *cfg)
 987 {
 988         int i;
 989         struct arm_smmu_smr *smrs;
 990         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
 991
 992         if (!(smmu->features & ARM_SMMU_FEAT_STREAM_MATCH))
 993                 return 0;
 994
 995         if (cfg->smrs)
 996                 return -EEXIST;
 997
 998         smrs = kmalloc_array(cfg->num_streamids, sizeof(*smrs), GFP_KERNEL);
 999         if (!smrs) {
1000                 dev_err(smmu->dev, "failed to allocate %d SMRs\n",
1001                         cfg->num_streamids);
1002                 return -ENOMEM;
1003         }
1004
1005         /* Allocate the SMRs on the SMMU */
1006         for (i = 0; i < cfg->num_streamids; ++i) {
1007                 int idx = __arm_smmu_alloc_bitmap(smmu->smr_map, 0,
1008                                                   smmu->num_mapping_groups);
1009                 if (IS_ERR_VALUE(idx)) {
1010                         dev_err(smmu->dev, "failed to allocate free SMR\n");
1011                         goto err_free_smrs;
1012                 }
1013
1014                 smrs[i] = (struct arm_smmu_smr) {
1015                         .idx    = idx,
1016                         .mask   = 0, /* We don't currently share SMRs */
1017                         .id     = cfg->streamids[i],
1018                 };
1019         }
1020
1021         /* It worked! Now, poke the actual hardware */
1022         for (i = 0; i < cfg->num_streamids; ++i) {
1023                 u32 reg = SMR_VALID | smrs[i].id << SMR_ID_SHIFT |
1024                           smrs[i].mask << SMR_MASK_SHIFT;
1025                 writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_SMR(smrs[i].idx));
1026         }
1027
1028         cfg->smrs = smrs;
1029         return 0;
1030
1031 err_free_smrs:
1032         while (--i >= 0)
1033                 __arm_smmu_free_bitmap(smmu->smr_map, smrs[i].idx);
1034         kfree(smrs);
1035         return -ENOSPC;
1036 }
1037
1038 static void arm_smmu_master_free_smrs(struct arm_smmu_device *smmu,
1039                                       struct arm_smmu_master_cfg *cfg)
1040 {
1041         int i;
1042         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1043         struct arm_smmu_smr *smrs = cfg->smrs;
1044
1045         if (!smrs)
1046                 return;
1047
1048         /* Invalidate the SMRs before freeing back to the allocator */
1049         for (i = 0; i < cfg->num_streamids; ++i) {
1050                 u8 idx = smrs[i].idx;
1051
1052                 writel_relaxed(~SMR_VALID, gr0_base + ARM_SMMU_GR0_SMR(idx));
1053                 __arm_smmu_free_bitmap(smmu->smr_map, idx);
1054         }
1055
1056         cfg->smrs = NULL;
1057         kfree(smrs);
1058 }
1059
1060 static int arm_smmu_domain_add_master(struct arm_smmu_domain *smmu_domain,
1061                                       struct arm_smmu_master_cfg *cfg)
1062 {
1063         int i, ret;
1064         struct arm_smmu_device *smmu = smmu_domain->smmu;
1065         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1066
1067         /* Devices in an IOMMU group may already be configured */
1068         ret = arm_smmu_master_configure_smrs(smmu, cfg);
1069         if (ret)
1070                 return ret == -EEXIST ? 0 : ret;
1071
1072         for (i = 0; i < cfg->num_streamids; ++i) {
1073                 u32 idx, s2cr;
1074
1075                 idx = cfg->smrs ? cfg->smrs[i].idx : cfg->streamids[i];
1076                 s2cr = S2CR_TYPE_TRANS |
1077                        (smmu_domain->cfg.cbndx << S2CR_CBNDX_SHIFT);
1078                 writel_relaxed(s2cr, gr0_base + ARM_SMMU_GR0_S2CR(idx));
1079         }
1080
1081         return 0;
1082 }
1083
1084 static void arm_smmu_domain_remove_master(struct arm_smmu_domain *smmu_domain,
1085                                           struct arm_smmu_master_cfg *cfg)
1086 {
1087         int i;
1088         struct arm_smmu_device *smmu = smmu_domain->smmu;
1089         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1090
1091         /* An IOMMU group is torn down by the first device to be removed */
1092         if ((smmu->features & ARM_SMMU_FEAT_STREAM_MATCH) && !cfg->smrs)
1093                 return;
1094
1095         /*
1096          * We *must* clear the S2CR first, because freeing the SMR means
1097          * that it can be re-allocated immediately.
1098          */
1099         for (i = 0; i < cfg->num_streamids; ++i) {
1100                 u32 idx = cfg->smrs ? cfg->smrs[i].idx : cfg->streamids[i];
1101
1102                 writel_relaxed(S2CR_TYPE_BYPASS,
1103                                gr0_base + ARM_SMMU_GR0_S2CR(idx));
1104         }
1105
1106         arm_smmu_master_free_smrs(smmu, cfg);
1107 }
1108
1109 static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
1110 {
1111         int ret;
1112         struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1113         struct arm_smmu_device *smmu;
1114         struct arm_smmu_master_cfg *cfg;
1115
1116         smmu = find_smmu_for_device(dev);
1117         if (!smmu) {
1118                 dev_err(dev, "cannot attach to SMMU, is it on the same bus?\n");
1119                 return -ENXIO;
1120         }
1121
1122         if (dev->archdata.iommu) {
1123                 dev_err(dev, "already attached to IOMMU domain\n");
1124                 return -EEXIST;
1125         }
1126
1127         /* Ensure that the domain is finalised */
1128         ret = arm_smmu_init_domain_context(domain, smmu);
1129         if (IS_ERR_VALUE(ret))
1130                 return ret;
1131
1132         /*
1133          * Sanity check the domain. We don't support domains across
1134          * different SMMUs.
1135          */
1136         if (smmu_domain->smmu != smmu) {
1137                 dev_err(dev,
1138                         "cannot attach to SMMU %s whilst already attached to domain on SMMU %s\n",
1139                         dev_name(smmu_domain->smmu->dev), dev_name(smmu->dev));
1140                 return -EINVAL;
1141         }
1142
1143         /* Looks ok, so add the device to the domain */
1144         cfg = find_smmu_master_cfg(dev);
1145         if (!cfg)
1146                 return -ENODEV;
1147
1148         ret = arm_smmu_domain_add_master(smmu_domain, cfg);
1149         if (!ret)
1150                 dev->archdata.iommu = domain;
1151         return ret;
1152 }
1153
1154 static void arm_smmu_detach_dev(struct iommu_domain *domain, struct device *dev)
1155 {
1156         struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1157         struct arm_smmu_master_cfg *cfg;
1158
1159         cfg = find_smmu_master_cfg(dev);
1160         if (!cfg)
1161                 return;
1162
1163         dev->archdata.iommu = NULL;
1164         arm_smmu_domain_remove_master(smmu_domain, cfg);
1165 }
1166
1167 static int arm_smmu_map(struct iommu_domain *domain, unsigned long iova,
1168                         phys_addr_t paddr, size_t size, int prot)
1169 {
1170         int ret;
1171         unsigned long flags;
1172         struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1173         struct io_pgtable_ops *ops= smmu_domain->pgtbl_ops;
1174
1175         if (!ops)
1176                 return -ENODEV;
1177
1178         spin_lock_irqsave(&smmu_domain->pgtbl_lock, flags);
1179         ret = ops->map(ops, iova, paddr, size, prot);
1180         spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags);
1181         return ret;
1182 }
1183
1184 static size_t arm_smmu_unmap(struct iommu_domain *domain, unsigned long iova,
1185                              size_t size)
1186 {
1187         size_t ret;
1188         unsigned long flags;
1189         struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1190         struct io_pgtable_ops *ops= smmu_domain->pgtbl_ops;
1191
1192         if (!ops)
1193                 return 0;
1194
1195         spin_lock_irqsave(&smmu_domain->pgtbl_lock, flags);
1196         ret = ops->unmap(ops, iova, size);
1197         spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags);
1198         return ret;
1199 }
1200
1201 static phys_addr_t arm_smmu_iova_to_phys_hard(struct iommu_domain *domain,
1202                                               dma_addr_t iova)
1203 {
1204         struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1205         struct arm_smmu_device *smmu = smmu_domain->smmu;
1206         struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
1207         struct io_pgtable_ops *ops= smmu_domain->pgtbl_ops;
1208         struct device *dev = smmu->dev;
1209         void __iomem *cb_base;
1210         u32 tmp;
1211         u64 phys;
1212         unsigned long va;
1213
1214         cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
1215
1216         /* ATS1 registers can only be written atomically */
1217         va = iova & ~0xfffUL;
1218         if (smmu->version == ARM_SMMU_V2)
1219                 smmu_writeq(va, cb_base + ARM_SMMU_CB_ATS1PR);
1220         else
1221                 writel_relaxed(va, cb_base + ARM_SMMU_CB_ATS1PR);
1222
1223         if (readl_poll_timeout_atomic(cb_base + ARM_SMMU_CB_ATSR, tmp,
1224                                       !(tmp & ATSR_ACTIVE), 5, 50)) {
1225                 dev_err(dev,
1226                         "iova to phys timed out on %pad. Falling back to software table walk.\n",
1227                         &iova);
1228                 return ops->iova_to_phys(ops, iova);
1229         }
1230
1231         phys = readl_relaxed(cb_base + ARM_SMMU_CB_PAR_LO);
1232         phys |= ((u64)readl_relaxed(cb_base + ARM_SMMU_CB_PAR_HI)) << 32;
1233
1234         if (phys & CB_PAR_F) {
1235                 dev_err(dev, "translation fault!\n");
1236                 dev_err(dev, "PAR = 0x%llx\n", phys);
1237                 return 0;
1238         }
1239
1240         return (phys & GENMASK_ULL(39, 12)) | (iova & 0xfff);
1241 }
1242
1243 static phys_addr_t arm_smmu_iova_to_phys(struct iommu_domain *domain,
1244                                         dma_addr_t iova)
1245 {
1246         phys_addr_t ret;
1247         unsigned long flags;
1248         struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1249         struct io_pgtable_ops *ops= smmu_domain->pgtbl_ops;
1250
1251         if (!ops)
1252                 return 0;
1253
1254         spin_lock_irqsave(&smmu_domain->pgtbl_lock, flags);
1255         if (smmu_domain->smmu->features & ARM_SMMU_FEAT_TRANS_OPS &&
1256                         smmu_domain->stage == ARM_SMMU_DOMAIN_S1) {
1257                 ret = arm_smmu_iova_to_phys_hard(domain, iova);
1258         } else {
1259                 ret = ops->iova_to_phys(ops, iova);
1260         }
1261
1262         spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags);
1263
1264         return ret;
1265 }
1266
1267 static bool arm_smmu_capable(enum iommu_cap cap)
1268 {
1269         switch (cap) {
1270         case IOMMU_CAP_CACHE_COHERENCY:
1271                 /*
1272                  * Return true here as the SMMU can always send out coherent
1273                  * requests.
1274                  */
1275                 return true;
1276         case IOMMU_CAP_INTR_REMAP:
1277                 return true; /* MSIs are just memory writes */
1278         case IOMMU_CAP_NOEXEC:
1279                 return true;
1280         default:
1281                 return false;
1282         }
1283 }
1284
1285 static int __arm_smmu_get_pci_sid(struct pci_dev *pdev, u16 alias, void *data)
1286 {
1287         *((u16 *)data) = alias;
1288         return 0; /* Continue walking */
1289 }
1290
1291 static void __arm_smmu_release_pci_iommudata(void *data)
1292 {
1293         kfree(data);
1294 }
1295
1296 static int arm_smmu_init_pci_device(struct pci_dev *pdev,
1297                                     struct iommu_group *group)
1298 {
1299         struct arm_smmu_master_cfg *cfg;
1300         u16 sid;
1301         int i;
1302
1303         cfg = iommu_group_get_iommudata(group);
1304         if (!cfg) {
1305                 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
1306                 if (!cfg)
1307                         return -ENOMEM;
1308
1309                 iommu_group_set_iommudata(group, cfg,
1310                                           __arm_smmu_release_pci_iommudata);
1311         }
1312
1313         if (cfg->num_streamids >= MAX_MASTER_STREAMIDS)
1314                 return -ENOSPC;
1315
1316         /*
1317          * Assume Stream ID == Requester ID for now.
1318          * We need a way to describe the ID mappings in FDT.
1319          */
1320         pci_for_each_dma_alias(pdev, __arm_smmu_get_pci_sid, &sid);
1321         for (i = 0; i < cfg->num_streamids; ++i)
1322                 if (cfg->streamids[i] == sid)
1323                         break;
1324
1325         /* Avoid duplicate SIDs, as this can lead to SMR conflicts */
1326         if (i == cfg->num_streamids)
1327                 cfg->streamids[cfg->num_streamids++] = sid;
1328
1329         return 0;
1330 }
1331
1332 static int arm_smmu_init_platform_device(struct device *dev,
1333                                          struct iommu_group *group)
1334 {
1335         struct arm_smmu_device *smmu = find_smmu_for_device(dev);
1336         struct arm_smmu_master *master;
1337
1338         if (!smmu)
1339                 return -ENODEV;
1340
1341         master = find_smmu_master(smmu, dev->of_node);
1342         if (!master)
1343                 return -ENODEV;
1344
1345         iommu_group_set_iommudata(group, &master->cfg, NULL);
1346
1347         return 0;
1348 }
1349
1350 static int arm_smmu_add_device(struct device *dev)
1351 {
1352         struct iommu_group *group;
1353
1354         group = iommu_group_get_for_dev(dev);
1355         if (IS_ERR(group))
1356                 return PTR_ERR(group);
1357
1358         iommu_group_put(group);
1359         return 0;
1360 }
1361
1362 static void arm_smmu_remove_device(struct device *dev)
1363 {
1364         iommu_group_remove_device(dev);
1365 }
1366
1367 static struct iommu_group *arm_smmu_device_group(struct device *dev)
1368 {
1369         struct iommu_group *group;
1370         int ret;
1371
1372         if (dev_is_pci(dev))
1373                 group = pci_device_group(dev);
1374         else
1375                 group = generic_device_group(dev);
1376
1377         if (IS_ERR(group))
1378                 return group;
1379
1380         if (dev_is_pci(dev))
1381                 ret = arm_smmu_init_pci_device(to_pci_dev(dev), group);
1382         else
1383                 ret = arm_smmu_init_platform_device(dev, group);
1384
1385         if (ret) {
1386                 iommu_group_put(group);
1387                 group = ERR_PTR(ret);
1388         }
1389
1390         return group;
1391 }
1392
1393 static int arm_smmu_domain_get_attr(struct iommu_domain *domain,
1394                                     enum iommu_attr attr, void *data)
1395 {
1396         struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1397
1398         switch (attr) {
1399         case DOMAIN_ATTR_NESTING:
1400                 *(int *)data = (smmu_domain->stage == ARM_SMMU_DOMAIN_NESTED);
1401                 return 0;
1402         default:
1403                 return -ENODEV;
1404         }
1405 }
1406
1407 static int arm_smmu_domain_set_attr(struct iommu_domain *domain,
1408                                     enum iommu_attr attr, void *data)
1409 {
1410         int ret = 0;
1411         struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1412
1413         mutex_lock(&smmu_domain->init_mutex);
1414
1415         switch (attr) {
1416         case DOMAIN_ATTR_NESTING:
1417                 if (smmu_domain->smmu) {
1418                         ret = -EPERM;
1419                         goto out_unlock;
1420                 }
1421
1422                 if (*(int *)data)
1423                         smmu_domain->stage = ARM_SMMU_DOMAIN_NESTED;
1424                 else
1425                         smmu_domain->stage = ARM_SMMU_DOMAIN_S1;
1426
1427                 break;
1428         default:
1429                 ret = -ENODEV;
1430         }
1431
1432 out_unlock:
1433         mutex_unlock(&smmu_domain->init_mutex);
1434         return ret;
1435 }
1436
1437 static struct iommu_ops arm_smmu_ops = {
1438         .capable                = arm_smmu_capable,
1439         .domain_alloc           = arm_smmu_domain_alloc,
1440         .domain_free            = arm_smmu_domain_free,
1441         .attach_dev             = arm_smmu_attach_dev,
1442         .detach_dev             = arm_smmu_detach_dev,
1443         .map                    = arm_smmu_map,
1444         .unmap                  = arm_smmu_unmap,
1445         .map_sg                 = default_iommu_map_sg,
1446         .iova_to_phys           = arm_smmu_iova_to_phys,
1447         .add_device             = arm_smmu_add_device,
1448         .remove_device          = arm_smmu_remove_device,
1449         .device_group           = arm_smmu_device_group,
1450         .domain_get_attr        = arm_smmu_domain_get_attr,
1451         .domain_set_attr        = arm_smmu_domain_set_attr,
1452         .pgsize_bitmap          = -1UL, /* Restricted during device attach */
1453 };
1454
1455 static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
1456 {
1457         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1458         void __iomem *cb_base;
1459         int i = 0;
1460         u32 reg;
1461
1462         /* clear global FSR */
1463         reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR);
1464         writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR);
1465
1466         /* Mark all SMRn as invalid and all S2CRn as bypass */
1467         for (i = 0; i < smmu->num_mapping_groups; ++i) {
1468                 writel_relaxed(0, gr0_base + ARM_SMMU_GR0_SMR(i));
1469                 writel_relaxed(S2CR_TYPE_BYPASS,
1470                         gr0_base + ARM_SMMU_GR0_S2CR(i));
1471         }
1472
1473         /* Make sure all context banks are disabled and clear CB_FSR  */
1474         for (i = 0; i < smmu->num_context_banks; ++i) {
1475                 cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, i);
1476                 writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR);
1477                 writel_relaxed(FSR_FAULT, cb_base + ARM_SMMU_CB_FSR);
1478         }
1479
1480         /* Invalidate the TLB, just in case */
1481         writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLH);
1482         writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLNSNH);
1483
1484         reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
1485
1486         /* Enable fault reporting */
1487         reg |= (sCR0_GFRE | sCR0_GFIE | sCR0_GCFGFRE | sCR0_GCFGFIE);
1488
1489         /* Disable TLB broadcasting. */
1490         reg |= (sCR0_VMIDPNE | sCR0_PTM);
1491
1492         /* Enable client access, but bypass when no mapping is found */
1493         reg &= ~(sCR0_CLIENTPD | sCR0_USFCFG);
1494
1495         /* Disable forced broadcasting */
1496         reg &= ~sCR0_FB;
1497
1498         /* Don't upgrade barriers */
1499         reg &= ~(sCR0_BSU_MASK << sCR0_BSU_SHIFT);
1500
1501         /* Push the button */
1502         __arm_smmu_tlb_sync(smmu);
1503         writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
1504 }
1505
1506 static int arm_smmu_id_size_to_bits(int size)
1507 {
1508         switch (size) {
1509         case 0:
1510                 return 32;
1511         case 1:
1512                 return 36;
1513         case 2:
1514                 return 40;
1515         case 3:
1516                 return 42;
1517         case 4:
1518                 return 44;
1519         case 5:
1520         default:
1521                 return 48;
1522         }
1523 }
1524
1525 static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
1526 {
1527         unsigned long size;
1528         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1529         u32 id;
1530         bool cttw_dt, cttw_reg;
1531
1532         dev_notice(smmu->dev, "probing hardware configuration...\n");
1533         dev_notice(smmu->dev, "SMMUv%d with:\n", smmu->version);
1534
1535         /* ID0 */
1536         id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID0);
1537
1538         /* Restrict available stages based on module parameter */
1539         if (force_stage == 1)
1540                 id &= ~(ID0_S2TS | ID0_NTS);
1541         else if (force_stage == 2)
1542                 id &= ~(ID0_S1TS | ID0_NTS);
1543
1544         if (id & ID0_S1TS) {
1545                 smmu->features |= ARM_SMMU_FEAT_TRANS_S1;
1546                 dev_notice(smmu->dev, "\tstage 1 translation\n");
1547         }
1548
1549         if (id & ID0_S2TS) {
1550                 smmu->features |= ARM_SMMU_FEAT_TRANS_S2;
1551                 dev_notice(smmu->dev, "\tstage 2 translation\n");
1552         }
1553
1554         if (id & ID0_NTS) {
1555                 smmu->features |= ARM_SMMU_FEAT_TRANS_NESTED;
1556                 dev_notice(smmu->dev, "\tnested translation\n");
1557         }
1558
1559         if (!(smmu->features &
1560                 (ARM_SMMU_FEAT_TRANS_S1 | ARM_SMMU_FEAT_TRANS_S2))) {
1561                 dev_err(smmu->dev, "\tno translation support!\n");
1562                 return -ENODEV;
1563         }
1564
1565         if ((id & ID0_S1TS) && ((smmu->version == 1) || !(id & ID0_ATOSNS))) {
1566                 smmu->features |= ARM_SMMU_FEAT_TRANS_OPS;
1567                 dev_notice(smmu->dev, "\taddress translation ops\n");
1568         }
1569
1570         /*
1571          * In order for DMA API calls to work properly, we must defer to what
1572          * the DT says about coherency, regardless of what the hardware claims.
1573          * Fortunately, this also opens up a workaround for systems where the
1574          * ID register value has ended up configured incorrectly.
1575          */
1576         cttw_dt = of_dma_is_coherent(smmu->dev->of_node);
1577         cttw_reg = !!(id & ID0_CTTW);
1578         if (cttw_dt)
1579                 smmu->features |= ARM_SMMU_FEAT_COHERENT_WALK;
1580         if (cttw_dt || cttw_reg)
1581                 dev_notice(smmu->dev, "\t%scoherent table walk\n",
1582                            cttw_dt ? "" : "non-");
1583         if (cttw_dt != cttw_reg)
1584                 dev_notice(smmu->dev,
1585                            "\t(IDR0.CTTW overridden by dma-coherent property)\n");
1586
1587         if (id & ID0_SMS) {
1588                 u32 smr, sid, mask;
1589
1590                 smmu->features |= ARM_SMMU_FEAT_STREAM_MATCH;
1591                 smmu->num_mapping_groups = (id >> ID0_NUMSMRG_SHIFT) &
1592                                            ID0_NUMSMRG_MASK;
1593                 if (smmu->num_mapping_groups == 0) {
1594                         dev_err(smmu->dev,
1595                                 "stream-matching supported, but no SMRs present!\n");
1596                         return -ENODEV;
1597                 }
1598
1599                 smr = SMR_MASK_MASK << SMR_MASK_SHIFT;
1600                 smr |= (SMR_ID_MASK << SMR_ID_SHIFT);
1601                 writel_relaxed(smr, gr0_base + ARM_SMMU_GR0_SMR(0));
1602                 smr = readl_relaxed(gr0_base + ARM_SMMU_GR0_SMR(0));
1603
1604                 mask = (smr >> SMR_MASK_SHIFT) & SMR_MASK_MASK;
1605                 sid = (smr >> SMR_ID_SHIFT) & SMR_ID_MASK;
1606                 if ((mask & sid) != sid) {
1607                         dev_err(smmu->dev,
1608                                 "SMR mask bits (0x%x) insufficient for ID field (0x%x)\n",
1609                                 mask, sid);
1610                         return -ENODEV;
1611                 }
1612
1613                 dev_notice(smmu->dev,
1614                            "\tstream matching with %u register groups, mask 0x%x",
1615                            smmu->num_mapping_groups, mask);
1616         } else {
1617                 smmu->num_mapping_groups = (id >> ID0_NUMSIDB_SHIFT) &
1618                                            ID0_NUMSIDB_MASK;
1619         }
1620
1621         /* ID1 */
1622         id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID1);
1623         smmu->pgshift = (id & ID1_PAGESIZE) ? 16 : 12;
1624
1625         /* Check for size mismatch of SMMU address space from mapped region */
1626         size = 1 << (((id >> ID1_NUMPAGENDXB_SHIFT) & ID1_NUMPAGENDXB_MASK) + 1);
1627         size *= 2 << smmu->pgshift;
1628         if (smmu->size != size)
1629                 dev_warn(smmu->dev,
1630                         "SMMU address space size (0x%lx) differs from mapped region size (0x%lx)!\n",
1631                         size, smmu->size);
1632
1633         smmu->num_s2_context_banks = (id >> ID1_NUMS2CB_SHIFT) & ID1_NUMS2CB_MASK;
1634         smmu->num_context_banks = (id >> ID1_NUMCB_SHIFT) & ID1_NUMCB_MASK;
1635         if (smmu->num_s2_context_banks > smmu->num_context_banks) {
1636                 dev_err(smmu->dev, "impossible number of S2 context banks!\n");
1637                 return -ENODEV;
1638         }
1639         dev_notice(smmu->dev, "\t%u context banks (%u stage-2 only)\n",
1640                    smmu->num_context_banks, smmu->num_s2_context_banks);
1641
1642         /* ID2 */
1643         id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID2);
1644         size = arm_smmu_id_size_to_bits((id >> ID2_IAS_SHIFT) & ID2_IAS_MASK);
1645         smmu->ipa_size = size;
1646
1647         /* The output mask is also applied for bypass */
1648         size = arm_smmu_id_size_to_bits((id >> ID2_OAS_SHIFT) & ID2_OAS_MASK);
1649         smmu->pa_size = size;
1650
1651         /*
1652          * What the page table walker can address actually depends on which
1653          * descriptor format is in use, but since a) we don't know that yet,
1654          * and b) it can vary per context bank, this will have to do...
1655          */
1656         if (dma_set_mask_and_coherent(smmu->dev, DMA_BIT_MASK(size)))
1657                 dev_warn(smmu->dev,
1658                          "failed to set DMA mask for table walker\n");
1659
1660         if (smmu->version == ARM_SMMU_V1) {
1661                 smmu->va_size = smmu->ipa_size;
1662                 size = SZ_4K | SZ_2M | SZ_1G;
1663         } else {
1664                 size = (id >> ID2_UBS_SHIFT) & ID2_UBS_MASK;
1665                 smmu->va_size = arm_smmu_id_size_to_bits(size);
1666 #ifndef CONFIG_64BIT
1667                 smmu->va_size = min(32UL, smmu->va_size);
1668 #endif
1669                 size = 0;
1670                 if (id & ID2_PTFS_4K)
1671                         size |= SZ_4K | SZ_2M | SZ_1G;
1672                 if (id & ID2_PTFS_16K)
1673                         size |= SZ_16K | SZ_32M;
1674                 if (id & ID2_PTFS_64K)
1675                         size |= SZ_64K | SZ_512M;
1676         }
1677
1678         arm_smmu_ops.pgsize_bitmap &= size;
1679         dev_notice(smmu->dev, "\tSupported page sizes: 0x%08lx\n", size);
1680
1681         if (smmu->features & ARM_SMMU_FEAT_TRANS_S1)
1682                 dev_notice(smmu->dev, "\tStage-1: %lu-bit VA -> %lu-bit IPA\n",
1683                            smmu->va_size, smmu->ipa_size);
1684
1685         if (smmu->features & ARM_SMMU_FEAT_TRANS_S2)
1686                 dev_notice(smmu->dev, "\tStage-2: %lu-bit IPA -> %lu-bit PA\n",
1687                            smmu->ipa_size, smmu->pa_size);
1688
1689         return 0;
1690 }
1691
1692 static const struct of_device_id arm_smmu_of_match[] = {
1693         { .compatible = "arm,smmu-v1", .data = (void *)ARM_SMMU_V1 },
1694         { .compatible = "arm,smmu-v2", .data = (void *)ARM_SMMU_V2 },
1695         { .compatible = "arm,mmu-400", .data = (void *)ARM_SMMU_V1 },
1696         { .compatible = "arm,mmu-401", .data = (void *)ARM_SMMU_V1 },
1697         { .compatible = "arm,mmu-500", .data = (void *)ARM_SMMU_V2 },
1698         { },
1699 };
1700 MODULE_DEVICE_TABLE(of, arm_smmu_of_match);
1701
1702 static int arm_smmu_device_dt_probe(struct platform_device *pdev)
1703 {
1704         const struct of_device_id *of_id;
1705         struct resource *res;
1706         struct arm_smmu_device *smmu;
1707         struct device *dev = &pdev->dev;
1708         struct rb_node *node;
1709         struct of_phandle_args masterspec;
1710         int num_irqs, i, err;
1711
1712         smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL);
1713         if (!smmu) {
1714                 dev_err(dev, "failed to allocate arm_smmu_device\n");
1715                 return -ENOMEM;
1716         }
1717         smmu->dev = dev;
1718
1719         of_id = of_match_node(arm_smmu_of_match, dev->of_node);
1720         smmu->version = (enum arm_smmu_arch_version)of_id->data;
1721
1722         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1723         smmu->base = devm_ioremap_resource(dev, res);
1724         if (IS_ERR(smmu->base))
1725                 return PTR_ERR(smmu->base);
1726         smmu->size = resource_size(res);
1727
1728         if (of_property_read_u32(dev->of_node, "#global-interrupts",
1729                                  &smmu->num_global_irqs)) {
1730                 dev_err(dev, "missing #global-interrupts property\n");
1731                 return -ENODEV;
1732         }
1733
1734         num_irqs = 0;
1735         while ((res = platform_get_resource(pdev, IORESOURCE_IRQ, num_irqs))) {
1736                 num_irqs++;
1737                 if (num_irqs > smmu->num_global_irqs)
1738                         smmu->num_context_irqs++;
1739         }
1740
1741         if (!smmu->num_context_irqs) {
1742                 dev_err(dev, "found %d interrupts but expected at least %d\n",
1743                         num_irqs, smmu->num_global_irqs + 1);
1744                 return -ENODEV;
1745         }
1746
1747         smmu->irqs = devm_kzalloc(dev, sizeof(*smmu->irqs) * num_irqs,
1748                                   GFP_KERNEL);
1749         if (!smmu->irqs) {
1750                 dev_err(dev, "failed to allocate %d irqs\n", num_irqs);
1751                 return -ENOMEM;
1752         }
1753
1754         for (i = 0; i < num_irqs; ++i) {
1755                 int irq = platform_get_irq(pdev, i);
1756
1757                 if (irq < 0) {
1758                         dev_err(dev, "failed to get irq index %d\n", i);
1759                         return -ENODEV;
1760                 }
1761                 smmu->irqs[i] = irq;
1762         }
1763
1764         err = arm_smmu_device_cfg_probe(smmu);
1765         if (err)
1766                 return err;
1767
1768         i = 0;
1769         smmu->masters = RB_ROOT;
1770         while (!of_parse_phandle_with_args(dev->of_node, "mmu-masters",
1771                                            "#stream-id-cells", i,
1772                                            &masterspec)) {
1773                 err = register_smmu_master(smmu, dev, &masterspec);
1774                 if (err) {
1775                         dev_err(dev, "failed to add master %s\n",
1776                                 masterspec.np->name);
1777                         goto out_put_masters;
1778                 }
1779
1780                 i++;
1781         }
1782         dev_notice(dev, "registered %d master devices\n", i);
1783
1784         parse_driver_options(smmu);
1785
1786         if (smmu->version > ARM_SMMU_V1 &&
1787             smmu->num_context_banks != smmu->num_context_irqs) {
1788                 dev_err(dev,
1789                         "found only %d context interrupt(s) but %d required\n",
1790                         smmu->num_context_irqs, smmu->num_context_banks);
1791                 err = -ENODEV;
1792                 goto out_put_masters;
1793         }
1794
1795         for (i = 0; i < smmu->num_global_irqs; ++i) {
1796                 err = request_irq(smmu->irqs[i],
1797                                   arm_smmu_global_fault,
1798                                   IRQF_SHARED,
1799                                   "arm-smmu global fault",
1800                                   smmu);
1801                 if (err) {
1802                         dev_err(dev, "failed to request global IRQ %d (%u)\n",
1803                                 i, smmu->irqs[i]);
1804                         goto out_free_irqs;
1805                 }
1806         }
1807
1808         INIT_LIST_HEAD(&smmu->list);
1809         spin_lock(&arm_smmu_devices_lock);
1810         list_add(&smmu->list, &arm_smmu_devices);
1811         spin_unlock(&arm_smmu_devices_lock);
1812
1813         arm_smmu_device_reset(smmu);
1814         return 0;
1815
1816 out_free_irqs:
1817         while (i--)
1818                 free_irq(smmu->irqs[i], smmu);
1819
1820 out_put_masters:
1821         for (node = rb_first(&smmu->masters); node; node = rb_next(node)) {
1822                 struct arm_smmu_master *master
1823                         = container_of(node, struct arm_smmu_master, node);
1824                 of_node_put(master->of_node);
1825         }
1826
1827         return err;
1828 }
1829
1830 static int arm_smmu_device_remove(struct platform_device *pdev)
1831 {
1832         int i;
1833         struct device *dev = &pdev->dev;
1834         struct arm_smmu_device *curr, *smmu = NULL;
1835         struct rb_node *node;
1836
1837         spin_lock(&arm_smmu_devices_lock);
1838         list_for_each_entry(curr, &arm_smmu_devices, list) {
1839                 if (curr->dev == dev) {
1840                         smmu = curr;
1841                         list_del(&smmu->list);
1842                         break;
1843                 }
1844         }
1845         spin_unlock(&arm_smmu_devices_lock);
1846
1847         if (!smmu)
1848                 return -ENODEV;
1849
1850         for (node = rb_first(&smmu->masters); node; node = rb_next(node)) {
1851                 struct arm_smmu_master *master
1852                         = container_of(node, struct arm_smmu_master, node);
1853                 of_node_put(master->of_node);
1854         }
1855
1856         if (!bitmap_empty(smmu->context_map, ARM_SMMU_MAX_CBS))
1857                 dev_err(dev, "removing device with active domains!\n");
1858
1859         for (i = 0; i < smmu->num_global_irqs; ++i)
1860                 free_irq(smmu->irqs[i], smmu);
1861
1862         /* Turn the thing off */
1863         writel(sCR0_CLIENTPD, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
1864         return 0;
1865 }
1866
1867 static struct platform_driver arm_smmu_driver = {
1868         .driver = {
1869                 .name           = "arm-smmu",
1870                 .of_match_table = of_match_ptr(arm_smmu_of_match),
1871         },
1872         .probe  = arm_smmu_device_dt_probe,
1873         .remove = arm_smmu_device_remove,
1874 };
1875
1876 static int __init arm_smmu_init(void)
1877 {
1878         struct device_node *np;
1879         int ret;
1880
1881         /*
1882          * Play nice with systems that don't have an ARM SMMU by checking that
1883          * an ARM SMMU exists in the system before proceeding with the driver
1884          * and IOMMU bus operation registration.
1885          */
1886         np = of_find_matching_node(NULL, arm_smmu_of_match);
1887         if (!np)
1888                 return 0;
1889
1890         of_node_put(np);
1891
1892         ret = platform_driver_register(&arm_smmu_driver);
1893         if (ret)
1894                 return ret;
1895
1896         /* Oh, for a proper bus abstraction */
1897         if (!iommu_present(&platform_bus_type))
1898                 bus_set_iommu(&platform_bus_type, &arm_smmu_ops);
1899
1900 #ifdef CONFIG_ARM_AMBA
1901         if (!iommu_present(&amba_bustype))
1902                 bus_set_iommu(&amba_bustype, &arm_smmu_ops);
1903 #endif
1904
1905 #ifdef CONFIG_PCI
1906         if (!iommu_present(&pci_bus_type))
1907                 bus_set_iommu(&pci_bus_type, &arm_smmu_ops);
1908 #endif
1909
1910         return 0;
1911 }
1912
1913 static void __exit arm_smmu_exit(void)
1914 {
1915         return platform_driver_unregister(&arm_smmu_driver);
1916 }
1917
1918 subsys_initcall(arm_smmu_init);
1919 module_exit(arm_smmu_exit);
1920
1921 MODULE_DESCRIPTION("IOMMU API for ARM architected SMMU implementations");
1922 MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>");
1923 MODULE_LICENSE("GPL v2");