drivers/gpu/drm/i915/display/intel_hdmi.c

   1 /*
   2  * Copyright 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2009 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <eric@anholt.net>
  26  *      Jesse Barnes <jesse.barnes@intel.com>
  27  */
  28
  29 #include <linux/delay.h>
  30 #include <linux/hdmi.h>
  31 #include <linux/i2c.h>
  32 #include <linux/slab.h>
  33
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_crtc.h>
  36 #include <drm/drm_edid.h>
  37 #include <drm/drm_hdcp.h>
  38 #include <drm/drm_scdc_helper.h>
  39 #include <drm/i915_drm.h>
  40 #include <drm/intel_lpe_audio.h>
  41
  42 #include "i915_debugfs.h"
  43 #include "i915_drv.h"
  44 #include "intel_atomic.h"
  45 #include "intel_audio.h"
  46 #include "intel_connector.h"
  47 #include "intel_ddi.h"
  48 #include "intel_display_types.h"
  49 #include "intel_dp.h"
  50 #include "intel_dpio_phy.h"
  51 #include "intel_fifo_underrun.h"
  52 #include "intel_gmbus.h"
  53 #include "intel_hdcp.h"
  54 #include "intel_hdmi.h"
  55 #include "intel_hotplug.h"
  56 #include "intel_lspcon.h"
  57 #include "intel_panel.h"
  58 #include "intel_sdvo.h"
  59 #include "intel_sideband.h"
  60
  61 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
  62 {
  63         return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
  64 }
  65
  66 static void
  67 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
  68 {
  69         struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
  70         struct drm_i915_private *dev_priv = to_i915(dev);
  71         u32 enabled_bits;
  72
  73         enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
  74
  75         WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
  76              "HDMI port enabled, expecting disabled\n");
  77 }
  78
  79 static void
  80 assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv,
  81                                      enum transcoder cpu_transcoder)
  82 {
  83         WARN(I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)) &
  84              TRANS_DDI_FUNC_ENABLE,
  85              "HDMI transcoder function enabled, expecting disabled\n");
  86 }
  87
  88 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
  89 {
  90         struct intel_digital_port *intel_dig_port =
  91                 container_of(encoder, struct intel_digital_port, base.base);
  92         return &intel_dig_port->hdmi;
  93 }
  94
  95 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
  96 {
  97         return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
  98 }
  99
 100 static u32 g4x_infoframe_index(unsigned int type)
 101 {
 102         switch (type) {
 103         case HDMI_PACKET_TYPE_GAMUT_METADATA:
 104                 return VIDEO_DIP_SELECT_GAMUT;
 105         case HDMI_INFOFRAME_TYPE_AVI:
 106                 return VIDEO_DIP_SELECT_AVI;
 107         case HDMI_INFOFRAME_TYPE_SPD:
 108                 return VIDEO_DIP_SELECT_SPD;
 109         case HDMI_INFOFRAME_TYPE_VENDOR:
 110                 return VIDEO_DIP_SELECT_VENDOR;
 111         default:
 112                 MISSING_CASE(type);
 113                 return 0;
 114         }
 115 }
 116
 117 static u32 g4x_infoframe_enable(unsigned int type)
 118 {
 119         switch (type) {
 120         case HDMI_PACKET_TYPE_GENERAL_CONTROL:
 121                 return VIDEO_DIP_ENABLE_GCP;
 122         case HDMI_PACKET_TYPE_GAMUT_METADATA:
 123                 return VIDEO_DIP_ENABLE_GAMUT;
 124         case DP_SDP_VSC:
 125                 return 0;
 126         case HDMI_INFOFRAME_TYPE_AVI:
 127                 return VIDEO_DIP_ENABLE_AVI;
 128         case HDMI_INFOFRAME_TYPE_SPD:
 129                 return VIDEO_DIP_ENABLE_SPD;
 130         case HDMI_INFOFRAME_TYPE_VENDOR:
 131                 return VIDEO_DIP_ENABLE_VENDOR;
 132         case HDMI_INFOFRAME_TYPE_DRM:
 133                 return 0;
 134         default:
 135                 MISSING_CASE(type);
 136                 return 0;
 137         }
 138 }
 139
 140 static u32 hsw_infoframe_enable(unsigned int type)
 141 {
 142         switch (type) {
 143         case HDMI_PACKET_TYPE_GENERAL_CONTROL:
 144                 return VIDEO_DIP_ENABLE_GCP_HSW;
 145         case HDMI_PACKET_TYPE_GAMUT_METADATA:
 146                 return VIDEO_DIP_ENABLE_GMP_HSW;
 147         case DP_SDP_VSC:
 148                 return VIDEO_DIP_ENABLE_VSC_HSW;
 149         case DP_SDP_PPS:
 150                 return VDIP_ENABLE_PPS;
 151         case HDMI_INFOFRAME_TYPE_AVI:
 152                 return VIDEO_DIP_ENABLE_AVI_HSW;
 153         case HDMI_INFOFRAME_TYPE_SPD:
 154                 return VIDEO_DIP_ENABLE_SPD_HSW;
 155         case HDMI_INFOFRAME_TYPE_VENDOR:
 156                 return VIDEO_DIP_ENABLE_VS_HSW;
 157         case HDMI_INFOFRAME_TYPE_DRM:
 158                 return VIDEO_DIP_ENABLE_DRM_GLK;
 159         default:
 160                 MISSING_CASE(type);
 161                 return 0;
 162         }
 163 }
 164
 165 static i915_reg_t
 166 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
 167                  enum transcoder cpu_transcoder,
 168                  unsigned int type,
 169                  int i)
 170 {
 171         switch (type) {
 172         case HDMI_PACKET_TYPE_GAMUT_METADATA:
 173                 return HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder, i);
 174         case DP_SDP_VSC:
 175                 return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
 176         case DP_SDP_PPS:
 177                 return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i);
 178         case HDMI_INFOFRAME_TYPE_AVI:
 179                 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
 180         case HDMI_INFOFRAME_TYPE_SPD:
 181                 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
 182         case HDMI_INFOFRAME_TYPE_VENDOR:
 183                 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
 184         case HDMI_INFOFRAME_TYPE_DRM:
 185                 return GLK_TVIDEO_DIP_DRM_DATA(cpu_transcoder, i);
 186         default:
 187                 MISSING_CASE(type);
 188                 return INVALID_MMIO_REG;
 189         }
 190 }
 191
 192 static int hsw_dip_data_size(struct drm_i915_private *dev_priv,
 193                              unsigned int type)
 194 {
 195         switch (type) {
 196         case DP_SDP_VSC:
 197                 return VIDEO_DIP_VSC_DATA_SIZE;
 198         case DP_SDP_PPS:
 199                 return VIDEO_DIP_PPS_DATA_SIZE;
 200         case HDMI_PACKET_TYPE_GAMUT_METADATA:
 201                 if (INTEL_GEN(dev_priv) >= 11)
 202                         return VIDEO_DIP_GMP_DATA_SIZE;
 203                 else
 204                         return VIDEO_DIP_DATA_SIZE;
 205         default:
 206                 return VIDEO_DIP_DATA_SIZE;
 207         }
 208 }
 209
 210 static void g4x_write_infoframe(struct intel_encoder *encoder,
 211                                 const struct intel_crtc_state *crtc_state,
 212                                 unsigned int type,
 213                                 const void *frame, ssize_t len)
 214 {
 215         const u32 *data = frame;
 216         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 217         u32 val = I915_READ(VIDEO_DIP_CTL);
 218         int i;
 219
 220         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 221
 222         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 223         val |= g4x_infoframe_index(type);
 224
 225         val &= ~g4x_infoframe_enable(type);
 226
 227         I915_WRITE(VIDEO_DIP_CTL, val);
 228
 229         for (i = 0; i < len; i += 4) {
 230                 I915_WRITE(VIDEO_DIP_DATA, *data);
 231                 data++;
 232         }
 233         /* Write every possible data byte to force correct ECC calculation. */
 234         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 235                 I915_WRITE(VIDEO_DIP_DATA, 0);
 236
 237         val |= g4x_infoframe_enable(type);
 238         val &= ~VIDEO_DIP_FREQ_MASK;
 239         val |= VIDEO_DIP_FREQ_VSYNC;
 240
 241         I915_WRITE(VIDEO_DIP_CTL, val);
 242         POSTING_READ(VIDEO_DIP_CTL);
 243 }
 244
 245 static void g4x_read_infoframe(struct intel_encoder *encoder,
 246                                const struct intel_crtc_state *crtc_state,
 247                                unsigned int type,
 248                                void *frame, ssize_t len)
 249 {
 250         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 251         u32 val, *data = frame;
 252         int i;
 253
 254         val = I915_READ(VIDEO_DIP_CTL);
 255
 256         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 257         val |= g4x_infoframe_index(type);
 258
 259         I915_WRITE(VIDEO_DIP_CTL, val);
 260
 261         for (i = 0; i < len; i += 4)
 262                 *data++ = I915_READ(VIDEO_DIP_DATA);
 263 }
 264
 265 static u32 g4x_infoframes_enabled(struct intel_encoder *encoder,
 266                                   const struct intel_crtc_state *pipe_config)
 267 {
 268         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 269         u32 val = I915_READ(VIDEO_DIP_CTL);
 270
 271         if ((val & VIDEO_DIP_ENABLE) == 0)
 272                 return 0;
 273
 274         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
 275                 return 0;
 276
 277         return val & (VIDEO_DIP_ENABLE_AVI |
 278                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 279 }
 280
 281 static void ibx_write_infoframe(struct intel_encoder *encoder,
 282                                 const struct intel_crtc_state *crtc_state,
 283                                 unsigned int type,
 284                                 const void *frame, ssize_t len)
 285 {
 286         const u32 *data = frame;
 287         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 288         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 289         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 290         u32 val = I915_READ(reg);
 291         int i;
 292
 293         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 294
 295         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 296         val |= g4x_infoframe_index(type);
 297
 298         val &= ~g4x_infoframe_enable(type);
 299
 300         I915_WRITE(reg, val);
 301
 302         for (i = 0; i < len; i += 4) {
 303                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 304                 data++;
 305         }
 306         /* Write every possible data byte to force correct ECC calculation. */
 307         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 308                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 309
 310         val |= g4x_infoframe_enable(type);
 311         val &= ~VIDEO_DIP_FREQ_MASK;
 312         val |= VIDEO_DIP_FREQ_VSYNC;
 313
 314         I915_WRITE(reg, val);
 315         POSTING_READ(reg);
 316 }
 317
 318 static void ibx_read_infoframe(struct intel_encoder *encoder,
 319                                const struct intel_crtc_state *crtc_state,
 320                                unsigned int type,
 321                                void *frame, ssize_t len)
 322 {
 323         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 324         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 325         u32 val, *data = frame;
 326         int i;
 327
 328         val = I915_READ(TVIDEO_DIP_CTL(crtc->pipe));
 329
 330         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 331         val |= g4x_infoframe_index(type);
 332
 333         I915_WRITE(TVIDEO_DIP_CTL(crtc->pipe), val);
 334
 335         for (i = 0; i < len; i += 4)
 336                 *data++ = I915_READ(TVIDEO_DIP_DATA(crtc->pipe));
 337 }
 338
 339 static u32 ibx_infoframes_enabled(struct intel_encoder *encoder,
 340                                   const struct intel_crtc_state *pipe_config)
 341 {
 342         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 343         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
 344         i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
 345         u32 val = I915_READ(reg);
 346
 347         if ((val & VIDEO_DIP_ENABLE) == 0)
 348                 return 0;
 349
 350         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
 351                 return 0;
 352
 353         return val & (VIDEO_DIP_ENABLE_AVI |
 354                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 355                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 356 }
 357
 358 static void cpt_write_infoframe(struct intel_encoder *encoder,
 359                                 const struct intel_crtc_state *crtc_state,
 360                                 unsigned int type,
 361                                 const void *frame, ssize_t len)
 362 {
 363         const u32 *data = frame;
 364         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 365         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 366         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 367         u32 val = I915_READ(reg);
 368         int i;
 369
 370         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 371
 372         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 373         val |= g4x_infoframe_index(type);
 374
 375         /* The DIP control register spec says that we need to update the AVI
 376          * infoframe without clearing its enable bit */
 377         if (type != HDMI_INFOFRAME_TYPE_AVI)
 378                 val &= ~g4x_infoframe_enable(type);
 379
 380         I915_WRITE(reg, val);
 381
 382         for (i = 0; i < len; i += 4) {
 383                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 384                 data++;
 385         }
 386         /* Write every possible data byte to force correct ECC calculation. */
 387         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 388                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 389
 390         val |= g4x_infoframe_enable(type);
 391         val &= ~VIDEO_DIP_FREQ_MASK;
 392         val |= VIDEO_DIP_FREQ_VSYNC;
 393
 394         I915_WRITE(reg, val);
 395         POSTING_READ(reg);
 396 }
 397
 398 static void cpt_read_infoframe(struct intel_encoder *encoder,
 399                                const struct intel_crtc_state *crtc_state,
 400                                unsigned int type,
 401                                void *frame, ssize_t len)
 402 {
 403         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 404         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 405         u32 val, *data = frame;
 406         int i;
 407
 408         val = I915_READ(TVIDEO_DIP_CTL(crtc->pipe));
 409
 410         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 411         val |= g4x_infoframe_index(type);
 412
 413         I915_WRITE(TVIDEO_DIP_CTL(crtc->pipe), val);
 414
 415         for (i = 0; i < len; i += 4)
 416                 *data++ = I915_READ(TVIDEO_DIP_DATA(crtc->pipe));
 417 }
 418
 419 static u32 cpt_infoframes_enabled(struct intel_encoder *encoder,
 420                                   const struct intel_crtc_state *pipe_config)
 421 {
 422         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 423         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
 424         u32 val = I915_READ(TVIDEO_DIP_CTL(pipe));
 425
 426         if ((val & VIDEO_DIP_ENABLE) == 0)
 427                 return 0;
 428
 429         return val & (VIDEO_DIP_ENABLE_AVI |
 430                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 431                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 432 }
 433
 434 static void vlv_write_infoframe(struct intel_encoder *encoder,
 435                                 const struct intel_crtc_state *crtc_state,
 436                                 unsigned int type,
 437                                 const void *frame, ssize_t len)
 438 {
 439         const u32 *data = frame;
 440         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 441         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 442         i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 443         u32 val = I915_READ(reg);
 444         int i;
 445
 446         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 447
 448         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 449         val |= g4x_infoframe_index(type);
 450
 451         val &= ~g4x_infoframe_enable(type);
 452
 453         I915_WRITE(reg, val);
 454
 455         for (i = 0; i < len; i += 4) {
 456                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 457                 data++;
 458         }
 459         /* Write every possible data byte to force correct ECC calculation. */
 460         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 461                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 462
 463         val |= g4x_infoframe_enable(type);
 464         val &= ~VIDEO_DIP_FREQ_MASK;
 465         val |= VIDEO_DIP_FREQ_VSYNC;
 466
 467         I915_WRITE(reg, val);
 468         POSTING_READ(reg);
 469 }
 470
 471 static void vlv_read_infoframe(struct intel_encoder *encoder,
 472                                const struct intel_crtc_state *crtc_state,
 473                                unsigned int type,
 474                                void *frame, ssize_t len)
 475 {
 476         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 477         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 478         u32 val, *data = frame;
 479         int i;
 480
 481         val = I915_READ(VLV_TVIDEO_DIP_CTL(crtc->pipe));
 482
 483         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 484         val |= g4x_infoframe_index(type);
 485
 486         I915_WRITE(VLV_TVIDEO_DIP_CTL(crtc->pipe), val);
 487
 488         for (i = 0; i < len; i += 4)
 489                 *data++ = I915_READ(VLV_TVIDEO_DIP_DATA(crtc->pipe));
 490 }
 491
 492 static u32 vlv_infoframes_enabled(struct intel_encoder *encoder,
 493                                   const struct intel_crtc_state *pipe_config)
 494 {
 495         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 496         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
 497         u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe));
 498
 499         if ((val & VIDEO_DIP_ENABLE) == 0)
 500                 return 0;
 501
 502         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
 503                 return 0;
 504
 505         return val & (VIDEO_DIP_ENABLE_AVI |
 506                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 507                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 508 }
 509
 510 static void hsw_write_infoframe(struct intel_encoder *encoder,
 511                                 const struct intel_crtc_state *crtc_state,
 512                                 unsigned int type,
 513                                 const void *frame, ssize_t len)
 514 {
 515         const u32 *data = frame;
 516         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 517         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 518         i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
 519         int data_size;
 520         int i;
 521         u32 val = I915_READ(ctl_reg);
 522
 523         data_size = hsw_dip_data_size(dev_priv, type);
 524
 525         WARN_ON(len > data_size);
 526
 527         val &= ~hsw_infoframe_enable(type);
 528         I915_WRITE(ctl_reg, val);
 529
 530         for (i = 0; i < len; i += 4) {
 531                 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
 532                                             type, i >> 2), *data);
 533                 data++;
 534         }
 535         /* Write every possible data byte to force correct ECC calculation. */
 536         for (; i < data_size; i += 4)
 537                 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
 538                                             type, i >> 2), 0);
 539
 540         val |= hsw_infoframe_enable(type);
 541         I915_WRITE(ctl_reg, val);
 542         POSTING_READ(ctl_reg);
 543 }
 544
 545 static void hsw_read_infoframe(struct intel_encoder *encoder,
 546                                const struct intel_crtc_state *crtc_state,
 547                                unsigned int type,
 548                                void *frame, ssize_t len)
 549 {
 550         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 551         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 552         u32 val, *data = frame;
 553         int i;
 554
 555         val = I915_READ(HSW_TVIDEO_DIP_CTL(cpu_transcoder));
 556
 557         for (i = 0; i < len; i += 4)
 558                 *data++ = I915_READ(hsw_dip_data_reg(dev_priv, cpu_transcoder,
 559                                                      type, i >> 2));
 560 }
 561
 562 static u32 hsw_infoframes_enabled(struct intel_encoder *encoder,
 563                                   const struct intel_crtc_state *pipe_config)
 564 {
 565         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 566         u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
 567         u32 mask;
 568
 569         mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
 570                 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
 571                 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
 572
 573         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
 574                 mask |= VIDEO_DIP_ENABLE_DRM_GLK;
 575
 576         return val & mask;
 577 }
 578
 579 static const u8 infoframe_type_to_idx[] = {
 580         HDMI_PACKET_TYPE_GENERAL_CONTROL,
 581         HDMI_PACKET_TYPE_GAMUT_METADATA,
 582         DP_SDP_VSC,
 583         HDMI_INFOFRAME_TYPE_AVI,
 584         HDMI_INFOFRAME_TYPE_SPD,
 585         HDMI_INFOFRAME_TYPE_VENDOR,
 586         HDMI_INFOFRAME_TYPE_DRM,
 587 };
 588
 589 u32 intel_hdmi_infoframe_enable(unsigned int type)
 590 {
 591         int i;
 592
 593         for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
 594                 if (infoframe_type_to_idx[i] == type)
 595                         return BIT(i);
 596         }
 597
 598         return 0;
 599 }
 600
 601 u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder,
 602                                   const struct intel_crtc_state *crtc_state)
 603 {
 604         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 605         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
 606         u32 val, ret = 0;
 607         int i;
 608
 609         val = dig_port->infoframes_enabled(encoder, crtc_state);
 610
 611         /* map from hardware bits to dip idx */
 612         for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
 613                 unsigned int type = infoframe_type_to_idx[i];
 614
 615                 if (HAS_DDI(dev_priv)) {
 616                         if (val & hsw_infoframe_enable(type))
 617                                 ret |= BIT(i);
 618                 } else {
 619                         if (val & g4x_infoframe_enable(type))
 620                                 ret |= BIT(i);
 621                 }
 622         }
 623
 624         return ret;
 625 }
 626
 627 /*
 628  * The data we write to the DIP data buffer registers is 1 byte bigger than the
 629  * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
 630  * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
 631  * used for both technologies.
 632  *
 633  * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
 634  * DW1:       DB3       | DB2 | DB1 | DB0
 635  * DW2:       DB7       | DB6 | DB5 | DB4
 636  * DW3: ...
 637  *
 638  * (HB is Header Byte, DB is Data Byte)
 639  *
 640  * The hdmi pack() functions don't know about that hardware specific hole so we
 641  * trick them by giving an offset into the buffer and moving back the header
 642  * bytes by one.
 643  */
 644 static void intel_write_infoframe(struct intel_encoder *encoder,
 645                                   const struct intel_crtc_state *crtc_state,
 646                                   enum hdmi_infoframe_type type,
 647                                   const union hdmi_infoframe *frame)
 648 {
 649         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
 650         u8 buffer[VIDEO_DIP_DATA_SIZE];
 651         ssize_t len;
 652
 653         if ((crtc_state->infoframes.enable &
 654              intel_hdmi_infoframe_enable(type)) == 0)
 655                 return;
 656
 657         if (WARN_ON(frame->any.type != type))
 658                 return;
 659
 660         /* see comment above for the reason for this offset */
 661         len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1);
 662         if (WARN_ON(len < 0))
 663                 return;
 664
 665         /* Insert the 'hole' (see big comment above) at position 3 */
 666         memmove(&buffer[0], &buffer[1], 3);
 667         buffer[3] = 0;
 668         len++;
 669
 670         intel_dig_port->write_infoframe(encoder, crtc_state, type, buffer, len);
 671 }
 672
 673 void intel_read_infoframe(struct intel_encoder *encoder,
 674                           const struct intel_crtc_state *crtc_state,
 675                           enum hdmi_infoframe_type type,
 676                           union hdmi_infoframe *frame)
 677 {
 678         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
 679         u8 buffer[VIDEO_DIP_DATA_SIZE];
 680         int ret;
 681
 682         if ((crtc_state->infoframes.enable &
 683              intel_hdmi_infoframe_enable(type)) == 0)
 684                 return;
 685
 686         intel_dig_port->read_infoframe(encoder, crtc_state,
 687                                        type, buffer, sizeof(buffer));
 688
 689         /* Fill the 'hole' (see big comment above) at position 3 */
 690         memmove(&buffer[1], &buffer[0], 3);
 691
 692         /* see comment above for the reason for this offset */
 693         ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1);
 694         if (ret) {
 695                 DRM_DEBUG_KMS("Failed to unpack infoframe type 0x%02x\n", type);
 696                 return;
 697         }
 698
 699         if (frame->any.type != type)
 700                 DRM_DEBUG_KMS("Found the wrong infoframe type 0x%x (expected 0x%02x)\n",
 701                               frame->any.type, type);
 702 }
 703
 704 static bool
 705 intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder,
 706                                  struct intel_crtc_state *crtc_state,
 707                                  struct drm_connector_state *conn_state)
 708 {
 709         struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;
 710         const struct drm_display_mode *adjusted_mode =
 711                 &crtc_state->base.adjusted_mode;
 712         struct drm_connector *connector = conn_state->connector;
 713         int ret;
 714
 715         if (!crtc_state->has_infoframe)
 716                 return true;
 717
 718         crtc_state->infoframes.enable |=
 719                 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI);
 720
 721         ret = drm_hdmi_avi_infoframe_from_display_mode(frame, connector,
 722                                                        adjusted_mode);
 723         if (ret)
 724                 return false;
 725
 726         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 727                 frame->colorspace = HDMI_COLORSPACE_YUV420;
 728         else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
 729                 frame->colorspace = HDMI_COLORSPACE_YUV444;
 730         else
 731                 frame->colorspace = HDMI_COLORSPACE_RGB;
 732
 733         drm_hdmi_avi_infoframe_colorspace(frame, conn_state);
 734
 735         /* nonsense combination */
 736         WARN_ON(crtc_state->limited_color_range &&
 737                 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
 738
 739         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) {
 740                 drm_hdmi_avi_infoframe_quant_range(frame, connector,
 741                                                    adjusted_mode,
 742                                                    crtc_state->limited_color_range ?
 743                                                    HDMI_QUANTIZATION_RANGE_LIMITED :
 744                                                    HDMI_QUANTIZATION_RANGE_FULL);
 745         } else {
 746                 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
 747                 frame->ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
 748         }
 749
 750         drm_hdmi_avi_infoframe_content_type(frame, conn_state);
 751
 752         /* TODO: handle pixel repetition for YCBCR420 outputs */
 753
 754         ret = hdmi_avi_infoframe_check(frame);
 755         if (WARN_ON(ret))
 756                 return false;
 757
 758         return true;
 759 }
 760
 761 static bool
 762 intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder,
 763                                  struct intel_crtc_state *crtc_state,
 764                                  struct drm_connector_state *conn_state)
 765 {
 766         struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd;
 767         int ret;
 768
 769         if (!crtc_state->has_infoframe)
 770                 return true;
 771
 772         crtc_state->infoframes.enable |=
 773                 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD);
 774
 775         ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx");
 776         if (WARN_ON(ret))
 777                 return false;
 778
 779         frame->sdi = HDMI_SPD_SDI_PC;
 780
 781         ret = hdmi_spd_infoframe_check(frame);
 782         if (WARN_ON(ret))
 783                 return false;
 784
 785         return true;
 786 }
 787
 788 static bool
 789 intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder,
 790                                   struct intel_crtc_state *crtc_state,
 791                                   struct drm_connector_state *conn_state)
 792 {
 793         struct hdmi_vendor_infoframe *frame =
 794                 &crtc_state->infoframes.hdmi.vendor.hdmi;
 795         const struct drm_display_info *info =
 796                 &conn_state->connector->display_info;
 797         int ret;
 798
 799         if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe)
 800                 return true;
 801
 802         crtc_state->infoframes.enable |=
 803                 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR);
 804
 805         ret = drm_hdmi_vendor_infoframe_from_display_mode(frame,
 806                                                           conn_state->connector,
 807                                                           &crtc_state->base.adjusted_mode);
 808         if (WARN_ON(ret))
 809                 return false;
 810
 811         ret = hdmi_vendor_infoframe_check(frame);
 812         if (WARN_ON(ret))
 813                 return false;
 814
 815         return true;
 816 }
 817
 818 static bool
 819 intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder,
 820                                  struct intel_crtc_state *crtc_state,
 821                                  struct drm_connector_state *conn_state)
 822 {
 823         struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm;
 824         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 825         int ret;
 826
 827         if (!(INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)))
 828                 return true;
 829
 830         if (!crtc_state->has_infoframe)
 831                 return true;
 832
 833         if (!conn_state->hdr_output_metadata)
 834                 return true;
 835
 836         crtc_state->infoframes.enable |=
 837                 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM);
 838
 839         ret = drm_hdmi_infoframe_set_hdr_metadata(frame, conn_state);
 840         if (ret < 0) {
 841                 DRM_DEBUG_KMS("couldn't set HDR metadata in infoframe\n");
 842                 return false;
 843         }
 844
 845         ret = hdmi_drm_infoframe_check(frame);
 846         if (WARN_ON(ret))
 847                 return false;
 848
 849         return true;
 850 }
 851
 852 static void g4x_set_infoframes(struct intel_encoder *encoder,
 853                                bool enable,
 854                                const struct intel_crtc_state *crtc_state,
 855                                const struct drm_connector_state *conn_state)
 856 {
 857         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 858         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
 859         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 860         i915_reg_t reg = VIDEO_DIP_CTL;
 861         u32 val = I915_READ(reg);
 862         u32 port = VIDEO_DIP_PORT(encoder->port);
 863
 864         assert_hdmi_port_disabled(intel_hdmi);
 865
 866         /* If the registers were not initialized yet, they might be zeroes,
 867          * which means we're selecting the AVI DIP and we're setting its
 868          * frequency to once. This seems to really confuse the HW and make
 869          * things stop working (the register spec says the AVI always needs to
 870          * be sent every VSync). So here we avoid writing to the register more
 871          * than we need and also explicitly select the AVI DIP and explicitly
 872          * set its frequency to every VSync. Avoiding to write it twice seems to
 873          * be enough to solve the problem, but being defensive shouldn't hurt us
 874          * either. */
 875         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 876
 877         if (!enable) {
 878                 if (!(val & VIDEO_DIP_ENABLE))
 879                         return;
 880                 if (port != (val & VIDEO_DIP_PORT_MASK)) {
 881                         DRM_DEBUG_KMS("video DIP still enabled on port %c\n",
 882                                       (val & VIDEO_DIP_PORT_MASK) >> 29);
 883                         return;
 884                 }
 885                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 886                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 887                 I915_WRITE(reg, val);
 888                 POSTING_READ(reg);
 889                 return;
 890         }
 891
 892         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 893                 if (val & VIDEO_DIP_ENABLE) {
 894                         DRM_DEBUG_KMS("video DIP already enabled on port %c\n",
 895                                       (val & VIDEO_DIP_PORT_MASK) >> 29);
 896                         return;
 897                 }
 898                 val &= ~VIDEO_DIP_PORT_MASK;
 899                 val |= port;
 900         }
 901
 902         val |= VIDEO_DIP_ENABLE;
 903         val &= ~(VIDEO_DIP_ENABLE_AVI |
 904                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 905
 906         I915_WRITE(reg, val);
 907         POSTING_READ(reg);
 908
 909         intel_write_infoframe(encoder, crtc_state,
 910                               HDMI_INFOFRAME_TYPE_AVI,
 911                               &crtc_state->infoframes.avi);
 912         intel_write_infoframe(encoder, crtc_state,
 913                               HDMI_INFOFRAME_TYPE_SPD,
 914                               &crtc_state->infoframes.spd);
 915         intel_write_infoframe(encoder, crtc_state,
 916                               HDMI_INFOFRAME_TYPE_VENDOR,
 917                               &crtc_state->infoframes.hdmi);
 918 }
 919
 920 /*
 921  * Determine if default_phase=1 can be indicated in the GCP infoframe.
 922  *
 923  * From HDMI specification 1.4a:
 924  * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
 925  * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
 926  * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
 927  * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
 928  *   phase of 0
 929  */
 930 static bool gcp_default_phase_possible(int pipe_bpp,
 931                                        const struct drm_display_mode *mode)
 932 {
 933         unsigned int pixels_per_group;
 934
 935         switch (pipe_bpp) {
 936         case 30:
 937                 /* 4 pixels in 5 clocks */
 938                 pixels_per_group = 4;
 939                 break;
 940         case 36:
 941                 /* 2 pixels in 3 clocks */
 942                 pixels_per_group = 2;
 943                 break;
 944         case 48:
 945                 /* 1 pixel in 2 clocks */
 946                 pixels_per_group = 1;
 947                 break;
 948         default:
 949                 /* phase information not relevant for 8bpc */
 950                 return false;
 951         }
 952
 953         return mode->crtc_hdisplay % pixels_per_group == 0 &&
 954                 mode->crtc_htotal % pixels_per_group == 0 &&
 955                 mode->crtc_hblank_start % pixels_per_group == 0 &&
 956                 mode->crtc_hblank_end % pixels_per_group == 0 &&
 957                 mode->crtc_hsync_start % pixels_per_group == 0 &&
 958                 mode->crtc_hsync_end % pixels_per_group == 0 &&
 959                 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
 960                  mode->crtc_htotal/2 % pixels_per_group == 0);
 961 }
 962
 963 static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder,
 964                                          const struct intel_crtc_state *crtc_state,
 965                                          const struct drm_connector_state *conn_state)
 966 {
 967         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 968         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 969         i915_reg_t reg;
 970
 971         if ((crtc_state->infoframes.enable &
 972              intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
 973                 return false;
 974
 975         if (HAS_DDI(dev_priv))
 976                 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
 977         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 978                 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
 979         else if (HAS_PCH_SPLIT(dev_priv))
 980                 reg = TVIDEO_DIP_GCP(crtc->pipe);
 981         else
 982                 return false;
 983
 984         I915_WRITE(reg, crtc_state->infoframes.gcp);
 985
 986         return true;
 987 }
 988
 989 void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder,
 990                                    struct intel_crtc_state *crtc_state)
 991 {
 992         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 993         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 994         i915_reg_t reg;
 995
 996         if ((crtc_state->infoframes.enable &
 997              intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
 998                 return;
 999
1000         if (HAS_DDI(dev_priv))
1001                 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
1002         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1003                 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
1004         else if (HAS_PCH_SPLIT(dev_priv))
1005                 reg = TVIDEO_DIP_GCP(crtc->pipe);
1006         else
1007                 return;
1008
1009         crtc_state->infoframes.gcp = I915_READ(reg);
1010 }
1011
1012 static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder,
1013                                              struct intel_crtc_state *crtc_state,
1014                                              struct drm_connector_state *conn_state)
1015 {
1016         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1017
1018         if (IS_G4X(dev_priv) || !crtc_state->has_infoframe)
1019                 return;
1020
1021         crtc_state->infoframes.enable |=
1022                 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL);
1023
1024         /* Indicate color indication for deep color mode */
1025         if (crtc_state->pipe_bpp > 24)
1026                 crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION;
1027
1028         /* Enable default_phase whenever the display mode is suitably aligned */
1029         if (gcp_default_phase_possible(crtc_state->pipe_bpp,
1030                                        &crtc_state->base.adjusted_mode))
1031                 crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE;
1032 }
1033
1034 static void ibx_set_infoframes(struct intel_encoder *encoder,
1035                                bool enable,
1036                                const struct intel_crtc_state *crtc_state,
1037                                const struct drm_connector_state *conn_state)
1038 {
1039         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1040         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
1041         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
1042         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
1043         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
1044         u32 val = I915_READ(reg);
1045         u32 port = VIDEO_DIP_PORT(encoder->port);
1046
1047         assert_hdmi_port_disabled(intel_hdmi);
1048
1049         /* See the big comment in g4x_set_infoframes() */
1050         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1051
1052         if (!enable) {
1053                 if (!(val & VIDEO_DIP_ENABLE))
1054                         return;
1055                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1056                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1057                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1058                 I915_WRITE(reg, val);
1059                 POSTING_READ(reg);
1060                 return;
1061         }
1062
1063         if (port != (val & VIDEO_DIP_PORT_MASK)) {
1064                 WARN(val & VIDEO_DIP_ENABLE,
1065                      "DIP already enabled on port %c\n",
1066                      (val & VIDEO_DIP_PORT_MASK) >> 29);
1067                 val &= ~VIDEO_DIP_PORT_MASK;
1068                 val |= port;
1069         }
1070
1071         val |= VIDEO_DIP_ENABLE;
1072         val &= ~(VIDEO_DIP_ENABLE_AVI |
1073                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1074                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1075
1076         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1077                 val |= VIDEO_DIP_ENABLE_GCP;
1078
1079         I915_WRITE(reg, val);
1080         POSTING_READ(reg);
1081
1082         intel_write_infoframe(encoder, crtc_state,
1083                               HDMI_INFOFRAME_TYPE_AVI,
1084                               &crtc_state->infoframes.avi);
1085         intel_write_infoframe(encoder, crtc_state,
1086                               HDMI_INFOFRAME_TYPE_SPD,
1087                               &crtc_state->infoframes.spd);
1088         intel_write_infoframe(encoder, crtc_state,
1089                               HDMI_INFOFRAME_TYPE_VENDOR,
1090                               &crtc_state->infoframes.hdmi);
1091 }
1092
1093 static void cpt_set_infoframes(struct intel_encoder *encoder,
1094                                bool enable,
1095                                const struct intel_crtc_state *crtc_state,
1096                                const struct drm_connector_state *conn_state)
1097 {
1098         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1099         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
1100         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1101         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
1102         u32 val = I915_READ(reg);
1103
1104         assert_hdmi_port_disabled(intel_hdmi);
1105
1106         /* See the big comment in g4x_set_infoframes() */
1107         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1108
1109         if (!enable) {
1110                 if (!(val & VIDEO_DIP_ENABLE))
1111                         return;
1112                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1113                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1114                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1115                 I915_WRITE(reg, val);
1116                 POSTING_READ(reg);
1117                 return;
1118         }
1119
1120         /* Set both together, unset both together: see the spec. */
1121         val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
1122         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1123                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1124
1125         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1126                 val |= VIDEO_DIP_ENABLE_GCP;
1127
1128         I915_WRITE(reg, val);
1129         POSTING_READ(reg);
1130
1131         intel_write_infoframe(encoder, crtc_state,
1132                               HDMI_INFOFRAME_TYPE_AVI,
1133                               &crtc_state->infoframes.avi);
1134         intel_write_infoframe(encoder, crtc_state,
1135                               HDMI_INFOFRAME_TYPE_SPD,
1136                               &crtc_state->infoframes.spd);
1137         intel_write_infoframe(encoder, crtc_state,
1138                               HDMI_INFOFRAME_TYPE_VENDOR,
1139                               &crtc_state->infoframes.hdmi);
1140 }
1141
1142 static void vlv_set_infoframes(struct intel_encoder *encoder,
1143                                bool enable,
1144                                const struct intel_crtc_state *crtc_state,
1145                                const struct drm_connector_state *conn_state)
1146 {
1147         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1148         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
1149         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1150         i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
1151         u32 val = I915_READ(reg);
1152         u32 port = VIDEO_DIP_PORT(encoder->port);
1153
1154         assert_hdmi_port_disabled(intel_hdmi);
1155
1156         /* See the big comment in g4x_set_infoframes() */
1157         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1158
1159         if (!enable) {
1160                 if (!(val & VIDEO_DIP_ENABLE))
1161                         return;
1162                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1163                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1164                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1165                 I915_WRITE(reg, val);
1166                 POSTING_READ(reg);
1167                 return;
1168         }
1169
1170         if (port != (val & VIDEO_DIP_PORT_MASK)) {
1171                 WARN(val & VIDEO_DIP_ENABLE,
1172                      "DIP already enabled on port %c\n",
1173                      (val & VIDEO_DIP_PORT_MASK) >> 29);
1174                 val &= ~VIDEO_DIP_PORT_MASK;
1175                 val |= port;
1176         }
1177
1178         val |= VIDEO_DIP_ENABLE;
1179         val &= ~(VIDEO_DIP_ENABLE_AVI |
1180                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1181                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1182
1183         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1184                 val |= VIDEO_DIP_ENABLE_GCP;
1185
1186         I915_WRITE(reg, val);
1187         POSTING_READ(reg);
1188
1189         intel_write_infoframe(encoder, crtc_state,
1190                               HDMI_INFOFRAME_TYPE_AVI,
1191                               &crtc_state->infoframes.avi);
1192         intel_write_infoframe(encoder, crtc_state,
1193                               HDMI_INFOFRAME_TYPE_SPD,
1194                               &crtc_state->infoframes.spd);
1195         intel_write_infoframe(encoder, crtc_state,
1196                               HDMI_INFOFRAME_TYPE_VENDOR,
1197                               &crtc_state->infoframes.hdmi);
1198 }
1199
1200 static void hsw_set_infoframes(struct intel_encoder *encoder,
1201                                bool enable,
1202                                const struct intel_crtc_state *crtc_state,
1203                                const struct drm_connector_state *conn_state)
1204 {
1205         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1206         i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
1207         u32 val = I915_READ(reg);
1208
1209         assert_hdmi_transcoder_func_disabled(dev_priv,
1210                                              crtc_state->cpu_transcoder);
1211
1212         val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
1213                  VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
1214                  VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
1215                  VIDEO_DIP_ENABLE_DRM_GLK);
1216
1217         if (!enable) {
1218                 I915_WRITE(reg, val);
1219                 POSTING_READ(reg);
1220                 return;
1221         }
1222
1223         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1224                 val |= VIDEO_DIP_ENABLE_GCP_HSW;
1225
1226         I915_WRITE(reg, val);
1227         POSTING_READ(reg);
1228
1229         intel_write_infoframe(encoder, crtc_state,
1230                               HDMI_INFOFRAME_TYPE_AVI,
1231                               &crtc_state->infoframes.avi);
1232         intel_write_infoframe(encoder, crtc_state,
1233                               HDMI_INFOFRAME_TYPE_SPD,
1234                               &crtc_state->infoframes.spd);
1235         intel_write_infoframe(encoder, crtc_state,
1236                               HDMI_INFOFRAME_TYPE_VENDOR,
1237                               &crtc_state->infoframes.hdmi);
1238         intel_write_infoframe(encoder, crtc_state,
1239                               HDMI_INFOFRAME_TYPE_DRM,
1240                               &crtc_state->infoframes.drm);
1241 }
1242
1243 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
1244 {
1245         struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
1246         struct i2c_adapter *adapter =
1247                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
1248
1249         if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
1250                 return;
1251
1252         DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n",
1253                       enable ? "Enabling" : "Disabling");
1254
1255         drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type,
1256                                          adapter, enable);
1257 }
1258
1259 static int intel_hdmi_hdcp_read(struct intel_digital_port *intel_dig_port,
1260                                 unsigned int offset, void *buffer, size_t size)
1261 {
1262         struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
1263         struct drm_i915_private *dev_priv =
1264                 intel_dig_port->base.base.dev->dev_private;
1265         struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
1266                                                               hdmi->ddc_bus);
1267         int ret;
1268         u8 start = offset & 0xff;
1269         struct i2c_msg msgs[] = {
1270                 {
1271                         .addr = DRM_HDCP_DDC_ADDR,
1272                         .flags = 0,
1273                         .len = 1,
1274                         .buf = &start,
1275                 },
1276                 {
1277                         .addr = DRM_HDCP_DDC_ADDR,
1278                         .flags = I2C_M_RD,
1279                         .len = size,
1280                         .buf = buffer
1281                 }
1282         };
1283         ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs));
1284         if (ret == ARRAY_SIZE(msgs))
1285                 return 0;
1286         return ret >= 0 ? -EIO : ret;
1287 }
1288
1289 static int intel_hdmi_hdcp_write(struct intel_digital_port *intel_dig_port,
1290                                  unsigned int offset, void *buffer, size_t size)
1291 {
1292         struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
1293         struct drm_i915_private *dev_priv =
1294                 intel_dig_port->base.base.dev->dev_private;
1295         struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
1296                                                               hdmi->ddc_bus);
1297         int ret;
1298         u8 *write_buf;
1299         struct i2c_msg msg;
1300
1301         write_buf = kzalloc(size + 1, GFP_KERNEL);
1302         if (!write_buf)
1303                 return -ENOMEM;
1304
1305         write_buf[0] = offset & 0xff;
1306         memcpy(&write_buf[1], buffer, size);
1307
1308         msg.addr = DRM_HDCP_DDC_ADDR;
1309         msg.flags = 0,
1310         msg.len = size + 1,
1311         msg.buf = write_buf;
1312
1313         ret = i2c_transfer(adapter, &msg, 1);
1314         if (ret == 1)
1315                 ret = 0;
1316         else if (ret >= 0)
1317                 ret = -EIO;
1318
1319         kfree(write_buf);
1320         return ret;
1321 }
1322
1323 static
1324 int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
1325                                   u8 *an)
1326 {
1327         struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
1328         struct drm_i915_private *dev_priv =
1329                 intel_dig_port->base.base.dev->dev_private;
1330         struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
1331                                                               hdmi->ddc_bus);
1332         int ret;
1333
1334         ret = intel_hdmi_hdcp_write(intel_dig_port, DRM_HDCP_DDC_AN, an,
1335                                     DRM_HDCP_AN_LEN);
1336         if (ret) {
1337                 DRM_DEBUG_KMS("Write An over DDC failed (%d)\n", ret);
1338                 return ret;
1339         }
1340
1341         ret = intel_gmbus_output_aksv(adapter);
1342         if (ret < 0) {
1343                 DRM_DEBUG_KMS("Failed to output aksv (%d)\n", ret);
1344                 return ret;
1345         }
1346         return 0;
1347 }
1348
1349 static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,
1350                                      u8 *bksv)
1351 {
1352         int ret;
1353         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BKSV, bksv,
1354                                    DRM_HDCP_KSV_LEN);
1355         if (ret)
1356                 DRM_DEBUG_KMS("Read Bksv over DDC failed (%d)\n", ret);
1357         return ret;
1358 }
1359
1360 static
1361 int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port,
1362                                  u8 *bstatus)
1363 {
1364         int ret;
1365         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BSTATUS,
1366                                    bstatus, DRM_HDCP_BSTATUS_LEN);
1367         if (ret)
1368                 DRM_DEBUG_KMS("Read bstatus over DDC failed (%d)\n", ret);
1369         return ret;
1370 }
1371
1372 static
1373 int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *intel_dig_port,
1374                                      bool *repeater_present)
1375 {
1376         int ret;
1377         u8 val;
1378
1379         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1380         if (ret) {
1381                 DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret);
1382                 return ret;
1383         }
1384         *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT;
1385         return 0;
1386 }
1387
1388 static
1389 int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port,
1390                                   u8 *ri_prime)
1391 {
1392         int ret;
1393         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_RI_PRIME,
1394                                    ri_prime, DRM_HDCP_RI_LEN);
1395         if (ret)
1396                 DRM_DEBUG_KMS("Read Ri' over DDC failed (%d)\n", ret);
1397         return ret;
1398 }
1399
1400 static
1401 int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port,
1402                                    bool *ksv_ready)
1403 {
1404         int ret;
1405         u8 val;
1406
1407         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1408         if (ret) {
1409                 DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret);
1410                 return ret;
1411         }
1412         *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY;
1413         return 0;
1414 }
1415
1416 static
1417 int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port,
1418                                   int num_downstream, u8 *ksv_fifo)
1419 {
1420         int ret;
1421         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_KSV_FIFO,
1422                                    ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN);
1423         if (ret) {
1424                 DRM_DEBUG_KMS("Read ksv fifo over DDC failed (%d)\n", ret);
1425                 return ret;
1426         }
1427         return 0;
1428 }
1429
1430 static
1431 int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port,
1432                                       int i, u32 *part)
1433 {
1434         int ret;
1435
1436         if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
1437                 return -EINVAL;
1438
1439         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_V_PRIME(i),
1440                                    part, DRM_HDCP_V_PRIME_PART_LEN);
1441         if (ret)
1442                 DRM_DEBUG_KMS("Read V'[%d] over DDC failed (%d)\n", i, ret);
1443         return ret;
1444 }
1445
1446 static int kbl_repositioning_enc_en_signal(struct intel_connector *connector)
1447 {
1448         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1449         struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
1450         struct drm_crtc *crtc = connector->base.state->crtc;
1451         struct intel_crtc *intel_crtc = container_of(crtc,
1452                                                      struct intel_crtc, base);
1453         u32 scanline;
1454         int ret;
1455
1456         for (;;) {
1457                 scanline = I915_READ(PIPEDSL(intel_crtc->pipe));
1458                 if (scanline > 100 && scanline < 200)
1459                         break;
1460                 usleep_range(25, 50);
1461         }
1462
1463         ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, false);
1464         if (ret) {
1465                 DRM_ERROR("Disable HDCP signalling failed (%d)\n", ret);
1466                 return ret;
1467         }
1468         ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, true);
1469         if (ret) {
1470                 DRM_ERROR("Enable HDCP signalling failed (%d)\n", ret);
1471                 return ret;
1472         }
1473
1474         return 0;
1475 }
1476
1477 static
1478 int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port,
1479                                       bool enable)
1480 {
1481         struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
1482         struct intel_connector *connector = hdmi->attached_connector;
1483         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1484         int ret;
1485
1486         if (!enable)
1487                 usleep_range(6, 60); /* Bspec says >= 6us */
1488
1489         ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, enable);
1490         if (ret) {
1491                 DRM_ERROR("%s HDCP signalling failed (%d)\n",
1492                           enable ? "Enable" : "Disable", ret);
1493                 return ret;
1494         }
1495
1496         /*
1497          * WA: To fix incorrect positioning of the window of
1498          * opportunity and enc_en signalling in KABYLAKE.
1499          */
1500         if (IS_KABYLAKE(dev_priv) && enable)
1501                 return kbl_repositioning_enc_en_signal(connector);
1502
1503         return 0;
1504 }
1505
1506 static
1507 bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port)
1508 {
1509         struct drm_i915_private *dev_priv =
1510                 intel_dig_port->base.base.dev->dev_private;
1511         struct intel_connector *connector =
1512                 intel_dig_port->hdmi.attached_connector;
1513         enum port port = intel_dig_port->base.port;
1514         enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder;
1515         int ret;
1516         union {
1517                 u32 reg;
1518                 u8 shim[DRM_HDCP_RI_LEN];
1519         } ri;
1520
1521         ret = intel_hdmi_hdcp_read_ri_prime(intel_dig_port, ri.shim);
1522         if (ret)
1523                 return false;
1524
1525         I915_WRITE(HDCP_RPRIME(dev_priv, cpu_transcoder, port), ri.reg);
1526
1527         /* Wait for Ri prime match */
1528         if (wait_for(I915_READ(HDCP_STATUS(dev_priv, cpu_transcoder, port)) &
1529                      (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
1530                 DRM_ERROR("Ri' mismatch detected, link check failed (%x)\n",
1531                           I915_READ(HDCP_STATUS(dev_priv, cpu_transcoder,
1532                                                 port)));
1533                 return false;
1534         }
1535         return true;
1536 }
1537
1538 struct hdcp2_hdmi_msg_timeout {
1539         u8 msg_id;
1540         u32 timeout;
1541 };
1542
1543 static const struct hdcp2_hdmi_msg_timeout hdcp2_msg_timeout[] = {
1544         { HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, },
1545         { HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS, },
1546         { HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, },
1547         { HDCP_2_2_REP_SEND_RECVID_LIST, HDCP_2_2_RECVID_LIST_TIMEOUT_MS, },
1548         { HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS, },
1549 };
1550
1551 static
1552 int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port,
1553                                     u8 *rx_status)
1554 {
1555         return intel_hdmi_hdcp_read(intel_dig_port,
1556                                     HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET,
1557                                     rx_status,
1558                                     HDCP_2_2_HDMI_RXSTATUS_LEN);
1559 }
1560
1561 static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired)
1562 {
1563         int i;
1564
1565         if (msg_id == HDCP_2_2_AKE_SEND_HPRIME) {
1566                 if (is_paired)
1567                         return HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS;
1568                 else
1569                         return HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS;
1570         }
1571
1572         for (i = 0; i < ARRAY_SIZE(hdcp2_msg_timeout); i++) {
1573                 if (hdcp2_msg_timeout[i].msg_id == msg_id)
1574                         return hdcp2_msg_timeout[i].timeout;
1575         }
1576
1577         return -EINVAL;
1578 }
1579
1580 static inline
1581 int hdcp2_detect_msg_availability(struct intel_digital_port *intel_digital_port,
1582                                   u8 msg_id, bool *msg_ready,
1583                                   ssize_t *msg_sz)
1584 {
1585         u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1586         int ret;
1587
1588         ret = intel_hdmi_hdcp2_read_rx_status(intel_digital_port, rx_status);
1589         if (ret < 0) {
1590                 DRM_DEBUG_KMS("rx_status read failed. Err %d\n", ret);
1591                 return ret;
1592         }
1593
1594         *msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) |
1595                   rx_status[0]);
1596
1597         if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST)
1598                 *msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) &&
1599                              *msg_sz);
1600         else
1601                 *msg_ready = *msg_sz;
1602
1603         return 0;
1604 }
1605
1606 static ssize_t
1607 intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port,
1608                               u8 msg_id, bool paired)
1609 {
1610         bool msg_ready = false;
1611         int timeout, ret;
1612         ssize_t msg_sz = 0;
1613
1614         timeout = get_hdcp2_msg_timeout(msg_id, paired);
1615         if (timeout < 0)
1616                 return timeout;
1617
1618         ret = __wait_for(ret = hdcp2_detect_msg_availability(intel_dig_port,
1619                                                              msg_id, &msg_ready,
1620                                                              &msg_sz),
1621                          !ret && msg_ready && msg_sz, timeout * 1000,
1622                          1000, 5 * 1000);
1623         if (ret)
1624                 DRM_DEBUG_KMS("msg_id: %d, ret: %d, timeout: %d\n",
1625                               msg_id, ret, timeout);
1626
1627         return ret ? ret : msg_sz;
1628 }
1629
1630 static
1631 int intel_hdmi_hdcp2_write_msg(struct intel_digital_port *intel_dig_port,
1632                                void *buf, size_t size)
1633 {
1634         unsigned int offset;
1635
1636         offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET;
1637         return intel_hdmi_hdcp_write(intel_dig_port, offset, buf, size);
1638 }
1639
1640 static
1641 int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *intel_dig_port,
1642                               u8 msg_id, void *buf, size_t size)
1643 {
1644         struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
1645         struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp;
1646         unsigned int offset;
1647         ssize_t ret;
1648
1649         ret = intel_hdmi_hdcp2_wait_for_msg(intel_dig_port, msg_id,
1650                                             hdcp->is_paired);
1651         if (ret < 0)
1652                 return ret;
1653
1654         /*
1655          * Available msg size should be equal to or lesser than the
1656          * available buffer.
1657          */
1658         if (ret > size) {
1659                 DRM_DEBUG_KMS("msg_sz(%zd) is more than exp size(%zu)\n",
1660                               ret, size);
1661                 return -1;
1662         }
1663
1664         offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET;
1665         ret = intel_hdmi_hdcp_read(intel_dig_port, offset, buf, ret);
1666         if (ret)
1667                 DRM_DEBUG_KMS("Failed to read msg_id: %d(%zd)\n", msg_id, ret);
1668
1669         return ret;
1670 }
1671
1672 static
1673 int intel_hdmi_hdcp2_check_link(struct intel_digital_port *intel_dig_port)
1674 {
1675         u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1676         int ret;
1677
1678         ret = intel_hdmi_hdcp2_read_rx_status(intel_dig_port, rx_status);
1679         if (ret)
1680                 return ret;
1681
1682         /*
1683          * Re-auth request and Link Integrity Failures are represented by
1684          * same bit. i.e reauth_req.
1685          */
1686         if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status[1]))
1687                 ret = HDCP_REAUTH_REQUEST;
1688         else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]))
1689                 ret = HDCP_TOPOLOGY_CHANGE;
1690
1691         return ret;
1692 }
1693
1694 static
1695 int intel_hdmi_hdcp2_capable(struct intel_digital_port *intel_dig_port,
1696                              bool *capable)
1697 {
1698         u8 hdcp2_version;
1699         int ret;
1700
1701         *capable = false;
1702         ret = intel_hdmi_hdcp_read(intel_dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET,
1703                                    &hdcp2_version, sizeof(hdcp2_version));
1704         if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK)
1705                 *capable = true;
1706
1707         return ret;
1708 }
1709
1710 static inline
1711 enum hdcp_wired_protocol intel_hdmi_hdcp2_protocol(void)
1712 {
1713         return HDCP_PROTOCOL_HDMI;
1714 }
1715
1716 static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = {
1717         .write_an_aksv = intel_hdmi_hdcp_write_an_aksv,
1718         .read_bksv = intel_hdmi_hdcp_read_bksv,
1719         .read_bstatus = intel_hdmi_hdcp_read_bstatus,
1720         .repeater_present = intel_hdmi_hdcp_repeater_present,
1721         .read_ri_prime = intel_hdmi_hdcp_read_ri_prime,
1722         .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready,
1723         .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo,
1724         .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part,
1725         .toggle_signalling = intel_hdmi_hdcp_toggle_signalling,
1726         .check_link = intel_hdmi_hdcp_check_link,
1727         .write_2_2_msg = intel_hdmi_hdcp2_write_msg,
1728         .read_2_2_msg = intel_hdmi_hdcp2_read_msg,
1729         .check_2_2_link = intel_hdmi_hdcp2_check_link,
1730         .hdcp_2_2_capable = intel_hdmi_hdcp2_capable,
1731         .protocol = HDCP_PROTOCOL_HDMI,
1732 };
1733
1734 static void intel_hdmi_prepare(struct intel_encoder *encoder,
1735                                const struct intel_crtc_state *crtc_state)
1736 {
1737         struct drm_device *dev = encoder->base.dev;
1738         struct drm_i915_private *dev_priv = to_i915(dev);
1739         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1740         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1741         const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
1742         u32 hdmi_val;
1743
1744         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
1745
1746         hdmi_val = SDVO_ENCODING_HDMI;
1747         if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
1748                 hdmi_val |= HDMI_COLOR_RANGE_16_235;
1749         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1750                 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
1751         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1752                 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
1753
1754         if (crtc_state->pipe_bpp > 24)
1755                 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
1756         else
1757                 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
1758
1759         if (crtc_state->has_hdmi_sink)
1760                 hdmi_val |= HDMI_MODE_SELECT_HDMI;
1761
1762         if (HAS_PCH_CPT(dev_priv))
1763                 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
1764         else if (IS_CHERRYVIEW(dev_priv))
1765                 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
1766         else
1767                 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
1768
1769         I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
1770         POSTING_READ(intel_hdmi->hdmi_reg);
1771 }
1772
1773 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
1774                                     enum pipe *pipe)
1775 {
1776         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1777         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1778         intel_wakeref_t wakeref;
1779         bool ret;
1780
1781         wakeref = intel_display_power_get_if_enabled(dev_priv,
1782                                                      encoder->power_domain);
1783         if (!wakeref)
1784                 return false;
1785
1786         ret = intel_sdvo_port_enabled(dev_priv, intel_hdmi->hdmi_reg, pipe);
1787
1788         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1789
1790         return ret;
1791 }
1792
1793 static void intel_hdmi_get_config(struct intel_encoder *encoder,
1794                                   struct intel_crtc_state *pipe_config)
1795 {
1796         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1797         struct drm_device *dev = encoder->base.dev;
1798         struct drm_i915_private *dev_priv = to_i915(dev);
1799         u32 tmp, flags = 0;
1800         int dotclock;
1801
1802         pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
1803
1804         tmp = I915_READ(intel_hdmi->hdmi_reg);
1805
1806         if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
1807                 flags |= DRM_MODE_FLAG_PHSYNC;
1808         else
1809                 flags |= DRM_MODE_FLAG_NHSYNC;
1810
1811         if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
1812                 flags |= DRM_MODE_FLAG_PVSYNC;
1813         else
1814                 flags |= DRM_MODE_FLAG_NVSYNC;
1815
1816         if (tmp & HDMI_MODE_SELECT_HDMI)
1817                 pipe_config->has_hdmi_sink = true;
1818
1819         pipe_config->infoframes.enable |=
1820                 intel_hdmi_infoframes_enabled(encoder, pipe_config);
1821
1822         if (pipe_config->infoframes.enable)
1823                 pipe_config->has_infoframe = true;
1824
1825         if (tmp & HDMI_AUDIO_ENABLE)
1826                 pipe_config->has_audio = true;
1827
1828         if (!HAS_PCH_SPLIT(dev_priv) &&
1829             tmp & HDMI_COLOR_RANGE_16_235)
1830                 pipe_config->limited_color_range = true;
1831
1832         pipe_config->base.adjusted_mode.flags |= flags;
1833
1834         if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
1835                 dotclock = pipe_config->port_clock * 2 / 3;
1836         else
1837                 dotclock = pipe_config->port_clock;
1838
1839         if (pipe_config->pixel_multiplier)
1840                 dotclock /= pipe_config->pixel_multiplier;
1841
1842         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1843
1844         pipe_config->lane_count = 4;
1845
1846         intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
1847
1848         intel_read_infoframe(encoder, pipe_config,
1849                              HDMI_INFOFRAME_TYPE_AVI,
1850                              &pipe_config->infoframes.avi);
1851         intel_read_infoframe(encoder, pipe_config,
1852                              HDMI_INFOFRAME_TYPE_SPD,
1853                              &pipe_config->infoframes.spd);
1854         intel_read_infoframe(encoder, pipe_config,
1855                              HDMI_INFOFRAME_TYPE_VENDOR,
1856                              &pipe_config->infoframes.hdmi);
1857 }
1858
1859 static void intel_enable_hdmi_audio(struct intel_encoder *encoder,
1860                                     const struct intel_crtc_state *pipe_config,
1861                                     const struct drm_connector_state *conn_state)
1862 {
1863         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1864
1865         WARN_ON(!pipe_config->has_hdmi_sink);
1866         DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
1867                          pipe_name(crtc->pipe));
1868         intel_audio_codec_enable(encoder, pipe_config, conn_state);
1869 }
1870
1871 static void g4x_enable_hdmi(struct intel_encoder *encoder,
1872                             const struct intel_crtc_state *pipe_config,
1873                             const struct drm_connector_state *conn_state)
1874 {
1875         struct drm_device *dev = encoder->base.dev;
1876         struct drm_i915_private *dev_priv = to_i915(dev);
1877         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1878         u32 temp;
1879
1880         temp = I915_READ(intel_hdmi->hdmi_reg);
1881
1882         temp |= SDVO_ENABLE;
1883         if (pipe_config->has_audio)
1884                 temp |= HDMI_AUDIO_ENABLE;
1885
1886         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1887         POSTING_READ(intel_hdmi->hdmi_reg);
1888
1889         if (pipe_config->has_audio)
1890                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1891 }
1892
1893 static void ibx_enable_hdmi(struct intel_encoder *encoder,
1894                             const struct intel_crtc_state *pipe_config,
1895                             const struct drm_connector_state *conn_state)
1896 {
1897         struct drm_device *dev = encoder->base.dev;
1898         struct drm_i915_private *dev_priv = to_i915(dev);
1899         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1900         u32 temp;
1901
1902         temp = I915_READ(intel_hdmi->hdmi_reg);
1903
1904         temp |= SDVO_ENABLE;
1905         if (pipe_config->has_audio)
1906                 temp |= HDMI_AUDIO_ENABLE;
1907
1908         /*
1909          * HW workaround, need to write this twice for issue
1910          * that may result in first write getting masked.
1911          */
1912         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1913         POSTING_READ(intel_hdmi->hdmi_reg);
1914         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1915         POSTING_READ(intel_hdmi->hdmi_reg);
1916
1917         /*
1918          * HW workaround, need to toggle enable bit off and on
1919          * for 12bpc with pixel repeat.
1920          *
1921          * FIXME: BSpec says this should be done at the end of
1922          * of the modeset sequence, so not sure if this isn't too soon.
1923          */
1924         if (pipe_config->pipe_bpp > 24 &&
1925             pipe_config->pixel_multiplier > 1) {
1926                 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
1927                 POSTING_READ(intel_hdmi->hdmi_reg);
1928
1929                 /*
1930                  * HW workaround, need to write this twice for issue
1931                  * that may result in first write getting masked.
1932                  */
1933                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1934                 POSTING_READ(intel_hdmi->hdmi_reg);
1935                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1936                 POSTING_READ(intel_hdmi->hdmi_reg);
1937         }
1938
1939         if (pipe_config->has_audio)
1940                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1941 }
1942
1943 static void cpt_enable_hdmi(struct intel_encoder *encoder,
1944                             const struct intel_crtc_state *pipe_config,
1945                             const struct drm_connector_state *conn_state)
1946 {
1947         struct drm_device *dev = encoder->base.dev;
1948         struct drm_i915_private *dev_priv = to_i915(dev);
1949         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1950         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1951         enum pipe pipe = crtc->pipe;
1952         u32 temp;
1953
1954         temp = I915_READ(intel_hdmi->hdmi_reg);
1955
1956         temp |= SDVO_ENABLE;
1957         if (pipe_config->has_audio)
1958                 temp |= HDMI_AUDIO_ENABLE;
1959
1960         /*
1961          * WaEnableHDMI8bpcBefore12bpc:snb,ivb
1962          *
1963          * The procedure for 12bpc is as follows:
1964          * 1. disable HDMI clock gating
1965          * 2. enable HDMI with 8bpc
1966          * 3. enable HDMI with 12bpc
1967          * 4. enable HDMI clock gating
1968          */
1969
1970         if (pipe_config->pipe_bpp > 24) {
1971                 I915_WRITE(TRANS_CHICKEN1(pipe),
1972                            I915_READ(TRANS_CHICKEN1(pipe)) |
1973                            TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1974
1975                 temp &= ~SDVO_COLOR_FORMAT_MASK;
1976                 temp |= SDVO_COLOR_FORMAT_8bpc;
1977         }
1978
1979         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1980         POSTING_READ(intel_hdmi->hdmi_reg);
1981
1982         if (pipe_config->pipe_bpp > 24) {
1983                 temp &= ~SDVO_COLOR_FORMAT_MASK;
1984                 temp |= HDMI_COLOR_FORMAT_12bpc;
1985
1986                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1987                 POSTING_READ(intel_hdmi->hdmi_reg);
1988
1989                 I915_WRITE(TRANS_CHICKEN1(pipe),
1990                            I915_READ(TRANS_CHICKEN1(pipe)) &
1991                            ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1992         }
1993
1994         if (pipe_config->has_audio)
1995                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1996 }
1997
1998 static void vlv_enable_hdmi(struct intel_encoder *encoder,
1999                             const struct intel_crtc_state *pipe_config,
2000                             const struct drm_connector_state *conn_state)
2001 {
2002 }
2003
2004 static void intel_disable_hdmi(struct intel_encoder *encoder,
2005                                const struct intel_crtc_state *old_crtc_state,
2006                                const struct drm_connector_state *old_conn_state)
2007 {
2008         struct drm_device *dev = encoder->base.dev;
2009         struct drm_i915_private *dev_priv = to_i915(dev);
2010         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2011         struct intel_digital_port *intel_dig_port =
2012                 hdmi_to_dig_port(intel_hdmi);
2013         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
2014         u32 temp;
2015
2016         temp = I915_READ(intel_hdmi->hdmi_reg);
2017
2018         temp &= ~(SDVO_ENABLE | HDMI_AUDIO_ENABLE);
2019         I915_WRITE(intel_hdmi->hdmi_reg, temp);
2020         POSTING_READ(intel_hdmi->hdmi_reg);
2021
2022         /*
2023          * HW workaround for IBX, we need to move the port
2024          * to transcoder A after disabling it to allow the
2025          * matching DP port to be enabled on transcoder A.
2026          */
2027         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
2028                 /*
2029                  * We get CPU/PCH FIFO underruns on the other pipe when
2030                  * doing the workaround. Sweep them under the rug.
2031                  */
2032                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
2033                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
2034
2035                 temp &= ~SDVO_PIPE_SEL_MASK;
2036                 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A);
2037                 /*
2038                  * HW workaround, need to write this twice for issue
2039                  * that may result in first write getting masked.
2040                  */
2041                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
2042                 POSTING_READ(intel_hdmi->hdmi_reg);
2043                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
2044                 POSTING_READ(intel_hdmi->hdmi_reg);
2045
2046                 temp &= ~SDVO_ENABLE;
2047                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
2048                 POSTING_READ(intel_hdmi->hdmi_reg);
2049
2050                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
2051                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
2052                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
2053         }
2054
2055         intel_dig_port->set_infoframes(encoder,
2056                                        false,
2057                                        old_crtc_state, old_conn_state);
2058
2059         intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
2060 }
2061
2062 static void g4x_disable_hdmi(struct intel_encoder *encoder,
2063                              const struct intel_crtc_state *old_crtc_state,
2064                              const struct drm_connector_state *old_conn_state)
2065 {
2066         if (old_crtc_state->has_audio)
2067                 intel_audio_codec_disable(encoder,
2068                                           old_crtc_state, old_conn_state);
2069
2070         intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
2071 }
2072
2073 static void pch_disable_hdmi(struct intel_encoder *encoder,
2074                              const struct intel_crtc_state *old_crtc_state,
2075                              const struct drm_connector_state *old_conn_state)
2076 {
2077         if (old_crtc_state->has_audio)
2078                 intel_audio_codec_disable(encoder,
2079                                           old_crtc_state, old_conn_state);
2080 }
2081
2082 static void pch_post_disable_hdmi(struct intel_encoder *encoder,
2083                                   const struct intel_crtc_state *old_crtc_state,
2084                                   const struct drm_connector_state *old_conn_state)
2085 {
2086         intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
2087 }
2088
2089 static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder)
2090 {
2091         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2092         const struct ddi_vbt_port_info *info =
2093                 &dev_priv->vbt.ddi_port_info[encoder->port];
2094         int max_tmds_clock;
2095
2096         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2097                 max_tmds_clock = 594000;
2098         else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
2099                 max_tmds_clock = 300000;
2100         else if (INTEL_GEN(dev_priv) >= 5)
2101                 max_tmds_clock = 225000;
2102         else
2103                 max_tmds_clock = 165000;
2104
2105         if (info->max_tmds_clock)
2106                 max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock);
2107
2108         return max_tmds_clock;
2109 }
2110
2111 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
2112                                  bool respect_downstream_limits,
2113                                  bool force_dvi)
2114 {
2115         struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
2116         int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder);
2117
2118         if (respect_downstream_limits) {
2119                 struct intel_connector *connector = hdmi->attached_connector;
2120                 const struct drm_display_info *info = &connector->base.display_info;
2121
2122                 if (hdmi->dp_dual_mode.max_tmds_clock)
2123                         max_tmds_clock = min(max_tmds_clock,
2124                                              hdmi->dp_dual_mode.max_tmds_clock);
2125
2126                 if (info->max_tmds_clock)
2127                         max_tmds_clock = min(max_tmds_clock,
2128                                              info->max_tmds_clock);
2129                 else if (!hdmi->has_hdmi_sink || force_dvi)
2130                         max_tmds_clock = min(max_tmds_clock, 165000);
2131         }
2132
2133         return max_tmds_clock;
2134 }
2135
2136 static enum drm_mode_status
2137 hdmi_port_clock_valid(struct intel_hdmi *hdmi,
2138                       int clock, bool respect_downstream_limits,
2139                       bool force_dvi)
2140 {
2141         struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
2142
2143         if (clock < 25000)
2144                 return MODE_CLOCK_LOW;
2145         if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, force_dvi))
2146                 return MODE_CLOCK_HIGH;
2147
2148         /* BXT DPLL can't generate 223-240 MHz */
2149         if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000)
2150                 return MODE_CLOCK_RANGE;
2151
2152         /* CHV DPLL can't generate 216-240 MHz */
2153         if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
2154                 return MODE_CLOCK_RANGE;
2155
2156         return MODE_OK;
2157 }
2158
2159 static enum drm_mode_status
2160 intel_hdmi_mode_valid(struct drm_connector *connector,
2161                       struct drm_display_mode *mode)
2162 {
2163         struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
2164         struct drm_device *dev = intel_hdmi_to_dev(hdmi);
2165         struct drm_i915_private *dev_priv = to_i915(dev);
2166         enum drm_mode_status status;
2167         int clock;
2168         int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
2169         bool force_dvi =
2170                 READ_ONCE(to_intel_digital_connector_state(connector->state)->force_audio) == HDMI_AUDIO_OFF_DVI;
2171
2172         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
2173                 return MODE_NO_DBLESCAN;
2174
2175         clock = mode->clock;
2176
2177         if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
2178                 clock *= 2;
2179
2180         if (clock > max_dotclk)
2181                 return MODE_CLOCK_HIGH;
2182
2183         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
2184                 clock *= 2;
2185
2186         if (drm_mode_is_420_only(&connector->display_info, mode))
2187                 clock /= 2;
2188
2189         /* check if we can do 8bpc */
2190         status = hdmi_port_clock_valid(hdmi, clock, true, force_dvi);
2191
2192         if (hdmi->has_hdmi_sink && !force_dvi) {
2193                 /* if we can't do 8bpc we may still be able to do 12bpc */
2194                 if (status != MODE_OK && !HAS_GMCH(dev_priv))
2195                         status = hdmi_port_clock_valid(hdmi, clock * 3 / 2,
2196                                                        true, force_dvi);
2197
2198                 /* if we can't do 8,12bpc we may still be able to do 10bpc */
2199                 if (status != MODE_OK && INTEL_GEN(dev_priv) >= 11)
2200                         status = hdmi_port_clock_valid(hdmi, clock * 5 / 4,
2201                                                        true, force_dvi);
2202         }
2203         if (status != MODE_OK)
2204                 return status;
2205
2206         return intel_mode_valid_max_plane_size(dev_priv, mode);
2207 }
2208
2209 static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
2210                                      int bpc)
2211 {
2212         struct drm_i915_private *dev_priv =
2213                 to_i915(crtc_state->base.crtc->dev);
2214         struct drm_atomic_state *state = crtc_state->base.state;
2215         struct drm_connector_state *connector_state;
2216         struct drm_connector *connector;
2217         const struct drm_display_mode *adjusted_mode =
2218                 &crtc_state->base.adjusted_mode;
2219         int i;
2220
2221         if (HAS_GMCH(dev_priv))
2222                 return false;
2223
2224         if (bpc == 10 && INTEL_GEN(dev_priv) < 11)
2225                 return false;
2226
2227         if (crtc_state->pipe_bpp < bpc * 3)
2228                 return false;
2229
2230         if (!crtc_state->has_hdmi_sink)
2231                 return false;
2232
2233         /*
2234          * HDMI deep color affects the clocks, so it's only possible
2235          * when not cloning with other encoder types.
2236          */
2237         if (crtc_state->output_types != 1 << INTEL_OUTPUT_HDMI)
2238                 return false;
2239
2240         for_each_new_connector_in_state(state, connector, connector_state, i) {
2241                 const struct drm_display_info *info = &connector->display_info;
2242
2243                 if (connector_state->crtc != crtc_state->base.crtc)
2244                         continue;
2245
2246                 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
2247                         const struct drm_hdmi_info *hdmi = &info->hdmi;
2248
2249                         if (bpc == 12 && !(hdmi->y420_dc_modes &
2250                                            DRM_EDID_YCBCR420_DC_36))
2251                                 return false;
2252                         else if (bpc == 10 && !(hdmi->y420_dc_modes &
2253                                                 DRM_EDID_YCBCR420_DC_30))
2254                                 return false;
2255                 } else {
2256                         if (bpc == 12 && !(info->edid_hdmi_dc_modes &
2257                                            DRM_EDID_HDMI_DC_36))
2258                                 return false;
2259                         else if (bpc == 10 && !(info->edid_hdmi_dc_modes &
2260                                                 DRM_EDID_HDMI_DC_30))
2261                                 return false;
2262                 }
2263         }
2264
2265         /* Display WA #1139: glk */
2266         if (bpc == 12 && IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) &&
2267             adjusted_mode->htotal > 5460)
2268                 return false;
2269
2270         /* Display Wa_1405510057:icl */
2271         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
2272             bpc == 10 && INTEL_GEN(dev_priv) >= 11 &&
2273             (adjusted_mode->crtc_hblank_end -
2274              adjusted_mode->crtc_hblank_start) % 8 == 2)
2275                 return false;
2276
2277         return true;
2278 }
2279
2280 static bool
2281 intel_hdmi_ycbcr420_config(struct drm_connector *connector,
2282                            struct intel_crtc_state *config)
2283 {
2284         struct intel_crtc *intel_crtc = to_intel_crtc(config->base.crtc);
2285
2286         if (!connector->ycbcr_420_allowed) {
2287                 DRM_ERROR("Platform doesn't support YCBCR420 output\n");
2288                 return false;
2289         }
2290
2291         config->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2292
2293         /* YCBCR 420 output conversion needs a scaler */
2294         if (skl_update_scaler_crtc(config)) {
2295                 DRM_DEBUG_KMS("Scaler allocation for output failed\n");
2296                 return false;
2297         }
2298
2299         intel_pch_panel_fitting(intel_crtc, config,
2300                                 DRM_MODE_SCALE_FULLSCREEN);
2301
2302         return true;
2303 }
2304
2305 static int intel_hdmi_port_clock(int clock, int bpc)
2306 {
2307         /*
2308          * Need to adjust the port link by:
2309          *  1.5x for 12bpc
2310          *  1.25x for 10bpc
2311          */
2312         return clock * bpc / 8;
2313 }
2314
2315 static int intel_hdmi_compute_bpc(struct intel_encoder *encoder,
2316                                   struct intel_crtc_state *crtc_state,
2317                                   int clock, bool force_dvi)
2318 {
2319         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2320         int bpc;
2321
2322         for (bpc = 12; bpc >= 10; bpc -= 2) {
2323                 if (hdmi_deep_color_possible(crtc_state, bpc) &&
2324                     hdmi_port_clock_valid(intel_hdmi,
2325                                           intel_hdmi_port_clock(clock, bpc),
2326                                           true, force_dvi) == MODE_OK)
2327                         return bpc;
2328         }
2329
2330         return 8;
2331 }
2332
2333 static int intel_hdmi_compute_clock(struct intel_encoder *encoder,
2334                                     struct intel_crtc_state *crtc_state,
2335                                     bool force_dvi)
2336 {
2337         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2338         const struct drm_display_mode *adjusted_mode =
2339                 &crtc_state->base.adjusted_mode;
2340         int bpc, clock = adjusted_mode->crtc_clock;
2341
2342         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2343                 clock *= 2;
2344
2345         /* YCBCR420 TMDS rate requirement is half the pixel clock */
2346         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
2347                 clock /= 2;
2348
2349         bpc = intel_hdmi_compute_bpc(encoder, crtc_state,
2350                                      clock, force_dvi);
2351
2352         crtc_state->port_clock = intel_hdmi_port_clock(clock, bpc);
2353
2354         /*
2355          * pipe_bpp could already be below 8bpc due to
2356          * FDI bandwidth constraints. We shouldn't bump it
2357          * back up to 8bpc in that case.
2358          */
2359         if (crtc_state->pipe_bpp > bpc * 3)
2360                 crtc_state->pipe_bpp = bpc * 3;
2361
2362         DRM_DEBUG_KMS("picking %d bpc for HDMI output (pipe bpp: %d)\n",
2363                       bpc, crtc_state->pipe_bpp);
2364
2365         if (hdmi_port_clock_valid(intel_hdmi, crtc_state->port_clock,
2366                                   false, force_dvi) != MODE_OK) {
2367                 DRM_DEBUG_KMS("unsupported HDMI clock (%d kHz), rejecting mode\n",
2368                               crtc_state->port_clock);
2369                 return -EINVAL;
2370         }
2371
2372         return 0;
2373 }
2374
2375 static bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state,
2376                                            const struct drm_connector_state *conn_state)
2377 {
2378         const struct intel_digital_connector_state *intel_conn_state =
2379                 to_intel_digital_connector_state(conn_state);
2380         const struct drm_display_mode *adjusted_mode =
2381                 &crtc_state->base.adjusted_mode;
2382
2383         /*
2384          * Our YCbCr output is always limited range.
2385          * crtc_state->limited_color_range only applies to RGB,
2386          * and it must never be set for YCbCr or we risk setting
2387          * some conflicting bits in PIPECONF which will mess up
2388          * the colors on the monitor.
2389          */
2390         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
2391                 return false;
2392
2393         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2394                 /* See CEA-861-E - 5.1 Default Encoding Parameters */
2395                 return crtc_state->has_hdmi_sink &&
2396                         drm_default_rgb_quant_range(adjusted_mode) ==
2397                         HDMI_QUANTIZATION_RANGE_LIMITED;
2398         } else {
2399                 return intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
2400         }
2401 }
2402
2403 int intel_hdmi_compute_config(struct intel_encoder *encoder,
2404                               struct intel_crtc_state *pipe_config,
2405                               struct drm_connector_state *conn_state)
2406 {
2407         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2408         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2409         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2410         struct drm_connector *connector = conn_state->connector;
2411         struct drm_scdc *scdc = &connector->display_info.hdmi.scdc;
2412         struct intel_digital_connector_state *intel_conn_state =
2413                 to_intel_digital_connector_state(conn_state);
2414         bool force_dvi = intel_conn_state->force_audio == HDMI_AUDIO_OFF_DVI;
2415         int ret;
2416
2417         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2418                 return -EINVAL;
2419
2420         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2421         pipe_config->has_hdmi_sink = !force_dvi && intel_hdmi->has_hdmi_sink;
2422
2423         if (pipe_config->has_hdmi_sink)
2424                 pipe_config->has_infoframe = true;
2425
2426         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2427                 pipe_config->pixel_multiplier = 2;
2428
2429         if (drm_mode_is_420_only(&connector->display_info, adjusted_mode)) {
2430                 if (!intel_hdmi_ycbcr420_config(connector, pipe_config)) {
2431                         DRM_ERROR("Can't support YCBCR420 output\n");
2432                         return -EINVAL;
2433                 }
2434         }
2435
2436         pipe_config->limited_color_range =
2437                 intel_hdmi_limited_color_range(pipe_config, conn_state);
2438
2439         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))
2440                 pipe_config->has_pch_encoder = true;
2441
2442         if (pipe_config->has_hdmi_sink) {
2443                 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2444                         pipe_config->has_audio = intel_hdmi->has_audio;
2445                 else
2446                         pipe_config->has_audio =
2447                                 intel_conn_state->force_audio == HDMI_AUDIO_ON;
2448         }
2449
2450         ret = intel_hdmi_compute_clock(encoder, pipe_config, force_dvi);
2451         if (ret)
2452                 return ret;
2453
2454         /* Set user selected PAR to incoming mode's member */
2455         adjusted_mode->picture_aspect_ratio = conn_state->picture_aspect_ratio;
2456
2457         pipe_config->lane_count = 4;
2458
2459         if (scdc->scrambling.supported && (INTEL_GEN(dev_priv) >= 10 ||
2460                                            IS_GEMINILAKE(dev_priv))) {
2461                 if (scdc->scrambling.low_rates)
2462                         pipe_config->hdmi_scrambling = true;
2463
2464                 if (pipe_config->port_clock > 340000) {
2465                         pipe_config->hdmi_scrambling = true;
2466                         pipe_config->hdmi_high_tmds_clock_ratio = true;
2467                 }
2468         }
2469
2470         intel_hdmi_compute_gcp_infoframe(encoder, pipe_config, conn_state);
2471
2472         if (!intel_hdmi_compute_avi_infoframe(encoder, pipe_config, conn_state)) {
2473                 DRM_DEBUG_KMS("bad AVI infoframe\n");
2474                 return -EINVAL;
2475         }
2476
2477         if (!intel_hdmi_compute_spd_infoframe(encoder, pipe_config, conn_state)) {
2478                 DRM_DEBUG_KMS("bad SPD infoframe\n");
2479                 return -EINVAL;
2480         }
2481
2482         if (!intel_hdmi_compute_hdmi_infoframe(encoder, pipe_config, conn_state)) {
2483                 DRM_DEBUG_KMS("bad HDMI infoframe\n");
2484                 return -EINVAL;
2485         }
2486
2487         if (!intel_hdmi_compute_drm_infoframe(encoder, pipe_config, conn_state)) {
2488                 DRM_DEBUG_KMS("bad DRM infoframe\n");
2489                 return -EINVAL;
2490         }
2491
2492         intel_hdcp_transcoder_config(intel_hdmi->attached_connector,
2493                                      pipe_config->cpu_transcoder);
2494
2495         return 0;
2496 }
2497
2498 static void
2499 intel_hdmi_unset_edid(struct drm_connector *connector)
2500 {
2501         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
2502
2503         intel_hdmi->has_hdmi_sink = false;
2504         intel_hdmi->has_audio = false;
2505
2506         intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
2507         intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
2508
2509         kfree(to_intel_connector(connector)->detect_edid);
2510         to_intel_connector(connector)->detect_edid = NULL;
2511 }
2512
2513 static void
2514 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid)
2515 {
2516         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2517         struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
2518         enum port port = hdmi_to_dig_port(hdmi)->base.port;
2519         struct i2c_adapter *adapter =
2520                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
2521         enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter);
2522
2523         /*
2524          * Type 1 DVI adaptors are not required to implement any
2525          * registers, so we can't always detect their presence.
2526          * Ideally we should be able to check the state of the
2527          * CONFIG1 pin, but no such luck on our hardware.
2528          *
2529          * The only method left to us is to check the VBT to see
2530          * if the port is a dual mode capable DP port. But let's
2531          * only do that when we sucesfully read the EDID, to avoid
2532          * confusing log messages about DP dual mode adaptors when
2533          * there's nothing connected to the port.
2534          */
2535         if (type == DRM_DP_DUAL_MODE_UNKNOWN) {
2536                 /* An overridden EDID imply that we want this port for testing.
2537                  * Make sure not to set limits for that port.
2538                  */
2539                 if (has_edid && !connector->override_edid &&
2540                     intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
2541                         DRM_DEBUG_KMS("Assuming DP dual mode adaptor presence based on VBT\n");
2542                         type = DRM_DP_DUAL_MODE_TYPE1_DVI;
2543                 } else {
2544                         type = DRM_DP_DUAL_MODE_NONE;
2545                 }
2546         }
2547
2548         if (type == DRM_DP_DUAL_MODE_NONE)
2549                 return;
2550
2551         hdmi->dp_dual_mode.type = type;
2552         hdmi->dp_dual_mode.max_tmds_clock =
2553                 drm_dp_dual_mode_max_tmds_clock(type, adapter);
2554
2555         DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
2556                       drm_dp_get_dual_mode_type_name(type),
2557                       hdmi->dp_dual_mode.max_tmds_clock);
2558 }
2559
2560 static bool
2561 intel_hdmi_set_edid(struct drm_connector *connector)
2562 {
2563         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2564         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
2565         intel_wakeref_t wakeref;
2566         struct edid *edid;
2567         bool connected = false;
2568         struct i2c_adapter *i2c;
2569
2570         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2571
2572         i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2573
2574         edid = drm_get_edid(connector, i2c);
2575
2576         if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
2577                 DRM_DEBUG_KMS("HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n");
2578                 intel_gmbus_force_bit(i2c, true);
2579                 edid = drm_get_edid(connector, i2c);
2580                 intel_gmbus_force_bit(i2c, false);
2581         }
2582
2583         intel_hdmi_dp_dual_mode_detect(connector, edid != NULL);
2584
2585         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2586
2587         to_intel_connector(connector)->detect_edid = edid;
2588         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
2589                 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
2590                 intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
2591
2592                 connected = true;
2593         }
2594
2595         cec_notifier_set_phys_addr_from_edid(intel_hdmi->cec_notifier, edid);
2596
2597         return connected;
2598 }
2599
2600 static enum drm_connector_status
2601 intel_hdmi_detect(struct drm_connector *connector, bool force)
2602 {
2603         enum drm_connector_status status = connector_status_disconnected;
2604         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2605         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
2606         struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base;
2607         intel_wakeref_t wakeref;
2608
2609         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2610                       connector->base.id, connector->name);
2611
2612         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2613
2614         if (INTEL_GEN(dev_priv) >= 11 &&
2615             !intel_digital_port_connected(encoder))
2616                 goto out;
2617
2618         intel_hdmi_unset_edid(connector);
2619
2620         if (intel_hdmi_set_edid(connector))
2621                 status = connector_status_connected;
2622
2623 out:
2624         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2625
2626         if (status != connector_status_connected)
2627                 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier);
2628
2629         return status;
2630 }
2631
2632 static void
2633 intel_hdmi_force(struct drm_connector *connector)
2634 {
2635         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2636                       connector->base.id, connector->name);
2637
2638         intel_hdmi_unset_edid(connector);
2639
2640         if (connector->status != connector_status_connected)
2641                 return;
2642
2643         intel_hdmi_set_edid(connector);
2644 }
2645
2646 static int intel_hdmi_get_modes(struct drm_connector *connector)
2647 {
2648         struct edid *edid;
2649
2650         edid = to_intel_connector(connector)->detect_edid;
2651         if (edid == NULL)
2652                 return 0;
2653
2654         return intel_connector_update_modes(connector, edid);
2655 }
2656
2657 static void intel_hdmi_pre_enable(struct intel_encoder *encoder,
2658                                   const struct intel_crtc_state *pipe_config,
2659                                   const struct drm_connector_state *conn_state)
2660 {
2661         struct intel_digital_port *intel_dig_port =
2662                 enc_to_dig_port(&encoder->base);
2663
2664         intel_hdmi_prepare(encoder, pipe_config);
2665
2666         intel_dig_port->set_infoframes(encoder,
2667                                        pipe_config->has_infoframe,
2668                                        pipe_config, conn_state);
2669 }
2670
2671 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder,
2672                                 const struct intel_crtc_state *pipe_config,
2673                                 const struct drm_connector_state *conn_state)
2674 {
2675         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2676         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2677
2678         vlv_phy_pre_encoder_enable(encoder, pipe_config);
2679
2680         /* HDMI 1.0V-2dB */
2681         vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a,
2682                                  0x2b247878);
2683
2684         dport->set_infoframes(encoder,
2685                               pipe_config->has_infoframe,
2686                               pipe_config, conn_state);
2687
2688         g4x_enable_hdmi(encoder, pipe_config, conn_state);
2689
2690         vlv_wait_port_ready(dev_priv, dport, 0x0);
2691 }
2692
2693 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
2694                                     const struct intel_crtc_state *pipe_config,
2695                                     const struct drm_connector_state *conn_state)
2696 {
2697         intel_hdmi_prepare(encoder, pipe_config);
2698
2699         vlv_phy_pre_pll_enable(encoder, pipe_config);
2700 }
2701
2702 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
2703                                     const struct intel_crtc_state *pipe_config,
2704                                     const struct drm_connector_state *conn_state)
2705 {
2706         intel_hdmi_prepare(encoder, pipe_config);
2707
2708         chv_phy_pre_pll_enable(encoder, pipe_config);
2709 }
2710
2711 static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder,
2712                                       const struct intel_crtc_state *old_crtc_state,
2713                                       const struct drm_connector_state *old_conn_state)
2714 {
2715         chv_phy_post_pll_disable(encoder, old_crtc_state);
2716 }
2717
2718 static void vlv_hdmi_post_disable(struct intel_encoder *encoder,
2719                                   const struct intel_crtc_state *old_crtc_state,
2720                                   const struct drm_connector_state *old_conn_state)
2721 {
2722         /* Reset lanes to avoid HDMI flicker (VLV w/a) */
2723         vlv_phy_reset_lanes(encoder, old_crtc_state);
2724 }
2725
2726 static void chv_hdmi_post_disable(struct intel_encoder *encoder,
2727                                   const struct intel_crtc_state *old_crtc_state,
2728                                   const struct drm_connector_state *old_conn_state)
2729 {
2730         struct drm_device *dev = encoder->base.dev;
2731         struct drm_i915_private *dev_priv = to_i915(dev);
2732
2733         vlv_dpio_get(dev_priv);
2734
2735         /* Assert data lane reset */
2736         chv_data_lane_soft_reset(encoder, old_crtc_state, true);
2737
2738         vlv_dpio_put(dev_priv);
2739 }
2740
2741 static void chv_hdmi_pre_enable(struct intel_encoder *encoder,
2742                                 const struct intel_crtc_state *pipe_config,
2743                                 const struct drm_connector_state *conn_state)
2744 {
2745         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2746         struct drm_device *dev = encoder->base.dev;
2747         struct drm_i915_private *dev_priv = to_i915(dev);
2748
2749         chv_phy_pre_encoder_enable(encoder, pipe_config);
2750
2751         /* FIXME: Program the support xxx V-dB */
2752         /* Use 800mV-0dB */
2753         chv_set_phy_signal_level(encoder, 128, 102, false);
2754
2755         dport->set_infoframes(encoder,
2756                               pipe_config->has_infoframe,
2757                               pipe_config, conn_state);
2758
2759         g4x_enable_hdmi(encoder, pipe_config, conn_state);
2760
2761         vlv_wait_port_ready(dev_priv, dport, 0x0);
2762
2763         /* Second common lane will stay alive on its own now */
2764         chv_phy_release_cl2_override(encoder);
2765 }
2766
2767 static struct i2c_adapter *
2768 intel_hdmi_get_i2c_adapter(struct drm_connector *connector)
2769 {
2770         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2771         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
2772
2773         return intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2774 }
2775
2776 static void intel_hdmi_create_i2c_symlink(struct drm_connector *connector)
2777 {
2778         struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector);
2779         struct kobject *i2c_kobj = &adapter->dev.kobj;
2780         struct kobject *connector_kobj = &connector->kdev->kobj;
2781         int ret;
2782
2783         ret = sysfs_create_link(connector_kobj, i2c_kobj, i2c_kobj->name);
2784         if (ret)
2785                 DRM_ERROR("Failed to create i2c symlink (%d)\n", ret);
2786 }
2787
2788 static void intel_hdmi_remove_i2c_symlink(struct drm_connector *connector)
2789 {
2790         struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector);
2791         struct kobject *i2c_kobj = &adapter->dev.kobj;
2792         struct kobject *connector_kobj = &connector->kdev->kobj;
2793
2794         sysfs_remove_link(connector_kobj, i2c_kobj->name);
2795 }
2796
2797 static int
2798 intel_hdmi_connector_register(struct drm_connector *connector)
2799 {
2800         int ret;
2801
2802         ret = intel_connector_register(connector);
2803         if (ret)
2804                 return ret;
2805
2806         i915_debugfs_connector_add(connector);
2807
2808         intel_hdmi_create_i2c_symlink(connector);
2809
2810         return ret;
2811 }
2812
2813 static void intel_hdmi_destroy(struct drm_connector *connector)
2814 {
2815         struct cec_notifier *n = intel_attached_hdmi(connector)->cec_notifier;
2816
2817         cec_notifier_conn_unregister(n);
2818
2819         intel_connector_destroy(connector);
2820 }
2821
2822 static void intel_hdmi_connector_unregister(struct drm_connector *connector)
2823 {
2824         intel_hdmi_remove_i2c_symlink(connector);
2825
2826         intel_connector_unregister(connector);
2827 }
2828
2829 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
2830         .detect = intel_hdmi_detect,
2831         .force = intel_hdmi_force,
2832         .fill_modes = drm_helper_probe_single_connector_modes,
2833         .atomic_get_property = intel_digital_connector_atomic_get_property,
2834         .atomic_set_property = intel_digital_connector_atomic_set_property,
2835         .late_register = intel_hdmi_connector_register,
2836         .early_unregister = intel_hdmi_connector_unregister,
2837         .destroy = intel_hdmi_destroy,
2838         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2839         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
2840 };
2841
2842 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
2843         .get_modes = intel_hdmi_get_modes,
2844         .mode_valid = intel_hdmi_mode_valid,
2845         .atomic_check = intel_digital_connector_atomic_check,
2846 };
2847
2848 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
2849         .destroy = intel_encoder_destroy,
2850 };
2851
2852 static void
2853 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
2854 {
2855         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2856         struct intel_digital_port *intel_dig_port =
2857                                 hdmi_to_dig_port(intel_hdmi);
2858
2859         intel_attach_force_audio_property(connector);
2860         intel_attach_broadcast_rgb_property(connector);
2861         intel_attach_aspect_ratio_property(connector);
2862
2863         /*
2864          * Attach Colorspace property for Non LSPCON based device
2865          * ToDo: This needs to be extended for LSPCON implementation
2866          * as well. Will be implemented separately.
2867          */
2868         if (!intel_dig_port->lspcon.active)
2869                 intel_attach_colorspace_property(connector);
2870
2871         drm_connector_attach_content_type_property(connector);
2872         connector->state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
2873
2874         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2875                 drm_object_attach_property(&connector->base,
2876                         connector->dev->mode_config.hdr_output_metadata_property, 0);
2877
2878         if (!HAS_GMCH(dev_priv))
2879                 drm_connector_attach_max_bpc_property(connector, 8, 12);
2880 }
2881
2882 /*
2883  * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup
2884  * @encoder: intel_encoder
2885  * @connector: drm_connector
2886  * @high_tmds_clock_ratio = bool to indicate if the function needs to set
2887  *  or reset the high tmds clock ratio for scrambling
2888  * @scrambling: bool to Indicate if the function needs to set or reset
2889  *  sink scrambling
2890  *
2891  * This function handles scrambling on HDMI 2.0 capable sinks.
2892  * If required clock rate is > 340 Mhz && scrambling is supported by sink
2893  * it enables scrambling. This should be called before enabling the HDMI
2894  * 2.0 port, as the sink can choose to disable the scrambling if it doesn't
2895  * detect a scrambled clock within 100 ms.
2896  *
2897  * Returns:
2898  * True on success, false on failure.
2899  */
2900 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
2901                                        struct drm_connector *connector,
2902                                        bool high_tmds_clock_ratio,
2903                                        bool scrambling)
2904 {
2905         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2906         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2907         struct drm_scrambling *sink_scrambling =
2908                 &connector->display_info.hdmi.scdc.scrambling;
2909         struct i2c_adapter *adapter =
2910                 intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2911
2912         if (!sink_scrambling->supported)
2913                 return true;
2914
2915         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n",
2916                       connector->base.id, connector->name,
2917                       yesno(scrambling), high_tmds_clock_ratio ? 40 : 10);
2918
2919         /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */
2920         return drm_scdc_set_high_tmds_clock_ratio(adapter,
2921                                                   high_tmds_clock_ratio) &&
2922                 drm_scdc_set_scrambling(adapter, scrambling);
2923 }
2924
2925 static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2926 {
2927         u8 ddc_pin;
2928
2929         switch (port) {
2930         case PORT_B:
2931                 ddc_pin = GMBUS_PIN_DPB;
2932                 break;
2933         case PORT_C:
2934                 ddc_pin = GMBUS_PIN_DPC;
2935                 break;
2936         case PORT_D:
2937                 ddc_pin = GMBUS_PIN_DPD_CHV;
2938                 break;
2939         default:
2940                 MISSING_CASE(port);
2941                 ddc_pin = GMBUS_PIN_DPB;
2942                 break;
2943         }
2944         return ddc_pin;
2945 }
2946
2947 static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2948 {
2949         u8 ddc_pin;
2950
2951         switch (port) {
2952         case PORT_B:
2953                 ddc_pin = GMBUS_PIN_1_BXT;
2954                 break;
2955         case PORT_C:
2956                 ddc_pin = GMBUS_PIN_2_BXT;
2957                 break;
2958         default:
2959                 MISSING_CASE(port);
2960                 ddc_pin = GMBUS_PIN_1_BXT;
2961                 break;
2962         }
2963         return ddc_pin;
2964 }
2965
2966 static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2967                               enum port port)
2968 {
2969         u8 ddc_pin;
2970
2971         switch (port) {
2972         case PORT_B:
2973                 ddc_pin = GMBUS_PIN_1_BXT;
2974                 break;
2975         case PORT_C:
2976                 ddc_pin = GMBUS_PIN_2_BXT;
2977                 break;
2978         case PORT_D:
2979                 ddc_pin = GMBUS_PIN_4_CNP;
2980                 break;
2981         case PORT_F:
2982                 ddc_pin = GMBUS_PIN_3_BXT;
2983                 break;
2984         default:
2985                 MISSING_CASE(port);
2986                 ddc_pin = GMBUS_PIN_1_BXT;
2987                 break;
2988         }
2989         return ddc_pin;
2990 }
2991
2992 static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2993 {
2994         enum phy phy = intel_port_to_phy(dev_priv, port);
2995
2996         if (intel_phy_is_combo(dev_priv, phy))
2997                 return GMBUS_PIN_1_BXT + port;
2998         else if (intel_phy_is_tc(dev_priv, phy))
2999                 return GMBUS_PIN_9_TC1_ICP + intel_port_to_tc(dev_priv, port);
3000
3001         WARN(1, "Unknown port:%c\n", port_name(port));
3002         return GMBUS_PIN_2_BXT;
3003 }
3004
3005 static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
3006 {
3007         enum phy phy = intel_port_to_phy(dev_priv, port);
3008         u8 ddc_pin;
3009
3010         switch (phy) {
3011         case PHY_A:
3012                 ddc_pin = GMBUS_PIN_1_BXT;
3013                 break;
3014         case PHY_B:
3015                 ddc_pin = GMBUS_PIN_2_BXT;
3016                 break;
3017         case PHY_C:
3018                 ddc_pin = GMBUS_PIN_9_TC1_ICP;
3019                 break;
3020         default:
3021                 MISSING_CASE(phy);
3022                 ddc_pin = GMBUS_PIN_1_BXT;
3023                 break;
3024         }
3025         return ddc_pin;
3026 }
3027
3028 static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
3029                               enum port port)
3030 {
3031         u8 ddc_pin;
3032
3033         switch (port) {
3034         case PORT_B:
3035                 ddc_pin = GMBUS_PIN_DPB;
3036                 break;
3037         case PORT_C:
3038                 ddc_pin = GMBUS_PIN_DPC;
3039                 break;
3040         case PORT_D:
3041                 ddc_pin = GMBUS_PIN_DPD;
3042                 break;
3043         default:
3044                 MISSING_CASE(port);
3045                 ddc_pin = GMBUS_PIN_DPB;
3046                 break;
3047         }
3048         return ddc_pin;
3049 }
3050
3051 static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
3052                              enum port port)
3053 {
3054         const struct ddi_vbt_port_info *info =
3055                 &dev_priv->vbt.ddi_port_info[port];
3056         u8 ddc_pin;
3057
3058         if (info->alternate_ddc_pin) {
3059                 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n",
3060                               info->alternate_ddc_pin, port_name(port));
3061                 return info->alternate_ddc_pin;
3062         }
3063
3064         if (HAS_PCH_MCC(dev_priv))
3065                 ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
3066         else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
3067                 ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
3068         else if (HAS_PCH_CNP(dev_priv))
3069                 ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
3070         else if (IS_GEN9_LP(dev_priv))
3071                 ddc_pin = bxt_port_to_ddc_pin(dev_priv, port);
3072         else if (IS_CHERRYVIEW(dev_priv))
3073                 ddc_pin = chv_port_to_ddc_pin(dev_priv, port);
3074         else
3075                 ddc_pin = g4x_port_to_ddc_pin(dev_priv, port);
3076
3077         DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n",
3078                       ddc_pin, port_name(port));
3079
3080         return ddc_pin;
3081 }
3082
3083 void intel_infoframe_init(struct intel_digital_port *intel_dig_port)
3084 {
3085         struct drm_i915_private *dev_priv =
3086                 to_i915(intel_dig_port->base.base.dev);
3087
3088         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3089                 intel_dig_port->write_infoframe = vlv_write_infoframe;
3090                 intel_dig_port->read_infoframe = vlv_read_infoframe;
3091                 intel_dig_port->set_infoframes = vlv_set_infoframes;
3092                 intel_dig_port->infoframes_enabled = vlv_infoframes_enabled;
3093         } else if (IS_G4X(dev_priv)) {
3094                 intel_dig_port->write_infoframe = g4x_write_infoframe;
3095                 intel_dig_port->read_infoframe = g4x_read_infoframe;
3096                 intel_dig_port->set_infoframes = g4x_set_infoframes;
3097                 intel_dig_port->infoframes_enabled = g4x_infoframes_enabled;
3098         } else if (HAS_DDI(dev_priv)) {
3099                 if (intel_dig_port->lspcon.active) {
3100                         intel_dig_port->write_infoframe = lspcon_write_infoframe;
3101                         intel_dig_port->read_infoframe = lspcon_read_infoframe;
3102                         intel_dig_port->set_infoframes = lspcon_set_infoframes;
3103                         intel_dig_port->infoframes_enabled = lspcon_infoframes_enabled;
3104                 } else {
3105                         intel_dig_port->write_infoframe = hsw_write_infoframe;
3106                         intel_dig_port->read_infoframe = hsw_read_infoframe;
3107                         intel_dig_port->set_infoframes = hsw_set_infoframes;
3108                         intel_dig_port->infoframes_enabled = hsw_infoframes_enabled;
3109                 }
3110         } else if (HAS_PCH_IBX(dev_priv)) {
3111                 intel_dig_port->write_infoframe = ibx_write_infoframe;
3112                 intel_dig_port->read_infoframe = ibx_read_infoframe;
3113                 intel_dig_port->set_infoframes = ibx_set_infoframes;
3114                 intel_dig_port->infoframes_enabled = ibx_infoframes_enabled;
3115         } else {
3116                 intel_dig_port->write_infoframe = cpt_write_infoframe;
3117                 intel_dig_port->read_infoframe = cpt_read_infoframe;
3118                 intel_dig_port->set_infoframes = cpt_set_infoframes;
3119                 intel_dig_port->infoframes_enabled = cpt_infoframes_enabled;
3120         }
3121 }
3122
3123 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
3124                                struct intel_connector *intel_connector)
3125 {
3126         struct drm_connector *connector = &intel_connector->base;
3127         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
3128         struct intel_encoder *intel_encoder = &intel_dig_port->base;
3129         struct drm_device *dev = intel_encoder->base.dev;
3130         struct drm_i915_private *dev_priv = to_i915(dev);
3131         enum port port = intel_encoder->port;
3132         struct cec_connector_info conn_info;
3133
3134         DRM_DEBUG_KMS("Adding HDMI connector on [ENCODER:%d:%s]\n",
3135                       intel_encoder->base.base.id, intel_encoder->base.name);
3136
3137         if (WARN(intel_dig_port->max_lanes < 4,
3138                  "Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n",
3139                  intel_dig_port->max_lanes, intel_encoder->base.base.id,
3140                  intel_encoder->base.name))
3141                 return;
3142
3143         drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
3144                            DRM_MODE_CONNECTOR_HDMIA);
3145         drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
3146
3147         connector->interlace_allowed = 1;
3148         connector->doublescan_allowed = 0;
3149         connector->stereo_allowed = 1;
3150
3151         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
3152                 connector->ycbcr_420_allowed = true;
3153
3154         intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port);
3155
3156         if (WARN_ON(port == PORT_A))
3157                 return;
3158         intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
3159
3160         if (HAS_DDI(dev_priv))
3161                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3162         else
3163                 intel_connector->get_hw_state = intel_connector_get_hw_state;
3164
3165         intel_hdmi_add_properties(intel_hdmi, connector);
3166
3167         intel_connector_attach_encoder(intel_connector, intel_encoder);
3168         intel_hdmi->attached_connector = intel_connector;
3169
3170         if (is_hdcp_supported(dev_priv, port)) {
3171                 int ret = intel_hdcp_init(intel_connector,
3172                                           &intel_hdmi_hdcp_shim);
3173                 if (ret)
3174                         DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
3175         }
3176
3177         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3178          * 0xd.  Failure to do so will result in spurious interrupts being
3179          * generated on the port when a cable is not attached.
3180          */
3181         if (IS_G45(dev_priv)) {
3182                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3183                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3184         }
3185
3186         cec_fill_conn_info_from_drm(&conn_info, connector);
3187
3188         intel_hdmi->cec_notifier =
3189                 cec_notifier_conn_register(dev->dev, port_identifier(port),
3190                                            &conn_info);
3191         if (!intel_hdmi->cec_notifier)
3192                 DRM_DEBUG_KMS("CEC notifier get failed\n");
3193 }
3194
3195 static enum intel_hotplug_state
3196 intel_hdmi_hotplug(struct intel_encoder *encoder,
3197                    struct intel_connector *connector, bool irq_received)
3198 {
3199         enum intel_hotplug_state state;
3200
3201         state = intel_encoder_hotplug(encoder, connector, irq_received);
3202
3203         /*
3204          * On many platforms the HDMI live state signal is known to be
3205          * unreliable, so we can't use it to detect if a sink is connected or
3206          * not. Instead we detect if it's connected based on whether we can
3207          * read the EDID or not. That in turn has a problem during disconnect,
3208          * since the HPD interrupt may be raised before the DDC lines get
3209          * disconnected (due to how the required length of DDC vs. HPD
3210          * connector pins are specified) and so we'll still be able to get a
3211          * valid EDID. To solve this schedule another detection cycle if this
3212          * time around we didn't detect any change in the sink's connection
3213          * status.
3214          */
3215         if (state == INTEL_HOTPLUG_UNCHANGED && irq_received)
3216                 state = INTEL_HOTPLUG_RETRY;
3217
3218         return state;
3219 }
3220
3221 void intel_hdmi_init(struct drm_i915_private *dev_priv,
3222                      i915_reg_t hdmi_reg, enum port port)
3223 {
3224         struct intel_digital_port *intel_dig_port;
3225         struct intel_encoder *intel_encoder;
3226         struct intel_connector *intel_connector;
3227
3228         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
3229         if (!intel_dig_port)
3230                 return;
3231
3232         intel_connector = intel_connector_alloc();
3233         if (!intel_connector) {
3234                 kfree(intel_dig_port);
3235                 return;
3236         }
3237
3238         intel_encoder = &intel_dig_port->base;
3239
3240         drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
3241                          &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS,
3242                          "HDMI %c", port_name(port));
3243
3244         intel_encoder->hotplug = intel_hdmi_hotplug;
3245         intel_encoder->compute_config = intel_hdmi_compute_config;
3246         if (HAS_PCH_SPLIT(dev_priv)) {
3247                 intel_encoder->disable = pch_disable_hdmi;
3248                 intel_encoder->post_disable = pch_post_disable_hdmi;
3249         } else {
3250                 intel_encoder->disable = g4x_disable_hdmi;
3251         }
3252         intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
3253         intel_encoder->get_config = intel_hdmi_get_config;
3254         if (IS_CHERRYVIEW(dev_priv)) {
3255                 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
3256                 intel_encoder->pre_enable = chv_hdmi_pre_enable;
3257                 intel_encoder->enable = vlv_enable_hdmi;
3258                 intel_encoder->post_disable = chv_hdmi_post_disable;
3259                 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
3260         } else if (IS_VALLEYVIEW(dev_priv)) {
3261                 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
3262                 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
3263                 intel_encoder->enable = vlv_enable_hdmi;
3264                 intel_encoder->post_disable = vlv_hdmi_post_disable;
3265         } else {
3266                 intel_encoder->pre_enable = intel_hdmi_pre_enable;
3267                 if (HAS_PCH_CPT(dev_priv))
3268                         intel_encoder->enable = cpt_enable_hdmi;
3269                 else if (HAS_PCH_IBX(dev_priv))
3270                         intel_encoder->enable = ibx_enable_hdmi;
3271                 else
3272                         intel_encoder->enable = g4x_enable_hdmi;
3273         }
3274
3275         intel_encoder->type = INTEL_OUTPUT_HDMI;
3276         intel_encoder->power_domain = intel_port_to_power_domain(port);
3277         intel_encoder->port = port;
3278         if (IS_CHERRYVIEW(dev_priv)) {
3279                 if (port == PORT_D)
3280                         intel_encoder->crtc_mask = BIT(PIPE_C);
3281                 else
3282                         intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B);
3283         } else {
3284                 intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C);
3285         }
3286         intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
3287         /*
3288          * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
3289          * to work on real hardware. And since g4x can send infoframes to
3290          * only one port anyway, nothing is lost by allowing it.
3291          */
3292         if (IS_G4X(dev_priv))
3293                 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
3294
3295         intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
3296         intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
3297         intel_dig_port->max_lanes = 4;
3298
3299         intel_infoframe_init(intel_dig_port);
3300
3301         intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
3302         intel_hdmi_init_connector(intel_dig_port, intel_connector);
3303 }