drivers/gpu/drm/i2c/tda998x_drv.c

   1 /*
   2  * Copyright (C) 2012 Texas Instruments
   3  * Author: Rob Clark <robdclark@gmail.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include <linux/component.h>
  19 #include <linux/gpio/consumer.h>
  20 #include <linux/hdmi.h>
  21 #include <linux/module.h>
  22 #include <linux/platform_data/tda9950.h>
  23 #include <linux/irq.h>
  24 #include <sound/asoundef.h>
  25 #include <sound/hdmi-codec.h>
  26
  27 #include <drm/drmP.h>
  28 #include <drm/drm_atomic_helper.h>
  29 #include <drm/drm_edid.h>
  30 #include <drm/drm_of.h>
  31 #include <drm/drm_probe_helper.h>
  32 #include <drm/i2c/tda998x.h>
  33
  34 #include <media/cec-notifier.h>
  35
  36 #define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
  37
  38 enum {
  39         AUDIO_ROUTE_I2S,
  40         AUDIO_ROUTE_SPDIF,
  41         AUDIO_ROUTE_NUM
  42 };
  43
  44 struct tda998x_audio_route {
  45         u8 ena_aclk;
  46         u8 mux_ap;
  47         u8 aip_clksel;
  48 };
  49
  50 struct tda998x_audio_settings {
  51         const struct tda998x_audio_route *route;
  52         struct hdmi_audio_infoframe cea;
  53         unsigned int sample_rate;
  54         u8 status[5];
  55         u8 ena_ap;
  56         u8 i2s_format;
  57         u8 cts_n;
  58 };
  59
  60 struct tda998x_priv {
  61         struct i2c_client *cec;
  62         struct i2c_client *hdmi;
  63         struct mutex mutex;
  64         u16 rev;
  65         u8 cec_addr;
  66         u8 current_page;
  67         bool is_on;
  68         bool supports_infoframes;
  69         bool sink_has_audio;
  70         u8 vip_cntrl_0;
  71         u8 vip_cntrl_1;
  72         u8 vip_cntrl_2;
  73         unsigned long tmds_clock;
  74         struct tda998x_audio_settings audio;
  75
  76         struct platform_device *audio_pdev;
  77         struct mutex audio_mutex;
  78
  79         struct mutex edid_mutex;
  80         wait_queue_head_t wq_edid;
  81         volatile int wq_edid_wait;
  82
  83         struct work_struct detect_work;
  84         struct timer_list edid_delay_timer;
  85         wait_queue_head_t edid_delay_waitq;
  86         bool edid_delay_active;
  87
  88         struct drm_encoder encoder;
  89         struct drm_bridge bridge;
  90         struct drm_connector connector;
  91
  92         u8 audio_port_enable[AUDIO_ROUTE_NUM];
  93         struct tda9950_glue cec_glue;
  94         struct gpio_desc *calib;
  95         struct cec_notifier *cec_notify;
  96 };
  97
  98 #define conn_to_tda998x_priv(x) \
  99         container_of(x, struct tda998x_priv, connector)
 100 #define enc_to_tda998x_priv(x) \
 101         container_of(x, struct tda998x_priv, encoder)
 102 #define bridge_to_tda998x_priv(x) \
 103         container_of(x, struct tda998x_priv, bridge)
 104
 105 /* The TDA9988 series of devices use a paged register scheme.. to simplify
 106  * things we encode the page # in upper bits of the register #.  To read/
 107  * write a given register, we need to make sure CURPAGE register is set
 108  * appropriately.  Which implies reads/writes are not atomic.  Fun!
 109  */
 110
 111 #define REG(page, addr) (((page) << 8) | (addr))
 112 #define REG2ADDR(reg)   ((reg) & 0xff)
 113 #define REG2PAGE(reg)   (((reg) >> 8) & 0xff)
 114
 115 #define REG_CURPAGE               0xff                /* write */
 116
 117
 118 /* Page 00h: General Control */
 119 #define REG_VERSION_LSB           REG(0x00, 0x00)     /* read */
 120 #define REG_MAIN_CNTRL0           REG(0x00, 0x01)     /* read/write */
 121 # define MAIN_CNTRL0_SR           (1 << 0)
 122 # define MAIN_CNTRL0_DECS         (1 << 1)
 123 # define MAIN_CNTRL0_DEHS         (1 << 2)
 124 # define MAIN_CNTRL0_CECS         (1 << 3)
 125 # define MAIN_CNTRL0_CEHS         (1 << 4)
 126 # define MAIN_CNTRL0_SCALER       (1 << 7)
 127 #define REG_VERSION_MSB           REG(0x00, 0x02)     /* read */
 128 #define REG_SOFTRESET             REG(0x00, 0x0a)     /* write */
 129 # define SOFTRESET_AUDIO          (1 << 0)
 130 # define SOFTRESET_I2C_MASTER     (1 << 1)
 131 #define REG_DDC_DISABLE           REG(0x00, 0x0b)     /* read/write */
 132 #define REG_CCLK_ON               REG(0x00, 0x0c)     /* read/write */
 133 #define REG_I2C_MASTER            REG(0x00, 0x0d)     /* read/write */
 134 # define I2C_MASTER_DIS_MM        (1 << 0)
 135 # define I2C_MASTER_DIS_FILT      (1 << 1)
 136 # define I2C_MASTER_APP_STRT_LAT  (1 << 2)
 137 #define REG_FEAT_POWERDOWN        REG(0x00, 0x0e)     /* read/write */
 138 # define FEAT_POWERDOWN_PREFILT   BIT(0)
 139 # define FEAT_POWERDOWN_CSC       BIT(1)
 140 # define FEAT_POWERDOWN_SPDIF     (1 << 3)
 141 #define REG_INT_FLAGS_0           REG(0x00, 0x0f)     /* read/write */
 142 #define REG_INT_FLAGS_1           REG(0x00, 0x10)     /* read/write */
 143 #define REG_INT_FLAGS_2           REG(0x00, 0x11)     /* read/write */
 144 # define INT_FLAGS_2_EDID_BLK_RD  (1 << 1)
 145 #define REG_ENA_ACLK              REG(0x00, 0x16)     /* read/write */
 146 #define REG_ENA_VP_0              REG(0x00, 0x18)     /* read/write */
 147 #define REG_ENA_VP_1              REG(0x00, 0x19)     /* read/write */
 148 #define REG_ENA_VP_2              REG(0x00, 0x1a)     /* read/write */
 149 #define REG_ENA_AP                REG(0x00, 0x1e)     /* read/write */
 150 #define REG_VIP_CNTRL_0           REG(0x00, 0x20)     /* write */
 151 # define VIP_CNTRL_0_MIRR_A       (1 << 7)
 152 # define VIP_CNTRL_0_SWAP_A(x)    (((x) & 7) << 4)
 153 # define VIP_CNTRL_0_MIRR_B       (1 << 3)
 154 # define VIP_CNTRL_0_SWAP_B(x)    (((x) & 7) << 0)
 155 #define REG_VIP_CNTRL_1           REG(0x00, 0x21)     /* write */
 156 # define VIP_CNTRL_1_MIRR_C       (1 << 7)
 157 # define VIP_CNTRL_1_SWAP_C(x)    (((x) & 7) << 4)
 158 # define VIP_CNTRL_1_MIRR_D       (1 << 3)
 159 # define VIP_CNTRL_1_SWAP_D(x)    (((x) & 7) << 0)
 160 #define REG_VIP_CNTRL_2           REG(0x00, 0x22)     /* write */
 161 # define VIP_CNTRL_2_MIRR_E       (1 << 7)
 162 # define VIP_CNTRL_2_SWAP_E(x)    (((x) & 7) << 4)
 163 # define VIP_CNTRL_2_MIRR_F       (1 << 3)
 164 # define VIP_CNTRL_2_SWAP_F(x)    (((x) & 7) << 0)
 165 #define REG_VIP_CNTRL_3           REG(0x00, 0x23)     /* write */
 166 # define VIP_CNTRL_3_X_TGL        (1 << 0)
 167 # define VIP_CNTRL_3_H_TGL        (1 << 1)
 168 # define VIP_CNTRL_3_V_TGL        (1 << 2)
 169 # define VIP_CNTRL_3_EMB          (1 << 3)
 170 # define VIP_CNTRL_3_SYNC_DE      (1 << 4)
 171 # define VIP_CNTRL_3_SYNC_HS      (1 << 5)
 172 # define VIP_CNTRL_3_DE_INT       (1 << 6)
 173 # define VIP_CNTRL_3_EDGE         (1 << 7)
 174 #define REG_VIP_CNTRL_4           REG(0x00, 0x24)     /* write */
 175 # define VIP_CNTRL_4_BLC(x)       (((x) & 3) << 0)
 176 # define VIP_CNTRL_4_BLANKIT(x)   (((x) & 3) << 2)
 177 # define VIP_CNTRL_4_CCIR656      (1 << 4)
 178 # define VIP_CNTRL_4_656_ALT      (1 << 5)
 179 # define VIP_CNTRL_4_TST_656      (1 << 6)
 180 # define VIP_CNTRL_4_TST_PAT      (1 << 7)
 181 #define REG_VIP_CNTRL_5           REG(0x00, 0x25)     /* write */
 182 # define VIP_CNTRL_5_CKCASE       (1 << 0)
 183 # define VIP_CNTRL_5_SP_CNT(x)    (((x) & 3) << 1)
 184 #define REG_MUX_AP                REG(0x00, 0x26)     /* read/write */
 185 # define MUX_AP_SELECT_I2S        0x64
 186 # define MUX_AP_SELECT_SPDIF      0x40
 187 #define REG_MUX_VP_VIP_OUT        REG(0x00, 0x27)     /* read/write */
 188 #define REG_MAT_CONTRL            REG(0x00, 0x80)     /* write */
 189 # define MAT_CONTRL_MAT_SC(x)     (((x) & 3) << 0)
 190 # define MAT_CONTRL_MAT_BP        (1 << 2)
 191 #define REG_VIDFORMAT             REG(0x00, 0xa0)     /* write */
 192 #define REG_REFPIX_MSB            REG(0x00, 0xa1)     /* write */
 193 #define REG_REFPIX_LSB            REG(0x00, 0xa2)     /* write */
 194 #define REG_REFLINE_MSB           REG(0x00, 0xa3)     /* write */
 195 #define REG_REFLINE_LSB           REG(0x00, 0xa4)     /* write */
 196 #define REG_NPIX_MSB              REG(0x00, 0xa5)     /* write */
 197 #define REG_NPIX_LSB              REG(0x00, 0xa6)     /* write */
 198 #define REG_NLINE_MSB             REG(0x00, 0xa7)     /* write */
 199 #define REG_NLINE_LSB             REG(0x00, 0xa8)     /* write */
 200 #define REG_VS_LINE_STRT_1_MSB    REG(0x00, 0xa9)     /* write */
 201 #define REG_VS_LINE_STRT_1_LSB    REG(0x00, 0xaa)     /* write */
 202 #define REG_VS_PIX_STRT_1_MSB     REG(0x00, 0xab)     /* write */
 203 #define REG_VS_PIX_STRT_1_LSB     REG(0x00, 0xac)     /* write */
 204 #define REG_VS_LINE_END_1_MSB     REG(0x00, 0xad)     /* write */
 205 #define REG_VS_LINE_END_1_LSB     REG(0x00, 0xae)     /* write */
 206 #define REG_VS_PIX_END_1_MSB      REG(0x00, 0xaf)     /* write */
 207 #define REG_VS_PIX_END_1_LSB      REG(0x00, 0xb0)     /* write */
 208 #define REG_VS_LINE_STRT_2_MSB    REG(0x00, 0xb1)     /* write */
 209 #define REG_VS_LINE_STRT_2_LSB    REG(0x00, 0xb2)     /* write */
 210 #define REG_VS_PIX_STRT_2_MSB     REG(0x00, 0xb3)     /* write */
 211 #define REG_VS_PIX_STRT_2_LSB     REG(0x00, 0xb4)     /* write */
 212 #define REG_VS_LINE_END_2_MSB     REG(0x00, 0xb5)     /* write */
 213 #define REG_VS_LINE_END_2_LSB     REG(0x00, 0xb6)     /* write */
 214 #define REG_VS_PIX_END_2_MSB      REG(0x00, 0xb7)     /* write */
 215 #define REG_VS_PIX_END_2_LSB      REG(0x00, 0xb8)     /* write */
 216 #define REG_HS_PIX_START_MSB      REG(0x00, 0xb9)     /* write */
 217 #define REG_HS_PIX_START_LSB      REG(0x00, 0xba)     /* write */
 218 #define REG_HS_PIX_STOP_MSB       REG(0x00, 0xbb)     /* write */
 219 #define REG_HS_PIX_STOP_LSB       REG(0x00, 0xbc)     /* write */
 220 #define REG_VWIN_START_1_MSB      REG(0x00, 0xbd)     /* write */
 221 #define REG_VWIN_START_1_LSB      REG(0x00, 0xbe)     /* write */
 222 #define REG_VWIN_END_1_MSB        REG(0x00, 0xbf)     /* write */
 223 #define REG_VWIN_END_1_LSB        REG(0x00, 0xc0)     /* write */
 224 #define REG_VWIN_START_2_MSB      REG(0x00, 0xc1)     /* write */
 225 #define REG_VWIN_START_2_LSB      REG(0x00, 0xc2)     /* write */
 226 #define REG_VWIN_END_2_MSB        REG(0x00, 0xc3)     /* write */
 227 #define REG_VWIN_END_2_LSB        REG(0x00, 0xc4)     /* write */
 228 #define REG_DE_START_MSB          REG(0x00, 0xc5)     /* write */
 229 #define REG_DE_START_LSB          REG(0x00, 0xc6)     /* write */
 230 #define REG_DE_STOP_MSB           REG(0x00, 0xc7)     /* write */
 231 #define REG_DE_STOP_LSB           REG(0x00, 0xc8)     /* write */
 232 #define REG_TBG_CNTRL_0           REG(0x00, 0xca)     /* write */
 233 # define TBG_CNTRL_0_TOP_TGL      (1 << 0)
 234 # define TBG_CNTRL_0_TOP_SEL      (1 << 1)
 235 # define TBG_CNTRL_0_DE_EXT       (1 << 2)
 236 # define TBG_CNTRL_0_TOP_EXT      (1 << 3)
 237 # define TBG_CNTRL_0_FRAME_DIS    (1 << 5)
 238 # define TBG_CNTRL_0_SYNC_MTHD    (1 << 6)
 239 # define TBG_CNTRL_0_SYNC_ONCE    (1 << 7)
 240 #define REG_TBG_CNTRL_1           REG(0x00, 0xcb)     /* write */
 241 # define TBG_CNTRL_1_H_TGL        (1 << 0)
 242 # define TBG_CNTRL_1_V_TGL        (1 << 1)
 243 # define TBG_CNTRL_1_TGL_EN       (1 << 2)
 244 # define TBG_CNTRL_1_X_EXT        (1 << 3)
 245 # define TBG_CNTRL_1_H_EXT        (1 << 4)
 246 # define TBG_CNTRL_1_V_EXT        (1 << 5)
 247 # define TBG_CNTRL_1_DWIN_DIS     (1 << 6)
 248 #define REG_ENABLE_SPACE          REG(0x00, 0xd6)     /* write */
 249 #define REG_HVF_CNTRL_0           REG(0x00, 0xe4)     /* write */
 250 # define HVF_CNTRL_0_SM           (1 << 7)
 251 # define HVF_CNTRL_0_RWB          (1 << 6)
 252 # define HVF_CNTRL_0_PREFIL(x)    (((x) & 3) << 2)
 253 # define HVF_CNTRL_0_INTPOL(x)    (((x) & 3) << 0)
 254 #define REG_HVF_CNTRL_1           REG(0x00, 0xe5)     /* write */
 255 # define HVF_CNTRL_1_FOR          (1 << 0)
 256 # define HVF_CNTRL_1_YUVBLK       (1 << 1)
 257 # define HVF_CNTRL_1_VQR(x)       (((x) & 3) << 2)
 258 # define HVF_CNTRL_1_PAD(x)       (((x) & 3) << 4)
 259 # define HVF_CNTRL_1_SEMI_PLANAR  (1 << 6)
 260 #define REG_RPT_CNTRL             REG(0x00, 0xf0)     /* write */
 261 # define RPT_CNTRL_REPEAT(x)      ((x) & 15)
 262 #define REG_I2S_FORMAT            REG(0x00, 0xfc)     /* read/write */
 263 # define I2S_FORMAT_PHILIPS       (0 << 0)
 264 # define I2S_FORMAT_LEFT_J        (2 << 0)
 265 # define I2S_FORMAT_RIGHT_J       (3 << 0)
 266 #define REG_AIP_CLKSEL            REG(0x00, 0xfd)     /* write */
 267 # define AIP_CLKSEL_AIP_SPDIF     (0 << 3)
 268 # define AIP_CLKSEL_AIP_I2S       (1 << 3)
 269 # define AIP_CLKSEL_FS_ACLK       (0 << 0)
 270 # define AIP_CLKSEL_FS_MCLK       (1 << 0)
 271 # define AIP_CLKSEL_FS_FS64SPDIF  (2 << 0)
 272
 273 /* Page 02h: PLL settings */
 274 #define REG_PLL_SERIAL_1          REG(0x02, 0x00)     /* read/write */
 275 # define PLL_SERIAL_1_SRL_FDN     (1 << 0)
 276 # define PLL_SERIAL_1_SRL_IZ(x)   (((x) & 3) << 1)
 277 # define PLL_SERIAL_1_SRL_MAN_IZ  (1 << 6)
 278 #define REG_PLL_SERIAL_2          REG(0x02, 0x01)     /* read/write */
 279 # define PLL_SERIAL_2_SRL_NOSC(x) ((x) << 0)
 280 # define PLL_SERIAL_2_SRL_PR(x)   (((x) & 0xf) << 4)
 281 #define REG_PLL_SERIAL_3          REG(0x02, 0x02)     /* read/write */
 282 # define PLL_SERIAL_3_SRL_CCIR    (1 << 0)
 283 # define PLL_SERIAL_3_SRL_DE      (1 << 2)
 284 # define PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4)
 285 #define REG_SERIALIZER            REG(0x02, 0x03)     /* read/write */
 286 #define REG_BUFFER_OUT            REG(0x02, 0x04)     /* read/write */
 287 #define REG_PLL_SCG1              REG(0x02, 0x05)     /* read/write */
 288 #define REG_PLL_SCG2              REG(0x02, 0x06)     /* read/write */
 289 #define REG_PLL_SCGN1             REG(0x02, 0x07)     /* read/write */
 290 #define REG_PLL_SCGN2             REG(0x02, 0x08)     /* read/write */
 291 #define REG_PLL_SCGR1             REG(0x02, 0x09)     /* read/write */
 292 #define REG_PLL_SCGR2             REG(0x02, 0x0a)     /* read/write */
 293 #define REG_AUDIO_DIV             REG(0x02, 0x0e)     /* read/write */
 294 # define AUDIO_DIV_SERCLK_1       0
 295 # define AUDIO_DIV_SERCLK_2       1
 296 # define AUDIO_DIV_SERCLK_4       2
 297 # define AUDIO_DIV_SERCLK_8       3
 298 # define AUDIO_DIV_SERCLK_16      4
 299 # define AUDIO_DIV_SERCLK_32      5
 300 #define REG_SEL_CLK               REG(0x02, 0x11)     /* read/write */
 301 # define SEL_CLK_SEL_CLK1         (1 << 0)
 302 # define SEL_CLK_SEL_VRF_CLK(x)   (((x) & 3) << 1)
 303 # define SEL_CLK_ENA_SC_CLK       (1 << 3)
 304 #define REG_ANA_GENERAL           REG(0x02, 0x12)     /* read/write */
 305
 306
 307 /* Page 09h: EDID Control */
 308 #define REG_EDID_DATA_0           REG(0x09, 0x00)     /* read */
 309 /* next 127 successive registers are the EDID block */
 310 #define REG_EDID_CTRL             REG(0x09, 0xfa)     /* read/write */
 311 #define REG_DDC_ADDR              REG(0x09, 0xfb)     /* read/write */
 312 #define REG_DDC_OFFS              REG(0x09, 0xfc)     /* read/write */
 313 #define REG_DDC_SEGM_ADDR         REG(0x09, 0xfd)     /* read/write */
 314 #define REG_DDC_SEGM              REG(0x09, 0xfe)     /* read/write */
 315
 316
 317 /* Page 10h: information frames and packets */
 318 #define REG_IF1_HB0               REG(0x10, 0x20)     /* read/write */
 319 #define REG_IF2_HB0               REG(0x10, 0x40)     /* read/write */
 320 #define REG_IF3_HB0               REG(0x10, 0x60)     /* read/write */
 321 #define REG_IF4_HB0               REG(0x10, 0x80)     /* read/write */
 322 #define REG_IF5_HB0               REG(0x10, 0xa0)     /* read/write */
 323
 324
 325 /* Page 11h: audio settings and content info packets */
 326 #define REG_AIP_CNTRL_0           REG(0x11, 0x00)     /* read/write */
 327 # define AIP_CNTRL_0_RST_FIFO     (1 << 0)
 328 # define AIP_CNTRL_0_SWAP         (1 << 1)
 329 # define AIP_CNTRL_0_LAYOUT       (1 << 2)
 330 # define AIP_CNTRL_0_ACR_MAN      (1 << 5)
 331 # define AIP_CNTRL_0_RST_CTS      (1 << 6)
 332 #define REG_CA_I2S                REG(0x11, 0x01)     /* read/write */
 333 # define CA_I2S_CA_I2S(x)         (((x) & 31) << 0)
 334 # define CA_I2S_HBR_CHSTAT        (1 << 6)
 335 #define REG_LATENCY_RD            REG(0x11, 0x04)     /* read/write */
 336 #define REG_ACR_CTS_0             REG(0x11, 0x05)     /* read/write */
 337 #define REG_ACR_CTS_1             REG(0x11, 0x06)     /* read/write */
 338 #define REG_ACR_CTS_2             REG(0x11, 0x07)     /* read/write */
 339 #define REG_ACR_N_0               REG(0x11, 0x08)     /* read/write */
 340 #define REG_ACR_N_1               REG(0x11, 0x09)     /* read/write */
 341 #define REG_ACR_N_2               REG(0x11, 0x0a)     /* read/write */
 342 #define REG_CTS_N                 REG(0x11, 0x0c)     /* read/write */
 343 # define CTS_N_K(x)               (((x) & 7) << 0)
 344 # define CTS_N_M(x)               (((x) & 3) << 4)
 345 #define REG_ENC_CNTRL             REG(0x11, 0x0d)     /* read/write */
 346 # define ENC_CNTRL_RST_ENC        (1 << 0)
 347 # define ENC_CNTRL_RST_SEL        (1 << 1)
 348 # define ENC_CNTRL_CTL_CODE(x)    (((x) & 3) << 2)
 349 #define REG_DIP_FLAGS             REG(0x11, 0x0e)     /* read/write */
 350 # define DIP_FLAGS_ACR            (1 << 0)
 351 # define DIP_FLAGS_GC             (1 << 1)
 352 #define REG_DIP_IF_FLAGS          REG(0x11, 0x0f)     /* read/write */
 353 # define DIP_IF_FLAGS_IF1         (1 << 1)
 354 # define DIP_IF_FLAGS_IF2         (1 << 2)
 355 # define DIP_IF_FLAGS_IF3         (1 << 3)
 356 # define DIP_IF_FLAGS_IF4         (1 << 4)
 357 # define DIP_IF_FLAGS_IF5         (1 << 5)
 358 #define REG_CH_STAT_B(x)          REG(0x11, 0x14 + (x)) /* read/write */
 359
 360
 361 /* Page 12h: HDCP and OTP */
 362 #define REG_TX3                   REG(0x12, 0x9a)     /* read/write */
 363 #define REG_TX4                   REG(0x12, 0x9b)     /* read/write */
 364 # define TX4_PD_RAM               (1 << 1)
 365 #define REG_TX33                  REG(0x12, 0xb8)     /* read/write */
 366 # define TX33_HDMI                (1 << 1)
 367
 368
 369 /* Page 13h: Gamut related metadata packets */
 370
 371
 372
 373 /* CEC registers: (not paged)
 374  */
 375 #define REG_CEC_INTSTATUS         0xee                /* read */
 376 # define CEC_INTSTATUS_CEC        (1 << 0)
 377 # define CEC_INTSTATUS_HDMI       (1 << 1)
 378 #define REG_CEC_CAL_XOSC_CTRL1    0xf2
 379 # define CEC_CAL_XOSC_CTRL1_ENA_CAL     BIT(0)
 380 #define REG_CEC_DES_FREQ2         0xf5
 381 # define CEC_DES_FREQ2_DIS_AUTOCAL BIT(7)
 382 #define REG_CEC_CLK               0xf6
 383 # define CEC_CLK_FRO              0x11
 384 #define REG_CEC_FRO_IM_CLK_CTRL   0xfb                /* read/write */
 385 # define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7)
 386 # define CEC_FRO_IM_CLK_CTRL_ENA_OTP   (1 << 6)
 387 # define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1)
 388 # define CEC_FRO_IM_CLK_CTRL_FRO_DIV   (1 << 0)
 389 #define REG_CEC_RXSHPDINTENA      0xfc                /* read/write */
 390 #define REG_CEC_RXSHPDINT         0xfd                /* read */
 391 # define CEC_RXSHPDINT_RXSENS     BIT(0)
 392 # define CEC_RXSHPDINT_HPD        BIT(1)
 393 #define REG_CEC_RXSHPDLEV         0xfe                /* read */
 394 # define CEC_RXSHPDLEV_RXSENS     (1 << 0)
 395 # define CEC_RXSHPDLEV_HPD        (1 << 1)
 396
 397 #define REG_CEC_ENAMODS           0xff                /* read/write */
 398 # define CEC_ENAMODS_EN_CEC_CLK   (1 << 7)
 399 # define CEC_ENAMODS_DIS_FRO      (1 << 6)
 400 # define CEC_ENAMODS_DIS_CCLK     (1 << 5)
 401 # define CEC_ENAMODS_EN_RXSENS    (1 << 2)
 402 # define CEC_ENAMODS_EN_HDMI      (1 << 1)
 403 # define CEC_ENAMODS_EN_CEC       (1 << 0)
 404
 405
 406 /* Device versions: */
 407 #define TDA9989N2                 0x0101
 408 #define TDA19989                  0x0201
 409 #define TDA19989N2                0x0202
 410 #define TDA19988                  0x0301
 411
 412 static void
 413 cec_write(struct tda998x_priv *priv, u16 addr, u8 val)
 414 {
 415         u8 buf[] = {addr, val};
 416         struct i2c_msg msg = {
 417                 .addr = priv->cec_addr,
 418                 .len = 2,
 419                 .buf = buf,
 420         };
 421         int ret;
 422
 423         ret = i2c_transfer(priv->hdmi->adapter, &msg, 1);
 424         if (ret < 0)
 425                 dev_err(&priv->hdmi->dev, "Error %d writing to cec:0x%x\n",
 426                         ret, addr);
 427 }
 428
 429 static u8
 430 cec_read(struct tda998x_priv *priv, u8 addr)
 431 {
 432         u8 val;
 433         struct i2c_msg msg[2] = {
 434                 {
 435                         .addr = priv->cec_addr,
 436                         .len = 1,
 437                         .buf = &addr,
 438                 }, {
 439                         .addr = priv->cec_addr,
 440                         .flags = I2C_M_RD,
 441                         .len = 1,
 442                         .buf = &val,
 443                 },
 444         };
 445         int ret;
 446
 447         ret = i2c_transfer(priv->hdmi->adapter, msg, ARRAY_SIZE(msg));
 448         if (ret < 0) {
 449                 dev_err(&priv->hdmi->dev, "Error %d reading from cec:0x%x\n",
 450                         ret, addr);
 451                 val = 0;
 452         }
 453
 454         return val;
 455 }
 456
 457 static void cec_enamods(struct tda998x_priv *priv, u8 mods, bool enable)
 458 {
 459         int val = cec_read(priv, REG_CEC_ENAMODS);
 460
 461         if (val < 0)
 462                 return;
 463
 464         if (enable)
 465                 val |= mods;
 466         else
 467                 val &= ~mods;
 468
 469         cec_write(priv, REG_CEC_ENAMODS, val);
 470 }
 471
 472 static void tda998x_cec_set_calibration(struct tda998x_priv *priv, bool enable)
 473 {
 474         if (enable) {
 475                 u8 val;
 476
 477                 cec_write(priv, 0xf3, 0xc0);
 478                 cec_write(priv, 0xf4, 0xd4);
 479
 480                 /* Enable automatic calibration mode */
 481                 val = cec_read(priv, REG_CEC_DES_FREQ2);
 482                 val &= ~CEC_DES_FREQ2_DIS_AUTOCAL;
 483                 cec_write(priv, REG_CEC_DES_FREQ2, val);
 484
 485                 /* Enable free running oscillator */
 486                 cec_write(priv, REG_CEC_CLK, CEC_CLK_FRO);
 487                 cec_enamods(priv, CEC_ENAMODS_DIS_FRO, false);
 488
 489                 cec_write(priv, REG_CEC_CAL_XOSC_CTRL1,
 490                           CEC_CAL_XOSC_CTRL1_ENA_CAL);
 491         } else {
 492                 cec_write(priv, REG_CEC_CAL_XOSC_CTRL1, 0);
 493         }
 494 }
 495
 496 /*
 497  * Calibration for the internal oscillator: we need to set calibration mode,
 498  * and then pulse the IRQ line low for a 10ms ± 1% period.
 499  */
 500 static void tda998x_cec_calibration(struct tda998x_priv *priv)
 501 {
 502         struct gpio_desc *calib = priv->calib;
 503
 504         mutex_lock(&priv->edid_mutex);
 505         if (priv->hdmi->irq > 0)
 506                 disable_irq(priv->hdmi->irq);
 507         gpiod_direction_output(calib, 1);
 508         tda998x_cec_set_calibration(priv, true);
 509
 510         local_irq_disable();
 511         gpiod_set_value(calib, 0);
 512         mdelay(10);
 513         gpiod_set_value(calib, 1);
 514         local_irq_enable();
 515
 516         tda998x_cec_set_calibration(priv, false);
 517         gpiod_direction_input(calib);
 518         if (priv->hdmi->irq > 0)
 519                 enable_irq(priv->hdmi->irq);
 520         mutex_unlock(&priv->edid_mutex);
 521 }
 522
 523 static int tda998x_cec_hook_init(void *data)
 524 {
 525         struct tda998x_priv *priv = data;
 526         struct gpio_desc *calib;
 527
 528         calib = gpiod_get(&priv->hdmi->dev, "nxp,calib", GPIOD_ASIS);
 529         if (IS_ERR(calib)) {
 530                 dev_warn(&priv->hdmi->dev, "failed to get calibration gpio: %ld\n",
 531                          PTR_ERR(calib));
 532                 return PTR_ERR(calib);
 533         }
 534
 535         priv->calib = calib;
 536
 537         return 0;
 538 }
 539
 540 static void tda998x_cec_hook_exit(void *data)
 541 {
 542         struct tda998x_priv *priv = data;
 543
 544         gpiod_put(priv->calib);
 545         priv->calib = NULL;
 546 }
 547
 548 static int tda998x_cec_hook_open(void *data)
 549 {
 550         struct tda998x_priv *priv = data;
 551
 552         cec_enamods(priv, CEC_ENAMODS_EN_CEC_CLK | CEC_ENAMODS_EN_CEC, true);
 553         tda998x_cec_calibration(priv);
 554
 555         return 0;
 556 }
 557
 558 static void tda998x_cec_hook_release(void *data)
 559 {
 560         struct tda998x_priv *priv = data;
 561
 562         cec_enamods(priv, CEC_ENAMODS_EN_CEC_CLK | CEC_ENAMODS_EN_CEC, false);
 563 }
 564
 565 static int
 566 set_page(struct tda998x_priv *priv, u16 reg)
 567 {
 568         if (REG2PAGE(reg) != priv->current_page) {
 569                 struct i2c_client *client = priv->hdmi;
 570                 u8 buf[] = {
 571                                 REG_CURPAGE, REG2PAGE(reg)
 572                 };
 573                 int ret = i2c_master_send(client, buf, sizeof(buf));
 574                 if (ret < 0) {
 575                         dev_err(&client->dev, "%s %04x err %d\n", __func__,
 576                                         reg, ret);
 577                         return ret;
 578                 }
 579
 580                 priv->current_page = REG2PAGE(reg);
 581         }
 582         return 0;
 583 }
 584
 585 static int
 586 reg_read_range(struct tda998x_priv *priv, u16 reg, char *buf, int cnt)
 587 {
 588         struct i2c_client *client = priv->hdmi;
 589         u8 addr = REG2ADDR(reg);
 590         int ret;
 591
 592         mutex_lock(&priv->mutex);
 593         ret = set_page(priv, reg);
 594         if (ret < 0)
 595                 goto out;
 596
 597         ret = i2c_master_send(client, &addr, sizeof(addr));
 598         if (ret < 0)
 599                 goto fail;
 600
 601         ret = i2c_master_recv(client, buf, cnt);
 602         if (ret < 0)
 603                 goto fail;
 604
 605         goto out;
 606
 607 fail:
 608         dev_err(&client->dev, "Error %d reading from 0x%x\n", ret, reg);
 609 out:
 610         mutex_unlock(&priv->mutex);
 611         return ret;
 612 }
 613
 614 #define MAX_WRITE_RANGE_BUF 32
 615
 616 static void
 617 reg_write_range(struct tda998x_priv *priv, u16 reg, u8 *p, int cnt)
 618 {
 619         struct i2c_client *client = priv->hdmi;
 620         /* This is the maximum size of the buffer passed in */
 621         u8 buf[MAX_WRITE_RANGE_BUF + 1];
 622         int ret;
 623
 624         if (cnt > MAX_WRITE_RANGE_BUF) {
 625                 dev_err(&client->dev, "Fixed write buffer too small (%d)\n",
 626                                 MAX_WRITE_RANGE_BUF);
 627                 return;
 628         }
 629
 630         buf[0] = REG2ADDR(reg);
 631         memcpy(&buf[1], p, cnt);
 632
 633         mutex_lock(&priv->mutex);
 634         ret = set_page(priv, reg);
 635         if (ret < 0)
 636                 goto out;
 637
 638         ret = i2c_master_send(client, buf, cnt + 1);
 639         if (ret < 0)
 640                 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
 641 out:
 642         mutex_unlock(&priv->mutex);
 643 }
 644
 645 static int
 646 reg_read(struct tda998x_priv *priv, u16 reg)
 647 {
 648         u8 val = 0;
 649         int ret;
 650
 651         ret = reg_read_range(priv, reg, &val, sizeof(val));
 652         if (ret < 0)
 653                 return ret;
 654         return val;
 655 }
 656
 657 static void
 658 reg_write(struct tda998x_priv *priv, u16 reg, u8 val)
 659 {
 660         struct i2c_client *client = priv->hdmi;
 661         u8 buf[] = {REG2ADDR(reg), val};
 662         int ret;
 663
 664         mutex_lock(&priv->mutex);
 665         ret = set_page(priv, reg);
 666         if (ret < 0)
 667                 goto out;
 668
 669         ret = i2c_master_send(client, buf, sizeof(buf));
 670         if (ret < 0)
 671                 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
 672 out:
 673         mutex_unlock(&priv->mutex);
 674 }
 675
 676 static void
 677 reg_write16(struct tda998x_priv *priv, u16 reg, u16 val)
 678 {
 679         struct i2c_client *client = priv->hdmi;
 680         u8 buf[] = {REG2ADDR(reg), val >> 8, val};
 681         int ret;
 682
 683         mutex_lock(&priv->mutex);
 684         ret = set_page(priv, reg);
 685         if (ret < 0)
 686                 goto out;
 687
 688         ret = i2c_master_send(client, buf, sizeof(buf));
 689         if (ret < 0)
 690                 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
 691 out:
 692         mutex_unlock(&priv->mutex);
 693 }
 694
 695 static void
 696 reg_set(struct tda998x_priv *priv, u16 reg, u8 val)
 697 {
 698         int old_val;
 699
 700         old_val = reg_read(priv, reg);
 701         if (old_val >= 0)
 702                 reg_write(priv, reg, old_val | val);
 703 }
 704
 705 static void
 706 reg_clear(struct tda998x_priv *priv, u16 reg, u8 val)
 707 {
 708         int old_val;
 709
 710         old_val = reg_read(priv, reg);
 711         if (old_val >= 0)
 712                 reg_write(priv, reg, old_val & ~val);
 713 }
 714
 715 static void
 716 tda998x_reset(struct tda998x_priv *priv)
 717 {
 718         /* reset audio and i2c master: */
 719         reg_write(priv, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER);
 720         msleep(50);
 721         reg_write(priv, REG_SOFTRESET, 0);
 722         msleep(50);
 723
 724         /* reset transmitter: */
 725         reg_set(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
 726         reg_clear(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
 727
 728         /* PLL registers common configuration */
 729         reg_write(priv, REG_PLL_SERIAL_1, 0x00);
 730         reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1));
 731         reg_write(priv, REG_PLL_SERIAL_3, 0x00);
 732         reg_write(priv, REG_SERIALIZER,   0x00);
 733         reg_write(priv, REG_BUFFER_OUT,   0x00);
 734         reg_write(priv, REG_PLL_SCG1,     0x00);
 735         reg_write(priv, REG_AUDIO_DIV,    AUDIO_DIV_SERCLK_8);
 736         reg_write(priv, REG_SEL_CLK,      SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
 737         reg_write(priv, REG_PLL_SCGN1,    0xfa);
 738         reg_write(priv, REG_PLL_SCGN2,    0x00);
 739         reg_write(priv, REG_PLL_SCGR1,    0x5b);
 740         reg_write(priv, REG_PLL_SCGR2,    0x00);
 741         reg_write(priv, REG_PLL_SCG2,     0x10);
 742
 743         /* Write the default value MUX register */
 744         reg_write(priv, REG_MUX_VP_VIP_OUT, 0x24);
 745 }
 746
 747 /*
 748  * The TDA998x has a problem when trying to read the EDID close to a
 749  * HPD assertion: it needs a delay of 100ms to avoid timing out while
 750  * trying to read EDID data.
 751  *
 752  * However, tda998x_connector_get_modes() may be called at any moment
 753  * after tda998x_connector_detect() indicates that we are connected, so
 754  * we need to delay probing modes in tda998x_connector_get_modes() after
 755  * we have seen a HPD inactive->active transition.  This code implements
 756  * that delay.
 757  */
 758 static void tda998x_edid_delay_done(struct timer_list *t)
 759 {
 760         struct tda998x_priv *priv = from_timer(priv, t, edid_delay_timer);
 761
 762         priv->edid_delay_active = false;
 763         wake_up(&priv->edid_delay_waitq);
 764         schedule_work(&priv->detect_work);
 765 }
 766
 767 static void tda998x_edid_delay_start(struct tda998x_priv *priv)
 768 {
 769         priv->edid_delay_active = true;
 770         mod_timer(&priv->edid_delay_timer, jiffies + HZ/10);
 771 }
 772
 773 static int tda998x_edid_delay_wait(struct tda998x_priv *priv)
 774 {
 775         return wait_event_killable(priv->edid_delay_waitq, !priv->edid_delay_active);
 776 }
 777
 778 /*
 779  * We need to run the KMS hotplug event helper outside of our threaded
 780  * interrupt routine as this can call back into our get_modes method,
 781  * which will want to make use of interrupts.
 782  */
 783 static void tda998x_detect_work(struct work_struct *work)
 784 {
 785         struct tda998x_priv *priv =
 786                 container_of(work, struct tda998x_priv, detect_work);
 787         struct drm_device *dev = priv->connector.dev;
 788
 789         if (dev)
 790                 drm_kms_helper_hotplug_event(dev);
 791 }
 792
 793 /*
 794  * only 2 interrupts may occur: screen plug/unplug and EDID read
 795  */
 796 static irqreturn_t tda998x_irq_thread(int irq, void *data)
 797 {
 798         struct tda998x_priv *priv = data;
 799         u8 sta, cec, lvl, flag0, flag1, flag2;
 800         bool handled = false;
 801
 802         sta = cec_read(priv, REG_CEC_INTSTATUS);
 803         if (sta & CEC_INTSTATUS_HDMI) {
 804                 cec = cec_read(priv, REG_CEC_RXSHPDINT);
 805                 lvl = cec_read(priv, REG_CEC_RXSHPDLEV);
 806                 flag0 = reg_read(priv, REG_INT_FLAGS_0);
 807                 flag1 = reg_read(priv, REG_INT_FLAGS_1);
 808                 flag2 = reg_read(priv, REG_INT_FLAGS_2);
 809                 DRM_DEBUG_DRIVER(
 810                         "tda irq sta %02x cec %02x lvl %02x f0 %02x f1 %02x f2 %02x\n",
 811                         sta, cec, lvl, flag0, flag1, flag2);
 812
 813                 if (cec & CEC_RXSHPDINT_HPD) {
 814                         if (lvl & CEC_RXSHPDLEV_HPD) {
 815                                 tda998x_edid_delay_start(priv);
 816                         } else {
 817                                 schedule_work(&priv->detect_work);
 818                                 cec_notifier_set_phys_addr(priv->cec_notify,
 819                                                    CEC_PHYS_ADDR_INVALID);
 820                         }
 821
 822                         handled = true;
 823                 }
 824
 825                 if ((flag2 & INT_FLAGS_2_EDID_BLK_RD) && priv->wq_edid_wait) {
 826                         priv->wq_edid_wait = 0;
 827                         wake_up(&priv->wq_edid);
 828                         handled = true;
 829                 }
 830         }
 831
 832         return IRQ_RETVAL(handled);
 833 }
 834
 835 static void
 836 tda998x_write_if(struct tda998x_priv *priv, u8 bit, u16 addr,
 837                  union hdmi_infoframe *frame)
 838 {
 839         u8 buf[MAX_WRITE_RANGE_BUF];
 840         ssize_t len;
 841
 842         len = hdmi_infoframe_pack(frame, buf, sizeof(buf));
 843         if (len < 0) {
 844                 dev_err(&priv->hdmi->dev,
 845                         "hdmi_infoframe_pack() type=0x%02x failed: %zd\n",
 846                         frame->any.type, len);
 847                 return;
 848         }
 849
 850         reg_clear(priv, REG_DIP_IF_FLAGS, bit);
 851         reg_write_range(priv, addr, buf, len);
 852         reg_set(priv, REG_DIP_IF_FLAGS, bit);
 853 }
 854
 855 static void tda998x_write_aif(struct tda998x_priv *priv,
 856                               const struct hdmi_audio_infoframe *cea)
 857 {
 858         union hdmi_infoframe frame;
 859
 860         frame.audio = *cea;
 861
 862         tda998x_write_if(priv, DIP_IF_FLAGS_IF4, REG_IF4_HB0, &frame);
 863 }
 864
 865 static void
 866 tda998x_write_avi(struct tda998x_priv *priv, const struct drm_display_mode *mode)
 867 {
 868         union hdmi_infoframe frame;
 869
 870         drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 871                                                  &priv->connector, mode);
 872         frame.avi.quantization_range = HDMI_QUANTIZATION_RANGE_FULL;
 873
 874         tda998x_write_if(priv, DIP_IF_FLAGS_IF2, REG_IF2_HB0, &frame);
 875 }
 876
 877 /* Audio support */
 878
 879 static const struct tda998x_audio_route tda998x_audio_route[AUDIO_ROUTE_NUM] = {
 880         [AUDIO_ROUTE_I2S] = {
 881                 .ena_aclk = 1,
 882                 .mux_ap = MUX_AP_SELECT_I2S,
 883                 .aip_clksel = AIP_CLKSEL_AIP_I2S | AIP_CLKSEL_FS_ACLK,
 884         },
 885         [AUDIO_ROUTE_SPDIF] = {
 886                 .ena_aclk = 0,
 887                 .mux_ap = MUX_AP_SELECT_SPDIF,
 888                 .aip_clksel = AIP_CLKSEL_AIP_SPDIF | AIP_CLKSEL_FS_FS64SPDIF,
 889         },
 890 };
 891
 892 /* Configure the TDA998x audio data and clock routing. */
 893 static int tda998x_derive_routing(struct tda998x_priv *priv,
 894                                   struct tda998x_audio_settings *s,
 895                                   unsigned int route)
 896 {
 897         s->route = &tda998x_audio_route[route];
 898         s->ena_ap = priv->audio_port_enable[route];
 899         if (s->ena_ap == 0) {
 900                 dev_err(&priv->hdmi->dev, "no audio configuration found\n");
 901                 return -EINVAL;
 902         }
 903
 904         return 0;
 905 }
 906
 907 /*
 908  * The audio clock divisor register controls a divider producing Audio_Clk_Out
 909  * from SERclk by dividing it by 2^n where 0 <= n <= 5.  We don't know what
 910  * Audio_Clk_Out or SERclk are. We guess SERclk is the same as TMDS clock.
 911  *
 912  * It seems that Audio_Clk_Out must be the smallest value that is greater
 913  * than 128*fs, otherwise audio does not function. There is some suggestion
 914  * that 126*fs is a better value.
 915  */
 916 static u8 tda998x_get_adiv(struct tda998x_priv *priv, unsigned int fs)
 917 {
 918         unsigned long min_audio_clk = fs * 128;
 919         unsigned long ser_clk = priv->tmds_clock * 1000;
 920         u8 adiv;
 921
 922         for (adiv = AUDIO_DIV_SERCLK_32; adiv != AUDIO_DIV_SERCLK_1; adiv--)
 923                 if (ser_clk > min_audio_clk << adiv)
 924                         break;
 925
 926         dev_dbg(&priv->hdmi->dev,
 927                 "ser_clk=%luHz fs=%uHz min_aclk=%luHz adiv=%d\n",
 928                 ser_clk, fs, min_audio_clk, adiv);
 929
 930         return adiv;
 931 }
 932
 933 /*
 934  * In auto-CTS mode, the TDA998x uses a "measured time stamp" counter to
 935  * generate the CTS value.  It appears that the "measured time stamp" is
 936  * the number of TDMS clock cycles within a number of audio input clock
 937  * cycles defined by the k and N parameters defined below, in a similar
 938  * way to that which is set out in the CTS generation in the HDMI spec.
 939  *
 940  *  tmdsclk ----> mts -> /m ---> CTS
 941  *                 ^
 942  *  sclk -> /k -> /N
 943  *
 944  * CTS = mts / m, where m is 2^M.
 945  * /k is a divider based on the K value below, K+1 for K < 4, or 8 for K >= 4
 946  * /N is a divider based on the HDMI specified N value.
 947  *
 948  * This produces the following equation:
 949  *  CTS = tmds_clock * k * N / (sclk * m)
 950  *
 951  * When combined with the sink-side equation, and realising that sclk is
 952  * bclk_ratio * fs, we end up with:
 953  *  k = m * bclk_ratio / 128.
 954  *
 955  * Note: S/PDIF always uses a bclk_ratio of 64.
 956  */
 957 static int tda998x_derive_cts_n(struct tda998x_priv *priv,
 958                                 struct tda998x_audio_settings *settings,
 959                                 unsigned int ratio)
 960 {
 961         switch (ratio) {
 962         case 16:
 963                 settings->cts_n = CTS_N_M(3) | CTS_N_K(0);
 964                 break;
 965         case 32:
 966                 settings->cts_n = CTS_N_M(3) | CTS_N_K(1);
 967                 break;
 968         case 48:
 969                 settings->cts_n = CTS_N_M(3) | CTS_N_K(2);
 970                 break;
 971         case 64:
 972                 settings->cts_n = CTS_N_M(3) | CTS_N_K(3);
 973                 break;
 974         case 128:
 975                 settings->cts_n = CTS_N_M(0) | CTS_N_K(0);
 976                 break;
 977         default:
 978                 dev_err(&priv->hdmi->dev, "unsupported bclk ratio %ufs\n",
 979                         ratio);
 980                 return -EINVAL;
 981         }
 982         return 0;
 983 }
 984
 985 static void tda998x_audio_mute(struct tda998x_priv *priv, bool on)
 986 {
 987         if (on) {
 988                 reg_set(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
 989                 reg_clear(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
 990                 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
 991         } else {
 992                 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
 993         }
 994 }
 995
 996 static void tda998x_configure_audio(struct tda998x_priv *priv)
 997 {
 998         const struct tda998x_audio_settings *settings = &priv->audio;
 999         u8 buf[6], adiv;
1000         u32 n;
1001
1002         /* If audio is not configured, there is nothing to do. */
1003         if (settings->ena_ap == 0)
1004                 return;
1005
1006         adiv = tda998x_get_adiv(priv, settings->sample_rate);
1007
1008         /* Enable audio ports */
1009         reg_write(priv, REG_ENA_AP, settings->ena_ap);
1010         reg_write(priv, REG_ENA_ACLK, settings->route->ena_aclk);
1011         reg_write(priv, REG_MUX_AP, settings->route->mux_ap);
1012         reg_write(priv, REG_I2S_FORMAT, settings->i2s_format);
1013         reg_write(priv, REG_AIP_CLKSEL, settings->route->aip_clksel);
1014         reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_LAYOUT |
1015                                         AIP_CNTRL_0_ACR_MAN);   /* auto CTS */
1016         reg_write(priv, REG_CTS_N, settings->cts_n);
1017         reg_write(priv, REG_AUDIO_DIV, adiv);
1018
1019         /*
1020          * This is the approximate value of N, which happens to be
1021          * the recommended values for non-coherent clocks.
1022          */
1023         n = 128 * settings->sample_rate / 1000;
1024
1025         /* Write the CTS and N values */
1026         buf[0] = 0x44;
1027         buf[1] = 0x42;
1028         buf[2] = 0x01;
1029         buf[3] = n;
1030         buf[4] = n >> 8;
1031         buf[5] = n >> 16;
1032         reg_write_range(priv, REG_ACR_CTS_0, buf, 6);
1033
1034         /* Reset CTS generator */
1035         reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
1036         reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
1037
1038         /* Write the channel status
1039          * The REG_CH_STAT_B-registers skip IEC958 AES2 byte, because
1040          * there is a separate register for each I2S wire.
1041          */
1042         buf[0] = settings->status[0];
1043         buf[1] = settings->status[1];
1044         buf[2] = settings->status[3];
1045         buf[3] = settings->status[4];
1046         reg_write_range(priv, REG_CH_STAT_B(0), buf, 4);
1047
1048         tda998x_audio_mute(priv, true);
1049         msleep(20);
1050         tda998x_audio_mute(priv, false);
1051
1052         tda998x_write_aif(priv, &settings->cea);
1053 }
1054
1055 static int tda998x_audio_hw_params(struct device *dev, void *data,
1056                                    struct hdmi_codec_daifmt *daifmt,
1057                                    struct hdmi_codec_params *params)
1058 {
1059         struct tda998x_priv *priv = dev_get_drvdata(dev);
1060         unsigned int bclk_ratio;
1061         bool spdif = daifmt->fmt == HDMI_SPDIF;
1062         int ret;
1063         struct tda998x_audio_settings audio = {
1064                 .sample_rate = params->sample_rate,
1065                 .cea = params->cea,
1066         };
1067
1068         memcpy(audio.status, params->iec.status,
1069                min(sizeof(audio.status), sizeof(params->iec.status)));
1070
1071         switch (daifmt->fmt) {
1072         case HDMI_I2S:
1073                 audio.i2s_format = I2S_FORMAT_PHILIPS;
1074                 break;
1075         case HDMI_LEFT_J:
1076                 audio.i2s_format = I2S_FORMAT_LEFT_J;
1077                 break;
1078         case HDMI_RIGHT_J:
1079                 audio.i2s_format = I2S_FORMAT_RIGHT_J;
1080                 break;
1081         case HDMI_SPDIF:
1082                 audio.i2s_format = 0;
1083                 break;
1084         default:
1085                 dev_err(dev, "%s: Invalid format %d\n", __func__, daifmt->fmt);
1086                 return -EINVAL;
1087         }
1088
1089         if (!spdif &&
1090             (daifmt->bit_clk_inv || daifmt->frame_clk_inv ||
1091              daifmt->bit_clk_master || daifmt->frame_clk_master)) {
1092                 dev_err(dev, "%s: Bad flags %d %d %d %d\n", __func__,
1093                         daifmt->bit_clk_inv, daifmt->frame_clk_inv,
1094                         daifmt->bit_clk_master,
1095                         daifmt->frame_clk_master);
1096                 return -EINVAL;
1097         }
1098
1099         ret = tda998x_derive_routing(priv, &audio, AUDIO_ROUTE_I2S + spdif);
1100         if (ret < 0)
1101                 return ret;
1102
1103         bclk_ratio = spdif ? 64 : params->sample_width * 2;
1104         ret = tda998x_derive_cts_n(priv, &audio, bclk_ratio);
1105         if (ret < 0)
1106                 return ret;
1107
1108         mutex_lock(&priv->audio_mutex);
1109         priv->audio = audio;
1110         if (priv->supports_infoframes && priv->sink_has_audio)
1111                 tda998x_configure_audio(priv);
1112         mutex_unlock(&priv->audio_mutex);
1113
1114         return 0;
1115 }
1116
1117 static void tda998x_audio_shutdown(struct device *dev, void *data)
1118 {
1119         struct tda998x_priv *priv = dev_get_drvdata(dev);
1120
1121         mutex_lock(&priv->audio_mutex);
1122
1123         reg_write(priv, REG_ENA_AP, 0);
1124         priv->audio.ena_ap = 0;
1125
1126         mutex_unlock(&priv->audio_mutex);
1127 }
1128
1129 int tda998x_audio_digital_mute(struct device *dev, void *data, bool enable)
1130 {
1131         struct tda998x_priv *priv = dev_get_drvdata(dev);
1132
1133         mutex_lock(&priv->audio_mutex);
1134
1135         tda998x_audio_mute(priv, enable);
1136
1137         mutex_unlock(&priv->audio_mutex);
1138         return 0;
1139 }
1140
1141 static int tda998x_audio_get_eld(struct device *dev, void *data,
1142                                  uint8_t *buf, size_t len)
1143 {
1144         struct tda998x_priv *priv = dev_get_drvdata(dev);
1145
1146         mutex_lock(&priv->audio_mutex);
1147         memcpy(buf, priv->connector.eld,
1148                min(sizeof(priv->connector.eld), len));
1149         mutex_unlock(&priv->audio_mutex);
1150
1151         return 0;
1152 }
1153
1154 static const struct hdmi_codec_ops audio_codec_ops = {
1155         .hw_params = tda998x_audio_hw_params,
1156         .audio_shutdown = tda998x_audio_shutdown,
1157         .digital_mute = tda998x_audio_digital_mute,
1158         .get_eld = tda998x_audio_get_eld,
1159 };
1160
1161 static int tda998x_audio_codec_init(struct tda998x_priv *priv,
1162                                     struct device *dev)
1163 {
1164         struct hdmi_codec_pdata codec_data = {
1165                 .ops = &audio_codec_ops,
1166                 .max_i2s_channels = 2,
1167         };
1168
1169         if (priv->audio_port_enable[AUDIO_ROUTE_I2S])
1170                 codec_data.i2s = 1;
1171         if (priv->audio_port_enable[AUDIO_ROUTE_SPDIF])
1172                 codec_data.spdif = 1;
1173
1174         priv->audio_pdev = platform_device_register_data(
1175                 dev, HDMI_CODEC_DRV_NAME, PLATFORM_DEVID_AUTO,
1176                 &codec_data, sizeof(codec_data));
1177
1178         return PTR_ERR_OR_ZERO(priv->audio_pdev);
1179 }
1180
1181 /* DRM connector functions */
1182
1183 static enum drm_connector_status
1184 tda998x_connector_detect(struct drm_connector *connector, bool force)
1185 {
1186         struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
1187         u8 val = cec_read(priv, REG_CEC_RXSHPDLEV);
1188
1189         return (val & CEC_RXSHPDLEV_HPD) ? connector_status_connected :
1190                         connector_status_disconnected;
1191 }
1192
1193 static void tda998x_connector_destroy(struct drm_connector *connector)
1194 {
1195         drm_connector_cleanup(connector);
1196 }
1197
1198 static const struct drm_connector_funcs tda998x_connector_funcs = {
1199         .reset = drm_atomic_helper_connector_reset,
1200         .fill_modes = drm_helper_probe_single_connector_modes,
1201         .detect = tda998x_connector_detect,
1202         .destroy = tda998x_connector_destroy,
1203         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1204         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1205 };
1206
1207 static int read_edid_block(void *data, u8 *buf, unsigned int blk, size_t length)
1208 {
1209         struct tda998x_priv *priv = data;
1210         u8 offset, segptr;
1211         int ret, i;
1212
1213         offset = (blk & 1) ? 128 : 0;
1214         segptr = blk / 2;
1215
1216         mutex_lock(&priv->edid_mutex);
1217
1218         reg_write(priv, REG_DDC_ADDR, 0xa0);
1219         reg_write(priv, REG_DDC_OFFS, offset);
1220         reg_write(priv, REG_DDC_SEGM_ADDR, 0x60);
1221         reg_write(priv, REG_DDC_SEGM, segptr);
1222
1223         /* enable reading EDID: */
1224         priv->wq_edid_wait = 1;
1225         reg_write(priv, REG_EDID_CTRL, 0x1);
1226
1227         /* flag must be cleared by sw: */
1228         reg_write(priv, REG_EDID_CTRL, 0x0);
1229
1230         /* wait for block read to complete: */
1231         if (priv->hdmi->irq) {
1232                 i = wait_event_timeout(priv->wq_edid,
1233                                         !priv->wq_edid_wait,
1234                                         msecs_to_jiffies(100));
1235                 if (i < 0) {
1236                         dev_err(&priv->hdmi->dev, "read edid wait err %d\n", i);
1237                         ret = i;
1238                         goto failed;
1239                 }
1240         } else {
1241                 for (i = 100; i > 0; i--) {
1242                         msleep(1);
1243                         ret = reg_read(priv, REG_INT_FLAGS_2);
1244                         if (ret < 0)
1245                                 goto failed;
1246                         if (ret & INT_FLAGS_2_EDID_BLK_RD)
1247                                 break;
1248                 }
1249         }
1250
1251         if (i == 0) {
1252                 dev_err(&priv->hdmi->dev, "read edid timeout\n");
1253                 ret = -ETIMEDOUT;
1254                 goto failed;
1255         }
1256
1257         ret = reg_read_range(priv, REG_EDID_DATA_0, buf, length);
1258         if (ret != length) {
1259                 dev_err(&priv->hdmi->dev, "failed to read edid block %d: %d\n",
1260                         blk, ret);
1261                 goto failed;
1262         }
1263
1264         ret = 0;
1265
1266  failed:
1267         mutex_unlock(&priv->edid_mutex);
1268         return ret;
1269 }
1270
1271 static int tda998x_connector_get_modes(struct drm_connector *connector)
1272 {
1273         struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
1274         struct edid *edid;
1275         int n;
1276
1277         /*
1278          * If we get killed while waiting for the HPD timeout, return
1279          * no modes found: we are not in a restartable path, so we
1280          * can't handle signals gracefully.
1281          */
1282         if (tda998x_edid_delay_wait(priv))
1283                 return 0;
1284
1285         if (priv->rev == TDA19988)
1286                 reg_clear(priv, REG_TX4, TX4_PD_RAM);
1287
1288         edid = drm_do_get_edid(connector, read_edid_block, priv);
1289
1290         if (priv->rev == TDA19988)
1291                 reg_set(priv, REG_TX4, TX4_PD_RAM);
1292
1293         if (!edid) {
1294                 dev_warn(&priv->hdmi->dev, "failed to read EDID\n");
1295                 return 0;
1296         }
1297
1298         drm_connector_update_edid_property(connector, edid);
1299         cec_notifier_set_phys_addr_from_edid(priv->cec_notify, edid);
1300
1301         mutex_lock(&priv->audio_mutex);
1302         n = drm_add_edid_modes(connector, edid);
1303         priv->sink_has_audio = drm_detect_monitor_audio(edid);
1304         mutex_unlock(&priv->audio_mutex);
1305
1306         kfree(edid);
1307
1308         return n;
1309 }
1310
1311 static struct drm_encoder *
1312 tda998x_connector_best_encoder(struct drm_connector *connector)
1313 {
1314         struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
1315
1316         return priv->bridge.encoder;
1317 }
1318
1319 static
1320 const struct drm_connector_helper_funcs tda998x_connector_helper_funcs = {
1321         .get_modes = tda998x_connector_get_modes,
1322         .best_encoder = tda998x_connector_best_encoder,
1323 };
1324
1325 static int tda998x_connector_init(struct tda998x_priv *priv,
1326                                   struct drm_device *drm)
1327 {
1328         struct drm_connector *connector = &priv->connector;
1329         int ret;
1330
1331         connector->interlace_allowed = 1;
1332
1333         if (priv->hdmi->irq)
1334                 connector->polled = DRM_CONNECTOR_POLL_HPD;
1335         else
1336                 connector->polled = DRM_CONNECTOR_POLL_CONNECT |
1337                         DRM_CONNECTOR_POLL_DISCONNECT;
1338
1339         drm_connector_helper_add(connector, &tda998x_connector_helper_funcs);
1340         ret = drm_connector_init(drm, connector, &tda998x_connector_funcs,
1341                                  DRM_MODE_CONNECTOR_HDMIA);
1342         if (ret)
1343                 return ret;
1344
1345         drm_connector_attach_encoder(&priv->connector,
1346                                      priv->bridge.encoder);
1347
1348         return 0;
1349 }
1350
1351 /* DRM bridge functions */
1352
1353 static int tda998x_bridge_attach(struct drm_bridge *bridge)
1354 {
1355         struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge);
1356
1357         return tda998x_connector_init(priv, bridge->dev);
1358 }
1359
1360 static void tda998x_bridge_detach(struct drm_bridge *bridge)
1361 {
1362         struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge);
1363
1364         drm_connector_cleanup(&priv->connector);
1365 }
1366
1367 static enum drm_mode_status tda998x_bridge_mode_valid(struct drm_bridge *bridge,
1368                                      const struct drm_display_mode *mode)
1369 {
1370         /* TDA19988 dotclock can go up to 165MHz */
1371         struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge);
1372
1373         if (mode->clock > ((priv->rev == TDA19988) ? 165000 : 150000))
1374                 return MODE_CLOCK_HIGH;
1375         if (mode->htotal >= BIT(13))
1376                 return MODE_BAD_HVALUE;
1377         if (mode->vtotal >= BIT(11))
1378                 return MODE_BAD_VVALUE;
1379         return MODE_OK;
1380 }
1381
1382 static void tda998x_bridge_enable(struct drm_bridge *bridge)
1383 {
1384         struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge);
1385
1386         if (!priv->is_on) {
1387                 /* enable video ports, audio will be enabled later */
1388                 reg_write(priv, REG_ENA_VP_0, 0xff);
1389                 reg_write(priv, REG_ENA_VP_1, 0xff);
1390                 reg_write(priv, REG_ENA_VP_2, 0xff);
1391                 /* set muxing after enabling ports: */
1392                 reg_write(priv, REG_VIP_CNTRL_0, priv->vip_cntrl_0);
1393                 reg_write(priv, REG_VIP_CNTRL_1, priv->vip_cntrl_1);
1394                 reg_write(priv, REG_VIP_CNTRL_2, priv->vip_cntrl_2);
1395
1396                 priv->is_on = true;
1397         }
1398 }
1399
1400 static void tda998x_bridge_disable(struct drm_bridge *bridge)
1401 {
1402         struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge);
1403
1404         if (priv->is_on) {
1405                 /* disable video ports */
1406                 reg_write(priv, REG_ENA_VP_0, 0x00);
1407                 reg_write(priv, REG_ENA_VP_1, 0x00);
1408                 reg_write(priv, REG_ENA_VP_2, 0x00);
1409
1410                 priv->is_on = false;
1411         }
1412 }
1413
1414 static void tda998x_bridge_mode_set(struct drm_bridge *bridge,
1415                                     const struct drm_display_mode *mode,
1416                                     const struct drm_display_mode *adjusted_mode)
1417 {
1418         struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge);
1419         unsigned long tmds_clock;
1420         u16 ref_pix, ref_line, n_pix, n_line;
1421         u16 hs_pix_s, hs_pix_e;
1422         u16 vs1_pix_s, vs1_pix_e, vs1_line_s, vs1_line_e;
1423         u16 vs2_pix_s, vs2_pix_e, vs2_line_s, vs2_line_e;
1424         u16 vwin1_line_s, vwin1_line_e;
1425         u16 vwin2_line_s, vwin2_line_e;
1426         u16 de_pix_s, de_pix_e;
1427         u8 reg, div, rep, sel_clk;
1428
1429         /*
1430          * Internally TDA998x is using ITU-R BT.656 style sync but
1431          * we get VESA style sync. TDA998x is using a reference pixel
1432          * relative to ITU to sync to the input frame and for output
1433          * sync generation. Currently, we are using reference detection
1434          * from HS/VS, i.e. REFPIX/REFLINE denote frame start sync point
1435          * which is position of rising VS with coincident rising HS.
1436          *
1437          * Now there is some issues to take care of:
1438          * - HDMI data islands require sync-before-active
1439          * - TDA998x register values must be > 0 to be enabled
1440          * - REFLINE needs an additional offset of +1
1441          * - REFPIX needs an addtional offset of +1 for UYUV and +3 for RGB
1442          *
1443          * So we add +1 to all horizontal and vertical register values,
1444          * plus an additional +3 for REFPIX as we are using RGB input only.
1445          */
1446         n_pix        = mode->htotal;
1447         n_line       = mode->vtotal;
1448
1449         hs_pix_e     = mode->hsync_end - mode->hdisplay;
1450         hs_pix_s     = mode->hsync_start - mode->hdisplay;
1451         de_pix_e     = mode->htotal;
1452         de_pix_s     = mode->htotal - mode->hdisplay;
1453         ref_pix      = 3 + hs_pix_s;
1454
1455         /*
1456          * Attached LCD controllers may generate broken sync. Allow
1457          * those to adjust the position of the rising VS edge by adding
1458          * HSKEW to ref_pix.
1459          */
1460         if (adjusted_mode->flags & DRM_MODE_FLAG_HSKEW)
1461                 ref_pix += adjusted_mode->hskew;
1462
1463         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0) {
1464                 ref_line     = 1 + mode->vsync_start - mode->vdisplay;
1465                 vwin1_line_s = mode->vtotal - mode->vdisplay - 1;
1466                 vwin1_line_e = vwin1_line_s + mode->vdisplay;
1467                 vs1_pix_s    = vs1_pix_e = hs_pix_s;
1468                 vs1_line_s   = mode->vsync_start - mode->vdisplay;
1469                 vs1_line_e   = vs1_line_s +
1470                                mode->vsync_end - mode->vsync_start;
1471                 vwin2_line_s = vwin2_line_e = 0;
1472                 vs2_pix_s    = vs2_pix_e  = 0;
1473                 vs2_line_s   = vs2_line_e = 0;
1474         } else {
1475                 ref_line     = 1 + (mode->vsync_start - mode->vdisplay)/2;
1476                 vwin1_line_s = (mode->vtotal - mode->vdisplay)/2;
1477                 vwin1_line_e = vwin1_line_s + mode->vdisplay/2;
1478                 vs1_pix_s    = vs1_pix_e = hs_pix_s;
1479                 vs1_line_s   = (mode->vsync_start - mode->vdisplay)/2;
1480                 vs1_line_e   = vs1_line_s +
1481                                (mode->vsync_end - mode->vsync_start)/2;
1482                 vwin2_line_s = vwin1_line_s + mode->vtotal/2;
1483                 vwin2_line_e = vwin2_line_s + mode->vdisplay/2;
1484                 vs2_pix_s    = vs2_pix_e = hs_pix_s + mode->htotal/2;
1485                 vs2_line_s   = vs1_line_s + mode->vtotal/2 ;
1486                 vs2_line_e   = vs2_line_s +
1487                                (mode->vsync_end - mode->vsync_start)/2;
1488         }
1489
1490         /*
1491          * Select pixel repeat depending on the double-clock flag
1492          * (which means we have to repeat each pixel once.)
1493          */
1494         rep = mode->flags & DRM_MODE_FLAG_DBLCLK ? 1 : 0;
1495         sel_clk = SEL_CLK_ENA_SC_CLK | SEL_CLK_SEL_CLK1 |
1496                   SEL_CLK_SEL_VRF_CLK(rep ? 2 : 0);
1497
1498         /* the TMDS clock is scaled up by the pixel repeat */
1499         tmds_clock = mode->clock * (1 + rep);
1500
1501         /*
1502          * The divisor is power-of-2. The TDA9983B datasheet gives
1503          * this as ranges of Msample/s, which is 10x the TMDS clock:
1504          *   0 - 800 to 1500 Msample/s
1505          *   1 - 400 to 800 Msample/s
1506          *   2 - 200 to 400 Msample/s
1507          *   3 - as 2 above
1508          */
1509         for (div = 0; div < 3; div++)
1510                 if (80000 >> div <= tmds_clock)
1511                         break;
1512
1513         mutex_lock(&priv->audio_mutex);
1514
1515         priv->tmds_clock = tmds_clock;
1516
1517         /* mute the audio FIFO: */
1518         reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
1519
1520         /* set HDMI HDCP mode off: */
1521         reg_write(priv, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS);
1522         reg_clear(priv, REG_TX33, TX33_HDMI);
1523         reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0));
1524
1525         /* no pre-filter or interpolator: */
1526         reg_write(priv, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) |
1527                         HVF_CNTRL_0_INTPOL(0));
1528         reg_set(priv, REG_FEAT_POWERDOWN, FEAT_POWERDOWN_PREFILT);
1529         reg_write(priv, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0));
1530         reg_write(priv, REG_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT(0) |
1531                         VIP_CNTRL_4_BLC(0));
1532
1533         reg_clear(priv, REG_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IZ);
1534         reg_clear(priv, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR |
1535                                           PLL_SERIAL_3_SRL_DE);
1536         reg_write(priv, REG_SERIALIZER, 0);
1537         reg_write(priv, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0));
1538
1539         reg_write(priv, REG_RPT_CNTRL, RPT_CNTRL_REPEAT(rep));
1540         reg_write(priv, REG_SEL_CLK, sel_clk);
1541         reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) |
1542                         PLL_SERIAL_2_SRL_PR(rep));
1543
1544         /* set color matrix bypass flag: */
1545         reg_write(priv, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP |
1546                                 MAT_CONTRL_MAT_SC(1));
1547         reg_set(priv, REG_FEAT_POWERDOWN, FEAT_POWERDOWN_CSC);
1548
1549         /* set BIAS tmds value: */
1550         reg_write(priv, REG_ANA_GENERAL, 0x09);
1551
1552         /*
1553          * Sync on rising HSYNC/VSYNC
1554          */
1555         reg = VIP_CNTRL_3_SYNC_HS;
1556
1557         /*
1558          * TDA19988 requires high-active sync at input stage,
1559          * so invert low-active sync provided by master encoder here
1560          */
1561         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1562                 reg |= VIP_CNTRL_3_H_TGL;
1563         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1564                 reg |= VIP_CNTRL_3_V_TGL;
1565         reg_write(priv, REG_VIP_CNTRL_3, reg);
1566
1567         reg_write(priv, REG_VIDFORMAT, 0x00);
1568         reg_write16(priv, REG_REFPIX_MSB, ref_pix);
1569         reg_write16(priv, REG_REFLINE_MSB, ref_line);
1570         reg_write16(priv, REG_NPIX_MSB, n_pix);
1571         reg_write16(priv, REG_NLINE_MSB, n_line);
1572         reg_write16(priv, REG_VS_LINE_STRT_1_MSB, vs1_line_s);
1573         reg_write16(priv, REG_VS_PIX_STRT_1_MSB, vs1_pix_s);
1574         reg_write16(priv, REG_VS_LINE_END_1_MSB, vs1_line_e);
1575         reg_write16(priv, REG_VS_PIX_END_1_MSB, vs1_pix_e);
1576         reg_write16(priv, REG_VS_LINE_STRT_2_MSB, vs2_line_s);
1577         reg_write16(priv, REG_VS_PIX_STRT_2_MSB, vs2_pix_s);
1578         reg_write16(priv, REG_VS_LINE_END_2_MSB, vs2_line_e);
1579         reg_write16(priv, REG_VS_PIX_END_2_MSB, vs2_pix_e);
1580         reg_write16(priv, REG_HS_PIX_START_MSB, hs_pix_s);
1581         reg_write16(priv, REG_HS_PIX_STOP_MSB, hs_pix_e);
1582         reg_write16(priv, REG_VWIN_START_1_MSB, vwin1_line_s);
1583         reg_write16(priv, REG_VWIN_END_1_MSB, vwin1_line_e);
1584         reg_write16(priv, REG_VWIN_START_2_MSB, vwin2_line_s);
1585         reg_write16(priv, REG_VWIN_END_2_MSB, vwin2_line_e);
1586         reg_write16(priv, REG_DE_START_MSB, de_pix_s);
1587         reg_write16(priv, REG_DE_STOP_MSB, de_pix_e);
1588
1589         if (priv->rev == TDA19988) {
1590                 /* let incoming pixels fill the active space (if any) */
1591                 reg_write(priv, REG_ENABLE_SPACE, 0x00);
1592         }
1593
1594         /*
1595          * Always generate sync polarity relative to input sync and
1596          * revert input stage toggled sync at output stage
1597          */
1598         reg = TBG_CNTRL_1_DWIN_DIS | TBG_CNTRL_1_TGL_EN;
1599         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1600                 reg |= TBG_CNTRL_1_H_TGL;
1601         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1602                 reg |= TBG_CNTRL_1_V_TGL;
1603         reg_write(priv, REG_TBG_CNTRL_1, reg);
1604
1605         /* must be last register set: */
1606         reg_write(priv, REG_TBG_CNTRL_0, 0);
1607
1608         /* CEA-861B section 6 says that:
1609          * CEA version 1 (CEA-861) has no support for infoframes.
1610          * CEA version 2 (CEA-861A) supports version 1 AVI infoframes,
1611          * and optional basic audio.
1612          * CEA version 3 (CEA-861B) supports version 1 and 2 AVI infoframes,
1613          * and optional digital audio, with audio infoframes.
1614          *
1615          * Since we only support generation of version 2 AVI infoframes,
1616          * ignore CEA version 2 and below (iow, behave as if we're a
1617          * CEA-861 source.)
1618          */
1619         priv->supports_infoframes = priv->connector.display_info.cea_rev >= 3;
1620
1621         if (priv->supports_infoframes) {
1622                 /* We need to turn HDMI HDCP stuff on to get audio through */
1623                 reg &= ~TBG_CNTRL_1_DWIN_DIS;
1624                 reg_write(priv, REG_TBG_CNTRL_1, reg);
1625                 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1));
1626                 reg_set(priv, REG_TX33, TX33_HDMI);
1627
1628                 tda998x_write_avi(priv, adjusted_mode);
1629
1630                 if (priv->sink_has_audio)
1631                         tda998x_configure_audio(priv);
1632         }
1633
1634         mutex_unlock(&priv->audio_mutex);
1635 }
1636
1637 static const struct drm_bridge_funcs tda998x_bridge_funcs = {
1638         .attach = tda998x_bridge_attach,
1639         .detach = tda998x_bridge_detach,
1640         .mode_valid = tda998x_bridge_mode_valid,
1641         .disable = tda998x_bridge_disable,
1642         .mode_set = tda998x_bridge_mode_set,
1643         .enable = tda998x_bridge_enable,
1644 };
1645
1646 /* I2C driver functions */
1647
1648 static int tda998x_get_audio_ports(struct tda998x_priv *priv,
1649                                    struct device_node *np)
1650 {
1651         const u32 *port_data;
1652         u32 size;
1653         int i;
1654
1655         port_data = of_get_property(np, "audio-ports", &size);
1656         if (!port_data)
1657                 return 0;
1658
1659         size /= sizeof(u32);
1660         if (size > 2 * ARRAY_SIZE(priv->audio_port_enable) || size % 2 != 0) {
1661                 dev_err(&priv->hdmi->dev,
1662                         "Bad number of elements in audio-ports dt-property\n");
1663                 return -EINVAL;
1664         }
1665
1666         size /= 2;
1667
1668         for (i = 0; i < size; i++) {
1669                 unsigned int route;
1670                 u8 afmt = be32_to_cpup(&port_data[2*i]);
1671                 u8 ena_ap = be32_to_cpup(&port_data[2*i+1]);
1672
1673                 switch (afmt) {
1674                 case AFMT_I2S:
1675                         route = AUDIO_ROUTE_I2S;
1676                         break;
1677                 case AFMT_SPDIF:
1678                         route = AUDIO_ROUTE_SPDIF;
1679                         break;
1680                 default:
1681                         dev_err(&priv->hdmi->dev,
1682                                 "Bad audio format %u\n", afmt);
1683                         return -EINVAL;
1684                 }
1685
1686                 if (!ena_ap) {
1687                         dev_err(&priv->hdmi->dev, "invalid zero port config\n");
1688                         continue;
1689                 }
1690
1691                 if (priv->audio_port_enable[route]) {
1692                         dev_err(&priv->hdmi->dev,
1693                                 "%s format already configured\n",
1694                                 route == AUDIO_ROUTE_SPDIF ? "SPDIF" : "I2S");
1695                         return -EINVAL;
1696                 }
1697
1698                 priv->audio_port_enable[route] = ena_ap;
1699         }
1700         return 0;
1701 }
1702
1703 static int tda998x_set_config(struct tda998x_priv *priv,
1704                               const struct tda998x_encoder_params *p)
1705 {
1706         priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(p->swap_a) |
1707                             (p->mirr_a ? VIP_CNTRL_0_MIRR_A : 0) |
1708                             VIP_CNTRL_0_SWAP_B(p->swap_b) |
1709                             (p->mirr_b ? VIP_CNTRL_0_MIRR_B : 0);
1710         priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(p->swap_c) |
1711                             (p->mirr_c ? VIP_CNTRL_1_MIRR_C : 0) |
1712                             VIP_CNTRL_1_SWAP_D(p->swap_d) |
1713                             (p->mirr_d ? VIP_CNTRL_1_MIRR_D : 0);
1714         priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(p->swap_e) |
1715                             (p->mirr_e ? VIP_CNTRL_2_MIRR_E : 0) |
1716                             VIP_CNTRL_2_SWAP_F(p->swap_f) |
1717                             (p->mirr_f ? VIP_CNTRL_2_MIRR_F : 0);
1718
1719         if (p->audio_params.format != AFMT_UNUSED) {
1720                 unsigned int ratio, route;
1721                 bool spdif = p->audio_params.format == AFMT_SPDIF;
1722
1723                 route = AUDIO_ROUTE_I2S + spdif;
1724
1725                 priv->audio.route = &tda998x_audio_route[route];
1726                 priv->audio.cea = p->audio_params.cea;
1727                 priv->audio.sample_rate = p->audio_params.sample_rate;
1728                 memcpy(priv->audio.status, p->audio_params.status,
1729                        min(sizeof(priv->audio.status),
1730                            sizeof(p->audio_params.status)));
1731                 priv->audio.ena_ap = p->audio_params.config;
1732                 priv->audio.i2s_format = I2S_FORMAT_PHILIPS;
1733
1734                 ratio = spdif ? 64 : p->audio_params.sample_width * 2;
1735                 return tda998x_derive_cts_n(priv, &priv->audio, ratio);
1736         }
1737
1738         return 0;
1739 }
1740
1741 static void tda998x_destroy(struct device *dev)
1742 {
1743         struct tda998x_priv *priv = dev_get_drvdata(dev);
1744
1745         drm_bridge_remove(&priv->bridge);
1746
1747         /* disable all IRQs and free the IRQ handler */
1748         cec_write(priv, REG_CEC_RXSHPDINTENA, 0);
1749         reg_clear(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
1750
1751         if (priv->audio_pdev)
1752                 platform_device_unregister(priv->audio_pdev);
1753
1754         if (priv->hdmi->irq)
1755                 free_irq(priv->hdmi->irq, priv);
1756
1757         del_timer_sync(&priv->edid_delay_timer);
1758         cancel_work_sync(&priv->detect_work);
1759
1760         i2c_unregister_device(priv->cec);
1761
1762         if (priv->cec_notify)
1763                 cec_notifier_put(priv->cec_notify);
1764 }
1765
1766 static int tda998x_create(struct device *dev)
1767 {
1768         struct i2c_client *client = to_i2c_client(dev);
1769         struct device_node *np = client->dev.of_node;
1770         struct i2c_board_info cec_info;
1771         struct tda998x_priv *priv;
1772         u32 video;
1773         int rev_lo, rev_hi, ret;
1774
1775         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1776         if (!priv)
1777                 return -ENOMEM;
1778
1779         dev_set_drvdata(dev, priv);
1780
1781         mutex_init(&priv->mutex);       /* protect the page access */
1782         mutex_init(&priv->audio_mutex); /* protect access from audio thread */
1783         mutex_init(&priv->edid_mutex);
1784         INIT_LIST_HEAD(&priv->bridge.list);
1785         init_waitqueue_head(&priv->edid_delay_waitq);
1786         timer_setup(&priv->edid_delay_timer, tda998x_edid_delay_done, 0);
1787         INIT_WORK(&priv->detect_work, tda998x_detect_work);
1788
1789         priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3);
1790         priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(0) | VIP_CNTRL_1_SWAP_D(1);
1791         priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(4) | VIP_CNTRL_2_SWAP_F(5);
1792
1793         /* CEC I2C address bound to TDA998x I2C addr by configuration pins */
1794         priv->cec_addr = 0x34 + (client->addr & 0x03);
1795         priv->current_page = 0xff;
1796         priv->hdmi = client;
1797
1798         /* wake up the device: */
1799         cec_write(priv, REG_CEC_ENAMODS,
1800                         CEC_ENAMODS_EN_RXSENS | CEC_ENAMODS_EN_HDMI);
1801
1802         tda998x_reset(priv);
1803
1804         /* read version: */
1805         rev_lo = reg_read(priv, REG_VERSION_LSB);
1806         if (rev_lo < 0) {
1807                 dev_err(dev, "failed to read version: %d\n", rev_lo);
1808                 return rev_lo;
1809         }
1810
1811         rev_hi = reg_read(priv, REG_VERSION_MSB);
1812         if (rev_hi < 0) {
1813                 dev_err(dev, "failed to read version: %d\n", rev_hi);
1814                 return rev_hi;
1815         }
1816
1817         priv->rev = rev_lo | rev_hi << 8;
1818
1819         /* mask off feature bits: */
1820         priv->rev &= ~0x30; /* not-hdcp and not-scalar bit */
1821
1822         switch (priv->rev) {
1823         case TDA9989N2:
1824                 dev_info(dev, "found TDA9989 n2");
1825                 break;
1826         case TDA19989:
1827                 dev_info(dev, "found TDA19989");
1828                 break;
1829         case TDA19989N2:
1830                 dev_info(dev, "found TDA19989 n2");
1831                 break;
1832         case TDA19988:
1833                 dev_info(dev, "found TDA19988");
1834                 break;
1835         default:
1836                 dev_err(dev, "found unsupported device: %04x\n", priv->rev);
1837                 return -ENXIO;
1838         }
1839
1840         /* after reset, enable DDC: */
1841         reg_write(priv, REG_DDC_DISABLE, 0x00);
1842
1843         /* set clock on DDC channel: */
1844         reg_write(priv, REG_TX3, 39);
1845
1846         /* if necessary, disable multi-master: */
1847         if (priv->rev == TDA19989)
1848                 reg_set(priv, REG_I2C_MASTER, I2C_MASTER_DIS_MM);
1849
1850         cec_write(priv, REG_CEC_FRO_IM_CLK_CTRL,
1851                         CEC_FRO_IM_CLK_CTRL_GHOST_DIS | CEC_FRO_IM_CLK_CTRL_IMCLK_SEL);
1852
1853         /* ensure interrupts are disabled */
1854         cec_write(priv, REG_CEC_RXSHPDINTENA, 0);
1855
1856         /* clear pending interrupts */
1857         cec_read(priv, REG_CEC_RXSHPDINT);
1858         reg_read(priv, REG_INT_FLAGS_0);
1859         reg_read(priv, REG_INT_FLAGS_1);
1860         reg_read(priv, REG_INT_FLAGS_2);
1861
1862         /* initialize the optional IRQ */
1863         if (client->irq) {
1864                 unsigned long irq_flags;
1865
1866                 /* init read EDID waitqueue and HDP work */
1867                 init_waitqueue_head(&priv->wq_edid);
1868
1869                 irq_flags =
1870                         irqd_get_trigger_type(irq_get_irq_data(client->irq));
1871
1872                 priv->cec_glue.irq_flags = irq_flags;
1873
1874                 irq_flags |= IRQF_SHARED | IRQF_ONESHOT;
1875                 ret = request_threaded_irq(client->irq, NULL,
1876                                            tda998x_irq_thread, irq_flags,
1877                                            "tda998x", priv);
1878                 if (ret) {
1879                         dev_err(dev, "failed to request IRQ#%u: %d\n",
1880                                 client->irq, ret);
1881                         goto err_irq;
1882                 }
1883
1884                 /* enable HPD irq */
1885                 cec_write(priv, REG_CEC_RXSHPDINTENA, CEC_RXSHPDLEV_HPD);
1886         }
1887
1888         priv->cec_notify = cec_notifier_get(dev);
1889         if (!priv->cec_notify) {
1890                 ret = -ENOMEM;
1891                 goto fail;
1892         }
1893
1894         priv->cec_glue.parent = dev;
1895         priv->cec_glue.data = priv;
1896         priv->cec_glue.init = tda998x_cec_hook_init;
1897         priv->cec_glue.exit = tda998x_cec_hook_exit;
1898         priv->cec_glue.open = tda998x_cec_hook_open;
1899         priv->cec_glue.release = tda998x_cec_hook_release;
1900
1901         /*
1902          * Some TDA998x are actually two I2C devices merged onto one piece
1903          * of silicon: TDA9989 and TDA19989 combine the HDMI transmitter
1904          * with a slightly modified TDA9950 CEC device.  The CEC device
1905          * is at the TDA9950 address, with the address pins strapped across
1906          * to the TDA998x address pins.  Hence, it always has the same
1907          * offset.
1908          */
1909         memset(&cec_info, 0, sizeof(cec_info));
1910         strlcpy(cec_info.type, "tda9950", sizeof(cec_info.type));
1911         cec_info.addr = priv->cec_addr;
1912         cec_info.platform_data = &priv->cec_glue;
1913         cec_info.irq = client->irq;
1914
1915         priv->cec = i2c_new_device(client->adapter, &cec_info);
1916         if (!priv->cec) {
1917                 ret = -ENODEV;
1918                 goto fail;
1919         }
1920
1921         /* enable EDID read irq: */
1922         reg_set(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
1923
1924         if (np) {
1925                 /* get the device tree parameters */
1926                 ret = of_property_read_u32(np, "video-ports", &video);
1927                 if (ret == 0) {
1928                         priv->vip_cntrl_0 = video >> 16;
1929                         priv->vip_cntrl_1 = video >> 8;
1930                         priv->vip_cntrl_2 = video;
1931                 }
1932
1933                 ret = tda998x_get_audio_ports(priv, np);
1934                 if (ret)
1935                         goto fail;
1936
1937                 if (priv->audio_port_enable[AUDIO_ROUTE_I2S] ||
1938                     priv->audio_port_enable[AUDIO_ROUTE_SPDIF])
1939                         tda998x_audio_codec_init(priv, &client->dev);
1940         } else if (dev->platform_data) {
1941                 ret = tda998x_set_config(priv, dev->platform_data);
1942                 if (ret)
1943                         goto fail;
1944         }
1945
1946         priv->bridge.funcs = &tda998x_bridge_funcs;
1947 #ifdef CONFIG_OF
1948         priv->bridge.of_node = dev->of_node;
1949 #endif
1950
1951         drm_bridge_add(&priv->bridge);
1952
1953         return 0;
1954
1955 fail:
1956         tda998x_destroy(dev);
1957 err_irq:
1958         return ret;
1959 }
1960
1961 /* DRM encoder functions */
1962
1963 static void tda998x_encoder_destroy(struct drm_encoder *encoder)
1964 {
1965         drm_encoder_cleanup(encoder);
1966 }
1967
1968 static const struct drm_encoder_funcs tda998x_encoder_funcs = {
1969         .destroy = tda998x_encoder_destroy,
1970 };
1971
1972 static int tda998x_encoder_init(struct device *dev, struct drm_device *drm)
1973 {
1974         struct tda998x_priv *priv = dev_get_drvdata(dev);
1975         u32 crtcs = 0;
1976         int ret;
1977
1978         if (dev->of_node)
1979                 crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
1980
1981         /* If no CRTCs were found, fall back to our old behaviour */
1982         if (crtcs == 0) {
1983                 dev_warn(dev, "Falling back to first CRTC\n");
1984                 crtcs = 1 << 0;
1985         }
1986
1987         priv->encoder.possible_crtcs = crtcs;
1988
1989         ret = drm_encoder_init(drm, &priv->encoder, &tda998x_encoder_funcs,
1990                                DRM_MODE_ENCODER_TMDS, NULL);
1991         if (ret)
1992                 goto err_encoder;
1993
1994         ret = drm_bridge_attach(&priv->encoder, &priv->bridge, NULL);
1995         if (ret)
1996                 goto err_bridge;
1997
1998         return 0;
1999
2000 err_bridge:
2001         drm_encoder_cleanup(&priv->encoder);
2002 err_encoder:
2003         return ret;
2004 }
2005
2006 static int tda998x_bind(struct device *dev, struct device *master, void *data)
2007 {
2008         struct drm_device *drm = data;
2009
2010         return tda998x_encoder_init(dev, drm);
2011 }
2012
2013 static void tda998x_unbind(struct device *dev, struct device *master,
2014                            void *data)
2015 {
2016         struct tda998x_priv *priv = dev_get_drvdata(dev);
2017
2018         drm_encoder_cleanup(&priv->encoder);
2019 }
2020
2021 static const struct component_ops tda998x_ops = {
2022         .bind = tda998x_bind,
2023         .unbind = tda998x_unbind,
2024 };
2025
2026 static int
2027 tda998x_probe(struct i2c_client *client, const struct i2c_device_id *id)
2028 {
2029         int ret;
2030
2031         if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
2032                 dev_warn(&client->dev, "adapter does not support I2C\n");
2033                 return -EIO;
2034         }
2035
2036         ret = tda998x_create(&client->dev);
2037         if (ret)
2038                 return ret;
2039
2040         ret = component_add(&client->dev, &tda998x_ops);
2041         if (ret)
2042                 tda998x_destroy(&client->dev);
2043         return ret;
2044 }
2045
2046 static int tda998x_remove(struct i2c_client *client)
2047 {
2048         component_del(&client->dev, &tda998x_ops);
2049         tda998x_destroy(&client->dev);
2050         return 0;
2051 }
2052
2053 #ifdef CONFIG_OF
2054 static const struct of_device_id tda998x_dt_ids[] = {
2055         { .compatible = "nxp,tda998x", },
2056         { }
2057 };
2058 MODULE_DEVICE_TABLE(of, tda998x_dt_ids);
2059 #endif
2060
2061 static const struct i2c_device_id tda998x_ids[] = {
2062         { "tda998x", 0 },
2063         { }
2064 };
2065 MODULE_DEVICE_TABLE(i2c, tda998x_ids);
2066
2067 static struct i2c_driver tda998x_driver = {
2068         .probe = tda998x_probe,
2069         .remove = tda998x_remove,
2070         .driver = {
2071                 .name = "tda998x",
2072                 .of_match_table = of_match_ptr(tda998x_dt_ids),
2073         },
2074         .id_table = tda998x_ids,
2075 };
2076
2077 module_i2c_driver(tda998x_driver);
2078
2079 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
2080 MODULE_DESCRIPTION("NXP Semiconductors TDA998X HDMI Encoder");
2081 MODULE_LICENSE("GPL");