drivers/gpu/drm/etnaviv/etnaviv_gpu.c

   1 /*
   2  * Copyright (C) 2015 Etnaviv Project
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License version 2 as published by
   6  * the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along with
  14  * this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #include <linux/component.h>
  18 #include <linux/fence.h>
  19 #include <linux/moduleparam.h>
  20 #include <linux/of_device.h>
  21 #include "etnaviv_dump.h"
  22 #include "etnaviv_gpu.h"
  23 #include "etnaviv_gem.h"
  24 #include "etnaviv_mmu.h"
  25 #include "etnaviv_iommu.h"
  26 #include "etnaviv_iommu_v2.h"
  27 #include "common.xml.h"
  28 #include "state.xml.h"
  29 #include "state_hi.xml.h"
  30 #include "cmdstream.xml.h"
  31
  32 static const struct platform_device_id gpu_ids[] = {
  33         { .name = "etnaviv-gpu,2d" },
  34         { },
  35 };
  36
  37 static bool etnaviv_dump_core = true;
  38 module_param_named(dump_core, etnaviv_dump_core, bool, 0600);
  39
  40 /*
  41  * Driver functions:
  42  */
  43
  44 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value)
  45 {
  46         switch (param) {
  47         case ETNAVIV_PARAM_GPU_MODEL:
  48                 *value = gpu->identity.model;
  49                 break;
  50
  51         case ETNAVIV_PARAM_GPU_REVISION:
  52                 *value = gpu->identity.revision;
  53                 break;
  54
  55         case ETNAVIV_PARAM_GPU_FEATURES_0:
  56                 *value = gpu->identity.features;
  57                 break;
  58
  59         case ETNAVIV_PARAM_GPU_FEATURES_1:
  60                 *value = gpu->identity.minor_features0;
  61                 break;
  62
  63         case ETNAVIV_PARAM_GPU_FEATURES_2:
  64                 *value = gpu->identity.minor_features1;
  65                 break;
  66
  67         case ETNAVIV_PARAM_GPU_FEATURES_3:
  68                 *value = gpu->identity.minor_features2;
  69                 break;
  70
  71         case ETNAVIV_PARAM_GPU_FEATURES_4:
  72                 *value = gpu->identity.minor_features3;
  73                 break;
  74
  75         case ETNAVIV_PARAM_GPU_STREAM_COUNT:
  76                 *value = gpu->identity.stream_count;
  77                 break;
  78
  79         case ETNAVIV_PARAM_GPU_REGISTER_MAX:
  80                 *value = gpu->identity.register_max;
  81                 break;
  82
  83         case ETNAVIV_PARAM_GPU_THREAD_COUNT:
  84                 *value = gpu->identity.thread_count;
  85                 break;
  86
  87         case ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE:
  88                 *value = gpu->identity.vertex_cache_size;
  89                 break;
  90
  91         case ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT:
  92                 *value = gpu->identity.shader_core_count;
  93                 break;
  94
  95         case ETNAVIV_PARAM_GPU_PIXEL_PIPES:
  96                 *value = gpu->identity.pixel_pipes;
  97                 break;
  98
  99         case ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE:
 100                 *value = gpu->identity.vertex_output_buffer_size;
 101                 break;
 102
 103         case ETNAVIV_PARAM_GPU_BUFFER_SIZE:
 104                 *value = gpu->identity.buffer_size;
 105                 break;
 106
 107         case ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT:
 108                 *value = gpu->identity.instruction_count;
 109                 break;
 110
 111         case ETNAVIV_PARAM_GPU_NUM_CONSTANTS:
 112                 *value = gpu->identity.num_constants;
 113                 break;
 114
 115         default:
 116                 DBG("%s: invalid param: %u", dev_name(gpu->dev), param);
 117                 return -EINVAL;
 118         }
 119
 120         return 0;
 121 }
 122
 123 static void etnaviv_hw_specs(struct etnaviv_gpu *gpu)
 124 {
 125         if (gpu->identity.minor_features0 &
 126             chipMinorFeatures0_MORE_MINOR_FEATURES) {
 127                 u32 specs[2];
 128
 129                 specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS);
 130                 specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2);
 131
 132                 gpu->identity.stream_count =
 133                         (specs[0] & VIVS_HI_CHIP_SPECS_STREAM_COUNT__MASK)
 134                                 >> VIVS_HI_CHIP_SPECS_STREAM_COUNT__SHIFT;
 135                 gpu->identity.register_max =
 136                         (specs[0] & VIVS_HI_CHIP_SPECS_REGISTER_MAX__MASK)
 137                                 >> VIVS_HI_CHIP_SPECS_REGISTER_MAX__SHIFT;
 138                 gpu->identity.thread_count =
 139                         (specs[0] & VIVS_HI_CHIP_SPECS_THREAD_COUNT__MASK)
 140                                 >> VIVS_HI_CHIP_SPECS_THREAD_COUNT__SHIFT;
 141                 gpu->identity.vertex_cache_size =
 142                         (specs[0] & VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE__MASK)
 143                                 >> VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE__SHIFT;
 144                 gpu->identity.shader_core_count =
 145                         (specs[0] & VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT__MASK)
 146                                 >> VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT__SHIFT;
 147                 gpu->identity.pixel_pipes =
 148                         (specs[0] & VIVS_HI_CHIP_SPECS_PIXEL_PIPES__MASK)
 149                                 >> VIVS_HI_CHIP_SPECS_PIXEL_PIPES__SHIFT;
 150                 gpu->identity.vertex_output_buffer_size =
 151                         (specs[0] & VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE__MASK)
 152                                 >> VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE__SHIFT;
 153
 154                 gpu->identity.buffer_size =
 155                         (specs[1] & VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE__MASK)
 156                                 >> VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE__SHIFT;
 157                 gpu->identity.instruction_count =
 158                         (specs[1] & VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT__MASK)
 159                                 >> VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT__SHIFT;
 160                 gpu->identity.num_constants =
 161                         (specs[1] & VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS__MASK)
 162                                 >> VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS__SHIFT;
 163         }
 164
 165         /* Fill in the stream count if not specified */
 166         if (gpu->identity.stream_count == 0) {
 167                 if (gpu->identity.model >= 0x1000)
 168                         gpu->identity.stream_count = 4;
 169                 else
 170                         gpu->identity.stream_count = 1;
 171         }
 172
 173         /* Convert the register max value */
 174         if (gpu->identity.register_max)
 175                 gpu->identity.register_max = 1 << gpu->identity.register_max;
 176         else if (gpu->identity.model == 0x0400)
 177                 gpu->identity.register_max = 32;
 178         else
 179                 gpu->identity.register_max = 64;
 180
 181         /* Convert thread count */
 182         if (gpu->identity.thread_count)
 183                 gpu->identity.thread_count = 1 << gpu->identity.thread_count;
 184         else if (gpu->identity.model == 0x0400)
 185                 gpu->identity.thread_count = 64;
 186         else if (gpu->identity.model == 0x0500 ||
 187                  gpu->identity.model == 0x0530)
 188                 gpu->identity.thread_count = 128;
 189         else
 190                 gpu->identity.thread_count = 256;
 191
 192         if (gpu->identity.vertex_cache_size == 0)
 193                 gpu->identity.vertex_cache_size = 8;
 194
 195         if (gpu->identity.shader_core_count == 0) {
 196                 if (gpu->identity.model >= 0x1000)
 197                         gpu->identity.shader_core_count = 2;
 198                 else
 199                         gpu->identity.shader_core_count = 1;
 200         }
 201
 202         if (gpu->identity.pixel_pipes == 0)
 203                 gpu->identity.pixel_pipes = 1;
 204
 205         /* Convert virtex buffer size */
 206         if (gpu->identity.vertex_output_buffer_size) {
 207                 gpu->identity.vertex_output_buffer_size =
 208                         1 << gpu->identity.vertex_output_buffer_size;
 209         } else if (gpu->identity.model == 0x0400) {
 210                 if (gpu->identity.revision < 0x4000)
 211                         gpu->identity.vertex_output_buffer_size = 512;
 212                 else if (gpu->identity.revision < 0x4200)
 213                         gpu->identity.vertex_output_buffer_size = 256;
 214                 else
 215                         gpu->identity.vertex_output_buffer_size = 128;
 216         } else {
 217                 gpu->identity.vertex_output_buffer_size = 512;
 218         }
 219
 220         switch (gpu->identity.instruction_count) {
 221         case 0:
 222                 if ((gpu->identity.model == 0x2000 &&
 223                      gpu->identity.revision == 0x5108) ||
 224                     gpu->identity.model == 0x880)
 225                         gpu->identity.instruction_count = 512;
 226                 else
 227                         gpu->identity.instruction_count = 256;
 228                 break;
 229
 230         case 1:
 231                 gpu->identity.instruction_count = 1024;
 232                 break;
 233
 234         case 2:
 235                 gpu->identity.instruction_count = 2048;
 236                 break;
 237
 238         default:
 239                 gpu->identity.instruction_count = 256;
 240                 break;
 241         }
 242
 243         if (gpu->identity.num_constants == 0)
 244                 gpu->identity.num_constants = 168;
 245 }
 246
 247 static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)
 248 {
 249         u32 chipIdentity;
 250
 251         chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY);
 252
 253         /* Special case for older graphic cores. */
 254         if (VIVS_HI_CHIP_IDENTITY_FAMILY(chipIdentity) ==  0x01) {
 255                 gpu->identity.model    = 0x500; /* gc500 */
 256                 gpu->identity.revision = VIVS_HI_CHIP_IDENTITY_REVISION(chipIdentity);
 257         } else {
 258
 259                 gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL);
 260                 gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV);
 261
 262                 /*
 263                  * !!!! HACK ALERT !!!!
 264                  * Because people change device IDs without letting software
 265                  * know about it - here is the hack to make it all look the
 266                  * same.  Only for GC400 family.
 267                  */
 268                 if ((gpu->identity.model & 0xff00) == 0x0400 &&
 269                     gpu->identity.model != 0x0420) {
 270                         gpu->identity.model = gpu->identity.model & 0x0400;
 271                 }
 272
 273                 /* Another special case */
 274                 if (gpu->identity.model == 0x300 &&
 275                     gpu->identity.revision == 0x2201) {
 276                         u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE);
 277                         u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME);
 278
 279                         if (chipDate == 0x20080814 && chipTime == 0x12051100) {
 280                                 /*
 281                                  * This IP has an ECO; put the correct
 282                                  * revision in it.
 283                                  */
 284                                 gpu->identity.revision = 0x1051;
 285                         }
 286                 }
 287         }
 288
 289         dev_info(gpu->dev, "model: GC%x, revision: %x\n",
 290                  gpu->identity.model, gpu->identity.revision);
 291
 292         gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE);
 293
 294         /* Disable fast clear on GC700. */
 295         if (gpu->identity.model == 0x700)
 296                 gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
 297
 298         if ((gpu->identity.model == 0x500 && gpu->identity.revision < 2) ||
 299             (gpu->identity.model == 0x300 && gpu->identity.revision < 0x2000)) {
 300
 301                 /*
 302                  * GC500 rev 1.x and GC300 rev < 2.0 doesn't have these
 303                  * registers.
 304                  */
 305                 gpu->identity.minor_features0 = 0;
 306                 gpu->identity.minor_features1 = 0;
 307                 gpu->identity.minor_features2 = 0;
 308                 gpu->identity.minor_features3 = 0;
 309         } else
 310                 gpu->identity.minor_features0 =
 311                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_0);
 312
 313         if (gpu->identity.minor_features0 &
 314             chipMinorFeatures0_MORE_MINOR_FEATURES) {
 315                 gpu->identity.minor_features1 =
 316                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_1);
 317                 gpu->identity.minor_features2 =
 318                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_2);
 319                 gpu->identity.minor_features3 =
 320                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_3);
 321         }
 322
 323         /* GC600 idle register reports zero bits where modules aren't present */
 324         if (gpu->identity.model == chipModel_GC600) {
 325                 gpu->idle_mask = VIVS_HI_IDLE_STATE_TX |
 326                                  VIVS_HI_IDLE_STATE_RA |
 327                                  VIVS_HI_IDLE_STATE_SE |
 328                                  VIVS_HI_IDLE_STATE_PA |
 329                                  VIVS_HI_IDLE_STATE_SH |
 330                                  VIVS_HI_IDLE_STATE_PE |
 331                                  VIVS_HI_IDLE_STATE_DE |
 332                                  VIVS_HI_IDLE_STATE_FE;
 333         } else {
 334                 gpu->idle_mask = ~VIVS_HI_IDLE_STATE_AXI_LP;
 335         }
 336
 337         etnaviv_hw_specs(gpu);
 338 }
 339
 340 static void etnaviv_gpu_load_clock(struct etnaviv_gpu *gpu, u32 clock)
 341 {
 342         gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock |
 343                   VIVS_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD);
 344         gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock);
 345 }
 346
 347 static int etnaviv_hw_reset(struct etnaviv_gpu *gpu)
 348 {
 349         u32 control, idle;
 350         unsigned long timeout;
 351         bool failed = true;
 352
 353         /* TODO
 354          *
 355          * - clock gating
 356          * - puls eater
 357          * - what about VG?
 358          */
 359
 360         /* We hope that the GPU resets in under one second */
 361         timeout = jiffies + msecs_to_jiffies(1000);
 362
 363         while (time_is_after_jiffies(timeout)) {
 364                 control = VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS |
 365                           VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(0x40);
 366
 367                 /* enable clock */
 368                 etnaviv_gpu_load_clock(gpu, control);
 369
 370                 /* Wait for stable clock.  Vivante's code waited for 1ms */
 371                 usleep_range(1000, 10000);
 372
 373                 /* isolate the GPU. */
 374                 control |= VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
 375                 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
 376
 377                 /* set soft reset. */
 378                 control |= VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
 379                 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
 380
 381                 /* wait for reset. */
 382                 msleep(1);
 383
 384                 /* reset soft reset bit. */
 385                 control &= ~VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
 386                 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
 387
 388                 /* reset GPU isolation. */
 389                 control &= ~VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
 390                 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
 391
 392                 /* read idle register. */
 393                 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
 394
 395                 /* try reseting again if FE it not idle */
 396                 if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) {
 397                         dev_dbg(gpu->dev, "FE is not idle\n");
 398                         continue;
 399                 }
 400
 401                 /* read reset register. */
 402                 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
 403
 404                 /* is the GPU idle? */
 405                 if (((control & VIVS_HI_CLOCK_CONTROL_IDLE_3D) == 0) ||
 406                     ((control & VIVS_HI_CLOCK_CONTROL_IDLE_2D) == 0)) {
 407                         dev_dbg(gpu->dev, "GPU is not idle\n");
 408                         continue;
 409                 }
 410
 411                 failed = false;
 412                 break;
 413         }
 414
 415         if (failed) {
 416                 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
 417                 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
 418
 419                 dev_err(gpu->dev, "GPU failed to reset: FE %sidle, 3D %sidle, 2D %sidle\n",
 420                         idle & VIVS_HI_IDLE_STATE_FE ? "" : "not ",
 421                         control & VIVS_HI_CLOCK_CONTROL_IDLE_3D ? "" : "not ",
 422                         control & VIVS_HI_CLOCK_CONTROL_IDLE_2D ? "" : "not ");
 423
 424                 return -EBUSY;
 425         }
 426
 427         /* We rely on the GPU running, so program the clock */
 428         control = VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS |
 429                   VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(0x40);
 430
 431         /* enable clock */
 432         etnaviv_gpu_load_clock(gpu, control);
 433
 434         return 0;
 435 }
 436
 437 static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu)
 438 {
 439         u16 prefetch;
 440
 441         if (gpu->identity.model == chipModel_GC320 &&
 442             gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400 &&
 443             (gpu->identity.revision == 0x5007 ||
 444              gpu->identity.revision == 0x5220)) {
 445                 u32 mc_memory_debug;
 446
 447                 mc_memory_debug = gpu_read(gpu, VIVS_MC_DEBUG_MEMORY) & ~0xff;
 448
 449                 if (gpu->identity.revision == 0x5007)
 450                         mc_memory_debug |= 0x0c;
 451                 else
 452                         mc_memory_debug |= 0x08;
 453
 454                 gpu_write(gpu, VIVS_MC_DEBUG_MEMORY, mc_memory_debug);
 455         }
 456
 457         /*
 458          * Update GPU AXI cache atttribute to "cacheable, no allocate".
 459          * This is necessary to prevent the iMX6 SoC locking up.
 460          */
 461         gpu_write(gpu, VIVS_HI_AXI_CONFIG,
 462                   VIVS_HI_AXI_CONFIG_AWCACHE(2) |
 463                   VIVS_HI_AXI_CONFIG_ARCACHE(2));
 464
 465         /* GC2000 rev 5108 needs a special bus config */
 466         if (gpu->identity.model == 0x2000 && gpu->identity.revision == 0x5108) {
 467                 u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG);
 468                 bus_config &= ~(VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK |
 469                                 VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK);
 470                 bus_config |= VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG(1) |
 471                               VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG(0);
 472                 gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config);
 473         }
 474
 475         /* set base addresses */
 476         gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_RA, gpu->memory_base);
 477         gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_FE, gpu->memory_base);
 478         gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_TX, gpu->memory_base);
 479         gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PEZ, gpu->memory_base);
 480         gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PE, gpu->memory_base);
 481
 482         /* setup the MMU page table pointers */
 483         etnaviv_iommu_domain_restore(gpu, gpu->mmu->domain);
 484
 485         /* Start command processor */
 486         prefetch = etnaviv_buffer_init(gpu);
 487
 488         gpu_write(gpu, VIVS_HI_INTR_ENBL, ~0U);
 489         gpu_write(gpu, VIVS_FE_COMMAND_ADDRESS,
 490                   gpu->buffer->paddr - gpu->memory_base);
 491         gpu_write(gpu, VIVS_FE_COMMAND_CONTROL,
 492                   VIVS_FE_COMMAND_CONTROL_ENABLE |
 493                   VIVS_FE_COMMAND_CONTROL_PREFETCH(prefetch));
 494 }
 495
 496 int etnaviv_gpu_init(struct etnaviv_gpu *gpu)
 497 {
 498         int ret, i;
 499         struct iommu_domain *iommu;
 500         enum etnaviv_iommu_version version;
 501         bool mmuv2;
 502
 503         ret = pm_runtime_get_sync(gpu->dev);
 504         if (ret < 0)
 505                 return ret;
 506
 507         etnaviv_hw_identify(gpu);
 508
 509         if (gpu->identity.model == 0) {
 510                 dev_err(gpu->dev, "Unknown GPU model\n");
 511                 pm_runtime_put_autosuspend(gpu->dev);
 512                 return -ENXIO;
 513         }
 514
 515         ret = etnaviv_hw_reset(gpu);
 516         if (ret)
 517                 goto fail;
 518
 519         /* Setup IOMMU.. eventually we will (I think) do this once per context
 520          * and have separate page tables per context.  For now, to keep things
 521          * simple and to get something working, just use a single address space:
 522          */
 523         mmuv2 = gpu->identity.minor_features1 & chipMinorFeatures1_MMU_VERSION;
 524         dev_dbg(gpu->dev, "mmuv2: %d\n", mmuv2);
 525
 526         if (!mmuv2) {
 527                 iommu = etnaviv_iommu_domain_alloc(gpu);
 528                 version = ETNAVIV_IOMMU_V1;
 529         } else {
 530                 iommu = etnaviv_iommu_v2_domain_alloc(gpu);
 531                 version = ETNAVIV_IOMMU_V2;
 532         }
 533
 534         if (!iommu) {
 535                 ret = -ENOMEM;
 536                 goto fail;
 537         }
 538
 539         /* TODO: we will leak here memory - fix it! */
 540
 541         gpu->mmu = etnaviv_iommu_new(gpu, iommu, version);
 542         if (!gpu->mmu) {
 543                 ret = -ENOMEM;
 544                 goto fail;
 545         }
 546
 547         /* Create buffer: */
 548         gpu->buffer = etnaviv_gpu_cmdbuf_new(gpu, PAGE_SIZE, 0);
 549         if (!gpu->buffer) {
 550                 ret = -ENOMEM;
 551                 dev_err(gpu->dev, "could not create command buffer\n");
 552                 goto fail;
 553         }
 554         if (gpu->buffer->paddr - gpu->memory_base > 0x80000000) {
 555                 ret = -EINVAL;
 556                 dev_err(gpu->dev,
 557                         "command buffer outside valid memory window\n");
 558                 goto free_buffer;
 559         }
 560
 561         /* Setup event management */
 562         spin_lock_init(&gpu->event_spinlock);
 563         init_completion(&gpu->event_free);
 564         for (i = 0; i < ARRAY_SIZE(gpu->event); i++) {
 565                 gpu->event[i].used = false;
 566                 complete(&gpu->event_free);
 567         }
 568
 569         /* Now program the hardware */
 570         mutex_lock(&gpu->lock);
 571         etnaviv_gpu_hw_init(gpu);
 572         mutex_unlock(&gpu->lock);
 573
 574         pm_runtime_mark_last_busy(gpu->dev);
 575         pm_runtime_put_autosuspend(gpu->dev);
 576
 577         return 0;
 578
 579 free_buffer:
 580         etnaviv_gpu_cmdbuf_free(gpu->buffer);
 581         gpu->buffer = NULL;
 582 fail:
 583         pm_runtime_mark_last_busy(gpu->dev);
 584         pm_runtime_put_autosuspend(gpu->dev);
 585
 586         return ret;
 587 }
 588
 589 #ifdef CONFIG_DEBUG_FS
 590 struct dma_debug {
 591         u32 address[2];
 592         u32 state[2];
 593 };
 594
 595 static void verify_dma(struct etnaviv_gpu *gpu, struct dma_debug *debug)
 596 {
 597         u32 i;
 598
 599         debug->address[0] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
 600         debug->state[0]   = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
 601
 602         for (i = 0; i < 500; i++) {
 603                 debug->address[1] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
 604                 debug->state[1]   = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
 605
 606                 if (debug->address[0] != debug->address[1])
 607                         break;
 608
 609                 if (debug->state[0] != debug->state[1])
 610                         break;
 611         }
 612 }
 613
 614 int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m)
 615 {
 616         struct dma_debug debug;
 617         u32 dma_lo, dma_hi, axi, idle;
 618         int ret;
 619
 620         seq_printf(m, "%s Status:\n", dev_name(gpu->dev));
 621
 622         ret = pm_runtime_get_sync(gpu->dev);
 623         if (ret < 0)
 624                 return ret;
 625
 626         dma_lo = gpu_read(gpu, VIVS_FE_DMA_LOW);
 627         dma_hi = gpu_read(gpu, VIVS_FE_DMA_HIGH);
 628         axi = gpu_read(gpu, VIVS_HI_AXI_STATUS);
 629         idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
 630
 631         verify_dma(gpu, &debug);
 632
 633         seq_puts(m, "\tfeatures\n");
 634         seq_printf(m, "\t minor_features0: 0x%08x\n",
 635                    gpu->identity.minor_features0);
 636         seq_printf(m, "\t minor_features1: 0x%08x\n",
 637                    gpu->identity.minor_features1);
 638         seq_printf(m, "\t minor_features2: 0x%08x\n",
 639                    gpu->identity.minor_features2);
 640         seq_printf(m, "\t minor_features3: 0x%08x\n",
 641                    gpu->identity.minor_features3);
 642
 643         seq_puts(m, "\tspecs\n");
 644         seq_printf(m, "\t stream_count:  %d\n",
 645                         gpu->identity.stream_count);
 646         seq_printf(m, "\t register_max: %d\n",
 647                         gpu->identity.register_max);
 648         seq_printf(m, "\t thread_count: %d\n",
 649                         gpu->identity.thread_count);
 650         seq_printf(m, "\t vertex_cache_size: %d\n",
 651                         gpu->identity.vertex_cache_size);
 652         seq_printf(m, "\t shader_core_count: %d\n",
 653                         gpu->identity.shader_core_count);
 654         seq_printf(m, "\t pixel_pipes: %d\n",
 655                         gpu->identity.pixel_pipes);
 656         seq_printf(m, "\t vertex_output_buffer_size: %d\n",
 657                         gpu->identity.vertex_output_buffer_size);
 658         seq_printf(m, "\t buffer_size: %d\n",
 659                         gpu->identity.buffer_size);
 660         seq_printf(m, "\t instruction_count: %d\n",
 661                         gpu->identity.instruction_count);
 662         seq_printf(m, "\t num_constants: %d\n",
 663                         gpu->identity.num_constants);
 664
 665         seq_printf(m, "\taxi: 0x%08x\n", axi);
 666         seq_printf(m, "\tidle: 0x%08x\n", idle);
 667         idle |= ~gpu->idle_mask & ~VIVS_HI_IDLE_STATE_AXI_LP;
 668         if ((idle & VIVS_HI_IDLE_STATE_FE) == 0)
 669                 seq_puts(m, "\t FE is not idle\n");
 670         if ((idle & VIVS_HI_IDLE_STATE_DE) == 0)
 671                 seq_puts(m, "\t DE is not idle\n");
 672         if ((idle & VIVS_HI_IDLE_STATE_PE) == 0)
 673                 seq_puts(m, "\t PE is not idle\n");
 674         if ((idle & VIVS_HI_IDLE_STATE_SH) == 0)
 675                 seq_puts(m, "\t SH is not idle\n");
 676         if ((idle & VIVS_HI_IDLE_STATE_PA) == 0)
 677                 seq_puts(m, "\t PA is not idle\n");
 678         if ((idle & VIVS_HI_IDLE_STATE_SE) == 0)
 679                 seq_puts(m, "\t SE is not idle\n");
 680         if ((idle & VIVS_HI_IDLE_STATE_RA) == 0)
 681                 seq_puts(m, "\t RA is not idle\n");
 682         if ((idle & VIVS_HI_IDLE_STATE_TX) == 0)
 683                 seq_puts(m, "\t TX is not idle\n");
 684         if ((idle & VIVS_HI_IDLE_STATE_VG) == 0)
 685                 seq_puts(m, "\t VG is not idle\n");
 686         if ((idle & VIVS_HI_IDLE_STATE_IM) == 0)
 687                 seq_puts(m, "\t IM is not idle\n");
 688         if ((idle & VIVS_HI_IDLE_STATE_FP) == 0)
 689                 seq_puts(m, "\t FP is not idle\n");
 690         if ((idle & VIVS_HI_IDLE_STATE_TS) == 0)
 691                 seq_puts(m, "\t TS is not idle\n");
 692         if (idle & VIVS_HI_IDLE_STATE_AXI_LP)
 693                 seq_puts(m, "\t AXI low power mode\n");
 694
 695         if (gpu->identity.features & chipFeatures_DEBUG_MODE) {
 696                 u32 read0 = gpu_read(gpu, VIVS_MC_DEBUG_READ0);
 697                 u32 read1 = gpu_read(gpu, VIVS_MC_DEBUG_READ1);
 698                 u32 write = gpu_read(gpu, VIVS_MC_DEBUG_WRITE);
 699
 700                 seq_puts(m, "\tMC\n");
 701                 seq_printf(m, "\t read0: 0x%08x\n", read0);
 702                 seq_printf(m, "\t read1: 0x%08x\n", read1);
 703                 seq_printf(m, "\t write: 0x%08x\n", write);
 704         }
 705
 706         seq_puts(m, "\tDMA ");
 707
 708         if (debug.address[0] == debug.address[1] &&
 709             debug.state[0] == debug.state[1]) {
 710                 seq_puts(m, "seems to be stuck\n");
 711         } else if (debug.address[0] == debug.address[1]) {
 712                 seq_puts(m, "adress is constant\n");
 713         } else {
 714                 seq_puts(m, "is runing\n");
 715         }
 716
 717         seq_printf(m, "\t address 0: 0x%08x\n", debug.address[0]);
 718         seq_printf(m, "\t address 1: 0x%08x\n", debug.address[1]);
 719         seq_printf(m, "\t state 0: 0x%08x\n", debug.state[0]);
 720         seq_printf(m, "\t state 1: 0x%08x\n", debug.state[1]);
 721         seq_printf(m, "\t last fetch 64 bit word: 0x%08x 0x%08x\n",
 722                    dma_lo, dma_hi);
 723
 724         ret = 0;
 725
 726         pm_runtime_mark_last_busy(gpu->dev);
 727         pm_runtime_put_autosuspend(gpu->dev);
 728
 729         return ret;
 730 }
 731 #endif
 732
 733 /*
 734  * Power Management:
 735  */
 736 static int enable_clk(struct etnaviv_gpu *gpu)
 737 {
 738         if (gpu->clk_core)
 739                 clk_prepare_enable(gpu->clk_core);
 740         if (gpu->clk_shader)
 741                 clk_prepare_enable(gpu->clk_shader);
 742
 743         return 0;
 744 }
 745
 746 static int disable_clk(struct etnaviv_gpu *gpu)
 747 {
 748         if (gpu->clk_core)
 749                 clk_disable_unprepare(gpu->clk_core);
 750         if (gpu->clk_shader)
 751                 clk_disable_unprepare(gpu->clk_shader);
 752
 753         return 0;
 754 }
 755
 756 static int enable_axi(struct etnaviv_gpu *gpu)
 757 {
 758         if (gpu->clk_bus)
 759                 clk_prepare_enable(gpu->clk_bus);
 760
 761         return 0;
 762 }
 763
 764 static int disable_axi(struct etnaviv_gpu *gpu)
 765 {
 766         if (gpu->clk_bus)
 767                 clk_disable_unprepare(gpu->clk_bus);
 768
 769         return 0;
 770 }
 771
 772 /*
 773  * Hangcheck detection for locked gpu:
 774  */
 775 static void recover_worker(struct work_struct *work)
 776 {
 777         struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu,
 778                                                recover_work);
 779         unsigned long flags;
 780         unsigned int i;
 781
 782         dev_err(gpu->dev, "hangcheck recover!\n");
 783
 784         if (pm_runtime_get_sync(gpu->dev) < 0)
 785                 return;
 786
 787         mutex_lock(&gpu->lock);
 788
 789         /* Only catch the first event, or when manually re-armed */
 790         if (etnaviv_dump_core) {
 791                 etnaviv_core_dump(gpu);
 792                 etnaviv_dump_core = false;
 793         }
 794
 795         etnaviv_hw_reset(gpu);
 796
 797         /* complete all events, the GPU won't do it after the reset */
 798         spin_lock_irqsave(&gpu->event_spinlock, flags);
 799         for (i = 0; i < ARRAY_SIZE(gpu->event); i++) {
 800                 if (!gpu->event[i].used)
 801                         continue;
 802                 fence_signal(gpu->event[i].fence);
 803                 gpu->event[i].fence = NULL;
 804                 gpu->event[i].used = false;
 805                 complete(&gpu->event_free);
 806                 /*
 807                  * Decrement the PM count for each stuck event. This is safe
 808                  * even in atomic context as we use ASYNC RPM here.
 809                  */
 810                 pm_runtime_put_autosuspend(gpu->dev);
 811         }
 812         spin_unlock_irqrestore(&gpu->event_spinlock, flags);
 813         gpu->completed_fence = gpu->active_fence;
 814
 815         etnaviv_gpu_hw_init(gpu);
 816         gpu->switch_context = true;
 817
 818         mutex_unlock(&gpu->lock);
 819         pm_runtime_mark_last_busy(gpu->dev);
 820         pm_runtime_put_autosuspend(gpu->dev);
 821
 822         /* Retire the buffer objects in a work */
 823         etnaviv_queue_work(gpu->drm, &gpu->retire_work);
 824 }
 825
 826 static void hangcheck_timer_reset(struct etnaviv_gpu *gpu)
 827 {
 828         DBG("%s", dev_name(gpu->dev));
 829         mod_timer(&gpu->hangcheck_timer,
 830                   round_jiffies_up(jiffies + DRM_ETNAVIV_HANGCHECK_JIFFIES));
 831 }
 832
 833 static void hangcheck_handler(unsigned long data)
 834 {
 835         struct etnaviv_gpu *gpu = (struct etnaviv_gpu *)data;
 836         u32 fence = gpu->completed_fence;
 837         bool progress = false;
 838
 839         if (fence != gpu->hangcheck_fence) {
 840                 gpu->hangcheck_fence = fence;
 841                 progress = true;
 842         }
 843
 844         if (!progress) {
 845                 u32 dma_addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
 846                 int change = dma_addr - gpu->hangcheck_dma_addr;
 847
 848                 if (change < 0 || change > 16) {
 849                         gpu->hangcheck_dma_addr = dma_addr;
 850                         progress = true;
 851                 }
 852         }
 853
 854         if (!progress && fence_after(gpu->active_fence, fence)) {
 855                 dev_err(gpu->dev, "hangcheck detected gpu lockup!\n");
 856                 dev_err(gpu->dev, "     completed fence: %u\n", fence);
 857                 dev_err(gpu->dev, "     active fence: %u\n",
 858                         gpu->active_fence);
 859                 etnaviv_queue_work(gpu->drm, &gpu->recover_work);
 860         }
 861
 862         /* if still more pending work, reset the hangcheck timer: */
 863         if (fence_after(gpu->active_fence, gpu->hangcheck_fence))
 864                 hangcheck_timer_reset(gpu);
 865 }
 866
 867 static void hangcheck_disable(struct etnaviv_gpu *gpu)
 868 {
 869         del_timer_sync(&gpu->hangcheck_timer);
 870         cancel_work_sync(&gpu->recover_work);
 871 }
 872
 873 /* fence object management */
 874 struct etnaviv_fence {
 875         struct etnaviv_gpu *gpu;
 876         struct fence base;
 877 };
 878
 879 static inline struct etnaviv_fence *to_etnaviv_fence(struct fence *fence)
 880 {
 881         return container_of(fence, struct etnaviv_fence, base);
 882 }
 883
 884 static const char *etnaviv_fence_get_driver_name(struct fence *fence)
 885 {
 886         return "etnaviv";
 887 }
 888
 889 static const char *etnaviv_fence_get_timeline_name(struct fence *fence)
 890 {
 891         struct etnaviv_fence *f = to_etnaviv_fence(fence);
 892
 893         return dev_name(f->gpu->dev);
 894 }
 895
 896 static bool etnaviv_fence_enable_signaling(struct fence *fence)
 897 {
 898         return true;
 899 }
 900
 901 static bool etnaviv_fence_signaled(struct fence *fence)
 902 {
 903         struct etnaviv_fence *f = to_etnaviv_fence(fence);
 904
 905         return fence_completed(f->gpu, f->base.seqno);
 906 }
 907
 908 static void etnaviv_fence_release(struct fence *fence)
 909 {
 910         struct etnaviv_fence *f = to_etnaviv_fence(fence);
 911
 912         kfree_rcu(f, base.rcu);
 913 }
 914
 915 static const struct fence_ops etnaviv_fence_ops = {
 916         .get_driver_name = etnaviv_fence_get_driver_name,
 917         .get_timeline_name = etnaviv_fence_get_timeline_name,
 918         .enable_signaling = etnaviv_fence_enable_signaling,
 919         .signaled = etnaviv_fence_signaled,
 920         .wait = fence_default_wait,
 921         .release = etnaviv_fence_release,
 922 };
 923
 924 static struct fence *etnaviv_gpu_fence_alloc(struct etnaviv_gpu *gpu)
 925 {
 926         struct etnaviv_fence *f;
 927
 928         f = kzalloc(sizeof(*f), GFP_KERNEL);
 929         if (!f)
 930                 return NULL;
 931
 932         f->gpu = gpu;
 933
 934         fence_init(&f->base, &etnaviv_fence_ops, &gpu->fence_spinlock,
 935                    gpu->fence_context, ++gpu->next_fence);
 936
 937         return &f->base;
 938 }
 939
 940 int etnaviv_gpu_fence_sync_obj(struct etnaviv_gem_object *etnaviv_obj,
 941         unsigned int context, bool exclusive)
 942 {
 943         struct reservation_object *robj = etnaviv_obj->resv;
 944         struct reservation_object_list *fobj;
 945         struct fence *fence;
 946         int i, ret;
 947
 948         if (!exclusive) {
 949                 ret = reservation_object_reserve_shared(robj);
 950                 if (ret)
 951                         return ret;
 952         }
 953
 954         /*
 955          * If we have any shared fences, then the exclusive fence
 956          * should be ignored as it will already have been signalled.
 957          */
 958         fobj = reservation_object_get_list(robj);
 959         if (!fobj || fobj->shared_count == 0) {
 960                 /* Wait on any existing exclusive fence which isn't our own */
 961                 fence = reservation_object_get_excl(robj);
 962                 if (fence && fence->context != context) {
 963                         ret = fence_wait(fence, true);
 964                         if (ret)
 965                                 return ret;
 966                 }
 967         }
 968
 969         if (!exclusive || !fobj)
 970                 return 0;
 971
 972         for (i = 0; i < fobj->shared_count; i++) {
 973                 fence = rcu_dereference_protected(fobj->shared[i],
 974                                                 reservation_object_held(robj));
 975                 if (fence->context != context) {
 976                         ret = fence_wait(fence, true);
 977                         if (ret)
 978                                 return ret;
 979                 }
 980         }
 981
 982         return 0;
 983 }
 984
 985 /*
 986  * event management:
 987  */
 988
 989 static unsigned int event_alloc(struct etnaviv_gpu *gpu)
 990 {
 991         unsigned long ret, flags;
 992         unsigned int i, event = ~0U;
 993
 994         ret = wait_for_completion_timeout(&gpu->event_free,
 995                                           msecs_to_jiffies(10 * 10000));
 996         if (!ret)
 997                 dev_err(gpu->dev, "wait_for_completion_timeout failed");
 998
 999         spin_lock_irqsave(&gpu->event_spinlock, flags);
1000
1001         /* find first free event */
1002         for (i = 0; i < ARRAY_SIZE(gpu->event); i++) {
1003                 if (gpu->event[i].used == false) {
1004                         gpu->event[i].used = true;
1005                         event = i;
1006                         break;
1007                 }
1008         }
1009
1010         spin_unlock_irqrestore(&gpu->event_spinlock, flags);
1011
1012         return event;
1013 }
1014
1015 static void event_free(struct etnaviv_gpu *gpu, unsigned int event)
1016 {
1017         unsigned long flags;
1018
1019         spin_lock_irqsave(&gpu->event_spinlock, flags);
1020
1021         if (gpu->event[event].used == false) {
1022                 dev_warn(gpu->dev, "event %u is already marked as free",
1023                          event);
1024                 spin_unlock_irqrestore(&gpu->event_spinlock, flags);
1025         } else {
1026                 gpu->event[event].used = false;
1027                 spin_unlock_irqrestore(&gpu->event_spinlock, flags);
1028
1029                 complete(&gpu->event_free);
1030         }
1031 }
1032
1033 /*
1034  * Cmdstream submission/retirement:
1035  */
1036
1037 struct etnaviv_cmdbuf *etnaviv_gpu_cmdbuf_new(struct etnaviv_gpu *gpu, u32 size,
1038         size_t nr_bos)
1039 {
1040         struct etnaviv_cmdbuf *cmdbuf;
1041         size_t sz = size_vstruct(nr_bos, sizeof(cmdbuf->bo[0]),
1042                                  sizeof(*cmdbuf));
1043
1044         cmdbuf = kzalloc(sz, GFP_KERNEL);
1045         if (!cmdbuf)
1046                 return NULL;
1047
1048         cmdbuf->vaddr = dma_alloc_writecombine(gpu->dev, size, &cmdbuf->paddr,
1049                                                GFP_KERNEL);
1050         if (!cmdbuf->vaddr) {
1051                 kfree(cmdbuf);
1052                 return NULL;
1053         }
1054
1055         cmdbuf->gpu = gpu;
1056         cmdbuf->size = size;
1057
1058         return cmdbuf;
1059 }
1060
1061 void etnaviv_gpu_cmdbuf_free(struct etnaviv_cmdbuf *cmdbuf)
1062 {
1063         dma_free_writecombine(cmdbuf->gpu->dev, cmdbuf->size,
1064                               cmdbuf->vaddr, cmdbuf->paddr);
1065         kfree(cmdbuf);
1066 }
1067
1068 static void retire_worker(struct work_struct *work)
1069 {
1070         struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu,
1071                                                retire_work);
1072         u32 fence = gpu->completed_fence;
1073         struct etnaviv_cmdbuf *cmdbuf, *tmp;
1074         unsigned int i;
1075
1076         mutex_lock(&gpu->lock);
1077         list_for_each_entry_safe(cmdbuf, tmp, &gpu->active_cmd_list, node) {
1078                 if (!fence_is_signaled(cmdbuf->fence))
1079                         break;
1080
1081                 list_del(&cmdbuf->node);
1082                 fence_put(cmdbuf->fence);
1083
1084                 for (i = 0; i < cmdbuf->nr_bos; i++) {
1085                         struct etnaviv_gem_object *etnaviv_obj = cmdbuf->bo[i];
1086
1087                         atomic_dec(&etnaviv_obj->gpu_active);
1088                         /* drop the refcount taken in etnaviv_gpu_submit */
1089                         etnaviv_gem_put_iova(gpu, &etnaviv_obj->base);
1090                 }
1091
1092                 etnaviv_gpu_cmdbuf_free(cmdbuf);
1093         }
1094
1095         gpu->retired_fence = fence;
1096
1097         mutex_unlock(&gpu->lock);
1098
1099         wake_up_all(&gpu->fence_event);
1100 }
1101
1102 int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu,
1103         u32 fence, struct timespec *timeout)
1104 {
1105         int ret;
1106
1107         if (fence_after(fence, gpu->next_fence)) {
1108                 DRM_ERROR("waiting on invalid fence: %u (of %u)\n",
1109                                 fence, gpu->next_fence);
1110                 return -EINVAL;
1111         }
1112
1113         if (!timeout) {
1114                 /* No timeout was requested: just test for completion */
1115                 ret = fence_completed(gpu, fence) ? 0 : -EBUSY;
1116         } else {
1117                 unsigned long remaining = etnaviv_timeout_to_jiffies(timeout);
1118
1119                 ret = wait_event_interruptible_timeout(gpu->fence_event,
1120                                                 fence_completed(gpu, fence),
1121                                                 remaining);
1122                 if (ret == 0) {
1123                         DBG("timeout waiting for fence: %u (retired: %u completed: %u)",
1124                                 fence, gpu->retired_fence,
1125                                 gpu->completed_fence);
1126                         ret = -ETIMEDOUT;
1127                 } else if (ret != -ERESTARTSYS) {
1128                         ret = 0;
1129                 }
1130         }
1131
1132         return ret;
1133 }
1134
1135 /*
1136  * Wait for an object to become inactive.  This, on it's own, is not race
1137  * free: the object is moved by the retire worker off the active list, and
1138  * then the iova is put.  Moreover, the object could be re-submitted just
1139  * after we notice that it's become inactive.
1140  *
1141  * Although the retirement happens under the gpu lock, we don't want to hold
1142  * that lock in this function while waiting.
1143  */
1144 int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu,
1145         struct etnaviv_gem_object *etnaviv_obj, struct timespec *timeout)
1146 {
1147         unsigned long remaining;
1148         long ret;
1149
1150         if (!timeout)
1151                 return !is_active(etnaviv_obj) ? 0 : -EBUSY;
1152
1153         remaining = etnaviv_timeout_to_jiffies(timeout);
1154
1155         ret = wait_event_interruptible_timeout(gpu->fence_event,
1156                                                !is_active(etnaviv_obj),
1157                                                remaining);
1158         if (ret > 0) {
1159                 struct etnaviv_drm_private *priv = gpu->drm->dev_private;
1160
1161                 /* Synchronise with the retire worker */
1162                 flush_workqueue(priv->wq);
1163                 return 0;
1164         } else if (ret == -ERESTARTSYS) {
1165                 return -ERESTARTSYS;
1166         } else {
1167                 return -ETIMEDOUT;
1168         }
1169 }
1170
1171 int etnaviv_gpu_pm_get_sync(struct etnaviv_gpu *gpu)
1172 {
1173         return pm_runtime_get_sync(gpu->dev);
1174 }
1175
1176 void etnaviv_gpu_pm_put(struct etnaviv_gpu *gpu)
1177 {
1178         pm_runtime_mark_last_busy(gpu->dev);
1179         pm_runtime_put_autosuspend(gpu->dev);
1180 }
1181
1182 /* add bo's to gpu's ring, and kick gpu: */
1183 int etnaviv_gpu_submit(struct etnaviv_gpu *gpu,
1184         struct etnaviv_gem_submit *submit, struct etnaviv_cmdbuf *cmdbuf)
1185 {
1186         struct fence *fence;
1187         unsigned int event, i;
1188         int ret;
1189
1190         ret = etnaviv_gpu_pm_get_sync(gpu);
1191         if (ret < 0)
1192                 return ret;
1193
1194         mutex_lock(&gpu->lock);
1195
1196         /*
1197          * TODO
1198          *
1199          * - flush
1200          * - data endian
1201          * - prefetch
1202          *
1203          */
1204
1205         event = event_alloc(gpu);
1206         if (unlikely(event == ~0U)) {
1207                 DRM_ERROR("no free event\n");
1208                 ret = -EBUSY;
1209                 goto out_unlock;
1210         }
1211
1212         fence = etnaviv_gpu_fence_alloc(gpu);
1213         if (!fence) {
1214                 event_free(gpu, event);
1215                 ret = -ENOMEM;
1216                 goto out_unlock;
1217         }
1218
1219         gpu->event[event].fence = fence;
1220         submit->fence = fence->seqno;
1221         gpu->active_fence = submit->fence;
1222
1223         if (gpu->lastctx != cmdbuf->ctx) {
1224                 gpu->mmu->need_flush = true;
1225                 gpu->switch_context = true;
1226                 gpu->lastctx = cmdbuf->ctx;
1227         }
1228
1229         etnaviv_buffer_queue(gpu, event, cmdbuf);
1230
1231         cmdbuf->fence = fence;
1232         list_add_tail(&cmdbuf->node, &gpu->active_cmd_list);
1233
1234         /* We're committed to adding this command buffer, hold a PM reference */
1235         pm_runtime_get_noresume(gpu->dev);
1236
1237         for (i = 0; i < submit->nr_bos; i++) {
1238                 struct etnaviv_gem_object *etnaviv_obj = submit->bos[i].obj;
1239                 u32 iova;
1240
1241                 /* Each cmdbuf takes a refcount on the iova */
1242                 etnaviv_gem_get_iova(gpu, &etnaviv_obj->base, &iova);
1243                 cmdbuf->bo[i] = etnaviv_obj;
1244                 atomic_inc(&etnaviv_obj->gpu_active);
1245
1246                 if (submit->bos[i].flags & ETNA_SUBMIT_BO_WRITE)
1247                         reservation_object_add_excl_fence(etnaviv_obj->resv,
1248                                                           fence);
1249                 else
1250                         reservation_object_add_shared_fence(etnaviv_obj->resv,
1251                                                             fence);
1252         }
1253         cmdbuf->nr_bos = submit->nr_bos;
1254         hangcheck_timer_reset(gpu);
1255         ret = 0;
1256
1257 out_unlock:
1258         mutex_unlock(&gpu->lock);
1259
1260         etnaviv_gpu_pm_put(gpu);
1261
1262         return ret;
1263 }
1264
1265 /*
1266  * Init/Cleanup:
1267  */
1268 static irqreturn_t irq_handler(int irq, void *data)
1269 {
1270         struct etnaviv_gpu *gpu = data;
1271         irqreturn_t ret = IRQ_NONE;
1272
1273         u32 intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE);
1274
1275         if (intr != 0) {
1276                 int event;
1277
1278                 pm_runtime_mark_last_busy(gpu->dev);
1279
1280                 dev_dbg(gpu->dev, "intr 0x%08x\n", intr);
1281
1282                 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR) {
1283                         dev_err(gpu->dev, "AXI bus error\n");
1284                         intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR;
1285                 }
1286
1287                 while ((event = ffs(intr)) != 0) {
1288                         struct fence *fence;
1289
1290                         event -= 1;
1291
1292                         intr &= ~(1 << event);
1293
1294                         dev_dbg(gpu->dev, "event %u\n", event);
1295
1296                         fence = gpu->event[event].fence;
1297                         gpu->event[event].fence = NULL;
1298                         fence_signal(fence);
1299
1300                         /*
1301                          * Events can be processed out of order.  Eg,
1302                          * - allocate and queue event 0
1303                          * - allocate event 1
1304                          * - event 0 completes, we process it
1305                          * - allocate and queue event 0
1306                          * - event 1 and event 0 complete
1307                          * we can end up processing event 0 first, then 1.
1308                          */
1309                         if (fence_after(fence->seqno, gpu->completed_fence))
1310                                 gpu->completed_fence = fence->seqno;
1311
1312                         event_free(gpu, event);
1313
1314                         /*
1315                          * We need to balance the runtime PM count caused by
1316                          * each submission.  Upon submission, we increment
1317                          * the runtime PM counter, and allocate one event.
1318                          * So here, we put the runtime PM count for each
1319                          * completed event.
1320                          */
1321                         pm_runtime_put_autosuspend(gpu->dev);
1322                 }
1323
1324                 /* Retire the buffer objects in a work */
1325                 etnaviv_queue_work(gpu->drm, &gpu->retire_work);
1326
1327                 ret = IRQ_HANDLED;
1328         }
1329
1330         return ret;
1331 }
1332
1333 static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu)
1334 {
1335         int ret;
1336
1337         ret = enable_clk(gpu);
1338         if (ret)
1339                 return ret;
1340
1341         ret = enable_axi(gpu);
1342         if (ret) {
1343                 disable_clk(gpu);
1344                 return ret;
1345         }
1346
1347         return 0;
1348 }
1349
1350 static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu)
1351 {
1352         int ret;
1353
1354         ret = disable_axi(gpu);
1355         if (ret)
1356                 return ret;
1357
1358         ret = disable_clk(gpu);
1359         if (ret)
1360                 return ret;
1361
1362         return 0;
1363 }
1364
1365 static int etnaviv_gpu_hw_suspend(struct etnaviv_gpu *gpu)
1366 {
1367         if (gpu->buffer) {
1368                 unsigned long timeout;
1369
1370                 /* Replace the last WAIT with END */
1371                 etnaviv_buffer_end(gpu);
1372
1373                 /*
1374                  * We know that only the FE is busy here, this should
1375                  * happen quickly (as the WAIT is only 200 cycles).  If
1376                  * we fail, just warn and continue.
1377                  */
1378                 timeout = jiffies + msecs_to_jiffies(100);
1379                 do {
1380                         u32 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
1381
1382                         if ((idle & gpu->idle_mask) == gpu->idle_mask)
1383                                 break;
1384
1385                         if (time_is_before_jiffies(timeout)) {
1386                                 dev_warn(gpu->dev,
1387                                          "timed out waiting for idle: idle=0x%x\n",
1388                                          idle);
1389                                 break;
1390                         }
1391
1392                         udelay(5);
1393                 } while (1);
1394         }
1395
1396         return etnaviv_gpu_clk_disable(gpu);
1397 }
1398
1399 #ifdef CONFIG_PM
1400 static int etnaviv_gpu_hw_resume(struct etnaviv_gpu *gpu)
1401 {
1402         u32 clock;
1403         int ret;
1404
1405         ret = mutex_lock_killable(&gpu->lock);
1406         if (ret)
1407                 return ret;
1408
1409         clock = VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS |
1410                 VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(0x40);
1411
1412         etnaviv_gpu_load_clock(gpu, clock);
1413         etnaviv_gpu_hw_init(gpu);
1414
1415         gpu->switch_context = true;
1416
1417         mutex_unlock(&gpu->lock);
1418
1419         return 0;
1420 }
1421 #endif
1422
1423 static int etnaviv_gpu_bind(struct device *dev, struct device *master,
1424         void *data)
1425 {
1426         struct drm_device *drm = data;
1427         struct etnaviv_drm_private *priv = drm->dev_private;
1428         struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1429         int ret;
1430
1431 #ifdef CONFIG_PM
1432         ret = pm_runtime_get_sync(gpu->dev);
1433 #else
1434         ret = etnaviv_gpu_clk_enable(gpu);
1435 #endif
1436         if (ret < 0)
1437                 return ret;
1438
1439         gpu->drm = drm;
1440         gpu->fence_context = fence_context_alloc(1);
1441         spin_lock_init(&gpu->fence_spinlock);
1442
1443         INIT_LIST_HEAD(&gpu->active_cmd_list);
1444         INIT_WORK(&gpu->retire_work, retire_worker);
1445         INIT_WORK(&gpu->recover_work, recover_worker);
1446         init_waitqueue_head(&gpu->fence_event);
1447
1448         setup_timer(&gpu->hangcheck_timer, hangcheck_handler,
1449                         (unsigned long)gpu);
1450
1451         priv->gpu[priv->num_gpus++] = gpu;
1452
1453         pm_runtime_mark_last_busy(gpu->dev);
1454         pm_runtime_put_autosuspend(gpu->dev);
1455
1456         return 0;
1457 }
1458
1459 static void etnaviv_gpu_unbind(struct device *dev, struct device *master,
1460         void *data)
1461 {
1462         struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1463
1464         DBG("%s", dev_name(gpu->dev));
1465
1466         hangcheck_disable(gpu);
1467
1468 #ifdef CONFIG_PM
1469         pm_runtime_get_sync(gpu->dev);
1470         pm_runtime_put_sync_suspend(gpu->dev);
1471 #else
1472         etnaviv_gpu_hw_suspend(gpu);
1473 #endif
1474
1475         if (gpu->buffer) {
1476                 etnaviv_gpu_cmdbuf_free(gpu->buffer);
1477                 gpu->buffer = NULL;
1478         }
1479
1480         if (gpu->mmu) {
1481                 etnaviv_iommu_destroy(gpu->mmu);
1482                 gpu->mmu = NULL;
1483         }
1484
1485         gpu->drm = NULL;
1486 }
1487
1488 static const struct component_ops gpu_ops = {
1489         .bind = etnaviv_gpu_bind,
1490         .unbind = etnaviv_gpu_unbind,
1491 };
1492
1493 static const struct of_device_id etnaviv_gpu_match[] = {
1494         {
1495                 .compatible = "vivante,gc"
1496         },
1497         { /* sentinel */ }
1498 };
1499
1500 static int etnaviv_gpu_platform_probe(struct platform_device *pdev)
1501 {
1502         struct device *dev = &pdev->dev;
1503         struct etnaviv_gpu *gpu;
1504         int err = 0;
1505
1506         gpu = devm_kzalloc(dev, sizeof(*gpu), GFP_KERNEL);
1507         if (!gpu)
1508                 return -ENOMEM;
1509
1510         gpu->dev = &pdev->dev;
1511         mutex_init(&gpu->lock);
1512
1513         /*
1514          * Set the GPU base address to the start of physical memory.  This
1515          * ensures that if we have up to 2GB, the v1 MMU can address the
1516          * highest memory.  This is important as command buffers may be
1517          * allocated outside of this limit.
1518          */
1519         gpu->memory_base = PHYS_OFFSET;
1520
1521         /* Map registers: */
1522         gpu->mmio = etnaviv_ioremap(pdev, NULL, dev_name(gpu->dev));
1523         if (IS_ERR(gpu->mmio))
1524                 return PTR_ERR(gpu->mmio);
1525
1526         /* Get Interrupt: */
1527         gpu->irq = platform_get_irq(pdev, 0);
1528         if (gpu->irq < 0) {
1529                 err = gpu->irq;
1530                 dev_err(dev, "failed to get irq: %d\n", err);
1531                 goto fail;
1532         }
1533
1534         err = devm_request_irq(&pdev->dev, gpu->irq, irq_handler, 0,
1535                                dev_name(gpu->dev), gpu);
1536         if (err) {
1537                 dev_err(dev, "failed to request IRQ%u: %d\n", gpu->irq, err);
1538                 goto fail;
1539         }
1540
1541         /* Get Clocks: */
1542         gpu->clk_bus = devm_clk_get(&pdev->dev, "bus");
1543         DBG("clk_bus: %p", gpu->clk_bus);
1544         if (IS_ERR(gpu->clk_bus))
1545                 gpu->clk_bus = NULL;
1546
1547         gpu->clk_core = devm_clk_get(&pdev->dev, "core");
1548         DBG("clk_core: %p", gpu->clk_core);
1549         if (IS_ERR(gpu->clk_core))
1550                 gpu->clk_core = NULL;
1551
1552         gpu->clk_shader = devm_clk_get(&pdev->dev, "shader");
1553         DBG("clk_shader: %p", gpu->clk_shader);
1554         if (IS_ERR(gpu->clk_shader))
1555                 gpu->clk_shader = NULL;
1556
1557         /* TODO: figure out max mapped size */
1558         dev_set_drvdata(dev, gpu);
1559
1560         /*
1561          * We treat the device as initially suspended.  The runtime PM
1562          * autosuspend delay is rather arbitary: no measurements have
1563          * yet been performed to determine an appropriate value.
1564          */
1565         pm_runtime_use_autosuspend(gpu->dev);
1566         pm_runtime_set_autosuspend_delay(gpu->dev, 200);
1567         pm_runtime_enable(gpu->dev);
1568
1569         err = component_add(&pdev->dev, &gpu_ops);
1570         if (err < 0) {
1571                 dev_err(&pdev->dev, "failed to register component: %d\n", err);
1572                 goto fail;
1573         }
1574
1575         return 0;
1576
1577 fail:
1578         return err;
1579 }
1580
1581 static int etnaviv_gpu_platform_remove(struct platform_device *pdev)
1582 {
1583         component_del(&pdev->dev, &gpu_ops);
1584         pm_runtime_disable(&pdev->dev);
1585         return 0;
1586 }
1587
1588 #ifdef CONFIG_PM
1589 static int etnaviv_gpu_rpm_suspend(struct device *dev)
1590 {
1591         struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1592         u32 idle, mask;
1593
1594         /* If we have outstanding fences, we're not idle */
1595         if (gpu->completed_fence != gpu->active_fence)
1596                 return -EBUSY;
1597
1598         /* Check whether the hardware (except FE) is idle */
1599         mask = gpu->idle_mask & ~VIVS_HI_IDLE_STATE_FE;
1600         idle = gpu_read(gpu, VIVS_HI_IDLE_STATE) & mask;
1601         if (idle != mask)
1602                 return -EBUSY;
1603
1604         return etnaviv_gpu_hw_suspend(gpu);
1605 }
1606
1607 static int etnaviv_gpu_rpm_resume(struct device *dev)
1608 {
1609         struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1610         int ret;
1611
1612         ret = etnaviv_gpu_clk_enable(gpu);
1613         if (ret)
1614                 return ret;
1615
1616         /* Re-initialise the basic hardware state */
1617         if (gpu->drm && gpu->buffer) {
1618                 ret = etnaviv_gpu_hw_resume(gpu);
1619                 if (ret) {
1620                         etnaviv_gpu_clk_disable(gpu);
1621                         return ret;
1622                 }
1623         }
1624
1625         return 0;
1626 }
1627 #endif
1628
1629 static const struct dev_pm_ops etnaviv_gpu_pm_ops = {
1630         SET_RUNTIME_PM_OPS(etnaviv_gpu_rpm_suspend, etnaviv_gpu_rpm_resume,
1631                            NULL)
1632 };
1633
1634 struct platform_driver etnaviv_gpu_driver = {
1635         .driver = {
1636                 .name = "etnaviv-gpu",
1637                 .owner = THIS_MODULE,
1638                 .pm = &etnaviv_gpu_pm_ops,
1639                 .of_match_table = etnaviv_gpu_match,
1640         },
1641         .probe = etnaviv_gpu_platform_probe,
1642         .remove = etnaviv_gpu_platform_remove,
1643         .id_table = gpu_ids,
1644 };