drivers/gpu/drm/etnaviv/etnaviv_gpu.c

   1 /*
   2  * Copyright (C) 2015 Etnaviv Project
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License version 2 as published by
   6  * the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along with
  14  * this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #include <linux/component.h>
  18 #include <linux/fence.h>
  19 #include <linux/moduleparam.h>
  20 #include <linux/of_device.h>
  21 #include "etnaviv_dump.h"
  22 #include "etnaviv_gpu.h"
  23 #include "etnaviv_gem.h"
  24 #include "etnaviv_mmu.h"
  25 #include "etnaviv_iommu.h"
  26 #include "etnaviv_iommu_v2.h"
  27 #include "common.xml.h"
  28 #include "state.xml.h"
  29 #include "state_hi.xml.h"
  30 #include "cmdstream.xml.h"
  31
  32 static const struct platform_device_id gpu_ids[] = {
  33         { .name = "etnaviv-gpu,2d" },
  34         { },
  35 };
  36
  37 static bool etnaviv_dump_core = true;
  38 module_param_named(dump_core, etnaviv_dump_core, bool, 0600);
  39
  40 /*
  41  * Driver functions:
  42  */
  43
  44 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value)
  45 {
  46         switch (param) {
  47         case ETNAVIV_PARAM_GPU_MODEL:
  48                 *value = gpu->identity.model;
  49                 break;
  50
  51         case ETNAVIV_PARAM_GPU_REVISION:
  52                 *value = gpu->identity.revision;
  53                 break;
  54
  55         case ETNAVIV_PARAM_GPU_FEATURES_0:
  56                 *value = gpu->identity.features;
  57                 break;
  58
  59         case ETNAVIV_PARAM_GPU_FEATURES_1:
  60                 *value = gpu->identity.minor_features0;
  61                 break;
  62
  63         case ETNAVIV_PARAM_GPU_FEATURES_2:
  64                 *value = gpu->identity.minor_features1;
  65                 break;
  66
  67         case ETNAVIV_PARAM_GPU_FEATURES_3:
  68                 *value = gpu->identity.minor_features2;
  69                 break;
  70
  71         case ETNAVIV_PARAM_GPU_FEATURES_4:
  72                 *value = gpu->identity.minor_features3;
  73                 break;
  74
  75         case ETNAVIV_PARAM_GPU_STREAM_COUNT:
  76                 *value = gpu->identity.stream_count;
  77                 break;
  78
  79         case ETNAVIV_PARAM_GPU_REGISTER_MAX:
  80                 *value = gpu->identity.register_max;
  81                 break;
  82
  83         case ETNAVIV_PARAM_GPU_THREAD_COUNT:
  84                 *value = gpu->identity.thread_count;
  85                 break;
  86
  87         case ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE:
  88                 *value = gpu->identity.vertex_cache_size;
  89                 break;
  90
  91         case ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT:
  92                 *value = gpu->identity.shader_core_count;
  93                 break;
  94
  95         case ETNAVIV_PARAM_GPU_PIXEL_PIPES:
  96                 *value = gpu->identity.pixel_pipes;
  97                 break;
  98
  99         case ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE:
 100                 *value = gpu->identity.vertex_output_buffer_size;
 101                 break;
 102
 103         case ETNAVIV_PARAM_GPU_BUFFER_SIZE:
 104                 *value = gpu->identity.buffer_size;
 105                 break;
 106
 107         case ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT:
 108                 *value = gpu->identity.instruction_count;
 109                 break;
 110
 111         case ETNAVIV_PARAM_GPU_NUM_CONSTANTS:
 112                 *value = gpu->identity.num_constants;
 113                 break;
 114
 115         default:
 116                 DBG("%s: invalid param: %u", dev_name(gpu->dev), param);
 117                 return -EINVAL;
 118         }
 119
 120         return 0;
 121 }
 122
 123 static void etnaviv_hw_specs(struct etnaviv_gpu *gpu)
 124 {
 125         if (gpu->identity.minor_features0 &
 126             chipMinorFeatures0_MORE_MINOR_FEATURES) {
 127                 u32 specs[2];
 128
 129                 specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS);
 130                 specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2);
 131
 132                 gpu->identity.stream_count =
 133                         (specs[0] & VIVS_HI_CHIP_SPECS_STREAM_COUNT__MASK)
 134                                 >> VIVS_HI_CHIP_SPECS_STREAM_COUNT__SHIFT;
 135                 gpu->identity.register_max =
 136                         (specs[0] & VIVS_HI_CHIP_SPECS_REGISTER_MAX__MASK)
 137                                 >> VIVS_HI_CHIP_SPECS_REGISTER_MAX__SHIFT;
 138                 gpu->identity.thread_count =
 139                         (specs[0] & VIVS_HI_CHIP_SPECS_THREAD_COUNT__MASK)
 140                                 >> VIVS_HI_CHIP_SPECS_THREAD_COUNT__SHIFT;
 141                 gpu->identity.vertex_cache_size =
 142                         (specs[0] & VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE__MASK)
 143                                 >> VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE__SHIFT;
 144                 gpu->identity.shader_core_count =
 145                         (specs[0] & VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT__MASK)
 146                                 >> VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT__SHIFT;
 147                 gpu->identity.pixel_pipes =
 148                         (specs[0] & VIVS_HI_CHIP_SPECS_PIXEL_PIPES__MASK)
 149                                 >> VIVS_HI_CHIP_SPECS_PIXEL_PIPES__SHIFT;
 150                 gpu->identity.vertex_output_buffer_size =
 151                         (specs[0] & VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE__MASK)
 152                                 >> VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE__SHIFT;
 153
 154                 gpu->identity.buffer_size =
 155                         (specs[1] & VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE__MASK)
 156                                 >> VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE__SHIFT;
 157                 gpu->identity.instruction_count =
 158                         (specs[1] & VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT__MASK)
 159                                 >> VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT__SHIFT;
 160                 gpu->identity.num_constants =
 161                         (specs[1] & VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS__MASK)
 162                                 >> VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS__SHIFT;
 163         }
 164
 165         /* Fill in the stream count if not specified */
 166         if (gpu->identity.stream_count == 0) {
 167                 if (gpu->identity.model >= 0x1000)
 168                         gpu->identity.stream_count = 4;
 169                 else
 170                         gpu->identity.stream_count = 1;
 171         }
 172
 173         /* Convert the register max value */
 174         if (gpu->identity.register_max)
 175                 gpu->identity.register_max = 1 << gpu->identity.register_max;
 176         else if (gpu->identity.model == chipModel_GC400)
 177                 gpu->identity.register_max = 32;
 178         else
 179                 gpu->identity.register_max = 64;
 180
 181         /* Convert thread count */
 182         if (gpu->identity.thread_count)
 183                 gpu->identity.thread_count = 1 << gpu->identity.thread_count;
 184         else if (gpu->identity.model == chipModel_GC400)
 185                 gpu->identity.thread_count = 64;
 186         else if (gpu->identity.model == chipModel_GC500 ||
 187                  gpu->identity.model == chipModel_GC530)
 188                 gpu->identity.thread_count = 128;
 189         else
 190                 gpu->identity.thread_count = 256;
 191
 192         if (gpu->identity.vertex_cache_size == 0)
 193                 gpu->identity.vertex_cache_size = 8;
 194
 195         if (gpu->identity.shader_core_count == 0) {
 196                 if (gpu->identity.model >= 0x1000)
 197                         gpu->identity.shader_core_count = 2;
 198                 else
 199                         gpu->identity.shader_core_count = 1;
 200         }
 201
 202         if (gpu->identity.pixel_pipes == 0)
 203                 gpu->identity.pixel_pipes = 1;
 204
 205         /* Convert virtex buffer size */
 206         if (gpu->identity.vertex_output_buffer_size) {
 207                 gpu->identity.vertex_output_buffer_size =
 208                         1 << gpu->identity.vertex_output_buffer_size;
 209         } else if (gpu->identity.model == chipModel_GC400) {
 210                 if (gpu->identity.revision < 0x4000)
 211                         gpu->identity.vertex_output_buffer_size = 512;
 212                 else if (gpu->identity.revision < 0x4200)
 213                         gpu->identity.vertex_output_buffer_size = 256;
 214                 else
 215                         gpu->identity.vertex_output_buffer_size = 128;
 216         } else {
 217                 gpu->identity.vertex_output_buffer_size = 512;
 218         }
 219
 220         switch (gpu->identity.instruction_count) {
 221         case 0:
 222                 if ((gpu->identity.model == chipModel_GC2000 &&
 223                      gpu->identity.revision == 0x5108) ||
 224                     gpu->identity.model == chipModel_GC880)
 225                         gpu->identity.instruction_count = 512;
 226                 else
 227                         gpu->identity.instruction_count = 256;
 228                 break;
 229
 230         case 1:
 231                 gpu->identity.instruction_count = 1024;
 232                 break;
 233
 234         case 2:
 235                 gpu->identity.instruction_count = 2048;
 236                 break;
 237
 238         default:
 239                 gpu->identity.instruction_count = 256;
 240                 break;
 241         }
 242
 243         if (gpu->identity.num_constants == 0)
 244                 gpu->identity.num_constants = 168;
 245 }
 246
 247 static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)
 248 {
 249         u32 chipIdentity;
 250
 251         chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY);
 252
 253         /* Special case for older graphic cores. */
 254         if (((chipIdentity & VIVS_HI_CHIP_IDENTITY_FAMILY__MASK)
 255              >> VIVS_HI_CHIP_IDENTITY_FAMILY__SHIFT) ==  0x01) {
 256                 gpu->identity.model    = chipModel_GC500;
 257                 gpu->identity.revision =
 258                         (chipIdentity & VIVS_HI_CHIP_IDENTITY_REVISION__MASK)
 259                         >> VIVS_HI_CHIP_IDENTITY_REVISION__SHIFT;
 260         } else {
 261
 262                 gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL);
 263                 gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV);
 264
 265                 /*
 266                  * !!!! HACK ALERT !!!!
 267                  * Because people change device IDs without letting software
 268                  * know about it - here is the hack to make it all look the
 269                  * same.  Only for GC400 family.
 270                  */
 271                 if ((gpu->identity.model & 0xff00) == 0x0400 &&
 272                     gpu->identity.model != chipModel_GC420) {
 273                         gpu->identity.model = gpu->identity.model & 0x0400;
 274                 }
 275
 276                 /* Another special case */
 277                 if (gpu->identity.model == chipModel_GC300 &&
 278                     gpu->identity.revision == 0x2201) {
 279                         u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE);
 280                         u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME);
 281
 282                         if (chipDate == 0x20080814 && chipTime == 0x12051100) {
 283                                 /*
 284                                  * This IP has an ECO; put the correct
 285                                  * revision in it.
 286                                  */
 287                                 gpu->identity.revision = 0x1051;
 288                         }
 289                 }
 290         }
 291
 292         dev_info(gpu->dev, "model: GC%x, revision: %x\n",
 293                  gpu->identity.model, gpu->identity.revision);
 294
 295         gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE);
 296
 297         /* Disable fast clear on GC700. */
 298         if (gpu->identity.model == chipModel_GC700)
 299                 gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
 300
 301         if ((gpu->identity.model == chipModel_GC500 &&
 302              gpu->identity.revision < 2) ||
 303             (gpu->identity.model == chipModel_GC300 &&
 304              gpu->identity.revision < 0x2000)) {
 305
 306                 /*
 307                  * GC500 rev 1.x and GC300 rev < 2.0 doesn't have these
 308                  * registers.
 309                  */
 310                 gpu->identity.minor_features0 = 0;
 311                 gpu->identity.minor_features1 = 0;
 312                 gpu->identity.minor_features2 = 0;
 313                 gpu->identity.minor_features3 = 0;
 314         } else
 315                 gpu->identity.minor_features0 =
 316                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_0);
 317
 318         if (gpu->identity.minor_features0 &
 319             chipMinorFeatures0_MORE_MINOR_FEATURES) {
 320                 gpu->identity.minor_features1 =
 321                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_1);
 322                 gpu->identity.minor_features2 =
 323                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_2);
 324                 gpu->identity.minor_features3 =
 325                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_3);
 326         }
 327
 328         /* GC600 idle register reports zero bits where modules aren't present */
 329         if (gpu->identity.model == chipModel_GC600) {
 330                 gpu->idle_mask = VIVS_HI_IDLE_STATE_TX |
 331                                  VIVS_HI_IDLE_STATE_RA |
 332                                  VIVS_HI_IDLE_STATE_SE |
 333                                  VIVS_HI_IDLE_STATE_PA |
 334                                  VIVS_HI_IDLE_STATE_SH |
 335                                  VIVS_HI_IDLE_STATE_PE |
 336                                  VIVS_HI_IDLE_STATE_DE |
 337                                  VIVS_HI_IDLE_STATE_FE;
 338         } else {
 339                 gpu->idle_mask = ~VIVS_HI_IDLE_STATE_AXI_LP;
 340         }
 341
 342         etnaviv_hw_specs(gpu);
 343 }
 344
 345 static void etnaviv_gpu_load_clock(struct etnaviv_gpu *gpu, u32 clock)
 346 {
 347         gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock |
 348                   VIVS_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD);
 349         gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock);
 350 }
 351
 352 static int etnaviv_hw_reset(struct etnaviv_gpu *gpu)
 353 {
 354         u32 control, idle;
 355         unsigned long timeout;
 356         bool failed = true;
 357
 358         /* TODO
 359          *
 360          * - clock gating
 361          * - puls eater
 362          * - what about VG?
 363          */
 364
 365         /* We hope that the GPU resets in under one second */
 366         timeout = jiffies + msecs_to_jiffies(1000);
 367
 368         while (time_is_after_jiffies(timeout)) {
 369                 control = VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS |
 370                           VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(0x40);
 371
 372                 /* enable clock */
 373                 etnaviv_gpu_load_clock(gpu, control);
 374
 375                 /* Wait for stable clock.  Vivante's code waited for 1ms */
 376                 usleep_range(1000, 10000);
 377
 378                 /* isolate the GPU. */
 379                 control |= VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
 380                 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
 381
 382                 /* set soft reset. */
 383                 control |= VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
 384                 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
 385
 386                 /* wait for reset. */
 387                 msleep(1);
 388
 389                 /* reset soft reset bit. */
 390                 control &= ~VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
 391                 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
 392
 393                 /* reset GPU isolation. */
 394                 control &= ~VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
 395                 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
 396
 397                 /* read idle register. */
 398                 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
 399
 400                 /* try reseting again if FE it not idle */
 401                 if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) {
 402                         dev_dbg(gpu->dev, "FE is not idle\n");
 403                         continue;
 404                 }
 405
 406                 /* read reset register. */
 407                 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
 408
 409                 /* is the GPU idle? */
 410                 if (((control & VIVS_HI_CLOCK_CONTROL_IDLE_3D) == 0) ||
 411                     ((control & VIVS_HI_CLOCK_CONTROL_IDLE_2D) == 0)) {
 412                         dev_dbg(gpu->dev, "GPU is not idle\n");
 413                         continue;
 414                 }
 415
 416                 failed = false;
 417                 break;
 418         }
 419
 420         if (failed) {
 421                 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
 422                 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
 423
 424                 dev_err(gpu->dev, "GPU failed to reset: FE %sidle, 3D %sidle, 2D %sidle\n",
 425                         idle & VIVS_HI_IDLE_STATE_FE ? "" : "not ",
 426                         control & VIVS_HI_CLOCK_CONTROL_IDLE_3D ? "" : "not ",
 427                         control & VIVS_HI_CLOCK_CONTROL_IDLE_2D ? "" : "not ");
 428
 429                 return -EBUSY;
 430         }
 431
 432         /* We rely on the GPU running, so program the clock */
 433         control = VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS |
 434                   VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(0x40);
 435
 436         /* enable clock */
 437         etnaviv_gpu_load_clock(gpu, control);
 438
 439         return 0;
 440 }
 441
 442 static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu)
 443 {
 444         u16 prefetch;
 445
 446         if (gpu->identity.model == chipModel_GC320 &&
 447             gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400 &&
 448             (gpu->identity.revision == 0x5007 ||
 449              gpu->identity.revision == 0x5220)) {
 450                 u32 mc_memory_debug;
 451
 452                 mc_memory_debug = gpu_read(gpu, VIVS_MC_DEBUG_MEMORY) & ~0xff;
 453
 454                 if (gpu->identity.revision == 0x5007)
 455                         mc_memory_debug |= 0x0c;
 456                 else
 457                         mc_memory_debug |= 0x08;
 458
 459                 gpu_write(gpu, VIVS_MC_DEBUG_MEMORY, mc_memory_debug);
 460         }
 461
 462         /*
 463          * Update GPU AXI cache atttribute to "cacheable, no allocate".
 464          * This is necessary to prevent the iMX6 SoC locking up.
 465          */
 466         gpu_write(gpu, VIVS_HI_AXI_CONFIG,
 467                   VIVS_HI_AXI_CONFIG_AWCACHE(2) |
 468                   VIVS_HI_AXI_CONFIG_ARCACHE(2));
 469
 470         /* GC2000 rev 5108 needs a special bus config */
 471         if (gpu->identity.model == chipModel_GC2000 &&
 472             gpu->identity.revision == 0x5108) {
 473                 u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG);
 474                 bus_config &= ~(VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK |
 475                                 VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK);
 476                 bus_config |= VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG(1) |
 477                               VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG(0);
 478                 gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config);
 479         }
 480
 481         /* set base addresses */
 482         gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_RA, gpu->memory_base);
 483         gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_FE, gpu->memory_base);
 484         gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_TX, gpu->memory_base);
 485         gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PEZ, gpu->memory_base);
 486         gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PE, gpu->memory_base);
 487
 488         /* setup the MMU page table pointers */
 489         etnaviv_iommu_domain_restore(gpu, gpu->mmu->domain);
 490
 491         /* Start command processor */
 492         prefetch = etnaviv_buffer_init(gpu);
 493
 494         gpu_write(gpu, VIVS_HI_INTR_ENBL, ~0U);
 495         gpu_write(gpu, VIVS_FE_COMMAND_ADDRESS,
 496                   gpu->buffer->paddr - gpu->memory_base);
 497         gpu_write(gpu, VIVS_FE_COMMAND_CONTROL,
 498                   VIVS_FE_COMMAND_CONTROL_ENABLE |
 499                   VIVS_FE_COMMAND_CONTROL_PREFETCH(prefetch));
 500 }
 501
 502 int etnaviv_gpu_init(struct etnaviv_gpu *gpu)
 503 {
 504         int ret, i;
 505         struct iommu_domain *iommu;
 506         enum etnaviv_iommu_version version;
 507         bool mmuv2;
 508
 509         ret = pm_runtime_get_sync(gpu->dev);
 510         if (ret < 0)
 511                 return ret;
 512
 513         etnaviv_hw_identify(gpu);
 514
 515         if (gpu->identity.model == 0) {
 516                 dev_err(gpu->dev, "Unknown GPU model\n");
 517                 ret = -ENXIO;
 518                 goto fail;
 519         }
 520
 521         /* Exclude VG cores with FE2.0 */
 522         if (gpu->identity.features & chipFeatures_PIPE_VG &&
 523             gpu->identity.features & chipFeatures_FE20) {
 524                 dev_info(gpu->dev, "Ignoring GPU with VG and FE2.0\n");
 525                 ret = -ENXIO;
 526                 goto fail;
 527         }
 528
 529         ret = etnaviv_hw_reset(gpu);
 530         if (ret)
 531                 goto fail;
 532
 533         /* Setup IOMMU.. eventually we will (I think) do this once per context
 534          * and have separate page tables per context.  For now, to keep things
 535          * simple and to get something working, just use a single address space:
 536          */
 537         mmuv2 = gpu->identity.minor_features1 & chipMinorFeatures1_MMU_VERSION;
 538         dev_dbg(gpu->dev, "mmuv2: %d\n", mmuv2);
 539
 540         if (!mmuv2) {
 541                 iommu = etnaviv_iommu_domain_alloc(gpu);
 542                 version = ETNAVIV_IOMMU_V1;
 543         } else {
 544                 iommu = etnaviv_iommu_v2_domain_alloc(gpu);
 545                 version = ETNAVIV_IOMMU_V2;
 546         }
 547
 548         if (!iommu) {
 549                 ret = -ENOMEM;
 550                 goto fail;
 551         }
 552
 553         /* TODO: we will leak here memory - fix it! */
 554
 555         gpu->mmu = etnaviv_iommu_new(gpu, iommu, version);
 556         if (!gpu->mmu) {
 557                 ret = -ENOMEM;
 558                 goto fail;
 559         }
 560
 561         /* Create buffer: */
 562         gpu->buffer = etnaviv_gpu_cmdbuf_new(gpu, PAGE_SIZE, 0);
 563         if (!gpu->buffer) {
 564                 ret = -ENOMEM;
 565                 dev_err(gpu->dev, "could not create command buffer\n");
 566                 goto fail;
 567         }
 568         if (gpu->buffer->paddr - gpu->memory_base > 0x80000000) {
 569                 ret = -EINVAL;
 570                 dev_err(gpu->dev,
 571                         "command buffer outside valid memory window\n");
 572                 goto free_buffer;
 573         }
 574
 575         /* Setup event management */
 576         spin_lock_init(&gpu->event_spinlock);
 577         init_completion(&gpu->event_free);
 578         for (i = 0; i < ARRAY_SIZE(gpu->event); i++) {
 579                 gpu->event[i].used = false;
 580                 complete(&gpu->event_free);
 581         }
 582
 583         /* Now program the hardware */
 584         mutex_lock(&gpu->lock);
 585         etnaviv_gpu_hw_init(gpu);
 586         mutex_unlock(&gpu->lock);
 587
 588         pm_runtime_mark_last_busy(gpu->dev);
 589         pm_runtime_put_autosuspend(gpu->dev);
 590
 591         return 0;
 592
 593 free_buffer:
 594         etnaviv_gpu_cmdbuf_free(gpu->buffer);
 595         gpu->buffer = NULL;
 596 fail:
 597         pm_runtime_mark_last_busy(gpu->dev);
 598         pm_runtime_put_autosuspend(gpu->dev);
 599
 600         return ret;
 601 }
 602
 603 #ifdef CONFIG_DEBUG_FS
 604 struct dma_debug {
 605         u32 address[2];
 606         u32 state[2];
 607 };
 608
 609 static void verify_dma(struct etnaviv_gpu *gpu, struct dma_debug *debug)
 610 {
 611         u32 i;
 612
 613         debug->address[0] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
 614         debug->state[0]   = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
 615
 616         for (i = 0; i < 500; i++) {
 617                 debug->address[1] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
 618                 debug->state[1]   = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
 619
 620                 if (debug->address[0] != debug->address[1])
 621                         break;
 622
 623                 if (debug->state[0] != debug->state[1])
 624                         break;
 625         }
 626 }
 627
 628 int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m)
 629 {
 630         struct dma_debug debug;
 631         u32 dma_lo, dma_hi, axi, idle;
 632         int ret;
 633
 634         seq_printf(m, "%s Status:\n", dev_name(gpu->dev));
 635
 636         ret = pm_runtime_get_sync(gpu->dev);
 637         if (ret < 0)
 638                 return ret;
 639
 640         dma_lo = gpu_read(gpu, VIVS_FE_DMA_LOW);
 641         dma_hi = gpu_read(gpu, VIVS_FE_DMA_HIGH);
 642         axi = gpu_read(gpu, VIVS_HI_AXI_STATUS);
 643         idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
 644
 645         verify_dma(gpu, &debug);
 646
 647         seq_puts(m, "\tfeatures\n");
 648         seq_printf(m, "\t minor_features0: 0x%08x\n",
 649                    gpu->identity.minor_features0);
 650         seq_printf(m, "\t minor_features1: 0x%08x\n",
 651                    gpu->identity.minor_features1);
 652         seq_printf(m, "\t minor_features2: 0x%08x\n",
 653                    gpu->identity.minor_features2);
 654         seq_printf(m, "\t minor_features3: 0x%08x\n",
 655                    gpu->identity.minor_features3);
 656
 657         seq_puts(m, "\tspecs\n");
 658         seq_printf(m, "\t stream_count:  %d\n",
 659                         gpu->identity.stream_count);
 660         seq_printf(m, "\t register_max: %d\n",
 661                         gpu->identity.register_max);
 662         seq_printf(m, "\t thread_count: %d\n",
 663                         gpu->identity.thread_count);
 664         seq_printf(m, "\t vertex_cache_size: %d\n",
 665                         gpu->identity.vertex_cache_size);
 666         seq_printf(m, "\t shader_core_count: %d\n",
 667                         gpu->identity.shader_core_count);
 668         seq_printf(m, "\t pixel_pipes: %d\n",
 669                         gpu->identity.pixel_pipes);
 670         seq_printf(m, "\t vertex_output_buffer_size: %d\n",
 671                         gpu->identity.vertex_output_buffer_size);
 672         seq_printf(m, "\t buffer_size: %d\n",
 673                         gpu->identity.buffer_size);
 674         seq_printf(m, "\t instruction_count: %d\n",
 675                         gpu->identity.instruction_count);
 676         seq_printf(m, "\t num_constants: %d\n",
 677                         gpu->identity.num_constants);
 678
 679         seq_printf(m, "\taxi: 0x%08x\n", axi);
 680         seq_printf(m, "\tidle: 0x%08x\n", idle);
 681         idle |= ~gpu->idle_mask & ~VIVS_HI_IDLE_STATE_AXI_LP;
 682         if ((idle & VIVS_HI_IDLE_STATE_FE) == 0)
 683                 seq_puts(m, "\t FE is not idle\n");
 684         if ((idle & VIVS_HI_IDLE_STATE_DE) == 0)
 685                 seq_puts(m, "\t DE is not idle\n");
 686         if ((idle & VIVS_HI_IDLE_STATE_PE) == 0)
 687                 seq_puts(m, "\t PE is not idle\n");
 688         if ((idle & VIVS_HI_IDLE_STATE_SH) == 0)
 689                 seq_puts(m, "\t SH is not idle\n");
 690         if ((idle & VIVS_HI_IDLE_STATE_PA) == 0)
 691                 seq_puts(m, "\t PA is not idle\n");
 692         if ((idle & VIVS_HI_IDLE_STATE_SE) == 0)
 693                 seq_puts(m, "\t SE is not idle\n");
 694         if ((idle & VIVS_HI_IDLE_STATE_RA) == 0)
 695                 seq_puts(m, "\t RA is not idle\n");
 696         if ((idle & VIVS_HI_IDLE_STATE_TX) == 0)
 697                 seq_puts(m, "\t TX is not idle\n");
 698         if ((idle & VIVS_HI_IDLE_STATE_VG) == 0)
 699                 seq_puts(m, "\t VG is not idle\n");
 700         if ((idle & VIVS_HI_IDLE_STATE_IM) == 0)
 701                 seq_puts(m, "\t IM is not idle\n");
 702         if ((idle & VIVS_HI_IDLE_STATE_FP) == 0)
 703                 seq_puts(m, "\t FP is not idle\n");
 704         if ((idle & VIVS_HI_IDLE_STATE_TS) == 0)
 705                 seq_puts(m, "\t TS is not idle\n");
 706         if (idle & VIVS_HI_IDLE_STATE_AXI_LP)
 707                 seq_puts(m, "\t AXI low power mode\n");
 708
 709         if (gpu->identity.features & chipFeatures_DEBUG_MODE) {
 710                 u32 read0 = gpu_read(gpu, VIVS_MC_DEBUG_READ0);
 711                 u32 read1 = gpu_read(gpu, VIVS_MC_DEBUG_READ1);
 712                 u32 write = gpu_read(gpu, VIVS_MC_DEBUG_WRITE);
 713
 714                 seq_puts(m, "\tMC\n");
 715                 seq_printf(m, "\t read0: 0x%08x\n", read0);
 716                 seq_printf(m, "\t read1: 0x%08x\n", read1);
 717                 seq_printf(m, "\t write: 0x%08x\n", write);
 718         }
 719
 720         seq_puts(m, "\tDMA ");
 721
 722         if (debug.address[0] == debug.address[1] &&
 723             debug.state[0] == debug.state[1]) {
 724                 seq_puts(m, "seems to be stuck\n");
 725         } else if (debug.address[0] == debug.address[1]) {
 726                 seq_puts(m, "adress is constant\n");
 727         } else {
 728                 seq_puts(m, "is runing\n");
 729         }
 730
 731         seq_printf(m, "\t address 0: 0x%08x\n", debug.address[0]);
 732         seq_printf(m, "\t address 1: 0x%08x\n", debug.address[1]);
 733         seq_printf(m, "\t state 0: 0x%08x\n", debug.state[0]);
 734         seq_printf(m, "\t state 1: 0x%08x\n", debug.state[1]);
 735         seq_printf(m, "\t last fetch 64 bit word: 0x%08x 0x%08x\n",
 736                    dma_lo, dma_hi);
 737
 738         ret = 0;
 739
 740         pm_runtime_mark_last_busy(gpu->dev);
 741         pm_runtime_put_autosuspend(gpu->dev);
 742
 743         return ret;
 744 }
 745 #endif
 746
 747 /*
 748  * Power Management:
 749  */
 750 static int enable_clk(struct etnaviv_gpu *gpu)
 751 {
 752         if (gpu->clk_core)
 753                 clk_prepare_enable(gpu->clk_core);
 754         if (gpu->clk_shader)
 755                 clk_prepare_enable(gpu->clk_shader);
 756
 757         return 0;
 758 }
 759
 760 static int disable_clk(struct etnaviv_gpu *gpu)
 761 {
 762         if (gpu->clk_core)
 763                 clk_disable_unprepare(gpu->clk_core);
 764         if (gpu->clk_shader)
 765                 clk_disable_unprepare(gpu->clk_shader);
 766
 767         return 0;
 768 }
 769
 770 static int enable_axi(struct etnaviv_gpu *gpu)
 771 {
 772         if (gpu->clk_bus)
 773                 clk_prepare_enable(gpu->clk_bus);
 774
 775         return 0;
 776 }
 777
 778 static int disable_axi(struct etnaviv_gpu *gpu)
 779 {
 780         if (gpu->clk_bus)
 781                 clk_disable_unprepare(gpu->clk_bus);
 782
 783         return 0;
 784 }
 785
 786 /*
 787  * Hangcheck detection for locked gpu:
 788  */
 789 static void recover_worker(struct work_struct *work)
 790 {
 791         struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu,
 792                                                recover_work);
 793         unsigned long flags;
 794         unsigned int i;
 795
 796         dev_err(gpu->dev, "hangcheck recover!\n");
 797
 798         if (pm_runtime_get_sync(gpu->dev) < 0)
 799                 return;
 800
 801         mutex_lock(&gpu->lock);
 802
 803         /* Only catch the first event, or when manually re-armed */
 804         if (etnaviv_dump_core) {
 805                 etnaviv_core_dump(gpu);
 806                 etnaviv_dump_core = false;
 807         }
 808
 809         etnaviv_hw_reset(gpu);
 810
 811         /* complete all events, the GPU won't do it after the reset */
 812         spin_lock_irqsave(&gpu->event_spinlock, flags);
 813         for (i = 0; i < ARRAY_SIZE(gpu->event); i++) {
 814                 if (!gpu->event[i].used)
 815                         continue;
 816                 fence_signal(gpu->event[i].fence);
 817                 gpu->event[i].fence = NULL;
 818                 gpu->event[i].used = false;
 819                 complete(&gpu->event_free);
 820                 /*
 821                  * Decrement the PM count for each stuck event. This is safe
 822                  * even in atomic context as we use ASYNC RPM here.
 823                  */
 824                 pm_runtime_put_autosuspend(gpu->dev);
 825         }
 826         spin_unlock_irqrestore(&gpu->event_spinlock, flags);
 827         gpu->completed_fence = gpu->active_fence;
 828
 829         etnaviv_gpu_hw_init(gpu);
 830         gpu->switch_context = true;
 831
 832         mutex_unlock(&gpu->lock);
 833         pm_runtime_mark_last_busy(gpu->dev);
 834         pm_runtime_put_autosuspend(gpu->dev);
 835
 836         /* Retire the buffer objects in a work */
 837         etnaviv_queue_work(gpu->drm, &gpu->retire_work);
 838 }
 839
 840 static void hangcheck_timer_reset(struct etnaviv_gpu *gpu)
 841 {
 842         DBG("%s", dev_name(gpu->dev));
 843         mod_timer(&gpu->hangcheck_timer,
 844                   round_jiffies_up(jiffies + DRM_ETNAVIV_HANGCHECK_JIFFIES));
 845 }
 846
 847 static void hangcheck_handler(unsigned long data)
 848 {
 849         struct etnaviv_gpu *gpu = (struct etnaviv_gpu *)data;
 850         u32 fence = gpu->completed_fence;
 851         bool progress = false;
 852
 853         if (fence != gpu->hangcheck_fence) {
 854                 gpu->hangcheck_fence = fence;
 855                 progress = true;
 856         }
 857
 858         if (!progress) {
 859                 u32 dma_addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
 860                 int change = dma_addr - gpu->hangcheck_dma_addr;
 861
 862                 if (change < 0 || change > 16) {
 863                         gpu->hangcheck_dma_addr = dma_addr;
 864                         progress = true;
 865                 }
 866         }
 867
 868         if (!progress && fence_after(gpu->active_fence, fence)) {
 869                 dev_err(gpu->dev, "hangcheck detected gpu lockup!\n");
 870                 dev_err(gpu->dev, "     completed fence: %u\n", fence);
 871                 dev_err(gpu->dev, "     active fence: %u\n",
 872                         gpu->active_fence);
 873                 etnaviv_queue_work(gpu->drm, &gpu->recover_work);
 874         }
 875
 876         /* if still more pending work, reset the hangcheck timer: */
 877         if (fence_after(gpu->active_fence, gpu->hangcheck_fence))
 878                 hangcheck_timer_reset(gpu);
 879 }
 880
 881 static void hangcheck_disable(struct etnaviv_gpu *gpu)
 882 {
 883         del_timer_sync(&gpu->hangcheck_timer);
 884         cancel_work_sync(&gpu->recover_work);
 885 }
 886
 887 /* fence object management */
 888 struct etnaviv_fence {
 889         struct etnaviv_gpu *gpu;
 890         struct fence base;
 891 };
 892
 893 static inline struct etnaviv_fence *to_etnaviv_fence(struct fence *fence)
 894 {
 895         return container_of(fence, struct etnaviv_fence, base);
 896 }
 897
 898 static const char *etnaviv_fence_get_driver_name(struct fence *fence)
 899 {
 900         return "etnaviv";
 901 }
 902
 903 static const char *etnaviv_fence_get_timeline_name(struct fence *fence)
 904 {
 905         struct etnaviv_fence *f = to_etnaviv_fence(fence);
 906
 907         return dev_name(f->gpu->dev);
 908 }
 909
 910 static bool etnaviv_fence_enable_signaling(struct fence *fence)
 911 {
 912         return true;
 913 }
 914
 915 static bool etnaviv_fence_signaled(struct fence *fence)
 916 {
 917         struct etnaviv_fence *f = to_etnaviv_fence(fence);
 918
 919         return fence_completed(f->gpu, f->base.seqno);
 920 }
 921
 922 static void etnaviv_fence_release(struct fence *fence)
 923 {
 924         struct etnaviv_fence *f = to_etnaviv_fence(fence);
 925
 926         kfree_rcu(f, base.rcu);
 927 }
 928
 929 static const struct fence_ops etnaviv_fence_ops = {
 930         .get_driver_name = etnaviv_fence_get_driver_name,
 931         .get_timeline_name = etnaviv_fence_get_timeline_name,
 932         .enable_signaling = etnaviv_fence_enable_signaling,
 933         .signaled = etnaviv_fence_signaled,
 934         .wait = fence_default_wait,
 935         .release = etnaviv_fence_release,
 936 };
 937
 938 static struct fence *etnaviv_gpu_fence_alloc(struct etnaviv_gpu *gpu)
 939 {
 940         struct etnaviv_fence *f;
 941
 942         f = kzalloc(sizeof(*f), GFP_KERNEL);
 943         if (!f)
 944                 return NULL;
 945
 946         f->gpu = gpu;
 947
 948         fence_init(&f->base, &etnaviv_fence_ops, &gpu->fence_spinlock,
 949                    gpu->fence_context, ++gpu->next_fence);
 950
 951         return &f->base;
 952 }
 953
 954 int etnaviv_gpu_fence_sync_obj(struct etnaviv_gem_object *etnaviv_obj,
 955         unsigned int context, bool exclusive)
 956 {
 957         struct reservation_object *robj = etnaviv_obj->resv;
 958         struct reservation_object_list *fobj;
 959         struct fence *fence;
 960         int i, ret;
 961
 962         if (!exclusive) {
 963                 ret = reservation_object_reserve_shared(robj);
 964                 if (ret)
 965                         return ret;
 966         }
 967
 968         /*
 969          * If we have any shared fences, then the exclusive fence
 970          * should be ignored as it will already have been signalled.
 971          */
 972         fobj = reservation_object_get_list(robj);
 973         if (!fobj || fobj->shared_count == 0) {
 974                 /* Wait on any existing exclusive fence which isn't our own */
 975                 fence = reservation_object_get_excl(robj);
 976                 if (fence && fence->context != context) {
 977                         ret = fence_wait(fence, true);
 978                         if (ret)
 979                                 return ret;
 980                 }
 981         }
 982
 983         if (!exclusive || !fobj)
 984                 return 0;
 985
 986         for (i = 0; i < fobj->shared_count; i++) {
 987                 fence = rcu_dereference_protected(fobj->shared[i],
 988                                                 reservation_object_held(robj));
 989                 if (fence->context != context) {
 990                         ret = fence_wait(fence, true);
 991                         if (ret)
 992                                 return ret;
 993                 }
 994         }
 995
 996         return 0;
 997 }
 998
 999 /*
1000  * event management:
1001  */
1002
1003 static unsigned int event_alloc(struct etnaviv_gpu *gpu)
1004 {
1005         unsigned long ret, flags;
1006         unsigned int i, event = ~0U;
1007
1008         ret = wait_for_completion_timeout(&gpu->event_free,
1009                                           msecs_to_jiffies(10 * 10000));
1010         if (!ret)
1011                 dev_err(gpu->dev, "wait_for_completion_timeout failed");
1012
1013         spin_lock_irqsave(&gpu->event_spinlock, flags);
1014
1015         /* find first free event */
1016         for (i = 0; i < ARRAY_SIZE(gpu->event); i++) {
1017                 if (gpu->event[i].used == false) {
1018                         gpu->event[i].used = true;
1019                         event = i;
1020                         break;
1021                 }
1022         }
1023
1024         spin_unlock_irqrestore(&gpu->event_spinlock, flags);
1025
1026         return event;
1027 }
1028
1029 static void event_free(struct etnaviv_gpu *gpu, unsigned int event)
1030 {
1031         unsigned long flags;
1032
1033         spin_lock_irqsave(&gpu->event_spinlock, flags);
1034
1035         if (gpu->event[event].used == false) {
1036                 dev_warn(gpu->dev, "event %u is already marked as free",
1037                          event);
1038                 spin_unlock_irqrestore(&gpu->event_spinlock, flags);
1039         } else {
1040                 gpu->event[event].used = false;
1041                 spin_unlock_irqrestore(&gpu->event_spinlock, flags);
1042
1043                 complete(&gpu->event_free);
1044         }
1045 }
1046
1047 /*
1048  * Cmdstream submission/retirement:
1049  */
1050
1051 struct etnaviv_cmdbuf *etnaviv_gpu_cmdbuf_new(struct etnaviv_gpu *gpu, u32 size,
1052         size_t nr_bos)
1053 {
1054         struct etnaviv_cmdbuf *cmdbuf;
1055         size_t sz = size_vstruct(nr_bos, sizeof(cmdbuf->bo[0]),
1056                                  sizeof(*cmdbuf));
1057
1058         cmdbuf = kzalloc(sz, GFP_KERNEL);
1059         if (!cmdbuf)
1060                 return NULL;
1061
1062         cmdbuf->vaddr = dma_alloc_writecombine(gpu->dev, size, &cmdbuf->paddr,
1063                                                GFP_KERNEL);
1064         if (!cmdbuf->vaddr) {
1065                 kfree(cmdbuf);
1066                 return NULL;
1067         }
1068
1069         cmdbuf->gpu = gpu;
1070         cmdbuf->size = size;
1071
1072         return cmdbuf;
1073 }
1074
1075 void etnaviv_gpu_cmdbuf_free(struct etnaviv_cmdbuf *cmdbuf)
1076 {
1077         dma_free_writecombine(cmdbuf->gpu->dev, cmdbuf->size,
1078                               cmdbuf->vaddr, cmdbuf->paddr);
1079         kfree(cmdbuf);
1080 }
1081
1082 static void retire_worker(struct work_struct *work)
1083 {
1084         struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu,
1085                                                retire_work);
1086         u32 fence = gpu->completed_fence;
1087         struct etnaviv_cmdbuf *cmdbuf, *tmp;
1088         unsigned int i;
1089
1090         mutex_lock(&gpu->lock);
1091         list_for_each_entry_safe(cmdbuf, tmp, &gpu->active_cmd_list, node) {
1092                 if (!fence_is_signaled(cmdbuf->fence))
1093                         break;
1094
1095                 list_del(&cmdbuf->node);
1096                 fence_put(cmdbuf->fence);
1097
1098                 for (i = 0; i < cmdbuf->nr_bos; i++) {
1099                         struct etnaviv_gem_object *etnaviv_obj = cmdbuf->bo[i];
1100
1101                         atomic_dec(&etnaviv_obj->gpu_active);
1102                         /* drop the refcount taken in etnaviv_gpu_submit */
1103                         etnaviv_gem_put_iova(gpu, &etnaviv_obj->base);
1104                 }
1105
1106                 etnaviv_gpu_cmdbuf_free(cmdbuf);
1107         }
1108
1109         gpu->retired_fence = fence;
1110
1111         mutex_unlock(&gpu->lock);
1112
1113         wake_up_all(&gpu->fence_event);
1114 }
1115
1116 int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu,
1117         u32 fence, struct timespec *timeout)
1118 {
1119         int ret;
1120
1121         if (fence_after(fence, gpu->next_fence)) {
1122                 DRM_ERROR("waiting on invalid fence: %u (of %u)\n",
1123                                 fence, gpu->next_fence);
1124                 return -EINVAL;
1125         }
1126
1127         if (!timeout) {
1128                 /* No timeout was requested: just test for completion */
1129                 ret = fence_completed(gpu, fence) ? 0 : -EBUSY;
1130         } else {
1131                 unsigned long remaining = etnaviv_timeout_to_jiffies(timeout);
1132
1133                 ret = wait_event_interruptible_timeout(gpu->fence_event,
1134                                                 fence_completed(gpu, fence),
1135                                                 remaining);
1136                 if (ret == 0) {
1137                         DBG("timeout waiting for fence: %u (retired: %u completed: %u)",
1138                                 fence, gpu->retired_fence,
1139                                 gpu->completed_fence);
1140                         ret = -ETIMEDOUT;
1141                 } else if (ret != -ERESTARTSYS) {
1142                         ret = 0;
1143                 }
1144         }
1145
1146         return ret;
1147 }
1148
1149 /*
1150  * Wait for an object to become inactive.  This, on it's own, is not race
1151  * free: the object is moved by the retire worker off the active list, and
1152  * then the iova is put.  Moreover, the object could be re-submitted just
1153  * after we notice that it's become inactive.
1154  *
1155  * Although the retirement happens under the gpu lock, we don't want to hold
1156  * that lock in this function while waiting.
1157  */
1158 int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu,
1159         struct etnaviv_gem_object *etnaviv_obj, struct timespec *timeout)
1160 {
1161         unsigned long remaining;
1162         long ret;
1163
1164         if (!timeout)
1165                 return !is_active(etnaviv_obj) ? 0 : -EBUSY;
1166
1167         remaining = etnaviv_timeout_to_jiffies(timeout);
1168
1169         ret = wait_event_interruptible_timeout(gpu->fence_event,
1170                                                !is_active(etnaviv_obj),
1171                                                remaining);
1172         if (ret > 0) {
1173                 struct etnaviv_drm_private *priv = gpu->drm->dev_private;
1174
1175                 /* Synchronise with the retire worker */
1176                 flush_workqueue(priv->wq);
1177                 return 0;
1178         } else if (ret == -ERESTARTSYS) {
1179                 return -ERESTARTSYS;
1180         } else {
1181                 return -ETIMEDOUT;
1182         }
1183 }
1184
1185 int etnaviv_gpu_pm_get_sync(struct etnaviv_gpu *gpu)
1186 {
1187         return pm_runtime_get_sync(gpu->dev);
1188 }
1189
1190 void etnaviv_gpu_pm_put(struct etnaviv_gpu *gpu)
1191 {
1192         pm_runtime_mark_last_busy(gpu->dev);
1193         pm_runtime_put_autosuspend(gpu->dev);
1194 }
1195
1196 /* add bo's to gpu's ring, and kick gpu: */
1197 int etnaviv_gpu_submit(struct etnaviv_gpu *gpu,
1198         struct etnaviv_gem_submit *submit, struct etnaviv_cmdbuf *cmdbuf)
1199 {
1200         struct fence *fence;
1201         unsigned int event, i;
1202         int ret;
1203
1204         ret = etnaviv_gpu_pm_get_sync(gpu);
1205         if (ret < 0)
1206                 return ret;
1207
1208         mutex_lock(&gpu->lock);
1209
1210         /*
1211          * TODO
1212          *
1213          * - flush
1214          * - data endian
1215          * - prefetch
1216          *
1217          */
1218
1219         event = event_alloc(gpu);
1220         if (unlikely(event == ~0U)) {
1221                 DRM_ERROR("no free event\n");
1222                 ret = -EBUSY;
1223                 goto out_unlock;
1224         }
1225
1226         fence = etnaviv_gpu_fence_alloc(gpu);
1227         if (!fence) {
1228                 event_free(gpu, event);
1229                 ret = -ENOMEM;
1230                 goto out_unlock;
1231         }
1232
1233         gpu->event[event].fence = fence;
1234         submit->fence = fence->seqno;
1235         gpu->active_fence = submit->fence;
1236
1237         if (gpu->lastctx != cmdbuf->ctx) {
1238                 gpu->mmu->need_flush = true;
1239                 gpu->switch_context = true;
1240                 gpu->lastctx = cmdbuf->ctx;
1241         }
1242
1243         etnaviv_buffer_queue(gpu, event, cmdbuf);
1244
1245         cmdbuf->fence = fence;
1246         list_add_tail(&cmdbuf->node, &gpu->active_cmd_list);
1247
1248         /* We're committed to adding this command buffer, hold a PM reference */
1249         pm_runtime_get_noresume(gpu->dev);
1250
1251         for (i = 0; i < submit->nr_bos; i++) {
1252                 struct etnaviv_gem_object *etnaviv_obj = submit->bos[i].obj;
1253                 u32 iova;
1254
1255                 /* Each cmdbuf takes a refcount on the iova */
1256                 etnaviv_gem_get_iova(gpu, &etnaviv_obj->base, &iova);
1257                 cmdbuf->bo[i] = etnaviv_obj;
1258                 atomic_inc(&etnaviv_obj->gpu_active);
1259
1260                 if (submit->bos[i].flags & ETNA_SUBMIT_BO_WRITE)
1261                         reservation_object_add_excl_fence(etnaviv_obj->resv,
1262                                                           fence);
1263                 else
1264                         reservation_object_add_shared_fence(etnaviv_obj->resv,
1265                                                             fence);
1266         }
1267         cmdbuf->nr_bos = submit->nr_bos;
1268         hangcheck_timer_reset(gpu);
1269         ret = 0;
1270
1271 out_unlock:
1272         mutex_unlock(&gpu->lock);
1273
1274         etnaviv_gpu_pm_put(gpu);
1275
1276         return ret;
1277 }
1278
1279 /*
1280  * Init/Cleanup:
1281  */
1282 static irqreturn_t irq_handler(int irq, void *data)
1283 {
1284         struct etnaviv_gpu *gpu = data;
1285         irqreturn_t ret = IRQ_NONE;
1286
1287         u32 intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE);
1288
1289         if (intr != 0) {
1290                 int event;
1291
1292                 pm_runtime_mark_last_busy(gpu->dev);
1293
1294                 dev_dbg(gpu->dev, "intr 0x%08x\n", intr);
1295
1296                 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR) {
1297                         dev_err(gpu->dev, "AXI bus error\n");
1298                         intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR;
1299                 }
1300
1301                 while ((event = ffs(intr)) != 0) {
1302                         struct fence *fence;
1303
1304                         event -= 1;
1305
1306                         intr &= ~(1 << event);
1307
1308                         dev_dbg(gpu->dev, "event %u\n", event);
1309
1310                         fence = gpu->event[event].fence;
1311                         gpu->event[event].fence = NULL;
1312                         fence_signal(fence);
1313
1314                         /*
1315                          * Events can be processed out of order.  Eg,
1316                          * - allocate and queue event 0
1317                          * - allocate event 1
1318                          * - event 0 completes, we process it
1319                          * - allocate and queue event 0
1320                          * - event 1 and event 0 complete
1321                          * we can end up processing event 0 first, then 1.
1322                          */
1323                         if (fence_after(fence->seqno, gpu->completed_fence))
1324                                 gpu->completed_fence = fence->seqno;
1325
1326                         event_free(gpu, event);
1327
1328                         /*
1329                          * We need to balance the runtime PM count caused by
1330                          * each submission.  Upon submission, we increment
1331                          * the runtime PM counter, and allocate one event.
1332                          * So here, we put the runtime PM count for each
1333                          * completed event.
1334                          */
1335                         pm_runtime_put_autosuspend(gpu->dev);
1336                 }
1337
1338                 /* Retire the buffer objects in a work */
1339                 etnaviv_queue_work(gpu->drm, &gpu->retire_work);
1340
1341                 ret = IRQ_HANDLED;
1342         }
1343
1344         return ret;
1345 }
1346
1347 static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu)
1348 {
1349         int ret;
1350
1351         ret = enable_clk(gpu);
1352         if (ret)
1353                 return ret;
1354
1355         ret = enable_axi(gpu);
1356         if (ret) {
1357                 disable_clk(gpu);
1358                 return ret;
1359         }
1360
1361         return 0;
1362 }
1363
1364 static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu)
1365 {
1366         int ret;
1367
1368         ret = disable_axi(gpu);
1369         if (ret)
1370                 return ret;
1371
1372         ret = disable_clk(gpu);
1373         if (ret)
1374                 return ret;
1375
1376         return 0;
1377 }
1378
1379 static int etnaviv_gpu_hw_suspend(struct etnaviv_gpu *gpu)
1380 {
1381         if (gpu->buffer) {
1382                 unsigned long timeout;
1383
1384                 /* Replace the last WAIT with END */
1385                 etnaviv_buffer_end(gpu);
1386
1387                 /*
1388                  * We know that only the FE is busy here, this should
1389                  * happen quickly (as the WAIT is only 200 cycles).  If
1390                  * we fail, just warn and continue.
1391                  */
1392                 timeout = jiffies + msecs_to_jiffies(100);
1393                 do {
1394                         u32 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
1395
1396                         if ((idle & gpu->idle_mask) == gpu->idle_mask)
1397                                 break;
1398
1399                         if (time_is_before_jiffies(timeout)) {
1400                                 dev_warn(gpu->dev,
1401                                          "timed out waiting for idle: idle=0x%x\n",
1402                                          idle);
1403                                 break;
1404                         }
1405
1406                         udelay(5);
1407                 } while (1);
1408         }
1409
1410         return etnaviv_gpu_clk_disable(gpu);
1411 }
1412
1413 #ifdef CONFIG_PM
1414 static int etnaviv_gpu_hw_resume(struct etnaviv_gpu *gpu)
1415 {
1416         u32 clock;
1417         int ret;
1418
1419         ret = mutex_lock_killable(&gpu->lock);
1420         if (ret)
1421                 return ret;
1422
1423         clock = VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS |
1424                 VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(0x40);
1425
1426         etnaviv_gpu_load_clock(gpu, clock);
1427         etnaviv_gpu_hw_init(gpu);
1428
1429         gpu->switch_context = true;
1430
1431         mutex_unlock(&gpu->lock);
1432
1433         return 0;
1434 }
1435 #endif
1436
1437 static int etnaviv_gpu_bind(struct device *dev, struct device *master,
1438         void *data)
1439 {
1440         struct drm_device *drm = data;
1441         struct etnaviv_drm_private *priv = drm->dev_private;
1442         struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1443         int ret;
1444
1445 #ifdef CONFIG_PM
1446         ret = pm_runtime_get_sync(gpu->dev);
1447 #else
1448         ret = etnaviv_gpu_clk_enable(gpu);
1449 #endif
1450         if (ret < 0)
1451                 return ret;
1452
1453         gpu->drm = drm;
1454         gpu->fence_context = fence_context_alloc(1);
1455         spin_lock_init(&gpu->fence_spinlock);
1456
1457         INIT_LIST_HEAD(&gpu->active_cmd_list);
1458         INIT_WORK(&gpu->retire_work, retire_worker);
1459         INIT_WORK(&gpu->recover_work, recover_worker);
1460         init_waitqueue_head(&gpu->fence_event);
1461
1462         setup_timer(&gpu->hangcheck_timer, hangcheck_handler,
1463                         (unsigned long)gpu);
1464
1465         priv->gpu[priv->num_gpus++] = gpu;
1466
1467         pm_runtime_mark_last_busy(gpu->dev);
1468         pm_runtime_put_autosuspend(gpu->dev);
1469
1470         return 0;
1471 }
1472
1473 static void etnaviv_gpu_unbind(struct device *dev, struct device *master,
1474         void *data)
1475 {
1476         struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1477
1478         DBG("%s", dev_name(gpu->dev));
1479
1480         hangcheck_disable(gpu);
1481
1482 #ifdef CONFIG_PM
1483         pm_runtime_get_sync(gpu->dev);
1484         pm_runtime_put_sync_suspend(gpu->dev);
1485 #else
1486         etnaviv_gpu_hw_suspend(gpu);
1487 #endif
1488
1489         if (gpu->buffer) {
1490                 etnaviv_gpu_cmdbuf_free(gpu->buffer);
1491                 gpu->buffer = NULL;
1492         }
1493
1494         if (gpu->mmu) {
1495                 etnaviv_iommu_destroy(gpu->mmu);
1496                 gpu->mmu = NULL;
1497         }
1498
1499         gpu->drm = NULL;
1500 }
1501
1502 static const struct component_ops gpu_ops = {
1503         .bind = etnaviv_gpu_bind,
1504         .unbind = etnaviv_gpu_unbind,
1505 };
1506
1507 static const struct of_device_id etnaviv_gpu_match[] = {
1508         {
1509                 .compatible = "vivante,gc"
1510         },
1511         { /* sentinel */ }
1512 };
1513
1514 static int etnaviv_gpu_platform_probe(struct platform_device *pdev)
1515 {
1516         struct device *dev = &pdev->dev;
1517         struct etnaviv_gpu *gpu;
1518         int err = 0;
1519
1520         gpu = devm_kzalloc(dev, sizeof(*gpu), GFP_KERNEL);
1521         if (!gpu)
1522                 return -ENOMEM;
1523
1524         gpu->dev = &pdev->dev;
1525         mutex_init(&gpu->lock);
1526
1527         /*
1528          * Set the GPU base address to the start of physical memory.  This
1529          * ensures that if we have up to 2GB, the v1 MMU can address the
1530          * highest memory.  This is important as command buffers may be
1531          * allocated outside of this limit.
1532          */
1533         gpu->memory_base = PHYS_OFFSET;
1534
1535         /* Map registers: */
1536         gpu->mmio = etnaviv_ioremap(pdev, NULL, dev_name(gpu->dev));
1537         if (IS_ERR(gpu->mmio))
1538                 return PTR_ERR(gpu->mmio);
1539
1540         /* Get Interrupt: */
1541         gpu->irq = platform_get_irq(pdev, 0);
1542         if (gpu->irq < 0) {
1543                 err = gpu->irq;
1544                 dev_err(dev, "failed to get irq: %d\n", err);
1545                 goto fail;
1546         }
1547
1548         err = devm_request_irq(&pdev->dev, gpu->irq, irq_handler, 0,
1549                                dev_name(gpu->dev), gpu);
1550         if (err) {
1551                 dev_err(dev, "failed to request IRQ%u: %d\n", gpu->irq, err);
1552                 goto fail;
1553         }
1554
1555         /* Get Clocks: */
1556         gpu->clk_bus = devm_clk_get(&pdev->dev, "bus");
1557         DBG("clk_bus: %p", gpu->clk_bus);
1558         if (IS_ERR(gpu->clk_bus))
1559                 gpu->clk_bus = NULL;
1560
1561         gpu->clk_core = devm_clk_get(&pdev->dev, "core");
1562         DBG("clk_core: %p", gpu->clk_core);
1563         if (IS_ERR(gpu->clk_core))
1564                 gpu->clk_core = NULL;
1565
1566         gpu->clk_shader = devm_clk_get(&pdev->dev, "shader");
1567         DBG("clk_shader: %p", gpu->clk_shader);
1568         if (IS_ERR(gpu->clk_shader))
1569                 gpu->clk_shader = NULL;
1570
1571         /* TODO: figure out max mapped size */
1572         dev_set_drvdata(dev, gpu);
1573
1574         /*
1575          * We treat the device as initially suspended.  The runtime PM
1576          * autosuspend delay is rather arbitary: no measurements have
1577          * yet been performed to determine an appropriate value.
1578          */
1579         pm_runtime_use_autosuspend(gpu->dev);
1580         pm_runtime_set_autosuspend_delay(gpu->dev, 200);
1581         pm_runtime_enable(gpu->dev);
1582
1583         err = component_add(&pdev->dev, &gpu_ops);
1584         if (err < 0) {
1585                 dev_err(&pdev->dev, "failed to register component: %d\n", err);
1586                 goto fail;
1587         }
1588
1589         return 0;
1590
1591 fail:
1592         return err;
1593 }
1594
1595 static int etnaviv_gpu_platform_remove(struct platform_device *pdev)
1596 {
1597         component_del(&pdev->dev, &gpu_ops);
1598         pm_runtime_disable(&pdev->dev);
1599         return 0;
1600 }
1601
1602 #ifdef CONFIG_PM
1603 static int etnaviv_gpu_rpm_suspend(struct device *dev)
1604 {
1605         struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1606         u32 idle, mask;
1607
1608         /* If we have outstanding fences, we're not idle */
1609         if (gpu->completed_fence != gpu->active_fence)
1610                 return -EBUSY;
1611
1612         /* Check whether the hardware (except FE) is idle */
1613         mask = gpu->idle_mask & ~VIVS_HI_IDLE_STATE_FE;
1614         idle = gpu_read(gpu, VIVS_HI_IDLE_STATE) & mask;
1615         if (idle != mask)
1616                 return -EBUSY;
1617
1618         return etnaviv_gpu_hw_suspend(gpu);
1619 }
1620
1621 static int etnaviv_gpu_rpm_resume(struct device *dev)
1622 {
1623         struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1624         int ret;
1625
1626         ret = etnaviv_gpu_clk_enable(gpu);
1627         if (ret)
1628                 return ret;
1629
1630         /* Re-initialise the basic hardware state */
1631         if (gpu->drm && gpu->buffer) {
1632                 ret = etnaviv_gpu_hw_resume(gpu);
1633                 if (ret) {
1634                         etnaviv_gpu_clk_disable(gpu);
1635                         return ret;
1636                 }
1637         }
1638
1639         return 0;
1640 }
1641 #endif
1642
1643 static const struct dev_pm_ops etnaviv_gpu_pm_ops = {
1644         SET_RUNTIME_PM_OPS(etnaviv_gpu_rpm_suspend, etnaviv_gpu_rpm_resume,
1645                            NULL)
1646 };
1647
1648 struct platform_driver etnaviv_gpu_driver = {
1649         .driver = {
1650                 .name = "etnaviv-gpu",
1651                 .owner = THIS_MODULE,
1652                 .pm = &etnaviv_gpu_pm_ops,
1653                 .of_match_table = etnaviv_gpu_match,
1654         },
1655         .probe = etnaviv_gpu_platform_probe,
1656         .remove = etnaviv_gpu_platform_remove,
1657         .id_table = gpu_ids,
1658 };