drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32 #include <ttm/ttm_bo_api.h>
  33 #include <ttm/ttm_bo_driver.h>
  34 #include <ttm/ttm_placement.h>
  35 #include <ttm/ttm_module.h>
  36 #include <ttm/ttm_page_alloc.h>
  37 #include <drm/drmP.h>
  38 #include <drm/amdgpu_drm.h>
  39 #include <linux/seq_file.h>
  40 #include <linux/slab.h>
  41 #include <linux/swiotlb.h>
  42 #include <linux/swap.h>
  43 #include <linux/pagemap.h>
  44 #include <linux/debugfs.h>
  45 #include "amdgpu.h"
  46 #include "bif/bif_4_1_d.h"
  47
  48 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
  49
  50 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
  51 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev);
  52
  53 static struct amdgpu_device *amdgpu_get_adev(struct ttm_bo_device *bdev)
  54 {
  55         struct amdgpu_mman *mman;
  56         struct amdgpu_device *adev;
  57
  58         mman = container_of(bdev, struct amdgpu_mman, bdev);
  59         adev = container_of(mman, struct amdgpu_device, mman);
  60         return adev;
  61 }
  62
  63
  64 /*
  65  * Global memory.
  66  */
  67 static int amdgpu_ttm_mem_global_init(struct drm_global_reference *ref)
  68 {
  69         return ttm_mem_global_init(ref->object);
  70 }
  71
  72 static void amdgpu_ttm_mem_global_release(struct drm_global_reference *ref)
  73 {
  74         ttm_mem_global_release(ref->object);
  75 }
  76
  77 static int amdgpu_ttm_global_init(struct amdgpu_device *adev)
  78 {
  79         struct drm_global_reference *global_ref;
  80         struct amdgpu_ring *ring;
  81         struct amd_sched_rq *rq;
  82         int r;
  83
  84         adev->mman.mem_global_referenced = false;
  85         global_ref = &adev->mman.mem_global_ref;
  86         global_ref->global_type = DRM_GLOBAL_TTM_MEM;
  87         global_ref->size = sizeof(struct ttm_mem_global);
  88         global_ref->init = &amdgpu_ttm_mem_global_init;
  89         global_ref->release = &amdgpu_ttm_mem_global_release;
  90         r = drm_global_item_ref(global_ref);
  91         if (r != 0) {
  92                 DRM_ERROR("Failed setting up TTM memory accounting "
  93                           "subsystem.\n");
  94                 return r;
  95         }
  96
  97         adev->mman.bo_global_ref.mem_glob =
  98                 adev->mman.mem_global_ref.object;
  99         global_ref = &adev->mman.bo_global_ref.ref;
 100         global_ref->global_type = DRM_GLOBAL_TTM_BO;
 101         global_ref->size = sizeof(struct ttm_bo_global);
 102         global_ref->init = &ttm_bo_global_init;
 103         global_ref->release = &ttm_bo_global_release;
 104         r = drm_global_item_ref(global_ref);
 105         if (r != 0) {
 106                 DRM_ERROR("Failed setting up TTM BO subsystem.\n");
 107                 drm_global_item_unref(&adev->mman.mem_global_ref);
 108                 return r;
 109         }
 110
 111         ring = adev->mman.buffer_funcs_ring;
 112         rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL];
 113         r = amd_sched_entity_init(&ring->sched, &adev->mman.entity,
 114                                   rq, amdgpu_sched_jobs);
 115         if (r != 0) {
 116                 DRM_ERROR("Failed setting up TTM BO move run queue.\n");
 117                 drm_global_item_unref(&adev->mman.mem_global_ref);
 118                 drm_global_item_unref(&adev->mman.bo_global_ref.ref);
 119                 return r;
 120         }
 121
 122         adev->mman.mem_global_referenced = true;
 123
 124         return 0;
 125 }
 126
 127 static void amdgpu_ttm_global_fini(struct amdgpu_device *adev)
 128 {
 129         if (adev->mman.mem_global_referenced) {
 130                 amd_sched_entity_fini(adev->mman.entity.sched,
 131                                       &adev->mman.entity);
 132                 drm_global_item_unref(&adev->mman.bo_global_ref.ref);
 133                 drm_global_item_unref(&adev->mman.mem_global_ref);
 134                 adev->mman.mem_global_referenced = false;
 135         }
 136 }
 137
 138 static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
 139 {
 140         return 0;
 141 }
 142
 143 static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
 144                                 struct ttm_mem_type_manager *man)
 145 {
 146         struct amdgpu_device *adev;
 147
 148         adev = amdgpu_get_adev(bdev);
 149
 150         switch (type) {
 151         case TTM_PL_SYSTEM:
 152                 /* System memory */
 153                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
 154                 man->available_caching = TTM_PL_MASK_CACHING;
 155                 man->default_caching = TTM_PL_FLAG_CACHED;
 156                 break;
 157         case TTM_PL_TT:
 158                 man->func = &ttm_bo_manager_func;
 159                 man->gpu_offset = adev->mc.gtt_start;
 160                 man->available_caching = TTM_PL_MASK_CACHING;
 161                 man->default_caching = TTM_PL_FLAG_CACHED;
 162                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
 163                 break;
 164         case TTM_PL_VRAM:
 165                 /* "On-card" video ram */
 166                 man->func = &ttm_bo_manager_func;
 167                 man->gpu_offset = adev->mc.vram_start;
 168                 man->flags = TTM_MEMTYPE_FLAG_FIXED |
 169                              TTM_MEMTYPE_FLAG_MAPPABLE;
 170                 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
 171                 man->default_caching = TTM_PL_FLAG_WC;
 172                 break;
 173         case AMDGPU_PL_GDS:
 174         case AMDGPU_PL_GWS:
 175         case AMDGPU_PL_OA:
 176                 /* On-chip GDS memory*/
 177                 man->func = &ttm_bo_manager_func;
 178                 man->gpu_offset = 0;
 179                 man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA;
 180                 man->available_caching = TTM_PL_FLAG_UNCACHED;
 181                 man->default_caching = TTM_PL_FLAG_UNCACHED;
 182                 break;
 183         default:
 184                 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
 185                 return -EINVAL;
 186         }
 187         return 0;
 188 }
 189
 190 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
 191                                 struct ttm_placement *placement)
 192 {
 193         struct amdgpu_bo *rbo;
 194         static struct ttm_place placements = {
 195                 .fpfn = 0,
 196                 .lpfn = 0,
 197                 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
 198         };
 199
 200         if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) {
 201                 placement->placement = &placements;
 202                 placement->busy_placement = &placements;
 203                 placement->num_placement = 1;
 204                 placement->num_busy_placement = 1;
 205                 return;
 206         }
 207         rbo = container_of(bo, struct amdgpu_bo, tbo);
 208         switch (bo->mem.mem_type) {
 209         case TTM_PL_VRAM:
 210                 if (rbo->adev->mman.buffer_funcs_ring->ready == false)
 211                         amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_CPU);
 212                 else
 213                         amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_GTT);
 214                 break;
 215         case TTM_PL_TT:
 216         default:
 217                 amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_CPU);
 218         }
 219         *placement = rbo->placement;
 220 }
 221
 222 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 223 {
 224         struct amdgpu_bo *rbo = container_of(bo, struct amdgpu_bo, tbo);
 225
 226         if (amdgpu_ttm_tt_get_usermm(bo->ttm))
 227                 return -EPERM;
 228         return drm_vma_node_verify_access(&rbo->gem_base.vma_node, filp);
 229 }
 230
 231 static void amdgpu_move_null(struct ttm_buffer_object *bo,
 232                              struct ttm_mem_reg *new_mem)
 233 {
 234         struct ttm_mem_reg *old_mem = &bo->mem;
 235
 236         BUG_ON(old_mem->mm_node != NULL);
 237         *old_mem = *new_mem;
 238         new_mem->mm_node = NULL;
 239 }
 240
 241 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 242                         bool evict, bool no_wait_gpu,
 243                         struct ttm_mem_reg *new_mem,
 244                         struct ttm_mem_reg *old_mem)
 245 {
 246         struct amdgpu_device *adev;
 247         struct amdgpu_ring *ring;
 248         uint64_t old_start, new_start;
 249         struct fence *fence;
 250         int r;
 251
 252         adev = amdgpu_get_adev(bo->bdev);
 253         ring = adev->mman.buffer_funcs_ring;
 254         old_start = old_mem->start << PAGE_SHIFT;
 255         new_start = new_mem->start << PAGE_SHIFT;
 256
 257         switch (old_mem->mem_type) {
 258         case TTM_PL_VRAM:
 259                 old_start += adev->mc.vram_start;
 260                 break;
 261         case TTM_PL_TT:
 262                 old_start += adev->mc.gtt_start;
 263                 break;
 264         default:
 265                 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
 266                 return -EINVAL;
 267         }
 268         switch (new_mem->mem_type) {
 269         case TTM_PL_VRAM:
 270                 new_start += adev->mc.vram_start;
 271                 break;
 272         case TTM_PL_TT:
 273                 new_start += adev->mc.gtt_start;
 274                 break;
 275         default:
 276                 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
 277                 return -EINVAL;
 278         }
 279         if (!ring->ready) {
 280                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 281                 return -EINVAL;
 282         }
 283
 284         BUILD_BUG_ON((PAGE_SIZE % AMDGPU_GPU_PAGE_SIZE) != 0);
 285
 286         r = amdgpu_copy_buffer(ring, old_start, new_start,
 287                                new_mem->num_pages * PAGE_SIZE, /* bytes */
 288                                bo->resv, &fence);
 289         /* FIXME: handle copy error */
 290         r = ttm_bo_move_accel_cleanup(bo, fence,
 291                                       evict, no_wait_gpu, new_mem);
 292         fence_put(fence);
 293         return r;
 294 }
 295
 296 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo,
 297                                 bool evict, bool interruptible,
 298                                 bool no_wait_gpu,
 299                                 struct ttm_mem_reg *new_mem)
 300 {
 301         struct amdgpu_device *adev;
 302         struct ttm_mem_reg *old_mem = &bo->mem;
 303         struct ttm_mem_reg tmp_mem;
 304         struct ttm_place placements;
 305         struct ttm_placement placement;
 306         int r;
 307
 308         adev = amdgpu_get_adev(bo->bdev);
 309         tmp_mem = *new_mem;
 310         tmp_mem.mm_node = NULL;
 311         placement.num_placement = 1;
 312         placement.placement = &placements;
 313         placement.num_busy_placement = 1;
 314         placement.busy_placement = &placements;
 315         placements.fpfn = 0;
 316         placements.lpfn = 0;
 317         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 318         r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
 319                              interruptible, no_wait_gpu);
 320         if (unlikely(r)) {
 321                 return r;
 322         }
 323
 324         r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
 325         if (unlikely(r)) {
 326                 goto out_cleanup;
 327         }
 328
 329         r = ttm_tt_bind(bo->ttm, &tmp_mem);
 330         if (unlikely(r)) {
 331                 goto out_cleanup;
 332         }
 333         r = amdgpu_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem);
 334         if (unlikely(r)) {
 335                 goto out_cleanup;
 336         }
 337         r = ttm_bo_move_ttm(bo, true, no_wait_gpu, new_mem);
 338 out_cleanup:
 339         ttm_bo_mem_put(bo, &tmp_mem);
 340         return r;
 341 }
 342
 343 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo,
 344                                 bool evict, bool interruptible,
 345                                 bool no_wait_gpu,
 346                                 struct ttm_mem_reg *new_mem)
 347 {
 348         struct amdgpu_device *adev;
 349         struct ttm_mem_reg *old_mem = &bo->mem;
 350         struct ttm_mem_reg tmp_mem;
 351         struct ttm_placement placement;
 352         struct ttm_place placements;
 353         int r;
 354
 355         adev = amdgpu_get_adev(bo->bdev);
 356         tmp_mem = *new_mem;
 357         tmp_mem.mm_node = NULL;
 358         placement.num_placement = 1;
 359         placement.placement = &placements;
 360         placement.num_busy_placement = 1;
 361         placement.busy_placement = &placements;
 362         placements.fpfn = 0;
 363         placements.lpfn = 0;
 364         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 365         r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
 366                              interruptible, no_wait_gpu);
 367         if (unlikely(r)) {
 368                 return r;
 369         }
 370         r = ttm_bo_move_ttm(bo, true, no_wait_gpu, &tmp_mem);
 371         if (unlikely(r)) {
 372                 goto out_cleanup;
 373         }
 374         r = amdgpu_move_blit(bo, true, no_wait_gpu, new_mem, old_mem);
 375         if (unlikely(r)) {
 376                 goto out_cleanup;
 377         }
 378 out_cleanup:
 379         ttm_bo_mem_put(bo, &tmp_mem);
 380         return r;
 381 }
 382
 383 static int amdgpu_bo_move(struct ttm_buffer_object *bo,
 384                         bool evict, bool interruptible,
 385                         bool no_wait_gpu,
 386                         struct ttm_mem_reg *new_mem)
 387 {
 388         struct amdgpu_device *adev;
 389         struct amdgpu_bo *abo;
 390         struct ttm_mem_reg *old_mem = &bo->mem;
 391         int r;
 392
 393         /* Can't move a pinned BO */
 394         abo = container_of(bo, struct amdgpu_bo, tbo);
 395         if (WARN_ON_ONCE(abo->pin_count > 0))
 396                 return -EINVAL;
 397
 398         adev = amdgpu_get_adev(bo->bdev);
 399         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
 400                 amdgpu_move_null(bo, new_mem);
 401                 return 0;
 402         }
 403         if ((old_mem->mem_type == TTM_PL_TT &&
 404              new_mem->mem_type == TTM_PL_SYSTEM) ||
 405             (old_mem->mem_type == TTM_PL_SYSTEM &&
 406              new_mem->mem_type == TTM_PL_TT)) {
 407                 /* bind is enough */
 408                 amdgpu_move_null(bo, new_mem);
 409                 return 0;
 410         }
 411         if (adev->mman.buffer_funcs == NULL ||
 412             adev->mman.buffer_funcs_ring == NULL ||
 413             !adev->mman.buffer_funcs_ring->ready) {
 414                 /* use memcpy */
 415                 goto memcpy;
 416         }
 417
 418         if (old_mem->mem_type == TTM_PL_VRAM &&
 419             new_mem->mem_type == TTM_PL_SYSTEM) {
 420                 r = amdgpu_move_vram_ram(bo, evict, interruptible,
 421                                         no_wait_gpu, new_mem);
 422         } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
 423                    new_mem->mem_type == TTM_PL_VRAM) {
 424                 r = amdgpu_move_ram_vram(bo, evict, interruptible,
 425                                             no_wait_gpu, new_mem);
 426         } else {
 427                 r = amdgpu_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem);
 428         }
 429
 430         if (r) {
 431 memcpy:
 432                 r = ttm_bo_move_memcpy(bo, evict, no_wait_gpu, new_mem);
 433                 if (r) {
 434                         return r;
 435                 }
 436         }
 437
 438         /* update statistics */
 439         atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
 440         return 0;
 441 }
 442
 443 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 444 {
 445         struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
 446         struct amdgpu_device *adev = amdgpu_get_adev(bdev);
 447
 448         mem->bus.addr = NULL;
 449         mem->bus.offset = 0;
 450         mem->bus.size = mem->num_pages << PAGE_SHIFT;
 451         mem->bus.base = 0;
 452         mem->bus.is_iomem = false;
 453         if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
 454                 return -EINVAL;
 455         switch (mem->mem_type) {
 456         case TTM_PL_SYSTEM:
 457                 /* system memory */
 458                 return 0;
 459         case TTM_PL_TT:
 460                 break;
 461         case TTM_PL_VRAM:
 462                 mem->bus.offset = mem->start << PAGE_SHIFT;
 463                 /* check if it's visible */
 464                 if ((mem->bus.offset + mem->bus.size) > adev->mc.visible_vram_size)
 465                         return -EINVAL;
 466                 mem->bus.base = adev->mc.aper_base;
 467                 mem->bus.is_iomem = true;
 468 #ifdef __alpha__
 469                 /*
 470                  * Alpha: use bus.addr to hold the ioremap() return,
 471                  * so we can modify bus.base below.
 472                  */
 473                 if (mem->placement & TTM_PL_FLAG_WC)
 474                         mem->bus.addr =
 475                                 ioremap_wc(mem->bus.base + mem->bus.offset,
 476                                            mem->bus.size);
 477                 else
 478                         mem->bus.addr =
 479                                 ioremap_nocache(mem->bus.base + mem->bus.offset,
 480                                                 mem->bus.size);
 481
 482                 /*
 483                  * Alpha: Use just the bus offset plus
 484                  * the hose/domain memory base for bus.base.
 485                  * It then can be used to build PTEs for VRAM
 486                  * access, as done in ttm_bo_vm_fault().
 487                  */
 488                 mem->bus.base = (mem->bus.base & 0x0ffffffffUL) +
 489                         adev->ddev->hose->dense_mem_base;
 490 #endif
 491                 break;
 492         default:
 493                 return -EINVAL;
 494         }
 495         return 0;
 496 }
 497
 498 static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 499 {
 500 }
 501
 502 /*
 503  * TTM backend functions.
 504  */
 505 struct amdgpu_ttm_gup_task_list {
 506         struct list_head        list;
 507         struct task_struct      *task;
 508 };
 509
 510 struct amdgpu_ttm_tt {
 511         struct ttm_dma_tt       ttm;
 512         struct amdgpu_device    *adev;
 513         u64                     offset;
 514         uint64_t                userptr;
 515         struct mm_struct        *usermm;
 516         uint32_t                userflags;
 517         spinlock_t              guptasklock;
 518         struct list_head        guptasks;
 519         atomic_t                mmu_invalidations;
 520 };
 521
 522 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages)
 523 {
 524         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 525         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 526         unsigned pinned = 0;
 527         int r;
 528
 529         if (gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) {
 530                 /* check that we only use anonymous memory
 531                    to prevent problems with writeback */
 532                 unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
 533                 struct vm_area_struct *vma;
 534
 535                 vma = find_vma(gtt->usermm, gtt->userptr);
 536                 if (!vma || vma->vm_file || vma->vm_end < end)
 537                         return -EPERM;
 538         }
 539
 540         do {
 541                 unsigned num_pages = ttm->num_pages - pinned;
 542                 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
 543                 struct page **p = pages + pinned;
 544                 struct amdgpu_ttm_gup_task_list guptask;
 545
 546                 guptask.task = current;
 547                 spin_lock(&gtt->guptasklock);
 548                 list_add(&guptask.list, &gtt->guptasks);
 549                 spin_unlock(&gtt->guptasklock);
 550
 551                 r = get_user_pages(userptr, num_pages, write, 0, p, NULL);
 552
 553                 spin_lock(&gtt->guptasklock);
 554                 list_del(&guptask.list);
 555                 spin_unlock(&gtt->guptasklock);
 556
 557                 if (r < 0)
 558                         goto release_pages;
 559
 560                 pinned += r;
 561
 562         } while (pinned < ttm->num_pages);
 563
 564         return 0;
 565
 566 release_pages:
 567         release_pages(pages, pinned, 0);
 568         return r;
 569 }
 570
 571 /* prepare the sg table with the user pages */
 572 static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
 573 {
 574         struct amdgpu_device *adev = amdgpu_get_adev(ttm->bdev);
 575         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 576         unsigned nents;
 577         int r;
 578
 579         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 580         enum dma_data_direction direction = write ?
 581                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 582
 583         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
 584                                       ttm->num_pages << PAGE_SHIFT,
 585                                       GFP_KERNEL);
 586         if (r)
 587                 goto release_sg;
 588
 589         r = -ENOMEM;
 590         nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 591         if (nents != ttm->sg->nents)
 592                 goto release_sg;
 593
 594         drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 595                                          gtt->ttm.dma_address, ttm->num_pages);
 596
 597         return 0;
 598
 599 release_sg:
 600         kfree(ttm->sg);
 601         return r;
 602 }
 603
 604 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
 605 {
 606         struct amdgpu_device *adev = amdgpu_get_adev(ttm->bdev);
 607         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 608         struct sg_page_iter sg_iter;
 609
 610         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 611         enum dma_data_direction direction = write ?
 612                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 613
 614         /* double check that we don't free the table twice */
 615         if (!ttm->sg->sgl)
 616                 return;
 617
 618         /* free the sg table and pages again */
 619         dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 620
 621         for_each_sg_page(ttm->sg->sgl, &sg_iter, ttm->sg->nents, 0) {
 622                 struct page *page = sg_page_iter_page(&sg_iter);
 623                 if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
 624                         set_page_dirty(page);
 625
 626                 mark_page_accessed(page);
 627                 put_page(page);
 628         }
 629
 630         sg_free_table(ttm->sg);
 631 }
 632
 633 static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
 634                                    struct ttm_mem_reg *bo_mem)
 635 {
 636         struct amdgpu_ttm_tt *gtt = (void*)ttm;
 637         uint32_t flags = amdgpu_ttm_tt_pte_flags(gtt->adev, ttm, bo_mem);
 638         int r;
 639
 640         if (gtt->userptr) {
 641                 r = amdgpu_ttm_tt_pin_userptr(ttm);
 642                 if (r) {
 643                         DRM_ERROR("failed to pin userptr\n");
 644                         return r;
 645                 }
 646         }
 647         gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT);
 648         if (!ttm->num_pages) {
 649                 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
 650                      ttm->num_pages, bo_mem, ttm);
 651         }
 652
 653         if (bo_mem->mem_type == AMDGPU_PL_GDS ||
 654             bo_mem->mem_type == AMDGPU_PL_GWS ||
 655             bo_mem->mem_type == AMDGPU_PL_OA)
 656                 return -EINVAL;
 657
 658         r = amdgpu_gart_bind(gtt->adev, gtt->offset, ttm->num_pages,
 659                 ttm->pages, gtt->ttm.dma_address, flags);
 660
 661         if (r) {
 662                 DRM_ERROR("failed to bind %lu pages at 0x%08X\n",
 663                           ttm->num_pages, (unsigned)gtt->offset);
 664                 return r;
 665         }
 666         return 0;
 667 }
 668
 669 static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
 670 {
 671         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 672
 673         /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
 674         if (gtt->adev->gart.ready)
 675                 amdgpu_gart_unbind(gtt->adev, gtt->offset, ttm->num_pages);
 676
 677         if (gtt->userptr)
 678                 amdgpu_ttm_tt_unpin_userptr(ttm);
 679
 680         return 0;
 681 }
 682
 683 static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm)
 684 {
 685         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 686
 687         ttm_dma_tt_fini(&gtt->ttm);
 688         kfree(gtt);
 689 }
 690
 691 static struct ttm_backend_func amdgpu_backend_func = {
 692         .bind = &amdgpu_ttm_backend_bind,
 693         .unbind = &amdgpu_ttm_backend_unbind,
 694         .destroy = &amdgpu_ttm_backend_destroy,
 695 };
 696
 697 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_bo_device *bdev,
 698                                     unsigned long size, uint32_t page_flags,
 699                                     struct page *dummy_read_page)
 700 {
 701         struct amdgpu_device *adev;
 702         struct amdgpu_ttm_tt *gtt;
 703
 704         adev = amdgpu_get_adev(bdev);
 705
 706         gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
 707         if (gtt == NULL) {
 708                 return NULL;
 709         }
 710         gtt->ttm.ttm.func = &amdgpu_backend_func;
 711         gtt->adev = adev;
 712         if (ttm_dma_tt_init(&gtt->ttm, bdev, size, page_flags, dummy_read_page)) {
 713                 kfree(gtt);
 714                 return NULL;
 715         }
 716         return &gtt->ttm.ttm;
 717 }
 718
 719 static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm)
 720 {
 721         struct amdgpu_device *adev;
 722         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 723         unsigned i;
 724         int r;
 725         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
 726
 727         if (ttm->state != tt_unpopulated)
 728                 return 0;
 729
 730         if (gtt && gtt->userptr) {
 731                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
 732                 if (!ttm->sg)
 733                         return -ENOMEM;
 734
 735                 ttm->page_flags |= TTM_PAGE_FLAG_SG;
 736                 ttm->state = tt_unbound;
 737                 return 0;
 738         }
 739
 740         if (slave && ttm->sg) {
 741                 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 742                                                  gtt->ttm.dma_address, ttm->num_pages);
 743                 ttm->state = tt_unbound;
 744                 return 0;
 745         }
 746
 747         adev = amdgpu_get_adev(ttm->bdev);
 748
 749 #ifdef CONFIG_SWIOTLB
 750         if (swiotlb_nr_tbl()) {
 751                 return ttm_dma_populate(&gtt->ttm, adev->dev);
 752         }
 753 #endif
 754
 755         r = ttm_pool_populate(ttm);
 756         if (r) {
 757                 return r;
 758         }
 759
 760         for (i = 0; i < ttm->num_pages; i++) {
 761                 gtt->ttm.dma_address[i] = pci_map_page(adev->pdev, ttm->pages[i],
 762                                                        0, PAGE_SIZE,
 763                                                        PCI_DMA_BIDIRECTIONAL);
 764                 if (pci_dma_mapping_error(adev->pdev, gtt->ttm.dma_address[i])) {
 765                         while (i--) {
 766                                 pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i],
 767                                                PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 768                                 gtt->ttm.dma_address[i] = 0;
 769                         }
 770                         ttm_pool_unpopulate(ttm);
 771                         return -EFAULT;
 772                 }
 773         }
 774         return 0;
 775 }
 776
 777 static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
 778 {
 779         struct amdgpu_device *adev;
 780         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 781         unsigned i;
 782         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
 783
 784         if (gtt && gtt->userptr) {
 785                 kfree(ttm->sg);
 786                 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
 787                 return;
 788         }
 789
 790         if (slave)
 791                 return;
 792
 793         adev = amdgpu_get_adev(ttm->bdev);
 794
 795 #ifdef CONFIG_SWIOTLB
 796         if (swiotlb_nr_tbl()) {
 797                 ttm_dma_unpopulate(&gtt->ttm, adev->dev);
 798                 return;
 799         }
 800 #endif
 801
 802         for (i = 0; i < ttm->num_pages; i++) {
 803                 if (gtt->ttm.dma_address[i]) {
 804                         pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i],
 805                                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 806                 }
 807         }
 808
 809         ttm_pool_unpopulate(ttm);
 810 }
 811
 812 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
 813                               uint32_t flags)
 814 {
 815         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 816
 817         if (gtt == NULL)
 818                 return -EINVAL;
 819
 820         gtt->userptr = addr;
 821         gtt->usermm = current->mm;
 822         gtt->userflags = flags;
 823         spin_lock_init(&gtt->guptasklock);
 824         INIT_LIST_HEAD(&gtt->guptasks);
 825         atomic_set(&gtt->mmu_invalidations, 0);
 826
 827         return 0;
 828 }
 829
 830 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
 831 {
 832         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 833
 834         if (gtt == NULL)
 835                 return NULL;
 836
 837         return gtt->usermm;
 838 }
 839
 840 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
 841                                   unsigned long end)
 842 {
 843         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 844         struct amdgpu_ttm_gup_task_list *entry;
 845         unsigned long size;
 846
 847         if (gtt == NULL || !gtt->userptr)
 848                 return false;
 849
 850         size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
 851         if (gtt->userptr > end || gtt->userptr + size <= start)
 852                 return false;
 853
 854         spin_lock(&gtt->guptasklock);
 855         list_for_each_entry(entry, &gtt->guptasks, list) {
 856                 if (entry->task == current) {
 857                         spin_unlock(&gtt->guptasklock);
 858                         return false;
 859                 }
 860         }
 861         spin_unlock(&gtt->guptasklock);
 862
 863         atomic_inc(&gtt->mmu_invalidations);
 864
 865         return true;
 866 }
 867
 868 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
 869                                        int *last_invalidated)
 870 {
 871         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 872         int prev_invalidated = *last_invalidated;
 873
 874         *last_invalidated = atomic_read(&gtt->mmu_invalidations);
 875         return prev_invalidated != *last_invalidated;
 876 }
 877
 878 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
 879 {
 880         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 881
 882         if (gtt == NULL)
 883                 return false;
 884
 885         return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 886 }
 887
 888 uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
 889                                  struct ttm_mem_reg *mem)
 890 {
 891         uint32_t flags = 0;
 892
 893         if (mem && mem->mem_type != TTM_PL_SYSTEM)
 894                 flags |= AMDGPU_PTE_VALID;
 895
 896         if (mem && mem->mem_type == TTM_PL_TT) {
 897                 flags |= AMDGPU_PTE_SYSTEM;
 898
 899                 if (ttm->caching_state == tt_cached)
 900                         flags |= AMDGPU_PTE_SNOOPED;
 901         }
 902
 903         if (adev->asic_type >= CHIP_TONGA)
 904                 flags |= AMDGPU_PTE_EXECUTABLE;
 905
 906         flags |= AMDGPU_PTE_READABLE;
 907
 908         if (!amdgpu_ttm_tt_is_readonly(ttm))
 909                 flags |= AMDGPU_PTE_WRITEABLE;
 910
 911         return flags;
 912 }
 913
 914 static struct ttm_bo_driver amdgpu_bo_driver = {
 915         .ttm_tt_create = &amdgpu_ttm_tt_create,
 916         .ttm_tt_populate = &amdgpu_ttm_tt_populate,
 917         .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
 918         .invalidate_caches = &amdgpu_invalidate_caches,
 919         .init_mem_type = &amdgpu_init_mem_type,
 920         .evict_flags = &amdgpu_evict_flags,
 921         .move = &amdgpu_bo_move,
 922         .verify_access = &amdgpu_verify_access,
 923         .move_notify = &amdgpu_bo_move_notify,
 924         .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
 925         .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
 926         .io_mem_free = &amdgpu_ttm_io_mem_free,
 927 };
 928
 929 int amdgpu_ttm_init(struct amdgpu_device *adev)
 930 {
 931         int r;
 932
 933         r = amdgpu_ttm_global_init(adev);
 934         if (r) {
 935                 return r;
 936         }
 937         /* No others user of address space so set it to 0 */
 938         r = ttm_bo_device_init(&adev->mman.bdev,
 939                                adev->mman.bo_global_ref.ref.object,
 940                                &amdgpu_bo_driver,
 941                                adev->ddev->anon_inode->i_mapping,
 942                                DRM_FILE_PAGE_OFFSET,
 943                                adev->need_dma32);
 944         if (r) {
 945                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
 946                 return r;
 947         }
 948         adev->mman.initialized = true;
 949         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM,
 950                                 adev->mc.real_vram_size >> PAGE_SHIFT);
 951         if (r) {
 952                 DRM_ERROR("Failed initializing VRAM heap.\n");
 953                 return r;
 954         }
 955         /* Change the size here instead of the init above so only lpfn is affected */
 956         amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
 957
 958         r = amdgpu_bo_create(adev, 256 * 1024, PAGE_SIZE, true,
 959                              AMDGPU_GEM_DOMAIN_VRAM,
 960                              AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
 961                              NULL, NULL, &adev->stollen_vga_memory);
 962         if (r) {
 963                 return r;
 964         }
 965         r = amdgpu_bo_reserve(adev->stollen_vga_memory, false);
 966         if (r)
 967                 return r;
 968         r = amdgpu_bo_pin(adev->stollen_vga_memory, AMDGPU_GEM_DOMAIN_VRAM, NULL);
 969         amdgpu_bo_unreserve(adev->stollen_vga_memory);
 970         if (r) {
 971                 amdgpu_bo_unref(&adev->stollen_vga_memory);
 972                 return r;
 973         }
 974         DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
 975                  (unsigned) (adev->mc.real_vram_size / (1024 * 1024)));
 976         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT,
 977                                 adev->mc.gtt_size >> PAGE_SHIFT);
 978         if (r) {
 979                 DRM_ERROR("Failed initializing GTT heap.\n");
 980                 return r;
 981         }
 982         DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
 983                  (unsigned)(adev->mc.gtt_size / (1024 * 1024)));
 984
 985         adev->gds.mem.total_size = adev->gds.mem.total_size << AMDGPU_GDS_SHIFT;
 986         adev->gds.mem.gfx_partition_size = adev->gds.mem.gfx_partition_size << AMDGPU_GDS_SHIFT;
 987         adev->gds.mem.cs_partition_size = adev->gds.mem.cs_partition_size << AMDGPU_GDS_SHIFT;
 988         adev->gds.gws.total_size = adev->gds.gws.total_size << AMDGPU_GWS_SHIFT;
 989         adev->gds.gws.gfx_partition_size = adev->gds.gws.gfx_partition_size << AMDGPU_GWS_SHIFT;
 990         adev->gds.gws.cs_partition_size = adev->gds.gws.cs_partition_size << AMDGPU_GWS_SHIFT;
 991         adev->gds.oa.total_size = adev->gds.oa.total_size << AMDGPU_OA_SHIFT;
 992         adev->gds.oa.gfx_partition_size = adev->gds.oa.gfx_partition_size << AMDGPU_OA_SHIFT;
 993         adev->gds.oa.cs_partition_size = adev->gds.oa.cs_partition_size << AMDGPU_OA_SHIFT;
 994         /* GDS Memory */
 995         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS,
 996                                 adev->gds.mem.total_size >> PAGE_SHIFT);
 997         if (r) {
 998                 DRM_ERROR("Failed initializing GDS heap.\n");
 999                 return r;
1000         }
1001
1002         /* GWS */
1003         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS,
1004                                 adev->gds.gws.total_size >> PAGE_SHIFT);
1005         if (r) {
1006                 DRM_ERROR("Failed initializing gws heap.\n");
1007                 return r;
1008         }
1009
1010         /* OA */
1011         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA,
1012                                 adev->gds.oa.total_size >> PAGE_SHIFT);
1013         if (r) {
1014                 DRM_ERROR("Failed initializing oa heap.\n");
1015                 return r;
1016         }
1017
1018         r = amdgpu_ttm_debugfs_init(adev);
1019         if (r) {
1020                 DRM_ERROR("Failed to init debugfs\n");
1021                 return r;
1022         }
1023         return 0;
1024 }
1025
1026 void amdgpu_ttm_fini(struct amdgpu_device *adev)
1027 {
1028         int r;
1029
1030         if (!adev->mman.initialized)
1031                 return;
1032         amdgpu_ttm_debugfs_fini(adev);
1033         if (adev->stollen_vga_memory) {
1034                 r = amdgpu_bo_reserve(adev->stollen_vga_memory, false);
1035                 if (r == 0) {
1036                         amdgpu_bo_unpin(adev->stollen_vga_memory);
1037                         amdgpu_bo_unreserve(adev->stollen_vga_memory);
1038                 }
1039                 amdgpu_bo_unref(&adev->stollen_vga_memory);
1040         }
1041         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM);
1042         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT);
1043         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS);
1044         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS);
1045         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA);
1046         ttm_bo_device_release(&adev->mman.bdev);
1047         amdgpu_gart_fini(adev);
1048         amdgpu_ttm_global_fini(adev);
1049         adev->mman.initialized = false;
1050         DRM_INFO("amdgpu: ttm finalized\n");
1051 }
1052
1053 /* this should only be called at bootup or when userspace
1054  * isn't running */
1055 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size)
1056 {
1057         struct ttm_mem_type_manager *man;
1058
1059         if (!adev->mman.initialized)
1060                 return;
1061
1062         man = &adev->mman.bdev.man[TTM_PL_VRAM];
1063         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
1064         man->size = size >> PAGE_SHIFT;
1065 }
1066
1067 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
1068 {
1069         struct drm_file *file_priv;
1070         struct amdgpu_device *adev;
1071
1072         if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET))
1073                 return -EINVAL;
1074
1075         file_priv = filp->private_data;
1076         adev = file_priv->minor->dev->dev_private;
1077         if (adev == NULL)
1078                 return -EINVAL;
1079
1080         return ttm_bo_mmap(filp, vma, &adev->mman.bdev);
1081 }
1082
1083 int amdgpu_copy_buffer(struct amdgpu_ring *ring,
1084                        uint64_t src_offset,
1085                        uint64_t dst_offset,
1086                        uint32_t byte_count,
1087                        struct reservation_object *resv,
1088                        struct fence **fence)
1089 {
1090         struct amdgpu_device *adev = ring->adev;
1091         struct amdgpu_job *job;
1092
1093         uint32_t max_bytes;
1094         unsigned num_loops, num_dw;
1095         unsigned i;
1096         int r;
1097
1098         max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
1099         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
1100         num_dw = num_loops * adev->mman.buffer_funcs->copy_num_dw;
1101
1102         /* for IB padding */
1103         while (num_dw & 0x7)
1104                 num_dw++;
1105
1106         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1107         if (r)
1108                 return r;
1109
1110         if (resv) {
1111                 r = amdgpu_sync_resv(adev, &job->sync, resv,
1112                                      AMDGPU_FENCE_OWNER_UNDEFINED);
1113                 if (r) {
1114                         DRM_ERROR("sync failed (%d).\n", r);
1115                         goto error_free;
1116                 }
1117         }
1118
1119         for (i = 0; i < num_loops; i++) {
1120                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1121
1122                 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
1123                                         dst_offset, cur_size_in_bytes);
1124
1125                 src_offset += cur_size_in_bytes;
1126                 dst_offset += cur_size_in_bytes;
1127                 byte_count -= cur_size_in_bytes;
1128         }
1129
1130         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1131         WARN_ON(job->ibs[0].length_dw > num_dw);
1132         r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1133                               AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1134         if (r)
1135                 goto error_free;
1136
1137         return 0;
1138
1139 error_free:
1140         amdgpu_job_free(job);
1141         return r;
1142 }
1143
1144 #if defined(CONFIG_DEBUG_FS)
1145
1146 static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
1147 {
1148         struct drm_info_node *node = (struct drm_info_node *)m->private;
1149         unsigned ttm_pl = *(int *)node->info_ent->data;
1150         struct drm_device *dev = node->minor->dev;
1151         struct amdgpu_device *adev = dev->dev_private;
1152         struct drm_mm *mm = (struct drm_mm *)adev->mman.bdev.man[ttm_pl].priv;
1153         int ret;
1154         struct ttm_bo_global *glob = adev->mman.bdev.glob;
1155
1156         spin_lock(&glob->lru_lock);
1157         ret = drm_mm_dump_table(m, mm);
1158         spin_unlock(&glob->lru_lock);
1159         if (ttm_pl == TTM_PL_VRAM)
1160                 seq_printf(m, "man size:%llu pages, ram usage:%lluMB, vis usage:%lluMB\n",
1161                            adev->mman.bdev.man[ttm_pl].size,
1162                            (u64)atomic64_read(&adev->vram_usage) >> 20,
1163                            (u64)atomic64_read(&adev->vram_vis_usage) >> 20);
1164         return ret;
1165 }
1166
1167 static int ttm_pl_vram = TTM_PL_VRAM;
1168 static int ttm_pl_tt = TTM_PL_TT;
1169
1170 static struct drm_info_list amdgpu_ttm_debugfs_list[] = {
1171         {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, &ttm_pl_vram},
1172         {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, &ttm_pl_tt},
1173         {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
1174 #ifdef CONFIG_SWIOTLB
1175         {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
1176 #endif
1177 };
1178
1179 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
1180                                     size_t size, loff_t *pos)
1181 {
1182         struct amdgpu_device *adev = f->f_inode->i_private;
1183         ssize_t result = 0;
1184         int r;
1185
1186         if (size & 0x3 || *pos & 0x3)
1187                 return -EINVAL;
1188
1189         while (size) {
1190                 unsigned long flags;
1191                 uint32_t value;
1192
1193                 if (*pos >= adev->mc.mc_vram_size)
1194                         return result;
1195
1196                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1197                 WREG32(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
1198                 WREG32(mmMM_INDEX_HI, *pos >> 31);
1199                 value = RREG32(mmMM_DATA);
1200                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1201
1202                 r = put_user(value, (uint32_t *)buf);
1203                 if (r)
1204                         return r;
1205
1206                 result += 4;
1207                 buf += 4;
1208                 *pos += 4;
1209                 size -= 4;
1210         }
1211
1212         return result;
1213 }
1214
1215 static const struct file_operations amdgpu_ttm_vram_fops = {
1216         .owner = THIS_MODULE,
1217         .read = amdgpu_ttm_vram_read,
1218         .llseek = default_llseek
1219 };
1220
1221 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
1222                                    size_t size, loff_t *pos)
1223 {
1224         struct amdgpu_device *adev = f->f_inode->i_private;
1225         ssize_t result = 0;
1226         int r;
1227
1228         while (size) {
1229                 loff_t p = *pos / PAGE_SIZE;
1230                 unsigned off = *pos & ~PAGE_MASK;
1231                 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
1232                 struct page *page;
1233                 void *ptr;
1234
1235                 if (p >= adev->gart.num_cpu_pages)
1236                         return result;
1237
1238                 page = adev->gart.pages[p];
1239                 if (page) {
1240                         ptr = kmap(page);
1241                         ptr += off;
1242
1243                         r = copy_to_user(buf, ptr, cur_size);
1244                         kunmap(adev->gart.pages[p]);
1245                 } else
1246                         r = clear_user(buf, cur_size);
1247
1248                 if (r)
1249                         return -EFAULT;
1250
1251                 result += cur_size;
1252                 buf += cur_size;
1253                 *pos += cur_size;
1254                 size -= cur_size;
1255         }
1256
1257         return result;
1258 }
1259
1260 static const struct file_operations amdgpu_ttm_gtt_fops = {
1261         .owner = THIS_MODULE,
1262         .read = amdgpu_ttm_gtt_read,
1263         .llseek = default_llseek
1264 };
1265
1266 #endif
1267
1268 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
1269 {
1270 #if defined(CONFIG_DEBUG_FS)
1271         unsigned count;
1272
1273         struct drm_minor *minor = adev->ddev->primary;
1274         struct dentry *ent, *root = minor->debugfs_root;
1275
1276         ent = debugfs_create_file("amdgpu_vram", S_IFREG | S_IRUGO, root,
1277                                   adev, &amdgpu_ttm_vram_fops);
1278         if (IS_ERR(ent))
1279                 return PTR_ERR(ent);
1280         i_size_write(ent->d_inode, adev->mc.mc_vram_size);
1281         adev->mman.vram = ent;
1282
1283         ent = debugfs_create_file("amdgpu_gtt", S_IFREG | S_IRUGO, root,
1284                                   adev, &amdgpu_ttm_gtt_fops);
1285         if (IS_ERR(ent))
1286                 return PTR_ERR(ent);
1287         i_size_write(ent->d_inode, adev->mc.gtt_size);
1288         adev->mman.gtt = ent;
1289
1290         count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
1291
1292 #ifdef CONFIG_SWIOTLB
1293         if (!swiotlb_nr_tbl())
1294                 --count;
1295 #endif
1296
1297         return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
1298 #else
1299
1300         return 0;
1301 #endif
1302 }
1303
1304 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev)
1305 {
1306 #if defined(CONFIG_DEBUG_FS)
1307
1308         debugfs_remove(adev->mman.vram);
1309         adev->mman.vram = NULL;
1310
1311         debugfs_remove(adev->mman.gtt);
1312         adev->mman.gtt = NULL;
1313 #endif
1314 }