drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Rafał Miłecki <zajec5@gmail.com>
  23  *          Alex Deucher <alexdeucher@gmail.com>
  24  */
  25
  26 #include <drm/drm_debugfs.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_drv.h"
  30 #include "amdgpu_pm.h"
  31 #include "amdgpu_dpm.h"
  32 #include "amdgpu_display.h"
  33 #include "amdgpu_smu.h"
  34 #include "atom.h"
  35 #include <linux/power_supply.h>
  36 #include <linux/pci.h>
  37 #include <linux/hwmon.h>
  38 #include <linux/hwmon-sysfs.h>
  39 #include <linux/nospec.h>
  40 #include "hwmgr.h"
  41 #define WIDTH_4K 3840
  42
  43 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev);
  44
  45 static const struct cg_flag_name clocks[] = {
  46         {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"},
  47         {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"},
  48         {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"},
  49         {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"},
  50         {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"},
  51         {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"},
  52         {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"},
  53         {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"},
  54         {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"},
  55         {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"},
  56         {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"},
  57         {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"},
  58         {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"},
  59         {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"},
  60         {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"},
  61         {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"},
  62         {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"},
  63         {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"},
  64         {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"},
  65         {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"},
  66         {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"},
  67         {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"},
  68         {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"},
  69         {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"},
  70
  71         {AMD_CG_SUPPORT_ATHUB_MGCG, "Address Translation Hub Medium Grain Clock Gating"},
  72         {AMD_CG_SUPPORT_ATHUB_LS, "Address Translation Hub Light Sleep"},
  73         {0, NULL},
  74 };
  75
  76 static const struct hwmon_temp_label {
  77         enum PP_HWMON_TEMP channel;
  78         const char *label;
  79 } temp_label[] = {
  80         {PP_TEMP_EDGE, "edge"},
  81         {PP_TEMP_JUNCTION, "junction"},
  82         {PP_TEMP_MEM, "mem"},
  83 };
  84
  85 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev)
  86 {
  87         if (adev->pm.dpm_enabled) {
  88                 mutex_lock(&adev->pm.mutex);
  89                 if (power_supply_is_system_supplied() > 0)
  90                         adev->pm.ac_power = true;
  91                 else
  92                         adev->pm.ac_power = false;
  93                 if (adev->powerplay.pp_funcs->enable_bapm)
  94                         amdgpu_dpm_enable_bapm(adev, adev->pm.ac_power);
  95                 mutex_unlock(&adev->pm.mutex);
  96         }
  97 }
  98
  99 int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors sensor,
 100                            void *data, uint32_t *size)
 101 {
 102         int ret = 0;
 103
 104         if (!data || !size)
 105                 return -EINVAL;
 106
 107         if (is_support_sw_smu(adev))
 108                 ret = smu_read_sensor(&adev->smu, sensor, data, size);
 109         else {
 110                 if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor)
 111                         ret = adev->powerplay.pp_funcs->read_sensor((adev)->powerplay.pp_handle,
 112                                                                     sensor, data, size);
 113                 else
 114                         ret = -EINVAL;
 115         }
 116
 117         return ret;
 118 }
 119
 120 /**
 121  * DOC: power_dpm_state
 122  *
 123  * The power_dpm_state file is a legacy interface and is only provided for
 124  * backwards compatibility. The amdgpu driver provides a sysfs API for adjusting
 125  * certain power related parameters.  The file power_dpm_state is used for this.
 126  * It accepts the following arguments:
 127  *
 128  * - battery
 129  *
 130  * - balanced
 131  *
 132  * - performance
 133  *
 134  * battery
 135  *
 136  * On older GPUs, the vbios provided a special power state for battery
 137  * operation.  Selecting battery switched to this state.  This is no
 138  * longer provided on newer GPUs so the option does nothing in that case.
 139  *
 140  * balanced
 141  *
 142  * On older GPUs, the vbios provided a special power state for balanced
 143  * operation.  Selecting balanced switched to this state.  This is no
 144  * longer provided on newer GPUs so the option does nothing in that case.
 145  *
 146  * performance
 147  *
 148  * On older GPUs, the vbios provided a special power state for performance
 149  * operation.  Selecting performance switched to this state.  This is no
 150  * longer provided on newer GPUs so the option does nothing in that case.
 151  *
 152  */
 153
 154 static ssize_t amdgpu_get_dpm_state(struct device *dev,
 155                                     struct device_attribute *attr,
 156                                     char *buf)
 157 {
 158         struct drm_device *ddev = dev_get_drvdata(dev);
 159         struct amdgpu_device *adev = ddev->dev_private;
 160         enum amd_pm_state_type pm;
 161
 162         if (is_support_sw_smu(adev)) {
 163                 if (adev->smu.ppt_funcs->get_current_power_state)
 164                         pm = amdgpu_smu_get_current_power_state(adev);
 165                 else
 166                         pm = adev->pm.dpm.user_state;
 167         } else if (adev->powerplay.pp_funcs->get_current_power_state) {
 168                 pm = amdgpu_dpm_get_current_power_state(adev);
 169         } else {
 170                 pm = adev->pm.dpm.user_state;
 171         }
 172
 173         return snprintf(buf, PAGE_SIZE, "%s\n",
 174                         (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
 175                         (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
 176 }
 177
 178 static ssize_t amdgpu_set_dpm_state(struct device *dev,
 179                                     struct device_attribute *attr,
 180                                     const char *buf,
 181                                     size_t count)
 182 {
 183         struct drm_device *ddev = dev_get_drvdata(dev);
 184         struct amdgpu_device *adev = ddev->dev_private;
 185         enum amd_pm_state_type  state;
 186
 187         if (strncmp("battery", buf, strlen("battery")) == 0)
 188                 state = POWER_STATE_TYPE_BATTERY;
 189         else if (strncmp("balanced", buf, strlen("balanced")) == 0)
 190                 state = POWER_STATE_TYPE_BALANCED;
 191         else if (strncmp("performance", buf, strlen("performance")) == 0)
 192                 state = POWER_STATE_TYPE_PERFORMANCE;
 193         else {
 194                 count = -EINVAL;
 195                 goto fail;
 196         }
 197
 198         if (is_support_sw_smu(adev)) {
 199                 mutex_lock(&adev->pm.mutex);
 200                 adev->pm.dpm.user_state = state;
 201                 mutex_unlock(&adev->pm.mutex);
 202         } else if (adev->powerplay.pp_funcs->dispatch_tasks) {
 203                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_ENABLE_USER_STATE, &state);
 204         } else {
 205                 mutex_lock(&adev->pm.mutex);
 206                 adev->pm.dpm.user_state = state;
 207                 mutex_unlock(&adev->pm.mutex);
 208
 209                 /* Can't set dpm state when the card is off */
 210                 if (!(adev->flags & AMD_IS_PX) ||
 211                     (ddev->switch_power_state == DRM_SWITCH_POWER_ON))
 212                         amdgpu_pm_compute_clocks(adev);
 213         }
 214 fail:
 215         return count;
 216 }
 217
 218
 219 /**
 220  * DOC: power_dpm_force_performance_level
 221  *
 222  * The amdgpu driver provides a sysfs API for adjusting certain power
 223  * related parameters.  The file power_dpm_force_performance_level is
 224  * used for this.  It accepts the following arguments:
 225  *
 226  * - auto
 227  *
 228  * - low
 229  *
 230  * - high
 231  *
 232  * - manual
 233  *
 234  * - profile_standard
 235  *
 236  * - profile_min_sclk
 237  *
 238  * - profile_min_mclk
 239  *
 240  * - profile_peak
 241  *
 242  * auto
 243  *
 244  * When auto is selected, the driver will attempt to dynamically select
 245  * the optimal power profile for current conditions in the driver.
 246  *
 247  * low
 248  *
 249  * When low is selected, the clocks are forced to the lowest power state.
 250  *
 251  * high
 252  *
 253  * When high is selected, the clocks are forced to the highest power state.
 254  *
 255  * manual
 256  *
 257  * When manual is selected, the user can manually adjust which power states
 258  * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk,
 259  * and pp_dpm_pcie files and adjust the power state transition heuristics
 260  * via the pp_power_profile_mode sysfs file.
 261  *
 262  * profile_standard
 263  * profile_min_sclk
 264  * profile_min_mclk
 265  * profile_peak
 266  *
 267  * When the profiling modes are selected, clock and power gating are
 268  * disabled and the clocks are set for different profiling cases. This
 269  * mode is recommended for profiling specific work loads where you do
 270  * not want clock or power gating for clock fluctuation to interfere
 271  * with your results. profile_standard sets the clocks to a fixed clock
 272  * level which varies from asic to asic.  profile_min_sclk forces the sclk
 273  * to the lowest level.  profile_min_mclk forces the mclk to the lowest level.
 274  * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels.
 275  *
 276  */
 277
 278 static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev,
 279                                                 struct device_attribute *attr,
 280                                                                 char *buf)
 281 {
 282         struct drm_device *ddev = dev_get_drvdata(dev);
 283         struct amdgpu_device *adev = ddev->dev_private;
 284         enum amd_dpm_forced_level level = 0xff;
 285
 286         if (amdgpu_sriov_vf(adev))
 287                 return 0;
 288
 289         if ((adev->flags & AMD_IS_PX) &&
 290             (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 291                 return snprintf(buf, PAGE_SIZE, "off\n");
 292
 293         if (is_support_sw_smu(adev))
 294                 level = smu_get_performance_level(&adev->smu);
 295         else if (adev->powerplay.pp_funcs->get_performance_level)
 296                 level = amdgpu_dpm_get_performance_level(adev);
 297         else
 298                 level = adev->pm.dpm.forced_level;
 299
 300         return snprintf(buf, PAGE_SIZE, "%s\n",
 301                         (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
 302                         (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
 303                         (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
 304                         (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" :
 305                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" :
 306                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" :
 307                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" :
 308                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" :
 309                         "unknown");
 310 }
 311
 312 static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
 313                                                        struct device_attribute *attr,
 314                                                        const char *buf,
 315                                                        size_t count)
 316 {
 317         struct drm_device *ddev = dev_get_drvdata(dev);
 318         struct amdgpu_device *adev = ddev->dev_private;
 319         enum amd_dpm_forced_level level;
 320         enum amd_dpm_forced_level current_level = 0xff;
 321         int ret = 0;
 322
 323         /* Can't force performance level when the card is off */
 324         if  ((adev->flags & AMD_IS_PX) &&
 325              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 326                 return -EINVAL;
 327
 328         if (strncmp("low", buf, strlen("low")) == 0) {
 329                 level = AMD_DPM_FORCED_LEVEL_LOW;
 330         } else if (strncmp("high", buf, strlen("high")) == 0) {
 331                 level = AMD_DPM_FORCED_LEVEL_HIGH;
 332         } else if (strncmp("auto", buf, strlen("auto")) == 0) {
 333                 level = AMD_DPM_FORCED_LEVEL_AUTO;
 334         } else if (strncmp("manual", buf, strlen("manual")) == 0) {
 335                 level = AMD_DPM_FORCED_LEVEL_MANUAL;
 336         } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) {
 337                 level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT;
 338         } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) {
 339                 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD;
 340         } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) {
 341                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK;
 342         } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) {
 343                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK;
 344         } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) {
 345                 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
 346         }  else {
 347                 count = -EINVAL;
 348                 goto fail;
 349         }
 350
 351         /* handle sriov case here */
 352         if (amdgpu_sriov_vf(adev)) {
 353                 if (amdgim_is_hwperf(adev) &&
 354                     adev->virt.ops->force_dpm_level) {
 355                         mutex_lock(&adev->pm.mutex);
 356                         adev->virt.ops->force_dpm_level(adev, level);
 357                         mutex_unlock(&adev->pm.mutex);
 358                         return count;
 359                 } else {
 360                         return -EINVAL;
 361                 }
 362         }
 363
 364         if (is_support_sw_smu(adev))
 365                 current_level = smu_get_performance_level(&adev->smu);
 366         else if (adev->powerplay.pp_funcs->get_performance_level)
 367                 current_level = amdgpu_dpm_get_performance_level(adev);
 368
 369         if (current_level == level)
 370                 return count;
 371
 372         /* profile_exit setting is valid only when current mode is in profile mode */
 373         if (!(current_level & (AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
 374             AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
 375             AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
 376             AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)) &&
 377             (level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)) {
 378                 pr_err("Currently not in any profile mode!\n");
 379                 return -EINVAL;
 380         }
 381
 382         if (is_support_sw_smu(adev)) {
 383                 ret = smu_force_performance_level(&adev->smu, level);
 384                 if (ret)
 385                         count = -EINVAL;
 386         } else if (adev->powerplay.pp_funcs->force_performance_level) {
 387                 mutex_lock(&adev->pm.mutex);
 388                 if (adev->pm.dpm.thermal_active) {
 389                         count = -EINVAL;
 390                         mutex_unlock(&adev->pm.mutex);
 391                         goto fail;
 392                 }
 393                 ret = amdgpu_dpm_force_performance_level(adev, level);
 394                 if (ret)
 395                         count = -EINVAL;
 396                 else
 397                         adev->pm.dpm.forced_level = level;
 398                 mutex_unlock(&adev->pm.mutex);
 399         }
 400
 401 fail:
 402         return count;
 403 }
 404
 405 static ssize_t amdgpu_get_pp_num_states(struct device *dev,
 406                 struct device_attribute *attr,
 407                 char *buf)
 408 {
 409         struct drm_device *ddev = dev_get_drvdata(dev);
 410         struct amdgpu_device *adev = ddev->dev_private;
 411         struct pp_states_info data;
 412         int i, buf_len, ret;
 413
 414         if (is_support_sw_smu(adev)) {
 415                 ret = smu_get_power_num_states(&adev->smu, &data);
 416                 if (ret)
 417                         return ret;
 418         } else if (adev->powerplay.pp_funcs->get_pp_num_states)
 419                 amdgpu_dpm_get_pp_num_states(adev, &data);
 420
 421         buf_len = snprintf(buf, PAGE_SIZE, "states: %d\n", data.nums);
 422         for (i = 0; i < data.nums; i++)
 423                 buf_len += snprintf(buf + buf_len, PAGE_SIZE, "%d %s\n", i,
 424                                 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" :
 425                                 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" :
 426                                 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" :
 427                                 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default");
 428
 429         return buf_len;
 430 }
 431
 432 static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
 433                 struct device_attribute *attr,
 434                 char *buf)
 435 {
 436         struct drm_device *ddev = dev_get_drvdata(dev);
 437         struct amdgpu_device *adev = ddev->dev_private;
 438         struct pp_states_info data;
 439         struct smu_context *smu = &adev->smu;
 440         enum amd_pm_state_type pm = 0;
 441         int i = 0, ret = 0;
 442
 443         if (is_support_sw_smu(adev)) {
 444                 pm = smu_get_current_power_state(smu);
 445                 ret = smu_get_power_num_states(smu, &data);
 446                 if (ret)
 447                         return ret;
 448         } else if (adev->powerplay.pp_funcs->get_current_power_state
 449                  && adev->powerplay.pp_funcs->get_pp_num_states) {
 450                 pm = amdgpu_dpm_get_current_power_state(adev);
 451                 amdgpu_dpm_get_pp_num_states(adev, &data);
 452         }
 453
 454         for (i = 0; i < data.nums; i++) {
 455                 if (pm == data.states[i])
 456                         break;
 457         }
 458
 459         if (i == data.nums)
 460                 i = -EINVAL;
 461
 462         return snprintf(buf, PAGE_SIZE, "%d\n", i);
 463 }
 464
 465 static ssize_t amdgpu_get_pp_force_state(struct device *dev,
 466                 struct device_attribute *attr,
 467                 char *buf)
 468 {
 469         struct drm_device *ddev = dev_get_drvdata(dev);
 470         struct amdgpu_device *adev = ddev->dev_private;
 471
 472         if (adev->pp_force_state_enabled)
 473                 return amdgpu_get_pp_cur_state(dev, attr, buf);
 474         else
 475                 return snprintf(buf, PAGE_SIZE, "\n");
 476 }
 477
 478 static ssize_t amdgpu_set_pp_force_state(struct device *dev,
 479                 struct device_attribute *attr,
 480                 const char *buf,
 481                 size_t count)
 482 {
 483         struct drm_device *ddev = dev_get_drvdata(dev);
 484         struct amdgpu_device *adev = ddev->dev_private;
 485         enum amd_pm_state_type state = 0;
 486         unsigned long idx;
 487         int ret;
 488
 489         if (strlen(buf) == 1)
 490                 adev->pp_force_state_enabled = false;
 491         else if (is_support_sw_smu(adev))
 492                 adev->pp_force_state_enabled = false;
 493         else if (adev->powerplay.pp_funcs->dispatch_tasks &&
 494                         adev->powerplay.pp_funcs->get_pp_num_states) {
 495                 struct pp_states_info data;
 496
 497                 ret = kstrtoul(buf, 0, &idx);
 498                 if (ret || idx >= ARRAY_SIZE(data.states)) {
 499                         count = -EINVAL;
 500                         goto fail;
 501                 }
 502                 idx = array_index_nospec(idx, ARRAY_SIZE(data.states));
 503
 504                 amdgpu_dpm_get_pp_num_states(adev, &data);
 505                 state = data.states[idx];
 506                 /* only set user selected power states */
 507                 if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
 508                     state != POWER_STATE_TYPE_DEFAULT) {
 509                         amdgpu_dpm_dispatch_task(adev,
 510                                         AMD_PP_TASK_ENABLE_USER_STATE, &state);
 511                         adev->pp_force_state_enabled = true;
 512                 }
 513         }
 514 fail:
 515         return count;
 516 }
 517
 518 /**
 519  * DOC: pp_table
 520  *
 521  * The amdgpu driver provides a sysfs API for uploading new powerplay
 522  * tables.  The file pp_table is used for this.  Reading the file
 523  * will dump the current power play table.  Writing to the file
 524  * will attempt to upload a new powerplay table and re-initialize
 525  * powerplay using that new table.
 526  *
 527  */
 528
 529 static ssize_t amdgpu_get_pp_table(struct device *dev,
 530                 struct device_attribute *attr,
 531                 char *buf)
 532 {
 533         struct drm_device *ddev = dev_get_drvdata(dev);
 534         struct amdgpu_device *adev = ddev->dev_private;
 535         char *table = NULL;
 536         int size;
 537
 538         if (is_support_sw_smu(adev)) {
 539                 size = smu_sys_get_pp_table(&adev->smu, (void **)&table);
 540                 if (size < 0)
 541                         return size;
 542         }
 543         else if (adev->powerplay.pp_funcs->get_pp_table)
 544                 size = amdgpu_dpm_get_pp_table(adev, &table);
 545         else
 546                 return 0;
 547
 548         if (size >= PAGE_SIZE)
 549                 size = PAGE_SIZE - 1;
 550
 551         memcpy(buf, table, size);
 552
 553         return size;
 554 }
 555
 556 static ssize_t amdgpu_set_pp_table(struct device *dev,
 557                 struct device_attribute *attr,
 558                 const char *buf,
 559                 size_t count)
 560 {
 561         struct drm_device *ddev = dev_get_drvdata(dev);
 562         struct amdgpu_device *adev = ddev->dev_private;
 563         int ret = 0;
 564
 565         if (is_support_sw_smu(adev)) {
 566                 ret = smu_sys_set_pp_table(&adev->smu, (void *)buf, count);
 567                 if (ret)
 568                         return ret;
 569         } else if (adev->powerplay.pp_funcs->set_pp_table)
 570                 amdgpu_dpm_set_pp_table(adev, buf, count);
 571
 572         return count;
 573 }
 574
 575 /**
 576  * DOC: pp_od_clk_voltage
 577  *
 578  * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages
 579  * in each power level within a power state.  The pp_od_clk_voltage is used for
 580  * this.
 581  *
 582  * < For Vega10 and previous ASICs >
 583  *
 584  * Reading the file will display:
 585  *
 586  * - a list of engine clock levels and voltages labeled OD_SCLK
 587  *
 588  * - a list of memory clock levels and voltages labeled OD_MCLK
 589  *
 590  * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE
 591  *
 592  * To manually adjust these settings, first select manual using
 593  * power_dpm_force_performance_level. Enter a new value for each
 594  * level by writing a string that contains "s/m level clock voltage" to
 595  * the file.  E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz
 596  * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at
 597  * 810 mV.  When you have edited all of the states as needed, write
 598  * "c" (commit) to the file to commit your changes.  If you want to reset to the
 599  * default power levels, write "r" (reset) to the file to reset them.
 600  *
 601  *
 602  * < For Vega20 >
 603  *
 604  * Reading the file will display:
 605  *
 606  * - minimum and maximum engine clock labeled OD_SCLK
 607  *
 608  * - maximum memory clock labeled OD_MCLK
 609  *
 610  * - three <frequency, voltage> points labeled OD_VDDC_CURVE.
 611  *   They can be used to calibrate the sclk voltage curve.
 612  *
 613  * - a list of valid ranges for sclk, mclk, and voltage curve points
 614  *   labeled OD_RANGE
 615  *
 616  * To manually adjust these settings:
 617  *
 618  * - First select manual using power_dpm_force_performance_level
 619  *
 620  * - For clock frequency setting, enter a new value by writing a
 621  *   string that contains "s/m index clock" to the file. The index
 622  *   should be 0 if to set minimum clock. And 1 if to set maximum
 623  *   clock. E.g., "s 0 500" will update minimum sclk to be 500 MHz.
 624  *   "m 1 800" will update maximum mclk to be 800Mhz.
 625  *
 626  *   For sclk voltage curve, enter the new values by writing a
 627  *   string that contains "vc point clock voltage" to the file. The
 628  *   points are indexed by 0, 1 and 2. E.g., "vc 0 300 600" will
 629  *   update point1 with clock set as 300Mhz and voltage as
 630  *   600mV. "vc 2 1000 1000" will update point3 with clock set
 631  *   as 1000Mhz and voltage 1000mV.
 632  *
 633  * - When you have edited all of the states as needed, write "c" (commit)
 634  *   to the file to commit your changes
 635  *
 636  * - If you want to reset to the default power levels, write "r" (reset)
 637  *   to the file to reset them
 638  *
 639  */
 640
 641 static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
 642                 struct device_attribute *attr,
 643                 const char *buf,
 644                 size_t count)
 645 {
 646         struct drm_device *ddev = dev_get_drvdata(dev);
 647         struct amdgpu_device *adev = ddev->dev_private;
 648         int ret;
 649         uint32_t parameter_size = 0;
 650         long parameter[64];
 651         char buf_cpy[128];
 652         char *tmp_str;
 653         char *sub_str;
 654         const char delimiter[3] = {' ', '\n', '\0'};
 655         uint32_t type;
 656
 657         if (count > 127)
 658                 return -EINVAL;
 659
 660         if (*buf == 's')
 661                 type = PP_OD_EDIT_SCLK_VDDC_TABLE;
 662         else if (*buf == 'm')
 663                 type = PP_OD_EDIT_MCLK_VDDC_TABLE;
 664         else if(*buf == 'r')
 665                 type = PP_OD_RESTORE_DEFAULT_TABLE;
 666         else if (*buf == 'c')
 667                 type = PP_OD_COMMIT_DPM_TABLE;
 668         else if (!strncmp(buf, "vc", 2))
 669                 type = PP_OD_EDIT_VDDC_CURVE;
 670         else
 671                 return -EINVAL;
 672
 673         memcpy(buf_cpy, buf, count+1);
 674
 675         tmp_str = buf_cpy;
 676
 677         if (type == PP_OD_EDIT_VDDC_CURVE)
 678                 tmp_str++;
 679         while (isspace(*++tmp_str));
 680
 681         while (tmp_str[0]) {
 682                 sub_str = strsep(&tmp_str, delimiter);
 683                 ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
 684                 if (ret)
 685                         return -EINVAL;
 686                 parameter_size++;
 687
 688                 while (isspace(*tmp_str))
 689                         tmp_str++;
 690         }
 691
 692         if (is_support_sw_smu(adev)) {
 693                 ret = smu_od_edit_dpm_table(&adev->smu, type,
 694                                             parameter, parameter_size);
 695
 696                 if (ret)
 697                         return -EINVAL;
 698         } else {
 699                 if (adev->powerplay.pp_funcs->odn_edit_dpm_table) {
 700                         ret = amdgpu_dpm_odn_edit_dpm_table(adev, type,
 701                                                 parameter, parameter_size);
 702                         if (ret)
 703                                 return -EINVAL;
 704                 }
 705
 706                 if (type == PP_OD_COMMIT_DPM_TABLE) {
 707                         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 708                                 amdgpu_dpm_dispatch_task(adev,
 709                                                 AMD_PP_TASK_READJUST_POWER_STATE,
 710                                                 NULL);
 711                                 return count;
 712                         } else {
 713                                 return -EINVAL;
 714                         }
 715                 }
 716         }
 717
 718         return count;
 719 }
 720
 721 static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
 722                 struct device_attribute *attr,
 723                 char *buf)
 724 {
 725         struct drm_device *ddev = dev_get_drvdata(dev);
 726         struct amdgpu_device *adev = ddev->dev_private;
 727         uint32_t size = 0;
 728
 729         if (is_support_sw_smu(adev)) {
 730                 size = smu_print_clk_levels(&adev->smu, SMU_OD_SCLK, buf);
 731                 size += smu_print_clk_levels(&adev->smu, SMU_OD_MCLK, buf+size);
 732                 size += smu_print_clk_levels(&adev->smu, SMU_OD_VDDC_CURVE, buf+size);
 733                 size += smu_print_clk_levels(&adev->smu, SMU_OD_RANGE, buf+size);
 734                 return size;
 735         } else if (adev->powerplay.pp_funcs->print_clock_levels) {
 736                 size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
 737                 size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf+size);
 738                 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE, buf+size);
 739                 size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf+size);
 740                 return size;
 741         } else {
 742                 return snprintf(buf, PAGE_SIZE, "\n");
 743         }
 744
 745 }
 746
 747 /**
 748  * DOC: pp_features
 749  *
 750  * The amdgpu driver provides a sysfs API for adjusting what powerplay
 751  * features to be enabled. The file pp_features is used for this. And
 752  * this is only available for Vega10 and later dGPUs.
 753  *
 754  * Reading back the file will show you the followings:
 755  * - Current ppfeature masks
 756  * - List of the all supported powerplay features with their naming,
 757  *   bitmasks and enablement status('Y'/'N' means "enabled"/"disabled").
 758  *
 759  * To manually enable or disable a specific feature, just set or clear
 760  * the corresponding bit from original ppfeature masks and input the
 761  * new ppfeature masks.
 762  */
 763 static ssize_t amdgpu_set_pp_feature_status(struct device *dev,
 764                 struct device_attribute *attr,
 765                 const char *buf,
 766                 size_t count)
 767 {
 768         struct drm_device *ddev = dev_get_drvdata(dev);
 769         struct amdgpu_device *adev = ddev->dev_private;
 770         uint64_t featuremask;
 771         int ret;
 772
 773         ret = kstrtou64(buf, 0, &featuremask);
 774         if (ret)
 775                 return -EINVAL;
 776
 777         pr_debug("featuremask = 0x%llx\n", featuremask);
 778
 779         if (is_support_sw_smu(adev)) {
 780                 ret = smu_sys_set_pp_feature_mask(&adev->smu, featuremask);
 781                 if (ret)
 782                         return -EINVAL;
 783         } else if (adev->powerplay.pp_funcs->set_ppfeature_status) {
 784                 ret = amdgpu_dpm_set_ppfeature_status(adev, featuremask);
 785                 if (ret)
 786                         return -EINVAL;
 787         }
 788
 789         return count;
 790 }
 791
 792 static ssize_t amdgpu_get_pp_feature_status(struct device *dev,
 793                 struct device_attribute *attr,
 794                 char *buf)
 795 {
 796         struct drm_device *ddev = dev_get_drvdata(dev);
 797         struct amdgpu_device *adev = ddev->dev_private;
 798
 799         if (is_support_sw_smu(adev)) {
 800                 return smu_sys_get_pp_feature_mask(&adev->smu, buf);
 801         } else if (adev->powerplay.pp_funcs->get_ppfeature_status)
 802                 return amdgpu_dpm_get_ppfeature_status(adev, buf);
 803
 804         return snprintf(buf, PAGE_SIZE, "\n");
 805 }
 806
 807 /**
 808  * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_dcefclk pp_dpm_pcie
 809  *
 810  * The amdgpu driver provides a sysfs API for adjusting what power levels
 811  * are enabled for a given power state.  The files pp_dpm_sclk, pp_dpm_mclk,
 812  * pp_dpm_socclk, pp_dpm_fclk, pp_dpm_dcefclk and pp_dpm_pcie are used for
 813  * this.
 814  *
 815  * pp_dpm_socclk and pp_dpm_dcefclk interfaces are only available for
 816  * Vega10 and later ASICs.
 817  * pp_dpm_fclk interface is only available for Vega20 and later ASICs.
 818  *
 819  * Reading back the files will show you the available power levels within
 820  * the power state and the clock information for those levels.
 821  *
 822  * To manually adjust these states, first select manual using
 823  * power_dpm_force_performance_level.
 824  * Secondly, enter a new value for each level by inputing a string that
 825  * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie"
 826  * E.g.,
 827  *
 828  * .. code-block:: bash
 829  *
 830  *      echo "4 5 6" > pp_dpm_sclk
 831  *
 832  * will enable sclk levels 4, 5, and 6.
 833  *
 834  * NOTE: change to the dcefclk max dpm level is not supported now
 835  */
 836
 837 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
 838                 struct device_attribute *attr,
 839                 char *buf)
 840 {
 841         struct drm_device *ddev = dev_get_drvdata(dev);
 842         struct amdgpu_device *adev = ddev->dev_private;
 843
 844         if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev) &&
 845             adev->virt.ops->get_pp_clk)
 846                 return adev->virt.ops->get_pp_clk(adev, PP_SCLK, buf);
 847
 848         if (is_support_sw_smu(adev))
 849                 return smu_print_clk_levels(&adev->smu, SMU_SCLK, buf);
 850         else if (adev->powerplay.pp_funcs->print_clock_levels)
 851                 return amdgpu_dpm_print_clock_levels(adev, PP_SCLK, buf);
 852         else
 853                 return snprintf(buf, PAGE_SIZE, "\n");
 854 }
 855
 856 /*
 857  * Worst case: 32 bits individually specified, in octal at 12 characters
 858  * per line (+1 for \n).
 859  */
 860 #define AMDGPU_MASK_BUF_MAX     (32 * 13)
 861
 862 static ssize_t amdgpu_read_mask(const char *buf, size_t count, uint32_t *mask)
 863 {
 864         int ret;
 865         long level;
 866         char *sub_str = NULL;
 867         char *tmp;
 868         char buf_cpy[AMDGPU_MASK_BUF_MAX + 1];
 869         const char delimiter[3] = {' ', '\n', '\0'};
 870         size_t bytes;
 871
 872         *mask = 0;
 873
 874         bytes = min(count, sizeof(buf_cpy) - 1);
 875         memcpy(buf_cpy, buf, bytes);
 876         buf_cpy[bytes] = '\0';
 877         tmp = buf_cpy;
 878         while (tmp[0]) {
 879                 sub_str = strsep(&tmp, delimiter);
 880                 if (strlen(sub_str)) {
 881                         ret = kstrtol(sub_str, 0, &level);
 882                         if (ret)
 883                                 return -EINVAL;
 884                         *mask |= 1 << level;
 885                 } else
 886                         break;
 887         }
 888
 889         return 0;
 890 }
 891
 892 static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
 893                 struct device_attribute *attr,
 894                 const char *buf,
 895                 size_t count)
 896 {
 897         struct drm_device *ddev = dev_get_drvdata(dev);
 898         struct amdgpu_device *adev = ddev->dev_private;
 899         int ret;
 900         uint32_t mask = 0;
 901
 902         if (amdgpu_sriov_vf(adev))
 903                 return 0;
 904
 905         ret = amdgpu_read_mask(buf, count, &mask);
 906         if (ret)
 907                 return ret;
 908
 909         if (is_support_sw_smu(adev))
 910                 ret = smu_force_clk_levels(&adev->smu, SMU_SCLK, mask);
 911         else if (adev->powerplay.pp_funcs->force_clock_level)
 912                 ret = amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
 913
 914         if (ret)
 915                 return -EINVAL;
 916
 917         return count;
 918 }
 919
 920 static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
 921                 struct device_attribute *attr,
 922                 char *buf)
 923 {
 924         struct drm_device *ddev = dev_get_drvdata(dev);
 925         struct amdgpu_device *adev = ddev->dev_private;
 926
 927         if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev) &&
 928             adev->virt.ops->get_pp_clk)
 929                 return adev->virt.ops->get_pp_clk(adev, PP_MCLK, buf);
 930
 931         if (is_support_sw_smu(adev))
 932                 return smu_print_clk_levels(&adev->smu, SMU_MCLK, buf);
 933         else if (adev->powerplay.pp_funcs->print_clock_levels)
 934                 return amdgpu_dpm_print_clock_levels(adev, PP_MCLK, buf);
 935         else
 936                 return snprintf(buf, PAGE_SIZE, "\n");
 937 }
 938
 939 static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
 940                 struct device_attribute *attr,
 941                 const char *buf,
 942                 size_t count)
 943 {
 944         struct drm_device *ddev = dev_get_drvdata(dev);
 945         struct amdgpu_device *adev = ddev->dev_private;
 946         int ret;
 947         uint32_t mask = 0;
 948
 949         if (amdgpu_sriov_vf(adev))
 950                 return 0;
 951
 952         ret = amdgpu_read_mask(buf, count, &mask);
 953         if (ret)
 954                 return ret;
 955
 956         if (is_support_sw_smu(adev))
 957                 ret = smu_force_clk_levels(&adev->smu, SMU_MCLK, mask);
 958         else if (adev->powerplay.pp_funcs->force_clock_level)
 959                 ret = amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
 960
 961         if (ret)
 962                 return -EINVAL;
 963
 964         return count;
 965 }
 966
 967 static ssize_t amdgpu_get_pp_dpm_socclk(struct device *dev,
 968                 struct device_attribute *attr,
 969                 char *buf)
 970 {
 971         struct drm_device *ddev = dev_get_drvdata(dev);
 972         struct amdgpu_device *adev = ddev->dev_private;
 973
 974         if (is_support_sw_smu(adev))
 975                 return smu_print_clk_levels(&adev->smu, SMU_SOCCLK, buf);
 976         else if (adev->powerplay.pp_funcs->print_clock_levels)
 977                 return amdgpu_dpm_print_clock_levels(adev, PP_SOCCLK, buf);
 978         else
 979                 return snprintf(buf, PAGE_SIZE, "\n");
 980 }
 981
 982 static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev,
 983                 struct device_attribute *attr,
 984                 const char *buf,
 985                 size_t count)
 986 {
 987         struct drm_device *ddev = dev_get_drvdata(dev);
 988         struct amdgpu_device *adev = ddev->dev_private;
 989         int ret;
 990         uint32_t mask = 0;
 991
 992         ret = amdgpu_read_mask(buf, count, &mask);
 993         if (ret)
 994                 return ret;
 995
 996         if (is_support_sw_smu(adev))
 997                 ret = smu_force_clk_levels(&adev->smu, SMU_SOCCLK, mask);
 998         else if (adev->powerplay.pp_funcs->force_clock_level)
 999                 ret = amdgpu_dpm_force_clock_level(adev, PP_SOCCLK, mask);
1000
1001         if (ret)
1002                 return -EINVAL;
1003
1004         return count;
1005 }
1006
1007 static ssize_t amdgpu_get_pp_dpm_fclk(struct device *dev,
1008                 struct device_attribute *attr,
1009                 char *buf)
1010 {
1011         struct drm_device *ddev = dev_get_drvdata(dev);
1012         struct amdgpu_device *adev = ddev->dev_private;
1013
1014         if (is_support_sw_smu(adev))
1015                 return smu_print_clk_levels(&adev->smu, SMU_FCLK, buf);
1016         else if (adev->powerplay.pp_funcs->print_clock_levels)
1017                 return amdgpu_dpm_print_clock_levels(adev, PP_FCLK, buf);
1018         else
1019                 return snprintf(buf, PAGE_SIZE, "\n");
1020 }
1021
1022 static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev,
1023                 struct device_attribute *attr,
1024                 const char *buf,
1025                 size_t count)
1026 {
1027         struct drm_device *ddev = dev_get_drvdata(dev);
1028         struct amdgpu_device *adev = ddev->dev_private;
1029         int ret;
1030         uint32_t mask = 0;
1031
1032         ret = amdgpu_read_mask(buf, count, &mask);
1033         if (ret)
1034                 return ret;
1035
1036         if (is_support_sw_smu(adev))
1037                 ret = smu_force_clk_levels(&adev->smu, SMU_FCLK, mask);
1038         else if (adev->powerplay.pp_funcs->force_clock_level)
1039                 ret = amdgpu_dpm_force_clock_level(adev, PP_FCLK, mask);
1040
1041         if (ret)
1042                 return -EINVAL;
1043
1044         return count;
1045 }
1046
1047 static ssize_t amdgpu_get_pp_dpm_dcefclk(struct device *dev,
1048                 struct device_attribute *attr,
1049                 char *buf)
1050 {
1051         struct drm_device *ddev = dev_get_drvdata(dev);
1052         struct amdgpu_device *adev = ddev->dev_private;
1053
1054         if (is_support_sw_smu(adev))
1055                 return smu_print_clk_levels(&adev->smu, SMU_DCEFCLK, buf);
1056         else if (adev->powerplay.pp_funcs->print_clock_levels)
1057                 return amdgpu_dpm_print_clock_levels(adev, PP_DCEFCLK, buf);
1058         else
1059                 return snprintf(buf, PAGE_SIZE, "\n");
1060 }
1061
1062 static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev,
1063                 struct device_attribute *attr,
1064                 const char *buf,
1065                 size_t count)
1066 {
1067         struct drm_device *ddev = dev_get_drvdata(dev);
1068         struct amdgpu_device *adev = ddev->dev_private;
1069         int ret;
1070         uint32_t mask = 0;
1071
1072         ret = amdgpu_read_mask(buf, count, &mask);
1073         if (ret)
1074                 return ret;
1075
1076         if (is_support_sw_smu(adev))
1077                 ret = smu_force_clk_levels(&adev->smu, SMU_DCEFCLK, mask);
1078         else if (adev->powerplay.pp_funcs->force_clock_level)
1079                 ret = amdgpu_dpm_force_clock_level(adev, PP_DCEFCLK, mask);
1080
1081         if (ret)
1082                 return -EINVAL;
1083
1084         return count;
1085 }
1086
1087 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
1088                 struct device_attribute *attr,
1089                 char *buf)
1090 {
1091         struct drm_device *ddev = dev_get_drvdata(dev);
1092         struct amdgpu_device *adev = ddev->dev_private;
1093
1094         if (is_support_sw_smu(adev))
1095                 return smu_print_clk_levels(&adev->smu, SMU_PCIE, buf);
1096         else if (adev->powerplay.pp_funcs->print_clock_levels)
1097                 return amdgpu_dpm_print_clock_levels(adev, PP_PCIE, buf);
1098         else
1099                 return snprintf(buf, PAGE_SIZE, "\n");
1100 }
1101
1102 static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
1103                 struct device_attribute *attr,
1104                 const char *buf,
1105                 size_t count)
1106 {
1107         struct drm_device *ddev = dev_get_drvdata(dev);
1108         struct amdgpu_device *adev = ddev->dev_private;
1109         int ret;
1110         uint32_t mask = 0;
1111
1112         ret = amdgpu_read_mask(buf, count, &mask);
1113         if (ret)
1114                 return ret;
1115
1116         if (is_support_sw_smu(adev))
1117                 ret = smu_force_clk_levels(&adev->smu, SMU_PCIE, mask);
1118         else if (adev->powerplay.pp_funcs->force_clock_level)
1119                 ret = amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
1120
1121         if (ret)
1122                 return -EINVAL;
1123
1124         return count;
1125 }
1126
1127 static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
1128                 struct device_attribute *attr,
1129                 char *buf)
1130 {
1131         struct drm_device *ddev = dev_get_drvdata(dev);
1132         struct amdgpu_device *adev = ddev->dev_private;
1133         uint32_t value = 0;
1134
1135         if (is_support_sw_smu(adev))
1136                 value = smu_get_od_percentage(&(adev->smu), SMU_OD_SCLK);
1137         else if (adev->powerplay.pp_funcs->get_sclk_od)
1138                 value = amdgpu_dpm_get_sclk_od(adev);
1139
1140         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1141 }
1142
1143 static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
1144                 struct device_attribute *attr,
1145                 const char *buf,
1146                 size_t count)
1147 {
1148         struct drm_device *ddev = dev_get_drvdata(dev);
1149         struct amdgpu_device *adev = ddev->dev_private;
1150         int ret;
1151         long int value;
1152
1153         ret = kstrtol(buf, 0, &value);
1154
1155         if (ret) {
1156                 count = -EINVAL;
1157                 goto fail;
1158         }
1159
1160         if (is_support_sw_smu(adev)) {
1161                 value = smu_set_od_percentage(&(adev->smu), SMU_OD_SCLK, (uint32_t)value);
1162         } else {
1163                 if (adev->powerplay.pp_funcs->set_sclk_od)
1164                         amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
1165
1166                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
1167                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
1168                 } else {
1169                         adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
1170                         amdgpu_pm_compute_clocks(adev);
1171                 }
1172         }
1173
1174 fail:
1175         return count;
1176 }
1177
1178 static ssize_t amdgpu_get_pp_mclk_od(struct device *dev,
1179                 struct device_attribute *attr,
1180                 char *buf)
1181 {
1182         struct drm_device *ddev = dev_get_drvdata(dev);
1183         struct amdgpu_device *adev = ddev->dev_private;
1184         uint32_t value = 0;
1185
1186         if (is_support_sw_smu(adev))
1187                 value = smu_get_od_percentage(&(adev->smu), SMU_OD_MCLK);
1188         else if (adev->powerplay.pp_funcs->get_mclk_od)
1189                 value = amdgpu_dpm_get_mclk_od(adev);
1190
1191         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1192 }
1193
1194 static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
1195                 struct device_attribute *attr,
1196                 const char *buf,
1197                 size_t count)
1198 {
1199         struct drm_device *ddev = dev_get_drvdata(dev);
1200         struct amdgpu_device *adev = ddev->dev_private;
1201         int ret;
1202         long int value;
1203
1204         ret = kstrtol(buf, 0, &value);
1205
1206         if (ret) {
1207                 count = -EINVAL;
1208                 goto fail;
1209         }
1210
1211         if (is_support_sw_smu(adev)) {
1212                 value = smu_set_od_percentage(&(adev->smu), SMU_OD_MCLK, (uint32_t)value);
1213         } else {
1214                 if (adev->powerplay.pp_funcs->set_mclk_od)
1215                         amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
1216
1217                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
1218                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
1219                 } else {
1220                         adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
1221                         amdgpu_pm_compute_clocks(adev);
1222                 }
1223         }
1224
1225 fail:
1226         return count;
1227 }
1228
1229 /**
1230  * DOC: pp_power_profile_mode
1231  *
1232  * The amdgpu driver provides a sysfs API for adjusting the heuristics
1233  * related to switching between power levels in a power state.  The file
1234  * pp_power_profile_mode is used for this.
1235  *
1236  * Reading this file outputs a list of all of the predefined power profiles
1237  * and the relevant heuristics settings for that profile.
1238  *
1239  * To select a profile or create a custom profile, first select manual using
1240  * power_dpm_force_performance_level.  Writing the number of a predefined
1241  * profile to pp_power_profile_mode will enable those heuristics.  To
1242  * create a custom set of heuristics, write a string of numbers to the file
1243  * starting with the number of the custom profile along with a setting
1244  * for each heuristic parameter.  Due to differences across asic families
1245  * the heuristic parameters vary from family to family.
1246  *
1247  */
1248
1249 static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev,
1250                 struct device_attribute *attr,
1251                 char *buf)
1252 {
1253         struct drm_device *ddev = dev_get_drvdata(dev);
1254         struct amdgpu_device *adev = ddev->dev_private;
1255
1256         if (is_support_sw_smu(adev))
1257                 return smu_get_power_profile_mode(&adev->smu, buf);
1258         else if (adev->powerplay.pp_funcs->get_power_profile_mode)
1259                 return amdgpu_dpm_get_power_profile_mode(adev, buf);
1260
1261         return snprintf(buf, PAGE_SIZE, "\n");
1262 }
1263
1264
1265 static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
1266                 struct device_attribute *attr,
1267                 const char *buf,
1268                 size_t count)
1269 {
1270         int ret = 0xff;
1271         struct drm_device *ddev = dev_get_drvdata(dev);
1272         struct amdgpu_device *adev = ddev->dev_private;
1273         uint32_t parameter_size = 0;
1274         long parameter[64];
1275         char *sub_str, buf_cpy[128];
1276         char *tmp_str;
1277         uint32_t i = 0;
1278         char tmp[2];
1279         long int profile_mode = 0;
1280         const char delimiter[3] = {' ', '\n', '\0'};
1281
1282         tmp[0] = *(buf);
1283         tmp[1] = '\0';
1284         ret = kstrtol(tmp, 0, &profile_mode);
1285         if (ret)
1286                 goto fail;
1287
1288         if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1289                 if (count < 2 || count > 127)
1290                         return -EINVAL;
1291                 while (isspace(*++buf))
1292                         i++;
1293                 memcpy(buf_cpy, buf, count-i);
1294                 tmp_str = buf_cpy;
1295                 while (tmp_str[0]) {
1296                         sub_str = strsep(&tmp_str, delimiter);
1297                         ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
1298                         if (ret) {
1299                                 count = -EINVAL;
1300                                 goto fail;
1301                         }
1302                         parameter_size++;
1303                         while (isspace(*tmp_str))
1304                                 tmp_str++;
1305                 }
1306         }
1307         parameter[parameter_size] = profile_mode;
1308         if (is_support_sw_smu(adev))
1309                 ret = smu_set_power_profile_mode(&adev->smu, parameter, parameter_size);
1310         else if (adev->powerplay.pp_funcs->set_power_profile_mode)
1311                 ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size);
1312         if (!ret)
1313                 return count;
1314 fail:
1315         return -EINVAL;
1316 }
1317
1318 /**
1319  * DOC: busy_percent
1320  *
1321  * The amdgpu driver provides a sysfs API for reading how busy the GPU
1322  * is as a percentage.  The file gpu_busy_percent is used for this.
1323  * The SMU firmware computes a percentage of load based on the
1324  * aggregate activity level in the IP cores.
1325  */
1326 static ssize_t amdgpu_get_busy_percent(struct device *dev,
1327                 struct device_attribute *attr,
1328                 char *buf)
1329 {
1330         struct drm_device *ddev = dev_get_drvdata(dev);
1331         struct amdgpu_device *adev = ddev->dev_private;
1332         int r, value, size = sizeof(value);
1333
1334         /* read the IP busy sensor */
1335         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD,
1336                                    (void *)&value, &size);
1337
1338         if (r)
1339                 return r;
1340
1341         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1342 }
1343
1344 /**
1345  * DOC: mem_busy_percent
1346  *
1347  * The amdgpu driver provides a sysfs API for reading how busy the VRAM
1348  * is as a percentage.  The file mem_busy_percent is used for this.
1349  * The SMU firmware computes a percentage of load based on the
1350  * aggregate activity level in the IP cores.
1351  */
1352 static ssize_t amdgpu_get_memory_busy_percent(struct device *dev,
1353                 struct device_attribute *attr,
1354                 char *buf)
1355 {
1356         struct drm_device *ddev = dev_get_drvdata(dev);
1357         struct amdgpu_device *adev = ddev->dev_private;
1358         int r, value, size = sizeof(value);
1359
1360         /* read the IP busy sensor */
1361         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD,
1362                                    (void *)&value, &size);
1363
1364         if (r)
1365                 return r;
1366
1367         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1368 }
1369
1370 /**
1371  * DOC: pcie_bw
1372  *
1373  * The amdgpu driver provides a sysfs API for estimating how much data
1374  * has been received and sent by the GPU in the last second through PCIe.
1375  * The file pcie_bw is used for this.
1376  * The Perf counters count the number of received and sent messages and return
1377  * those values, as well as the maximum payload size of a PCIe packet (mps).
1378  * Note that it is not possible to easily and quickly obtain the size of each
1379  * packet transmitted, so we output the max payload size (mps) to allow for
1380  * quick estimation of the PCIe bandwidth usage
1381  */
1382 static ssize_t amdgpu_get_pcie_bw(struct device *dev,
1383                 struct device_attribute *attr,
1384                 char *buf)
1385 {
1386         struct drm_device *ddev = dev_get_drvdata(dev);
1387         struct amdgpu_device *adev = ddev->dev_private;
1388         uint64_t count0, count1;
1389
1390         amdgpu_asic_get_pcie_usage(adev, &count0, &count1);
1391         return snprintf(buf, PAGE_SIZE, "%llu %llu %i\n",
1392                         count0, count1, pcie_get_mps(adev->pdev));
1393 }
1394
1395 /**
1396  * DOC: unique_id
1397  *
1398  * The amdgpu driver provides a sysfs API for providing a unique ID for the GPU
1399  * The file unique_id is used for this.
1400  * This will provide a Unique ID that will persist from machine to machine
1401  *
1402  * NOTE: This will only work for GFX9 and newer. This file will be absent
1403  * on unsupported ASICs (GFX8 and older)
1404  */
1405 static ssize_t amdgpu_get_unique_id(struct device *dev,
1406                 struct device_attribute *attr,
1407                 char *buf)
1408 {
1409         struct drm_device *ddev = dev_get_drvdata(dev);
1410         struct amdgpu_device *adev = ddev->dev_private;
1411
1412         if (adev->unique_id)
1413                 return snprintf(buf, PAGE_SIZE, "%016llx\n", adev->unique_id);
1414
1415         return 0;
1416 }
1417
1418 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, amdgpu_get_dpm_state, amdgpu_set_dpm_state);
1419 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
1420                    amdgpu_get_dpm_forced_performance_level,
1421                    amdgpu_set_dpm_forced_performance_level);
1422 static DEVICE_ATTR(pp_num_states, S_IRUGO, amdgpu_get_pp_num_states, NULL);
1423 static DEVICE_ATTR(pp_cur_state, S_IRUGO, amdgpu_get_pp_cur_state, NULL);
1424 static DEVICE_ATTR(pp_force_state, S_IRUGO | S_IWUSR,
1425                 amdgpu_get_pp_force_state,
1426                 amdgpu_set_pp_force_state);
1427 static DEVICE_ATTR(pp_table, S_IRUGO | S_IWUSR,
1428                 amdgpu_get_pp_table,
1429                 amdgpu_set_pp_table);
1430 static DEVICE_ATTR(pp_dpm_sclk, S_IRUGO | S_IWUSR,
1431                 amdgpu_get_pp_dpm_sclk,
1432                 amdgpu_set_pp_dpm_sclk);
1433 static DEVICE_ATTR(pp_dpm_mclk, S_IRUGO | S_IWUSR,
1434                 amdgpu_get_pp_dpm_mclk,
1435                 amdgpu_set_pp_dpm_mclk);
1436 static DEVICE_ATTR(pp_dpm_socclk, S_IRUGO | S_IWUSR,
1437                 amdgpu_get_pp_dpm_socclk,
1438                 amdgpu_set_pp_dpm_socclk);
1439 static DEVICE_ATTR(pp_dpm_fclk, S_IRUGO | S_IWUSR,
1440                 amdgpu_get_pp_dpm_fclk,
1441                 amdgpu_set_pp_dpm_fclk);
1442 static DEVICE_ATTR(pp_dpm_dcefclk, S_IRUGO | S_IWUSR,
1443                 amdgpu_get_pp_dpm_dcefclk,
1444                 amdgpu_set_pp_dpm_dcefclk);
1445 static DEVICE_ATTR(pp_dpm_pcie, S_IRUGO | S_IWUSR,
1446                 amdgpu_get_pp_dpm_pcie,
1447                 amdgpu_set_pp_dpm_pcie);
1448 static DEVICE_ATTR(pp_sclk_od, S_IRUGO | S_IWUSR,
1449                 amdgpu_get_pp_sclk_od,
1450                 amdgpu_set_pp_sclk_od);
1451 static DEVICE_ATTR(pp_mclk_od, S_IRUGO | S_IWUSR,
1452                 amdgpu_get_pp_mclk_od,
1453                 amdgpu_set_pp_mclk_od);
1454 static DEVICE_ATTR(pp_power_profile_mode, S_IRUGO | S_IWUSR,
1455                 amdgpu_get_pp_power_profile_mode,
1456                 amdgpu_set_pp_power_profile_mode);
1457 static DEVICE_ATTR(pp_od_clk_voltage, S_IRUGO | S_IWUSR,
1458                 amdgpu_get_pp_od_clk_voltage,
1459                 amdgpu_set_pp_od_clk_voltage);
1460 static DEVICE_ATTR(gpu_busy_percent, S_IRUGO,
1461                 amdgpu_get_busy_percent, NULL);
1462 static DEVICE_ATTR(mem_busy_percent, S_IRUGO,
1463                 amdgpu_get_memory_busy_percent, NULL);
1464 static DEVICE_ATTR(pcie_bw, S_IRUGO, amdgpu_get_pcie_bw, NULL);
1465 static DEVICE_ATTR(pp_features, S_IRUGO | S_IWUSR,
1466                 amdgpu_get_pp_feature_status,
1467                 amdgpu_set_pp_feature_status);
1468 static DEVICE_ATTR(unique_id, S_IRUGO, amdgpu_get_unique_id, NULL);
1469
1470 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
1471                                       struct device_attribute *attr,
1472                                       char *buf)
1473 {
1474         struct amdgpu_device *adev = dev_get_drvdata(dev);
1475         struct drm_device *ddev = adev->ddev;
1476         int channel = to_sensor_dev_attr(attr)->index;
1477         int r, temp = 0, size = sizeof(temp);
1478
1479         /* Can't get temperature when the card is off */
1480         if  ((adev->flags & AMD_IS_PX) &&
1481              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1482                 return -EINVAL;
1483
1484         if (channel >= PP_TEMP_MAX)
1485                 return -EINVAL;
1486
1487         switch (channel) {
1488         case PP_TEMP_JUNCTION:
1489                 /* get current junction temperature */
1490                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
1491                                            (void *)&temp, &size);
1492                 if (r)
1493                         return r;
1494                 break;
1495         case PP_TEMP_EDGE:
1496                 /* get current edge temperature */
1497                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_EDGE_TEMP,
1498                                            (void *)&temp, &size);
1499                 if (r)
1500                         return r;
1501                 break;
1502         case PP_TEMP_MEM:
1503                 /* get current memory temperature */
1504                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_TEMP,
1505                                            (void *)&temp, &size);
1506                 if (r)
1507                         return r;
1508                 break;
1509         }
1510
1511         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1512 }
1513
1514 static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev,
1515                                              struct device_attribute *attr,
1516                                              char *buf)
1517 {
1518         struct amdgpu_device *adev = dev_get_drvdata(dev);
1519         int hyst = to_sensor_dev_attr(attr)->index;
1520         int temp;
1521
1522         if (hyst)
1523                 temp = adev->pm.dpm.thermal.min_temp;
1524         else
1525                 temp = adev->pm.dpm.thermal.max_temp;
1526
1527         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1528 }
1529
1530 static ssize_t amdgpu_hwmon_show_hotspot_temp_thresh(struct device *dev,
1531                                              struct device_attribute *attr,
1532                                              char *buf)
1533 {
1534         struct amdgpu_device *adev = dev_get_drvdata(dev);
1535         int hyst = to_sensor_dev_attr(attr)->index;
1536         int temp;
1537
1538         if (hyst)
1539                 temp = adev->pm.dpm.thermal.min_hotspot_temp;
1540         else
1541                 temp = adev->pm.dpm.thermal.max_hotspot_crit_temp;
1542
1543         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1544 }
1545
1546 static ssize_t amdgpu_hwmon_show_mem_temp_thresh(struct device *dev,
1547                                              struct device_attribute *attr,
1548                                              char *buf)
1549 {
1550         struct amdgpu_device *adev = dev_get_drvdata(dev);
1551         int hyst = to_sensor_dev_attr(attr)->index;
1552         int temp;
1553
1554         if (hyst)
1555                 temp = adev->pm.dpm.thermal.min_mem_temp;
1556         else
1557                 temp = adev->pm.dpm.thermal.max_mem_crit_temp;
1558
1559         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1560 }
1561
1562 static ssize_t amdgpu_hwmon_show_temp_label(struct device *dev,
1563                                              struct device_attribute *attr,
1564                                              char *buf)
1565 {
1566         int channel = to_sensor_dev_attr(attr)->index;
1567
1568         if (channel >= PP_TEMP_MAX)
1569                 return -EINVAL;
1570
1571         return snprintf(buf, PAGE_SIZE, "%s\n", temp_label[channel].label);
1572 }
1573
1574 static ssize_t amdgpu_hwmon_show_temp_emergency(struct device *dev,
1575                                              struct device_attribute *attr,
1576                                              char *buf)
1577 {
1578         struct amdgpu_device *adev = dev_get_drvdata(dev);
1579         int channel = to_sensor_dev_attr(attr)->index;
1580         int temp = 0;
1581
1582         if (channel >= PP_TEMP_MAX)
1583                 return -EINVAL;
1584
1585         switch (channel) {
1586         case PP_TEMP_JUNCTION:
1587                 temp = adev->pm.dpm.thermal.max_hotspot_emergency_temp;
1588                 break;
1589         case PP_TEMP_EDGE:
1590                 temp = adev->pm.dpm.thermal.max_edge_emergency_temp;
1591                 break;
1592         case PP_TEMP_MEM:
1593                 temp = adev->pm.dpm.thermal.max_mem_emergency_temp;
1594                 break;
1595         }
1596
1597         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1598 }
1599
1600 static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
1601                                             struct device_attribute *attr,
1602                                             char *buf)
1603 {
1604         struct amdgpu_device *adev = dev_get_drvdata(dev);
1605         u32 pwm_mode = 0;
1606         if (is_support_sw_smu(adev)) {
1607                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
1608         } else {
1609                 if (!adev->powerplay.pp_funcs->get_fan_control_mode)
1610                         return -EINVAL;
1611
1612                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
1613         }
1614
1615         return sprintf(buf, "%i\n", pwm_mode);
1616 }
1617
1618 static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
1619                                             struct device_attribute *attr,
1620                                             const char *buf,
1621                                             size_t count)
1622 {
1623         struct amdgpu_device *adev = dev_get_drvdata(dev);
1624         int err;
1625         int value;
1626
1627         /* Can't adjust fan when the card is off */
1628         if  ((adev->flags & AMD_IS_PX) &&
1629              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1630                 return -EINVAL;
1631
1632         err = kstrtoint(buf, 10, &value);
1633         if (err)
1634                 return err;
1635
1636         if (is_support_sw_smu(adev)) {
1637                 smu_set_fan_control_mode(&adev->smu, value);
1638         } else {
1639                 if (!adev->powerplay.pp_funcs->set_fan_control_mode)
1640                         return -EINVAL;
1641
1642                 amdgpu_dpm_set_fan_control_mode(adev, value);
1643         }
1644
1645         return count;
1646 }
1647
1648 static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev,
1649                                          struct device_attribute *attr,
1650                                          char *buf)
1651 {
1652         return sprintf(buf, "%i\n", 0);
1653 }
1654
1655 static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev,
1656                                          struct device_attribute *attr,
1657                                          char *buf)
1658 {
1659         return sprintf(buf, "%i\n", 255);
1660 }
1661
1662 static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
1663                                      struct device_attribute *attr,
1664                                      const char *buf, size_t count)
1665 {
1666         struct amdgpu_device *adev = dev_get_drvdata(dev);
1667         int err;
1668         u32 value;
1669         u32 pwm_mode;
1670
1671         /* Can't adjust fan when the card is off */
1672         if  ((adev->flags & AMD_IS_PX) &&
1673              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1674                 return -EINVAL;
1675         if (is_support_sw_smu(adev))
1676                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
1677         else
1678                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
1679         if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
1680                 pr_info("manual fan speed control should be enabled first\n");
1681                 return -EINVAL;
1682         }
1683
1684         err = kstrtou32(buf, 10, &value);
1685         if (err)
1686                 return err;
1687
1688         value = (value * 100) / 255;
1689
1690         if (is_support_sw_smu(adev)) {
1691                 err = smu_set_fan_speed_percent(&adev->smu, value);
1692                 if (err)
1693                         return err;
1694         } else if (adev->powerplay.pp_funcs->set_fan_speed_percent) {
1695                 err = amdgpu_dpm_set_fan_speed_percent(adev, value);
1696                 if (err)
1697                         return err;
1698         }
1699
1700         return count;
1701 }
1702
1703 static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
1704                                      struct device_attribute *attr,
1705                                      char *buf)
1706 {
1707         struct amdgpu_device *adev = dev_get_drvdata(dev);
1708         int err;
1709         u32 speed = 0;
1710
1711         /* Can't adjust fan when the card is off */
1712         if  ((adev->flags & AMD_IS_PX) &&
1713              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1714                 return -EINVAL;
1715
1716         if (is_support_sw_smu(adev)) {
1717                 err = smu_get_fan_speed_percent(&adev->smu, &speed);
1718                 if (err)
1719                         return err;
1720         } else if (adev->powerplay.pp_funcs->get_fan_speed_percent) {
1721                 err = amdgpu_dpm_get_fan_speed_percent(adev, &speed);
1722                 if (err)
1723                         return err;
1724         }
1725
1726         speed = (speed * 255) / 100;
1727
1728         return sprintf(buf, "%i\n", speed);
1729 }
1730
1731 static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
1732                                            struct device_attribute *attr,
1733                                            char *buf)
1734 {
1735         struct amdgpu_device *adev = dev_get_drvdata(dev);
1736         int err;
1737         u32 speed = 0;
1738
1739         /* Can't adjust fan when the card is off */
1740         if  ((adev->flags & AMD_IS_PX) &&
1741              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1742                 return -EINVAL;
1743
1744         if (is_support_sw_smu(adev)) {
1745                 err = smu_get_fan_speed_rpm(&adev->smu, &speed);
1746                 if (err)
1747                         return err;
1748         } else if (adev->powerplay.pp_funcs->get_fan_speed_rpm) {
1749                 err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
1750                 if (err)
1751                         return err;
1752         }
1753
1754         return sprintf(buf, "%i\n", speed);
1755 }
1756
1757 static ssize_t amdgpu_hwmon_get_fan1_min(struct device *dev,
1758                                          struct device_attribute *attr,
1759                                          char *buf)
1760 {
1761         struct amdgpu_device *adev = dev_get_drvdata(dev);
1762         u32 min_rpm = 0;
1763         u32 size = sizeof(min_rpm);
1764         int r;
1765
1766         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MIN_FAN_RPM,
1767                                    (void *)&min_rpm, &size);
1768         if (r)
1769                 return r;
1770
1771         return snprintf(buf, PAGE_SIZE, "%d\n", min_rpm);
1772 }
1773
1774 static ssize_t amdgpu_hwmon_get_fan1_max(struct device *dev,
1775                                          struct device_attribute *attr,
1776                                          char *buf)
1777 {
1778         struct amdgpu_device *adev = dev_get_drvdata(dev);
1779         u32 max_rpm = 0;
1780         u32 size = sizeof(max_rpm);
1781         int r;
1782
1783         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MAX_FAN_RPM,
1784                                    (void *)&max_rpm, &size);
1785         if (r)
1786                 return r;
1787
1788         return snprintf(buf, PAGE_SIZE, "%d\n", max_rpm);
1789 }
1790
1791 static ssize_t amdgpu_hwmon_get_fan1_target(struct device *dev,
1792                                            struct device_attribute *attr,
1793                                            char *buf)
1794 {
1795         struct amdgpu_device *adev = dev_get_drvdata(dev);
1796         int err;
1797         u32 rpm = 0;
1798
1799         /* Can't adjust fan when the card is off */
1800         if  ((adev->flags & AMD_IS_PX) &&
1801              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1802                 return -EINVAL;
1803
1804         if (is_support_sw_smu(adev)) {
1805                 err = smu_get_fan_speed_rpm(&adev->smu, &rpm);
1806                 if (err)
1807                         return err;
1808         } else if (adev->powerplay.pp_funcs->get_fan_speed_rpm) {
1809                 err = amdgpu_dpm_get_fan_speed_rpm(adev, &rpm);
1810                 if (err)
1811                         return err;
1812         }
1813
1814         return sprintf(buf, "%i\n", rpm);
1815 }
1816
1817 static ssize_t amdgpu_hwmon_set_fan1_target(struct device *dev,
1818                                      struct device_attribute *attr,
1819                                      const char *buf, size_t count)
1820 {
1821         struct amdgpu_device *adev = dev_get_drvdata(dev);
1822         int err;
1823         u32 value;
1824         u32 pwm_mode;
1825
1826         if (is_support_sw_smu(adev))
1827                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
1828         else
1829                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
1830
1831         if (pwm_mode != AMD_FAN_CTRL_MANUAL)
1832                 return -ENODATA;
1833
1834         /* Can't adjust fan when the card is off */
1835         if  ((adev->flags & AMD_IS_PX) &&
1836              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1837                 return -EINVAL;
1838
1839         err = kstrtou32(buf, 10, &value);
1840         if (err)
1841                 return err;
1842
1843         if (is_support_sw_smu(adev)) {
1844                 err = smu_set_fan_speed_rpm(&adev->smu, value);
1845                 if (err)
1846                         return err;
1847         } else if (adev->powerplay.pp_funcs->set_fan_speed_rpm) {
1848                 err = amdgpu_dpm_set_fan_speed_rpm(adev, value);
1849                 if (err)
1850                         return err;
1851         }
1852
1853         return count;
1854 }
1855
1856 static ssize_t amdgpu_hwmon_get_fan1_enable(struct device *dev,
1857                                             struct device_attribute *attr,
1858                                             char *buf)
1859 {
1860         struct amdgpu_device *adev = dev_get_drvdata(dev);
1861         u32 pwm_mode = 0;
1862
1863         if (is_support_sw_smu(adev)) {
1864                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
1865         } else {
1866                 if (!adev->powerplay.pp_funcs->get_fan_control_mode)
1867                         return -EINVAL;
1868
1869                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
1870         }
1871         return sprintf(buf, "%i\n", pwm_mode == AMD_FAN_CTRL_AUTO ? 0 : 1);
1872 }
1873
1874 static ssize_t amdgpu_hwmon_set_fan1_enable(struct device *dev,
1875                                             struct device_attribute *attr,
1876                                             const char *buf,
1877                                             size_t count)
1878 {
1879         struct amdgpu_device *adev = dev_get_drvdata(dev);
1880         int err;
1881         int value;
1882         u32 pwm_mode;
1883
1884         /* Can't adjust fan when the card is off */
1885         if  ((adev->flags & AMD_IS_PX) &&
1886              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1887                 return -EINVAL;
1888
1889
1890         err = kstrtoint(buf, 10, &value);
1891         if (err)
1892                 return err;
1893
1894         if (value == 0)
1895                 pwm_mode = AMD_FAN_CTRL_AUTO;
1896         else if (value == 1)
1897                 pwm_mode = AMD_FAN_CTRL_MANUAL;
1898         else
1899                 return -EINVAL;
1900
1901         if (is_support_sw_smu(adev)) {
1902                 smu_set_fan_control_mode(&adev->smu, pwm_mode);
1903         } else {
1904                 if (!adev->powerplay.pp_funcs->set_fan_control_mode)
1905                         return -EINVAL;
1906                 amdgpu_dpm_set_fan_control_mode(adev, pwm_mode);
1907         }
1908
1909         return count;
1910 }
1911
1912 static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev,
1913                                         struct device_attribute *attr,
1914                                         char *buf)
1915 {
1916         struct amdgpu_device *adev = dev_get_drvdata(dev);
1917         struct drm_device *ddev = adev->ddev;
1918         u32 vddgfx;
1919         int r, size = sizeof(vddgfx);
1920
1921         /* Can't get voltage when the card is off */
1922         if  ((adev->flags & AMD_IS_PX) &&
1923              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1924                 return -EINVAL;
1925
1926         /* get the voltage */
1927         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX,
1928                                    (void *)&vddgfx, &size);
1929         if (r)
1930                 return r;
1931
1932         return snprintf(buf, PAGE_SIZE, "%d\n", vddgfx);
1933 }
1934
1935 static ssize_t amdgpu_hwmon_show_vddgfx_label(struct device *dev,
1936                                               struct device_attribute *attr,
1937                                               char *buf)
1938 {
1939         return snprintf(buf, PAGE_SIZE, "vddgfx\n");
1940 }
1941
1942 static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev,
1943                                        struct device_attribute *attr,
1944                                        char *buf)
1945 {
1946         struct amdgpu_device *adev = dev_get_drvdata(dev);
1947         struct drm_device *ddev = adev->ddev;
1948         u32 vddnb;
1949         int r, size = sizeof(vddnb);
1950
1951         /* only APUs have vddnb */
1952         if  (!(adev->flags & AMD_IS_APU))
1953                 return -EINVAL;
1954
1955         /* Can't get voltage when the card is off */
1956         if  ((adev->flags & AMD_IS_PX) &&
1957              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1958                 return -EINVAL;
1959
1960         /* get the voltage */
1961         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB,
1962                                    (void *)&vddnb, &size);
1963         if (r)
1964                 return r;
1965
1966         return snprintf(buf, PAGE_SIZE, "%d\n", vddnb);
1967 }
1968
1969 static ssize_t amdgpu_hwmon_show_vddnb_label(struct device *dev,
1970                                               struct device_attribute *attr,
1971                                               char *buf)
1972 {
1973         return snprintf(buf, PAGE_SIZE, "vddnb\n");
1974 }
1975
1976 static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev,
1977                                            struct device_attribute *attr,
1978                                            char *buf)
1979 {
1980         struct amdgpu_device *adev = dev_get_drvdata(dev);
1981         struct drm_device *ddev = adev->ddev;
1982         u32 query = 0;
1983         int r, size = sizeof(u32);
1984         unsigned uw;
1985
1986         /* Can't get power when the card is off */
1987         if  ((adev->flags & AMD_IS_PX) &&
1988              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1989                 return -EINVAL;
1990
1991         /* get the voltage */
1992         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER,
1993                                    (void *)&query, &size);
1994         if (r)
1995                 return r;
1996
1997         /* convert to microwatts */
1998         uw = (query >> 8) * 1000000 + (query & 0xff) * 1000;
1999
2000         return snprintf(buf, PAGE_SIZE, "%u\n", uw);
2001 }
2002
2003 static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev,
2004                                          struct device_attribute *attr,
2005                                          char *buf)
2006 {
2007         return sprintf(buf, "%i\n", 0);
2008 }
2009
2010 static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
2011                                          struct device_attribute *attr,
2012                                          char *buf)
2013 {
2014         struct amdgpu_device *adev = dev_get_drvdata(dev);
2015         uint32_t limit = 0;
2016
2017         if (is_support_sw_smu(adev)) {
2018                 smu_get_power_limit(&adev->smu, &limit, true);
2019                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
2020         } else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
2021                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, true);
2022                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
2023         } else {
2024                 return snprintf(buf, PAGE_SIZE, "\n");
2025         }
2026 }
2027
2028 static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
2029                                          struct device_attribute *attr,
2030                                          char *buf)
2031 {
2032         struct amdgpu_device *adev = dev_get_drvdata(dev);
2033         uint32_t limit = 0;
2034
2035         if (is_support_sw_smu(adev)) {
2036                 smu_get_power_limit(&adev->smu, &limit, false);
2037                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
2038         } else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
2039                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, false);
2040                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
2041         } else {
2042                 return snprintf(buf, PAGE_SIZE, "\n");
2043         }
2044 }
2045
2046
2047 static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
2048                 struct device_attribute *attr,
2049                 const char *buf,
2050                 size_t count)
2051 {
2052         struct amdgpu_device *adev = dev_get_drvdata(dev);
2053         int err;
2054         u32 value;
2055
2056         err = kstrtou32(buf, 10, &value);
2057         if (err)
2058                 return err;
2059
2060         value = value / 1000000; /* convert to Watt */
2061
2062         if (is_support_sw_smu(adev)) {
2063                 err = smu_set_power_limit(&adev->smu, value);
2064         } else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->set_power_limit) {
2065                 err = adev->powerplay.pp_funcs->set_power_limit(adev->powerplay.pp_handle, value);
2066         } else {
2067                 err = -EINVAL;
2068         }
2069
2070         if (err)
2071                 return err;
2072
2073         return count;
2074 }
2075
2076 static ssize_t amdgpu_hwmon_show_sclk(struct device *dev,
2077                                       struct device_attribute *attr,
2078                                       char *buf)
2079 {
2080         struct amdgpu_device *adev = dev_get_drvdata(dev);
2081         struct drm_device *ddev = adev->ddev;
2082         uint32_t sclk;
2083         int r, size = sizeof(sclk);
2084
2085         /* Can't get voltage when the card is off */
2086         if  ((adev->flags & AMD_IS_PX) &&
2087              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
2088                 return -EINVAL;
2089
2090         /* get the sclk */
2091         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK,
2092                                    (void *)&sclk, &size);
2093         if (r)
2094                 return r;
2095
2096         return snprintf(buf, PAGE_SIZE, "%d\n", sclk * 10 * 1000);
2097 }
2098
2099 static ssize_t amdgpu_hwmon_show_sclk_label(struct device *dev,
2100                                             struct device_attribute *attr,
2101                                             char *buf)
2102 {
2103         return snprintf(buf, PAGE_SIZE, "sclk\n");
2104 }
2105
2106 static ssize_t amdgpu_hwmon_show_mclk(struct device *dev,
2107                                       struct device_attribute *attr,
2108                                       char *buf)
2109 {
2110         struct amdgpu_device *adev = dev_get_drvdata(dev);
2111         struct drm_device *ddev = adev->ddev;
2112         uint32_t mclk;
2113         int r, size = sizeof(mclk);
2114
2115         /* Can't get voltage when the card is off */
2116         if  ((adev->flags & AMD_IS_PX) &&
2117              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
2118                 return -EINVAL;
2119
2120         /* get the sclk */
2121         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK,
2122                                    (void *)&mclk, &size);
2123         if (r)
2124                 return r;
2125
2126         return snprintf(buf, PAGE_SIZE, "%d\n", mclk * 10 * 1000);
2127 }
2128
2129 static ssize_t amdgpu_hwmon_show_mclk_label(struct device *dev,
2130                                             struct device_attribute *attr,
2131                                             char *buf)
2132 {
2133         return snprintf(buf, PAGE_SIZE, "mclk\n");
2134 }
2135
2136 /**
2137  * DOC: hwmon
2138  *
2139  * The amdgpu driver exposes the following sensor interfaces:
2140  *
2141  * - GPU temperature (via the on-die sensor)
2142  *
2143  * - GPU voltage
2144  *
2145  * - Northbridge voltage (APUs only)
2146  *
2147  * - GPU power
2148  *
2149  * - GPU fan
2150  *
2151  * - GPU gfx/compute engine clock
2152  *
2153  * - GPU memory clock (dGPU only)
2154  *
2155  * hwmon interfaces for GPU temperature:
2156  *
2157  * - temp[1-3]_input: the on die GPU temperature in millidegrees Celsius
2158  *   - temp2_input and temp3_input are supported on SOC15 dGPUs only
2159  *
2160  * - temp[1-3]_label: temperature channel label
2161  *   - temp2_label and temp3_label are supported on SOC15 dGPUs only
2162  *
2163  * - temp[1-3]_crit: temperature critical max value in millidegrees Celsius
2164  *   - temp2_crit and temp3_crit are supported on SOC15 dGPUs only
2165  *
2166  * - temp[1-3]_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius
2167  *   - temp2_crit_hyst and temp3_crit_hyst are supported on SOC15 dGPUs only
2168  *
2169  * - temp[1-3]_emergency: temperature emergency max value(asic shutdown) in millidegrees Celsius
2170  *   - these are supported on SOC15 dGPUs only
2171  *
2172  * hwmon interfaces for GPU voltage:
2173  *
2174  * - in0_input: the voltage on the GPU in millivolts
2175  *
2176  * - in1_input: the voltage on the Northbridge in millivolts
2177  *
2178  * hwmon interfaces for GPU power:
2179  *
2180  * - power1_average: average power used by the GPU in microWatts
2181  *
2182  * - power1_cap_min: minimum cap supported in microWatts
2183  *
2184  * - power1_cap_max: maximum cap supported in microWatts
2185  *
2186  * - power1_cap: selected power cap in microWatts
2187  *
2188  * hwmon interfaces for GPU fan:
2189  *
2190  * - pwm1: pulse width modulation fan level (0-255)
2191  *
2192  * - pwm1_enable: pulse width modulation fan control method (0: no fan speed control, 1: manual fan speed control using pwm interface, 2: automatic fan speed control)
2193  *
2194  * - pwm1_min: pulse width modulation fan control minimum level (0)
2195  *
2196  * - pwm1_max: pulse width modulation fan control maximum level (255)
2197  *
2198  * - fan1_min: an minimum value Unit: revolution/min (RPM)
2199  *
2200  * - fan1_max: an maxmum value Unit: revolution/max (RPM)
2201  *
2202  * - fan1_input: fan speed in RPM
2203  *
2204  * - fan[1-\*]_target: Desired fan speed Unit: revolution/min (RPM)
2205  *
2206  * - fan[1-\*]_enable: Enable or disable the sensors.1: Enable 0: Disable
2207  *
2208  * hwmon interfaces for GPU clocks:
2209  *
2210  * - freq1_input: the gfx/compute clock in hertz
2211  *
2212  * - freq2_input: the memory clock in hertz
2213  *
2214  * You can use hwmon tools like sensors to view this information on your system.
2215  *
2216  */
2217
2218 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_EDGE);
2219 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
2220 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
2221 static SENSOR_DEVICE_ATTR(temp1_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_EDGE);
2222 static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_JUNCTION);
2223 static SENSOR_DEVICE_ATTR(temp2_crit, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 0);
2224 static SENSOR_DEVICE_ATTR(temp2_crit_hyst, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 1);
2225 static SENSOR_DEVICE_ATTR(temp2_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_JUNCTION);
2226 static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_MEM);
2227 static SENSOR_DEVICE_ATTR(temp3_crit, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 0);
2228 static SENSOR_DEVICE_ATTR(temp3_crit_hyst, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 1);
2229 static SENSOR_DEVICE_ATTR(temp3_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_MEM);
2230 static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_EDGE);
2231 static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_JUNCTION);
2232 static SENSOR_DEVICE_ATTR(temp3_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_MEM);
2233 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0);
2234 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
2235 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
2236 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
2237 static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0);
2238 static SENSOR_DEVICE_ATTR(fan1_min, S_IRUGO, amdgpu_hwmon_get_fan1_min, NULL, 0);
2239 static SENSOR_DEVICE_ATTR(fan1_max, S_IRUGO, amdgpu_hwmon_get_fan1_max, NULL, 0);
2240 static SENSOR_DEVICE_ATTR(fan1_target, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_target, amdgpu_hwmon_set_fan1_target, 0);
2241 static SENSOR_DEVICE_ATTR(fan1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_enable, amdgpu_hwmon_set_fan1_enable, 0);
2242 static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, amdgpu_hwmon_show_vddgfx, NULL, 0);
2243 static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, amdgpu_hwmon_show_vddgfx_label, NULL, 0);
2244 static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0);
2245 static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0);
2246 static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0);
2247 static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0);
2248 static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0);
2249 static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0);
2250 static SENSOR_DEVICE_ATTR(freq1_input, S_IRUGO, amdgpu_hwmon_show_sclk, NULL, 0);
2251 static SENSOR_DEVICE_ATTR(freq1_label, S_IRUGO, amdgpu_hwmon_show_sclk_label, NULL, 0);
2252 static SENSOR_DEVICE_ATTR(freq2_input, S_IRUGO, amdgpu_hwmon_show_mclk, NULL, 0);
2253 static SENSOR_DEVICE_ATTR(freq2_label, S_IRUGO, amdgpu_hwmon_show_mclk_label, NULL, 0);
2254
2255 static struct attribute *hwmon_attributes[] = {
2256         &sensor_dev_attr_temp1_input.dev_attr.attr,
2257         &sensor_dev_attr_temp1_crit.dev_attr.attr,
2258         &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
2259         &sensor_dev_attr_temp2_input.dev_attr.attr,
2260         &sensor_dev_attr_temp2_crit.dev_attr.attr,
2261         &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr,
2262         &sensor_dev_attr_temp3_input.dev_attr.attr,
2263         &sensor_dev_attr_temp3_crit.dev_attr.attr,
2264         &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr,
2265         &sensor_dev_attr_temp1_emergency.dev_attr.attr,
2266         &sensor_dev_attr_temp2_emergency.dev_attr.attr,
2267         &sensor_dev_attr_temp3_emergency.dev_attr.attr,
2268         &sensor_dev_attr_temp1_label.dev_attr.attr,
2269         &sensor_dev_attr_temp2_label.dev_attr.attr,
2270         &sensor_dev_attr_temp3_label.dev_attr.attr,
2271         &sensor_dev_attr_pwm1.dev_attr.attr,
2272         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
2273         &sensor_dev_attr_pwm1_min.dev_attr.attr,
2274         &sensor_dev_attr_pwm1_max.dev_attr.attr,
2275         &sensor_dev_attr_fan1_input.dev_attr.attr,
2276         &sensor_dev_attr_fan1_min.dev_attr.attr,
2277         &sensor_dev_attr_fan1_max.dev_attr.attr,
2278         &sensor_dev_attr_fan1_target.dev_attr.attr,
2279         &sensor_dev_attr_fan1_enable.dev_attr.attr,
2280         &sensor_dev_attr_in0_input.dev_attr.attr,
2281         &sensor_dev_attr_in0_label.dev_attr.attr,
2282         &sensor_dev_attr_in1_input.dev_attr.attr,
2283         &sensor_dev_attr_in1_label.dev_attr.attr,
2284         &sensor_dev_attr_power1_average.dev_attr.attr,
2285         &sensor_dev_attr_power1_cap_max.dev_attr.attr,
2286         &sensor_dev_attr_power1_cap_min.dev_attr.attr,
2287         &sensor_dev_attr_power1_cap.dev_attr.attr,
2288         &sensor_dev_attr_freq1_input.dev_attr.attr,
2289         &sensor_dev_attr_freq1_label.dev_attr.attr,
2290         &sensor_dev_attr_freq2_input.dev_attr.attr,
2291         &sensor_dev_attr_freq2_label.dev_attr.attr,
2292         NULL
2293 };
2294
2295 static umode_t hwmon_attributes_visible(struct kobject *kobj,
2296                                         struct attribute *attr, int index)
2297 {
2298         struct device *dev = kobj_to_dev(kobj);
2299         struct amdgpu_device *adev = dev_get_drvdata(dev);
2300         umode_t effective_mode = attr->mode;
2301
2302         /* Skip fan attributes if fan is not present */
2303         if (adev->pm.no_fan && (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
2304             attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
2305             attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
2306             attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
2307             attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
2308             attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
2309             attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
2310             attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
2311             attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
2312                 return 0;
2313
2314         /* Skip fan attributes on APU */
2315         if ((adev->flags & AMD_IS_APU) &&
2316             (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
2317              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
2318              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
2319              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
2320              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
2321              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
2322              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
2323              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
2324              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
2325                 return 0;
2326
2327         /* Skip limit attributes if DPM is not enabled */
2328         if (!adev->pm.dpm_enabled &&
2329             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
2330              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
2331              attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
2332              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
2333              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
2334              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
2335              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
2336              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
2337              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
2338              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
2339              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
2340                 return 0;
2341
2342         if (!is_support_sw_smu(adev)) {
2343                 /* mask fan attributes if we have no bindings for this asic to expose */
2344                 if ((!adev->powerplay.pp_funcs->get_fan_speed_percent &&
2345                      attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
2346                     (!adev->powerplay.pp_funcs->get_fan_control_mode &&
2347                      attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
2348                         effective_mode &= ~S_IRUGO;
2349
2350                 if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
2351                      attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
2352                     (!adev->powerplay.pp_funcs->set_fan_control_mode &&
2353                      attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
2354                         effective_mode &= ~S_IWUSR;
2355         }
2356
2357         if (((adev->flags & AMD_IS_APU) ||
2358              adev->family == AMDGPU_FAMILY_SI ||        /* not implemented yet */
2359              adev->family == AMDGPU_FAMILY_KV) &&       /* not implemented yet */
2360             (attr == &sensor_dev_attr_power1_average.dev_attr.attr ||
2361              attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||
2362              attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr||
2363              attr == &sensor_dev_attr_power1_cap.dev_attr.attr))
2364                 return 0;
2365
2366         if (!is_support_sw_smu(adev)) {
2367                 /* hide max/min values if we can't both query and manage the fan */
2368                 if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
2369                      !adev->powerplay.pp_funcs->get_fan_speed_percent) &&
2370                      (!adev->powerplay.pp_funcs->set_fan_speed_rpm &&
2371                      !adev->powerplay.pp_funcs->get_fan_speed_rpm) &&
2372                     (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
2373                      attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
2374                         return 0;
2375
2376                 if ((!adev->powerplay.pp_funcs->set_fan_speed_rpm &&
2377                      !adev->powerplay.pp_funcs->get_fan_speed_rpm) &&
2378                     (attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
2379                      attr == &sensor_dev_attr_fan1_min.dev_attr.attr))
2380                         return 0;
2381         }
2382
2383         if ((adev->family == AMDGPU_FAMILY_SI ||        /* not implemented yet */
2384              adev->family == AMDGPU_FAMILY_KV) &&       /* not implemented yet */
2385             (attr == &sensor_dev_attr_in0_input.dev_attr.attr ||
2386              attr == &sensor_dev_attr_in0_label.dev_attr.attr))
2387                 return 0;
2388
2389         /* only APUs have vddnb */
2390         if (!(adev->flags & AMD_IS_APU) &&
2391             (attr == &sensor_dev_attr_in1_input.dev_attr.attr ||
2392              attr == &sensor_dev_attr_in1_label.dev_attr.attr))
2393                 return 0;
2394
2395         /* no mclk on APUs */
2396         if ((adev->flags & AMD_IS_APU) &&
2397             (attr == &sensor_dev_attr_freq2_input.dev_attr.attr ||
2398              attr == &sensor_dev_attr_freq2_label.dev_attr.attr))
2399                 return 0;
2400
2401         /* only SOC15 dGPUs support hotspot and mem temperatures */
2402         if (((adev->flags & AMD_IS_APU) ||
2403              adev->asic_type < CHIP_VEGA10) &&
2404             (attr == &sensor_dev_attr_temp2_crit.dev_attr.attr ||
2405              attr == &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr ||
2406              attr == &sensor_dev_attr_temp3_crit.dev_attr.attr ||
2407              attr == &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr ||
2408              attr == &sensor_dev_attr_temp1_emergency.dev_attr.attr ||
2409              attr == &sensor_dev_attr_temp2_emergency.dev_attr.attr ||
2410              attr == &sensor_dev_attr_temp3_emergency.dev_attr.attr ||
2411              attr == &sensor_dev_attr_temp2_input.dev_attr.attr ||
2412              attr == &sensor_dev_attr_temp3_input.dev_attr.attr ||
2413              attr == &sensor_dev_attr_temp2_label.dev_attr.attr ||
2414              attr == &sensor_dev_attr_temp3_label.dev_attr.attr))
2415                 return 0;
2416
2417         return effective_mode;
2418 }
2419
2420 static const struct attribute_group hwmon_attrgroup = {
2421         .attrs = hwmon_attributes,
2422         .is_visible = hwmon_attributes_visible,
2423 };
2424
2425 static const struct attribute_group *hwmon_groups[] = {
2426         &hwmon_attrgroup,
2427         NULL
2428 };
2429
2430 void amdgpu_dpm_thermal_work_handler(struct work_struct *work)
2431 {
2432         struct amdgpu_device *adev =
2433                 container_of(work, struct amdgpu_device,
2434                              pm.dpm.thermal.work);
2435         /* switch to the thermal state */
2436         enum amd_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
2437         int temp, size = sizeof(temp);
2438
2439         if (!adev->pm.dpm_enabled)
2440                 return;
2441
2442         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP,
2443                                     (void *)&temp, &size)) {
2444                 if (temp < adev->pm.dpm.thermal.min_temp)
2445                         /* switch back the user state */
2446                         dpm_state = adev->pm.dpm.user_state;
2447         } else {
2448                 if (adev->pm.dpm.thermal.high_to_low)
2449                         /* switch back the user state */
2450                         dpm_state = adev->pm.dpm.user_state;
2451         }
2452         mutex_lock(&adev->pm.mutex);
2453         if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
2454                 adev->pm.dpm.thermal_active = true;
2455         else
2456                 adev->pm.dpm.thermal_active = false;
2457         adev->pm.dpm.state = dpm_state;
2458         mutex_unlock(&adev->pm.mutex);
2459
2460         amdgpu_pm_compute_clocks(adev);
2461 }
2462
2463 static struct amdgpu_ps *amdgpu_dpm_pick_power_state(struct amdgpu_device *adev,
2464                                                      enum amd_pm_state_type dpm_state)
2465 {
2466         int i;
2467         struct amdgpu_ps *ps;
2468         u32 ui_class;
2469         bool single_display = (adev->pm.dpm.new_active_crtc_count < 2) ?
2470                 true : false;
2471
2472         /* check if the vblank period is too short to adjust the mclk */
2473         if (single_display && adev->powerplay.pp_funcs->vblank_too_short) {
2474                 if (amdgpu_dpm_vblank_too_short(adev))
2475                         single_display = false;
2476         }
2477
2478         /* certain older asics have a separare 3D performance state,
2479          * so try that first if the user selected performance
2480          */
2481         if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
2482                 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
2483         /* balanced states don't exist at the moment */
2484         if (dpm_state == POWER_STATE_TYPE_BALANCED)
2485                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
2486
2487 restart_search:
2488         /* Pick the best power state based on current conditions */
2489         for (i = 0; i < adev->pm.dpm.num_ps; i++) {
2490                 ps = &adev->pm.dpm.ps[i];
2491                 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
2492                 switch (dpm_state) {
2493                 /* user states */
2494                 case POWER_STATE_TYPE_BATTERY:
2495                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
2496                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
2497                                         if (single_display)
2498                                                 return ps;
2499                                 } else
2500                                         return ps;
2501                         }
2502                         break;
2503                 case POWER_STATE_TYPE_BALANCED:
2504                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
2505                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
2506                                         if (single_display)
2507                                                 return ps;
2508                                 } else
2509                                         return ps;
2510                         }
2511                         break;
2512                 case POWER_STATE_TYPE_PERFORMANCE:
2513                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
2514                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
2515                                         if (single_display)
2516                                                 return ps;
2517                                 } else
2518                                         return ps;
2519                         }
2520                         break;
2521                 /* internal states */
2522                 case POWER_STATE_TYPE_INTERNAL_UVD:
2523                         if (adev->pm.dpm.uvd_ps)
2524                                 return adev->pm.dpm.uvd_ps;
2525                         else
2526                                 break;
2527                 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
2528                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
2529                                 return ps;
2530                         break;
2531                 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
2532                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
2533                                 return ps;
2534                         break;
2535                 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
2536                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
2537                                 return ps;
2538                         break;
2539                 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
2540                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
2541                                 return ps;
2542                         break;
2543                 case POWER_STATE_TYPE_INTERNAL_BOOT:
2544                         return adev->pm.dpm.boot_ps;
2545                 case POWER_STATE_TYPE_INTERNAL_THERMAL:
2546                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
2547                                 return ps;
2548                         break;
2549                 case POWER_STATE_TYPE_INTERNAL_ACPI:
2550                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
2551                                 return ps;
2552                         break;
2553                 case POWER_STATE_TYPE_INTERNAL_ULV:
2554                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
2555                                 return ps;
2556                         break;
2557                 case POWER_STATE_TYPE_INTERNAL_3DPERF:
2558                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2559                                 return ps;
2560                         break;
2561                 default:
2562                         break;
2563                 }
2564         }
2565         /* use a fallback state if we didn't match */
2566         switch (dpm_state) {
2567         case POWER_STATE_TYPE_INTERNAL_UVD_SD:
2568                 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
2569                 goto restart_search;
2570         case POWER_STATE_TYPE_INTERNAL_UVD_HD:
2571         case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
2572         case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
2573                 if (adev->pm.dpm.uvd_ps) {
2574                         return adev->pm.dpm.uvd_ps;
2575                 } else {
2576                         dpm_state = POWER_STATE_TYPE_PERFORMANCE;
2577                         goto restart_search;
2578                 }
2579         case POWER_STATE_TYPE_INTERNAL_THERMAL:
2580                 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
2581                 goto restart_search;
2582         case POWER_STATE_TYPE_INTERNAL_ACPI:
2583                 dpm_state = POWER_STATE_TYPE_BATTERY;
2584                 goto restart_search;
2585         case POWER_STATE_TYPE_BATTERY:
2586         case POWER_STATE_TYPE_BALANCED:
2587         case POWER_STATE_TYPE_INTERNAL_3DPERF:
2588                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
2589                 goto restart_search;
2590         default:
2591                 break;
2592         }
2593
2594         return NULL;
2595 }
2596
2597 static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
2598 {
2599         struct amdgpu_ps *ps;
2600         enum amd_pm_state_type dpm_state;
2601         int ret;
2602         bool equal = false;
2603
2604         /* if dpm init failed */
2605         if (!adev->pm.dpm_enabled)
2606                 return;
2607
2608         if (adev->pm.dpm.user_state != adev->pm.dpm.state) {
2609                 /* add other state override checks here */
2610                 if ((!adev->pm.dpm.thermal_active) &&
2611                     (!adev->pm.dpm.uvd_active))
2612                         adev->pm.dpm.state = adev->pm.dpm.user_state;
2613         }
2614         dpm_state = adev->pm.dpm.state;
2615
2616         ps = amdgpu_dpm_pick_power_state(adev, dpm_state);
2617         if (ps)
2618                 adev->pm.dpm.requested_ps = ps;
2619         else
2620                 return;
2621
2622         if (amdgpu_dpm == 1 && adev->powerplay.pp_funcs->print_power_state) {
2623                 printk("switching from power state:\n");
2624                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps);
2625                 printk("switching to power state:\n");
2626                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.requested_ps);
2627         }
2628
2629         /* update whether vce is active */
2630         ps->vce_active = adev->pm.dpm.vce_active;
2631         if (adev->powerplay.pp_funcs->display_configuration_changed)
2632                 amdgpu_dpm_display_configuration_changed(adev);
2633
2634         ret = amdgpu_dpm_pre_set_power_state(adev);
2635         if (ret)
2636                 return;
2637
2638         if (adev->powerplay.pp_funcs->check_state_equal) {
2639                 if (0 != amdgpu_dpm_check_state_equal(adev, adev->pm.dpm.current_ps, adev->pm.dpm.requested_ps, &equal))
2640                         equal = false;
2641         }
2642
2643         if (equal)
2644                 return;
2645
2646         amdgpu_dpm_set_power_state(adev);
2647         amdgpu_dpm_post_set_power_state(adev);
2648
2649         adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
2650         adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
2651
2652         if (adev->powerplay.pp_funcs->force_performance_level) {
2653                 if (adev->pm.dpm.thermal_active) {
2654                         enum amd_dpm_forced_level level = adev->pm.dpm.forced_level;
2655                         /* force low perf level for thermal */
2656                         amdgpu_dpm_force_performance_level(adev, AMD_DPM_FORCED_LEVEL_LOW);
2657                         /* save the user's level */
2658                         adev->pm.dpm.forced_level = level;
2659                 } else {
2660                         /* otherwise, user selected level */
2661                         amdgpu_dpm_force_performance_level(adev, adev->pm.dpm.forced_level);
2662                 }
2663         }
2664 }
2665
2666 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
2667 {
2668         int ret = 0;
2669         if (is_support_sw_smu(adev)) {
2670             ret = smu_dpm_set_power_gate(&adev->smu, AMD_IP_BLOCK_TYPE_UVD, enable);
2671             if (ret)
2672                 DRM_ERROR("[SW SMU]: dpm enable uvd failed, state = %s, ret = %d. \n",
2673                           enable ? "true" : "false", ret);
2674         } else if (adev->powerplay.pp_funcs->set_powergating_by_smu) {
2675                 /* enable/disable UVD */
2676                 mutex_lock(&adev->pm.mutex);
2677                 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable);
2678                 mutex_unlock(&adev->pm.mutex);
2679         }
2680         /* enable/disable Low Memory PState for UVD (4k videos) */
2681         if (adev->asic_type == CHIP_STONEY &&
2682                 adev->uvd.decode_image_width >= WIDTH_4K) {
2683                 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
2684
2685                 if (hwmgr && hwmgr->hwmgr_func &&
2686                     hwmgr->hwmgr_func->update_nbdpm_pstate)
2687                         hwmgr->hwmgr_func->update_nbdpm_pstate(hwmgr,
2688                                                                !enable,
2689                                                                true);
2690         }
2691 }
2692
2693 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
2694 {
2695         int ret = 0;
2696         if (is_support_sw_smu(adev)) {
2697             ret = smu_dpm_set_power_gate(&adev->smu, AMD_IP_BLOCK_TYPE_VCE, enable);
2698             if (ret)
2699                 DRM_ERROR("[SW SMU]: dpm enable vce failed, state = %s, ret = %d. \n",
2700                           enable ? "true" : "false", ret);
2701         } else if (adev->powerplay.pp_funcs->set_powergating_by_smu) {
2702                 /* enable/disable VCE */
2703                 mutex_lock(&adev->pm.mutex);
2704                 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCE, !enable);
2705                 mutex_unlock(&adev->pm.mutex);
2706         }
2707 }
2708
2709 void amdgpu_pm_print_power_states(struct amdgpu_device *adev)
2710 {
2711         int i;
2712
2713         if (adev->powerplay.pp_funcs->print_power_state == NULL)
2714                 return;
2715
2716         for (i = 0; i < adev->pm.dpm.num_ps; i++)
2717                 amdgpu_dpm_print_power_state(adev, &adev->pm.dpm.ps[i]);
2718
2719 }
2720
2721 int amdgpu_pm_virt_sysfs_init(struct amdgpu_device *adev)
2722 {
2723         int ret = 0;
2724
2725         if (!(amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev)))
2726                 return ret;
2727
2728         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_sclk);
2729         if (ret) {
2730                 DRM_ERROR("failed to create device file pp_dpm_sclk\n");
2731                 return ret;
2732         }
2733
2734         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_mclk);
2735         if (ret) {
2736                 DRM_ERROR("failed to create device file pp_dpm_mclk\n");
2737                 return ret;
2738         }
2739
2740         ret = device_create_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
2741         if (ret) {
2742                 DRM_ERROR("failed to create device file for dpm state\n");
2743                 return ret;
2744         }
2745
2746         return ret;
2747 }
2748
2749 void amdgpu_pm_virt_sysfs_fini(struct amdgpu_device *adev)
2750 {
2751         if (!(amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev)))
2752                 return;
2753
2754         device_remove_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
2755         device_remove_file(adev->dev, &dev_attr_pp_dpm_sclk);
2756         device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk);
2757 }
2758
2759 int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version)
2760 {
2761         int r;
2762
2763         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->load_firmware) {
2764                 r = adev->powerplay.pp_funcs->load_firmware(adev->powerplay.pp_handle);
2765                 if (r) {
2766                         pr_err("smu firmware loading failed\n");
2767                         return r;
2768                 }
2769                 *smu_version = adev->pm.fw_version;
2770         }
2771         return 0;
2772 }
2773
2774 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
2775 {
2776         struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
2777         int ret;
2778
2779         if (adev->pm.sysfs_initialized)
2780                 return 0;
2781
2782         if (adev->pm.dpm_enabled == 0)
2783                 return 0;
2784
2785         adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
2786                                                                    DRIVER_NAME, adev,
2787                                                                    hwmon_groups);
2788         if (IS_ERR(adev->pm.int_hwmon_dev)) {
2789                 ret = PTR_ERR(adev->pm.int_hwmon_dev);
2790                 dev_err(adev->dev,
2791                         "Unable to register hwmon device: %d\n", ret);
2792                 return ret;
2793         }
2794
2795         ret = device_create_file(adev->dev, &dev_attr_power_dpm_state);
2796         if (ret) {
2797                 DRM_ERROR("failed to create device file for dpm state\n");
2798                 return ret;
2799         }
2800         ret = device_create_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
2801         if (ret) {
2802                 DRM_ERROR("failed to create device file for dpm state\n");
2803                 return ret;
2804         }
2805
2806
2807         ret = device_create_file(adev->dev, &dev_attr_pp_num_states);
2808         if (ret) {
2809                 DRM_ERROR("failed to create device file pp_num_states\n");
2810                 return ret;
2811         }
2812         ret = device_create_file(adev->dev, &dev_attr_pp_cur_state);
2813         if (ret) {
2814                 DRM_ERROR("failed to create device file pp_cur_state\n");
2815                 return ret;
2816         }
2817         ret = device_create_file(adev->dev, &dev_attr_pp_force_state);
2818         if (ret) {
2819                 DRM_ERROR("failed to create device file pp_force_state\n");
2820                 return ret;
2821         }
2822         ret = device_create_file(adev->dev, &dev_attr_pp_table);
2823         if (ret) {
2824                 DRM_ERROR("failed to create device file pp_table\n");
2825                 return ret;
2826         }
2827
2828         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_sclk);
2829         if (ret) {
2830                 DRM_ERROR("failed to create device file pp_dpm_sclk\n");
2831                 return ret;
2832         }
2833         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_mclk);
2834         if (ret) {
2835                 DRM_ERROR("failed to create device file pp_dpm_mclk\n");
2836                 return ret;
2837         }
2838         if (adev->asic_type >= CHIP_VEGA10) {
2839                 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_socclk);
2840                 if (ret) {
2841                         DRM_ERROR("failed to create device file pp_dpm_socclk\n");
2842                         return ret;
2843                 }
2844                 if (adev->asic_type != CHIP_ARCTURUS) {
2845                         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_dcefclk);
2846                         if (ret) {
2847                                 DRM_ERROR("failed to create device file pp_dpm_dcefclk\n");
2848                                 return ret;
2849                         }
2850                 }
2851         }
2852         if (adev->asic_type >= CHIP_VEGA20) {
2853                 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_fclk);
2854                 if (ret) {
2855                         DRM_ERROR("failed to create device file pp_dpm_fclk\n");
2856                         return ret;
2857                 }
2858         }
2859         if (adev->asic_type != CHIP_ARCTURUS) {
2860                 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);
2861                 if (ret) {
2862                         DRM_ERROR("failed to create device file pp_dpm_pcie\n");
2863                         return ret;
2864                 }
2865         }
2866         ret = device_create_file(adev->dev, &dev_attr_pp_sclk_od);
2867         if (ret) {
2868                 DRM_ERROR("failed to create device file pp_sclk_od\n");
2869                 return ret;
2870         }
2871         ret = device_create_file(adev->dev, &dev_attr_pp_mclk_od);
2872         if (ret) {
2873                 DRM_ERROR("failed to create device file pp_mclk_od\n");
2874                 return ret;
2875         }
2876         ret = device_create_file(adev->dev,
2877                         &dev_attr_pp_power_profile_mode);
2878         if (ret) {
2879                 DRM_ERROR("failed to create device file "
2880                                 "pp_power_profile_mode\n");
2881                 return ret;
2882         }
2883         if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||
2884             (!is_support_sw_smu(adev) && hwmgr->od_enabled)) {
2885                 ret = device_create_file(adev->dev,
2886                                 &dev_attr_pp_od_clk_voltage);
2887                 if (ret) {
2888                         DRM_ERROR("failed to create device file "
2889                                         "pp_od_clk_voltage\n");
2890                         return ret;
2891                 }
2892         }
2893         ret = device_create_file(adev->dev,
2894                         &dev_attr_gpu_busy_percent);
2895         if (ret) {
2896                 DRM_ERROR("failed to create device file "
2897                                 "gpu_busy_level\n");
2898                 return ret;
2899         }
2900         /* APU does not have its own dedicated memory */
2901         if (!(adev->flags & AMD_IS_APU) &&
2902              (adev->asic_type != CHIP_VEGA10)) {
2903                 ret = device_create_file(adev->dev,
2904                                 &dev_attr_mem_busy_percent);
2905                 if (ret) {
2906                         DRM_ERROR("failed to create device file "
2907                                         "mem_busy_percent\n");
2908                         return ret;
2909                 }
2910         }
2911         /* PCIe Perf counters won't work on APU nodes */
2912         if (!(adev->flags & AMD_IS_APU)) {
2913                 ret = device_create_file(adev->dev, &dev_attr_pcie_bw);
2914                 if (ret) {
2915                         DRM_ERROR("failed to create device file pcie_bw\n");
2916                         return ret;
2917                 }
2918         }
2919         if (adev->unique_id)
2920                 ret = device_create_file(adev->dev, &dev_attr_unique_id);
2921         if (ret) {
2922                 DRM_ERROR("failed to create device file unique_id\n");
2923                 return ret;
2924         }
2925         ret = amdgpu_debugfs_pm_init(adev);
2926         if (ret) {
2927                 DRM_ERROR("Failed to register debugfs file for dpm!\n");
2928                 return ret;
2929         }
2930
2931         if ((adev->asic_type >= CHIP_VEGA10) &&
2932             !(adev->flags & AMD_IS_APU)) {
2933                 ret = device_create_file(adev->dev,
2934                                 &dev_attr_pp_features);
2935                 if (ret) {
2936                         DRM_ERROR("failed to create device file "
2937                                         "pp_features\n");
2938                         return ret;
2939                 }
2940         }
2941
2942         adev->pm.sysfs_initialized = true;
2943
2944         return 0;
2945 }
2946
2947 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
2948 {
2949         struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
2950
2951         if (adev->pm.dpm_enabled == 0)
2952                 return;
2953
2954         if (adev->pm.int_hwmon_dev)
2955                 hwmon_device_unregister(adev->pm.int_hwmon_dev);
2956         device_remove_file(adev->dev, &dev_attr_power_dpm_state);
2957         device_remove_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
2958
2959         device_remove_file(adev->dev, &dev_attr_pp_num_states);
2960         device_remove_file(adev->dev, &dev_attr_pp_cur_state);
2961         device_remove_file(adev->dev, &dev_attr_pp_force_state);
2962         device_remove_file(adev->dev, &dev_attr_pp_table);
2963
2964         device_remove_file(adev->dev, &dev_attr_pp_dpm_sclk);
2965         device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk);
2966         if (adev->asic_type >= CHIP_VEGA10) {
2967                 device_remove_file(adev->dev, &dev_attr_pp_dpm_socclk);
2968                 if (adev->asic_type != CHIP_ARCTURUS)
2969                         device_remove_file(adev->dev, &dev_attr_pp_dpm_dcefclk);
2970         }
2971         if (adev->asic_type != CHIP_ARCTURUS)
2972                 device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);
2973         if (adev->asic_type >= CHIP_VEGA20)
2974                 device_remove_file(adev->dev, &dev_attr_pp_dpm_fclk);
2975         device_remove_file(adev->dev, &dev_attr_pp_sclk_od);
2976         device_remove_file(adev->dev, &dev_attr_pp_mclk_od);
2977         device_remove_file(adev->dev,
2978                         &dev_attr_pp_power_profile_mode);
2979         if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||
2980             (!is_support_sw_smu(adev) && hwmgr->od_enabled))
2981                 device_remove_file(adev->dev,
2982                                 &dev_attr_pp_od_clk_voltage);
2983         device_remove_file(adev->dev, &dev_attr_gpu_busy_percent);
2984         if (!(adev->flags & AMD_IS_APU) &&
2985              (adev->asic_type != CHIP_VEGA10))
2986                 device_remove_file(adev->dev, &dev_attr_mem_busy_percent);
2987         if (!(adev->flags & AMD_IS_APU))
2988                 device_remove_file(adev->dev, &dev_attr_pcie_bw);
2989         if (adev->unique_id)
2990                 device_remove_file(adev->dev, &dev_attr_unique_id);
2991         if ((adev->asic_type >= CHIP_VEGA10) &&
2992             !(adev->flags & AMD_IS_APU))
2993                 device_remove_file(adev->dev, &dev_attr_pp_features);
2994 }
2995
2996 void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
2997 {
2998         int i = 0;
2999
3000         if (!adev->pm.dpm_enabled)
3001                 return;
3002
3003         if (adev->mode_info.num_crtc)
3004                 amdgpu_display_bandwidth_update(adev);
3005
3006         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
3007                 struct amdgpu_ring *ring = adev->rings[i];
3008                 if (ring && ring->sched.ready)
3009                         amdgpu_fence_wait_empty(ring);
3010         }
3011
3012         if (is_support_sw_smu(adev)) {
3013                 struct smu_dpm_context *smu_dpm = &adev->smu.smu_dpm;
3014                 smu_handle_task(&adev->smu,
3015                                 smu_dpm->dpm_level,
3016                                 AMD_PP_TASK_DISPLAY_CONFIG_CHANGE);
3017         } else {
3018                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
3019                         if (!amdgpu_device_has_dc_support(adev)) {
3020                                 mutex_lock(&adev->pm.mutex);
3021                                 amdgpu_dpm_get_active_displays(adev);
3022                                 adev->pm.pm_display_cfg.num_display = adev->pm.dpm.new_active_crtc_count;
3023                                 adev->pm.pm_display_cfg.vrefresh = amdgpu_dpm_get_vrefresh(adev);
3024                                 adev->pm.pm_display_cfg.min_vblank_time = amdgpu_dpm_get_vblank_time(adev);
3025                                 /* we have issues with mclk switching with refresh rates over 120 hz on the non-DC code. */
3026                                 if (adev->pm.pm_display_cfg.vrefresh > 120)
3027                                         adev->pm.pm_display_cfg.min_vblank_time = 0;
3028                                 if (adev->powerplay.pp_funcs->display_configuration_change)
3029                                         adev->powerplay.pp_funcs->display_configuration_change(
3030                                                                         adev->powerplay.pp_handle,
3031                                                                         &adev->pm.pm_display_cfg);
3032                                 mutex_unlock(&adev->pm.mutex);
3033                         }
3034                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, NULL);
3035                 } else {
3036                         mutex_lock(&adev->pm.mutex);
3037                         amdgpu_dpm_get_active_displays(adev);
3038                         amdgpu_dpm_change_power_state_locked(adev);
3039                         mutex_unlock(&adev->pm.mutex);
3040                 }
3041         }
3042 }
3043
3044 /*
3045  * Debugfs info
3046  */
3047 #if defined(CONFIG_DEBUG_FS)
3048
3049 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
3050 {
3051         uint32_t value;
3052         uint64_t value64;
3053         uint32_t query = 0;
3054         int size;
3055
3056         /* GPU Clocks */
3057         size = sizeof(value);
3058         seq_printf(m, "GFX Clocks and Power:\n");
3059         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size))
3060                 seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
3061         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size))
3062                 seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
3063         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size))
3064                 seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100);
3065         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size))
3066                 seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100);
3067         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size))
3068                 seq_printf(m, "\t%u mV (VDDGFX)\n", value);
3069         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size))
3070                 seq_printf(m, "\t%u mV (VDDNB)\n", value);
3071         size = sizeof(uint32_t);
3072         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, (void *)&query, &size))
3073                 seq_printf(m, "\t%u.%u W (average GPU)\n", query >> 8, query & 0xff);
3074         size = sizeof(value);
3075         seq_printf(m, "\n");
3076
3077         /* GPU Temp */
3078         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size))
3079                 seq_printf(m, "GPU Temperature: %u C\n", value/1000);
3080
3081         /* GPU Load */
3082         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size))
3083                 seq_printf(m, "GPU Load: %u %%\n", value);
3084         /* MEM Load */
3085         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD, (void *)&value, &size))
3086                 seq_printf(m, "MEM Load: %u %%\n", value);
3087
3088         seq_printf(m, "\n");
3089
3090         /* SMC feature mask */
3091         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, (void *)&value64, &size))
3092                 seq_printf(m, "SMC Feature Mask: 0x%016llx\n", value64);
3093
3094         if (adev->asic_type > CHIP_VEGA20) {
3095                 /* VCN clocks */
3096                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCN_POWER_STATE, (void *)&value, &size)) {
3097                         if (!value) {
3098                                 seq_printf(m, "VCN: Disabled\n");
3099                         } else {
3100                                 seq_printf(m, "VCN: Enabled\n");
3101                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
3102                                         seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
3103                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
3104                                         seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
3105                         }
3106                 }
3107                 seq_printf(m, "\n");
3108         } else {
3109                 /* UVD clocks */
3110                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) {
3111                         if (!value) {
3112                                 seq_printf(m, "UVD: Disabled\n");
3113                         } else {
3114                                 seq_printf(m, "UVD: Enabled\n");
3115                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
3116                                         seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
3117                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
3118                                         seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
3119                         }
3120                 }
3121                 seq_printf(m, "\n");
3122
3123                 /* VCE clocks */
3124                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) {
3125                         if (!value) {
3126                                 seq_printf(m, "VCE: Disabled\n");
3127                         } else {
3128                                 seq_printf(m, "VCE: Enabled\n");
3129                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size))
3130                                         seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
3131                         }
3132                 }
3133         }
3134
3135         return 0;
3136 }
3137
3138 static void amdgpu_parse_cg_state(struct seq_file *m, u32 flags)
3139 {
3140         int i;
3141
3142         for (i = 0; clocks[i].flag; i++)
3143                 seq_printf(m, "\t%s: %s\n", clocks[i].name,
3144                            (flags & clocks[i].flag) ? "On" : "Off");
3145 }
3146
3147 static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
3148 {
3149         struct drm_info_node *node = (struct drm_info_node *) m->private;
3150         struct drm_device *dev = node->minor->dev;
3151         struct amdgpu_device *adev = dev->dev_private;
3152         struct drm_device *ddev = adev->ddev;
3153         u32 flags = 0;
3154
3155         amdgpu_device_ip_get_clockgating_state(adev, &flags);
3156         seq_printf(m, "Clock Gating Flags Mask: 0x%x\n", flags);
3157         amdgpu_parse_cg_state(m, flags);
3158         seq_printf(m, "\n");
3159
3160         if (!adev->pm.dpm_enabled) {
3161                 seq_printf(m, "dpm not enabled\n");
3162                 return 0;
3163         }
3164         if  ((adev->flags & AMD_IS_PX) &&
3165              (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
3166                 seq_printf(m, "PX asic powered off\n");
3167         } else if (!is_support_sw_smu(adev) && adev->powerplay.pp_funcs->debugfs_print_current_performance_level) {
3168                 mutex_lock(&adev->pm.mutex);
3169                 if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level)
3170                         adev->powerplay.pp_funcs->debugfs_print_current_performance_level(adev, m);
3171                 else
3172                         seq_printf(m, "Debugfs support not implemented for this asic\n");
3173                 mutex_unlock(&adev->pm.mutex);
3174         } else {
3175                 return amdgpu_debugfs_pm_info_pp(m, adev);
3176         }
3177
3178         return 0;
3179 }
3180
3181 static const struct drm_info_list amdgpu_pm_info_list[] = {
3182         {"amdgpu_pm_info", amdgpu_debugfs_pm_info, 0, NULL},
3183 };
3184 #endif
3185
3186 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
3187 {
3188 #if defined(CONFIG_DEBUG_FS)
3189         return amdgpu_debugfs_add_files(adev, amdgpu_pm_info_list, ARRAY_SIZE(amdgpu_pm_info_list));
3190 #else
3191         return 0;
3192 #endif
3193 }