drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/kthread.h>
  29 #include <linux/console.h>
  30 #include <linux/slab.h>
  31 #include <linux/debugfs.h>
  32 #include <drm/drmP.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/amdgpu_drm.h>
  35 #include <linux/vgaarb.h>
  36 #include <linux/vga_switcheroo.h>
  37 #include <linux/efi.h>
  38 #include "amdgpu.h"
  39 #include "amdgpu_trace.h"
  40 #include "amdgpu_i2c.h"
  41 #include "atom.h"
  42 #include "amdgpu_atombios.h"
  43 #include "amd_pcie.h"
  44 #ifdef CONFIG_DRM_AMDGPU_SI
  45 #include "si.h"
  46 #endif
  47 #ifdef CONFIG_DRM_AMDGPU_CIK
  48 #include "cik.h"
  49 #endif
  50 #include "vi.h"
  51 #include "bif/bif_4_1_d.h"
  52 #include <linux/pci.h>
  53 #include <linux/firmware.h>
  54
  55 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev);
  56 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev);
  57
  58 static const char *amdgpu_asic_name[] = {
  59         "TAHITI",
  60         "PITCAIRN",
  61         "VERDE",
  62         "OLAND",
  63         "HAINAN",
  64         "BONAIRE",
  65         "KAVERI",
  66         "KABINI",
  67         "HAWAII",
  68         "MULLINS",
  69         "TOPAZ",
  70         "TONGA",
  71         "FIJI",
  72         "CARRIZO",
  73         "STONEY",
  74         "POLARIS10",
  75         "POLARIS11",
  76         "LAST",
  77 };
  78
  79 bool amdgpu_device_is_px(struct drm_device *dev)
  80 {
  81         struct amdgpu_device *adev = dev->dev_private;
  82
  83         if (adev->flags & AMD_IS_PX)
  84                 return true;
  85         return false;
  86 }
  87
  88 /*
  89  * MMIO register access helper functions.
  90  */
  91 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
  92                         bool always_indirect)
  93 {
  94         uint32_t ret;
  95
  96         if ((reg * 4) < adev->rmmio_size && !always_indirect)
  97                 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
  98         else {
  99                 unsigned long flags;
 100
 101                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
 102                 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
 103                 ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
 104                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
 105         }
 106         trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret);
 107         return ret;
 108 }
 109
 110 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
 111                     bool always_indirect)
 112 {
 113         trace_amdgpu_mm_wreg(adev->pdev->device, reg, v);
 114
 115         if ((reg * 4) < adev->rmmio_size && !always_indirect)
 116                 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
 117         else {
 118                 unsigned long flags;
 119
 120                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
 121                 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
 122                 writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
 123                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
 124         }
 125 }
 126
 127 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
 128 {
 129         if ((reg * 4) < adev->rio_mem_size)
 130                 return ioread32(adev->rio_mem + (reg * 4));
 131         else {
 132                 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
 133                 return ioread32(adev->rio_mem + (mmMM_DATA * 4));
 134         }
 135 }
 136
 137 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 138 {
 139
 140         if ((reg * 4) < adev->rio_mem_size)
 141                 iowrite32(v, adev->rio_mem + (reg * 4));
 142         else {
 143                 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
 144                 iowrite32(v, adev->rio_mem + (mmMM_DATA * 4));
 145         }
 146 }
 147
 148 /**
 149  * amdgpu_mm_rdoorbell - read a doorbell dword
 150  *
 151  * @adev: amdgpu_device pointer
 152  * @index: doorbell index
 153  *
 154  * Returns the value in the doorbell aperture at the
 155  * requested doorbell index (CIK).
 156  */
 157 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
 158 {
 159         if (index < adev->doorbell.num_doorbells) {
 160                 return readl(adev->doorbell.ptr + index);
 161         } else {
 162                 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
 163                 return 0;
 164         }
 165 }
 166
 167 /**
 168  * amdgpu_mm_wdoorbell - write a doorbell dword
 169  *
 170  * @adev: amdgpu_device pointer
 171  * @index: doorbell index
 172  * @v: value to write
 173  *
 174  * Writes @v to the doorbell aperture at the
 175  * requested doorbell index (CIK).
 176  */
 177 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
 178 {
 179         if (index < adev->doorbell.num_doorbells) {
 180                 writel(v, adev->doorbell.ptr + index);
 181         } else {
 182                 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
 183         }
 184 }
 185
 186 /**
 187  * amdgpu_invalid_rreg - dummy reg read function
 188  *
 189  * @adev: amdgpu device pointer
 190  * @reg: offset of register
 191  *
 192  * Dummy register read function.  Used for register blocks
 193  * that certain asics don't have (all asics).
 194  * Returns the value in the register.
 195  */
 196 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
 197 {
 198         DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
 199         BUG();
 200         return 0;
 201 }
 202
 203 /**
 204  * amdgpu_invalid_wreg - dummy reg write function
 205  *
 206  * @adev: amdgpu device pointer
 207  * @reg: offset of register
 208  * @v: value to write to the register
 209  *
 210  * Dummy register read function.  Used for register blocks
 211  * that certain asics don't have (all asics).
 212  */
 213 static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
 214 {
 215         DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
 216                   reg, v);
 217         BUG();
 218 }
 219
 220 /**
 221  * amdgpu_block_invalid_rreg - dummy reg read function
 222  *
 223  * @adev: amdgpu device pointer
 224  * @block: offset of instance
 225  * @reg: offset of register
 226  *
 227  * Dummy register read function.  Used for register blocks
 228  * that certain asics don't have (all asics).
 229  * Returns the value in the register.
 230  */
 231 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
 232                                           uint32_t block, uint32_t reg)
 233 {
 234         DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
 235                   reg, block);
 236         BUG();
 237         return 0;
 238 }
 239
 240 /**
 241  * amdgpu_block_invalid_wreg - dummy reg write function
 242  *
 243  * @adev: amdgpu device pointer
 244  * @block: offset of instance
 245  * @reg: offset of register
 246  * @v: value to write to the register
 247  *
 248  * Dummy register read function.  Used for register blocks
 249  * that certain asics don't have (all asics).
 250  */
 251 static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
 252                                       uint32_t block,
 253                                       uint32_t reg, uint32_t v)
 254 {
 255         DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
 256                   reg, block, v);
 257         BUG();
 258 }
 259
 260 static int amdgpu_vram_scratch_init(struct amdgpu_device *adev)
 261 {
 262         int r;
 263
 264         if (adev->vram_scratch.robj == NULL) {
 265                 r = amdgpu_bo_create(adev, AMDGPU_GPU_PAGE_SIZE,
 266                                      PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM,
 267                                      AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
 268                                      NULL, NULL, &adev->vram_scratch.robj);
 269                 if (r) {
 270                         return r;
 271                 }
 272         }
 273
 274         r = amdgpu_bo_reserve(adev->vram_scratch.robj, false);
 275         if (unlikely(r != 0))
 276                 return r;
 277         r = amdgpu_bo_pin(adev->vram_scratch.robj,
 278                           AMDGPU_GEM_DOMAIN_VRAM, &adev->vram_scratch.gpu_addr);
 279         if (r) {
 280                 amdgpu_bo_unreserve(adev->vram_scratch.robj);
 281                 return r;
 282         }
 283         r = amdgpu_bo_kmap(adev->vram_scratch.robj,
 284                                 (void **)&adev->vram_scratch.ptr);
 285         if (r)
 286                 amdgpu_bo_unpin(adev->vram_scratch.robj);
 287         amdgpu_bo_unreserve(adev->vram_scratch.robj);
 288
 289         return r;
 290 }
 291
 292 static void amdgpu_vram_scratch_fini(struct amdgpu_device *adev)
 293 {
 294         int r;
 295
 296         if (adev->vram_scratch.robj == NULL) {
 297                 return;
 298         }
 299         r = amdgpu_bo_reserve(adev->vram_scratch.robj, false);
 300         if (likely(r == 0)) {
 301                 amdgpu_bo_kunmap(adev->vram_scratch.robj);
 302                 amdgpu_bo_unpin(adev->vram_scratch.robj);
 303                 amdgpu_bo_unreserve(adev->vram_scratch.robj);
 304         }
 305         amdgpu_bo_unref(&adev->vram_scratch.robj);
 306 }
 307
 308 /**
 309  * amdgpu_program_register_sequence - program an array of registers.
 310  *
 311  * @adev: amdgpu_device pointer
 312  * @registers: pointer to the register array
 313  * @array_size: size of the register array
 314  *
 315  * Programs an array or registers with and and or masks.
 316  * This is a helper for setting golden registers.
 317  */
 318 void amdgpu_program_register_sequence(struct amdgpu_device *adev,
 319                                       const u32 *registers,
 320                                       const u32 array_size)
 321 {
 322         u32 tmp, reg, and_mask, or_mask;
 323         int i;
 324
 325         if (array_size % 3)
 326                 return;
 327
 328         for (i = 0; i < array_size; i +=3) {
 329                 reg = registers[i + 0];
 330                 and_mask = registers[i + 1];
 331                 or_mask = registers[i + 2];
 332
 333                 if (and_mask == 0xffffffff) {
 334                         tmp = or_mask;
 335                 } else {
 336                         tmp = RREG32(reg);
 337                         tmp &= ~and_mask;
 338                         tmp |= or_mask;
 339                 }
 340                 WREG32(reg, tmp);
 341         }
 342 }
 343
 344 void amdgpu_pci_config_reset(struct amdgpu_device *adev)
 345 {
 346         pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
 347 }
 348
 349 /*
 350  * GPU doorbell aperture helpers function.
 351  */
 352 /**
 353  * amdgpu_doorbell_init - Init doorbell driver information.
 354  *
 355  * @adev: amdgpu_device pointer
 356  *
 357  * Init doorbell driver information (CIK)
 358  * Returns 0 on success, error on failure.
 359  */
 360 static int amdgpu_doorbell_init(struct amdgpu_device *adev)
 361 {
 362         /* doorbell bar mapping */
 363         adev->doorbell.base = pci_resource_start(adev->pdev, 2);
 364         adev->doorbell.size = pci_resource_len(adev->pdev, 2);
 365
 366         adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),
 367                                              AMDGPU_DOORBELL_MAX_ASSIGNMENT+1);
 368         if (adev->doorbell.num_doorbells == 0)
 369                 return -EINVAL;
 370
 371         adev->doorbell.ptr = ioremap(adev->doorbell.base, adev->doorbell.num_doorbells * sizeof(u32));
 372         if (adev->doorbell.ptr == NULL) {
 373                 return -ENOMEM;
 374         }
 375         DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)adev->doorbell.base);
 376         DRM_INFO("doorbell mmio size: %u\n", (unsigned)adev->doorbell.size);
 377
 378         return 0;
 379 }
 380
 381 /**
 382  * amdgpu_doorbell_fini - Tear down doorbell driver information.
 383  *
 384  * @adev: amdgpu_device pointer
 385  *
 386  * Tear down doorbell driver information (CIK)
 387  */
 388 static void amdgpu_doorbell_fini(struct amdgpu_device *adev)
 389 {
 390         iounmap(adev->doorbell.ptr);
 391         adev->doorbell.ptr = NULL;
 392 }
 393
 394 /**
 395  * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
 396  *                                setup amdkfd
 397  *
 398  * @adev: amdgpu_device pointer
 399  * @aperture_base: output returning doorbell aperture base physical address
 400  * @aperture_size: output returning doorbell aperture size in bytes
 401  * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
 402  *
 403  * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
 404  * takes doorbells required for its own rings and reports the setup to amdkfd.
 405  * amdgpu reserved doorbells are at the start of the doorbell aperture.
 406  */
 407 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
 408                                 phys_addr_t *aperture_base,
 409                                 size_t *aperture_size,
 410                                 size_t *start_offset)
 411 {
 412         /*
 413          * The first num_doorbells are used by amdgpu.
 414          * amdkfd takes whatever's left in the aperture.
 415          */
 416         if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {
 417                 *aperture_base = adev->doorbell.base;
 418                 *aperture_size = adev->doorbell.size;
 419                 *start_offset = adev->doorbell.num_doorbells * sizeof(u32);
 420         } else {
 421                 *aperture_base = 0;
 422                 *aperture_size = 0;
 423                 *start_offset = 0;
 424         }
 425 }
 426
 427 /*
 428  * amdgpu_wb_*()
 429  * Writeback is the the method by which the the GPU updates special pages
 430  * in memory with the status of certain GPU events (fences, ring pointers,
 431  * etc.).
 432  */
 433
 434 /**
 435  * amdgpu_wb_fini - Disable Writeback and free memory
 436  *
 437  * @adev: amdgpu_device pointer
 438  *
 439  * Disables Writeback and frees the Writeback memory (all asics).
 440  * Used at driver shutdown.
 441  */
 442 static void amdgpu_wb_fini(struct amdgpu_device *adev)
 443 {
 444         if (adev->wb.wb_obj) {
 445                 if (!amdgpu_bo_reserve(adev->wb.wb_obj, false)) {
 446                         amdgpu_bo_kunmap(adev->wb.wb_obj);
 447                         amdgpu_bo_unpin(adev->wb.wb_obj);
 448                         amdgpu_bo_unreserve(adev->wb.wb_obj);
 449                 }
 450                 amdgpu_bo_unref(&adev->wb.wb_obj);
 451                 adev->wb.wb = NULL;
 452                 adev->wb.wb_obj = NULL;
 453         }
 454 }
 455
 456 /**
 457  * amdgpu_wb_init- Init Writeback driver info and allocate memory
 458  *
 459  * @adev: amdgpu_device pointer
 460  *
 461  * Disables Writeback and frees the Writeback memory (all asics).
 462  * Used at driver startup.
 463  * Returns 0 on success or an -error on failure.
 464  */
 465 static int amdgpu_wb_init(struct amdgpu_device *adev)
 466 {
 467         int r;
 468
 469         if (adev->wb.wb_obj == NULL) {
 470                 r = amdgpu_bo_create(adev, AMDGPU_MAX_WB * 4, PAGE_SIZE, true,
 471                                      AMDGPU_GEM_DOMAIN_GTT, 0,  NULL, NULL,
 472                                      &adev->wb.wb_obj);
 473                 if (r) {
 474                         dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
 475                         return r;
 476                 }
 477                 r = amdgpu_bo_reserve(adev->wb.wb_obj, false);
 478                 if (unlikely(r != 0)) {
 479                         amdgpu_wb_fini(adev);
 480                         return r;
 481                 }
 482                 r = amdgpu_bo_pin(adev->wb.wb_obj, AMDGPU_GEM_DOMAIN_GTT,
 483                                 &adev->wb.gpu_addr);
 484                 if (r) {
 485                         amdgpu_bo_unreserve(adev->wb.wb_obj);
 486                         dev_warn(adev->dev, "(%d) pin WB bo failed\n", r);
 487                         amdgpu_wb_fini(adev);
 488                         return r;
 489                 }
 490                 r = amdgpu_bo_kmap(adev->wb.wb_obj, (void **)&adev->wb.wb);
 491                 amdgpu_bo_unreserve(adev->wb.wb_obj);
 492                 if (r) {
 493                         dev_warn(adev->dev, "(%d) map WB bo failed\n", r);
 494                         amdgpu_wb_fini(adev);
 495                         return r;
 496                 }
 497
 498                 adev->wb.num_wb = AMDGPU_MAX_WB;
 499                 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
 500
 501                 /* clear wb memory */
 502                 memset((char *)adev->wb.wb, 0, AMDGPU_GPU_PAGE_SIZE);
 503         }
 504
 505         return 0;
 506 }
 507
 508 /**
 509  * amdgpu_wb_get - Allocate a wb entry
 510  *
 511  * @adev: amdgpu_device pointer
 512  * @wb: wb index
 513  *
 514  * Allocate a wb slot for use by the driver (all asics).
 515  * Returns 0 on success or -EINVAL on failure.
 516  */
 517 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb)
 518 {
 519         unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
 520         if (offset < adev->wb.num_wb) {
 521                 __set_bit(offset, adev->wb.used);
 522                 *wb = offset;
 523                 return 0;
 524         } else {
 525                 return -EINVAL;
 526         }
 527 }
 528
 529 /**
 530  * amdgpu_wb_free - Free a wb entry
 531  *
 532  * @adev: amdgpu_device pointer
 533  * @wb: wb index
 534  *
 535  * Free a wb slot allocated for use by the driver (all asics)
 536  */
 537 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb)
 538 {
 539         if (wb < adev->wb.num_wb)
 540                 __clear_bit(wb, adev->wb.used);
 541 }
 542
 543 /**
 544  * amdgpu_vram_location - try to find VRAM location
 545  * @adev: amdgpu device structure holding all necessary informations
 546  * @mc: memory controller structure holding memory informations
 547  * @base: base address at which to put VRAM
 548  *
 549  * Function will place try to place VRAM at base address provided
 550  * as parameter (which is so far either PCI aperture address or
 551  * for IGP TOM base address).
 552  *
 553  * If there is not enough space to fit the unvisible VRAM in the 32bits
 554  * address space then we limit the VRAM size to the aperture.
 555  *
 556  * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
 557  * this shouldn't be a problem as we are using the PCI aperture as a reference.
 558  * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
 559  * not IGP.
 560  *
 561  * Note: we use mc_vram_size as on some board we need to program the mc to
 562  * cover the whole aperture even if VRAM size is inferior to aperture size
 563  * Novell bug 204882 + along with lots of ubuntu ones
 564  *
 565  * Note: when limiting vram it's safe to overwritte real_vram_size because
 566  * we are not in case where real_vram_size is inferior to mc_vram_size (ie
 567  * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
 568  * ones)
 569  *
 570  * Note: IGP TOM addr should be the same as the aperture addr, we don't
 571  * explicitly check for that thought.
 572  *
 573  * FIXME: when reducing VRAM size align new size on power of 2.
 574  */
 575 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base)
 576 {
 577         uint64_t limit = (uint64_t)amdgpu_vram_limit << 20;
 578
 579         mc->vram_start = base;
 580         if (mc->mc_vram_size > (adev->mc.mc_mask - base + 1)) {
 581                 dev_warn(adev->dev, "limiting VRAM to PCI aperture size\n");
 582                 mc->real_vram_size = mc->aper_size;
 583                 mc->mc_vram_size = mc->aper_size;
 584         }
 585         mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
 586         if (limit && limit < mc->real_vram_size)
 587                 mc->real_vram_size = limit;
 588         dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
 589                         mc->mc_vram_size >> 20, mc->vram_start,
 590                         mc->vram_end, mc->real_vram_size >> 20);
 591 }
 592
 593 /**
 594  * amdgpu_gtt_location - try to find GTT location
 595  * @adev: amdgpu device structure holding all necessary informations
 596  * @mc: memory controller structure holding memory informations
 597  *
 598  * Function will place try to place GTT before or after VRAM.
 599  *
 600  * If GTT size is bigger than space left then we ajust GTT size.
 601  * Thus function will never fails.
 602  *
 603  * FIXME: when reducing GTT size align new size on power of 2.
 604  */
 605 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc)
 606 {
 607         u64 size_af, size_bf;
 608
 609         size_af = ((adev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
 610         size_bf = mc->vram_start & ~mc->gtt_base_align;
 611         if (size_bf > size_af) {
 612                 if (mc->gtt_size > size_bf) {
 613                         dev_warn(adev->dev, "limiting GTT\n");
 614                         mc->gtt_size = size_bf;
 615                 }
 616                 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
 617         } else {
 618                 if (mc->gtt_size > size_af) {
 619                         dev_warn(adev->dev, "limiting GTT\n");
 620                         mc->gtt_size = size_af;
 621                 }
 622                 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
 623         }
 624         mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
 625         dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
 626                         mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
 627 }
 628
 629 /*
 630  * GPU helpers function.
 631  */
 632 /**
 633  * amdgpu_card_posted - check if the hw has already been initialized
 634  *
 635  * @adev: amdgpu_device pointer
 636  *
 637  * Check if the asic has been initialized (all asics).
 638  * Used at driver startup.
 639  * Returns true if initialized or false if not.
 640  */
 641 bool amdgpu_card_posted(struct amdgpu_device *adev)
 642 {
 643         uint32_t reg;
 644
 645         /* then check MEM_SIZE, in case the crtcs are off */
 646         reg = RREG32(mmCONFIG_MEMSIZE);
 647
 648         if (reg)
 649                 return true;
 650
 651         return false;
 652
 653 }
 654
 655 static bool amdgpu_vpost_needed(struct amdgpu_device *adev)
 656 {
 657         if (amdgpu_sriov_vf(adev))
 658                 return false;
 659
 660         if (amdgpu_passthrough(adev)) {
 661                 /* for FIJI: In whole GPU pass-through virtualization case
 662                  * old smc fw won't clear some registers (e.g. MEM_SIZE, BIOS_SCRATCH)
 663                  * so amdgpu_card_posted return false and driver will incorrectly skip vPost.
 664                  * but if we force vPost do in pass-through case, the driver reload will hang.
 665                  * whether doing vPost depends on amdgpu_card_posted if smc version is above
 666                  * 00160e00 for FIJI.
 667                  */
 668                 if (adev->asic_type == CHIP_FIJI) {
 669                         int err;
 670                         uint32_t fw_ver;
 671                         err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev);
 672                         /* force vPost if error occured */
 673                         if (err)
 674                                 return true;
 675
 676                         fw_ver = *((uint32_t *)adev->pm.fw->data + 69);
 677                         if (fw_ver >= 0x00160e00)
 678                                 return !amdgpu_card_posted(adev);
 679                 }
 680         } else {
 681                 /* in bare-metal case, amdgpu_card_posted return false
 682                  * after system reboot/boot, and return true if driver
 683                  * reloaded.
 684                  * we shouldn't do vPost after driver reload otherwise GPU
 685                  * could hang.
 686                  */
 687                 if (amdgpu_card_posted(adev))
 688                         return false;
 689         }
 690
 691         /* we assume vPost is neede for all other cases */
 692         return true;
 693 }
 694
 695 /**
 696  * amdgpu_dummy_page_init - init dummy page used by the driver
 697  *
 698  * @adev: amdgpu_device pointer
 699  *
 700  * Allocate the dummy page used by the driver (all asics).
 701  * This dummy page is used by the driver as a filler for gart entries
 702  * when pages are taken out of the GART
 703  * Returns 0 on sucess, -ENOMEM on failure.
 704  */
 705 int amdgpu_dummy_page_init(struct amdgpu_device *adev)
 706 {
 707         if (adev->dummy_page.page)
 708                 return 0;
 709         adev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
 710         if (adev->dummy_page.page == NULL)
 711                 return -ENOMEM;
 712         adev->dummy_page.addr = pci_map_page(adev->pdev, adev->dummy_page.page,
 713                                         0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 714         if (pci_dma_mapping_error(adev->pdev, adev->dummy_page.addr)) {
 715                 dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n");
 716                 __free_page(adev->dummy_page.page);
 717                 adev->dummy_page.page = NULL;
 718                 return -ENOMEM;
 719         }
 720         return 0;
 721 }
 722
 723 /**
 724  * amdgpu_dummy_page_fini - free dummy page used by the driver
 725  *
 726  * @adev: amdgpu_device pointer
 727  *
 728  * Frees the dummy page used by the driver (all asics).
 729  */
 730 void amdgpu_dummy_page_fini(struct amdgpu_device *adev)
 731 {
 732         if (adev->dummy_page.page == NULL)
 733                 return;
 734         pci_unmap_page(adev->pdev, adev->dummy_page.addr,
 735                         PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 736         __free_page(adev->dummy_page.page);
 737         adev->dummy_page.page = NULL;
 738 }
 739
 740
 741 /* ATOM accessor methods */
 742 /*
 743  * ATOM is an interpreted byte code stored in tables in the vbios.  The
 744  * driver registers callbacks to access registers and the interpreter
 745  * in the driver parses the tables and executes then to program specific
 746  * actions (set display modes, asic init, etc.).  See amdgpu_atombios.c,
 747  * atombios.h, and atom.c
 748  */
 749
 750 /**
 751  * cail_pll_read - read PLL register
 752  *
 753  * @info: atom card_info pointer
 754  * @reg: PLL register offset
 755  *
 756  * Provides a PLL register accessor for the atom interpreter (r4xx+).
 757  * Returns the value of the PLL register.
 758  */
 759 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
 760 {
 761         return 0;
 762 }
 763
 764 /**
 765  * cail_pll_write - write PLL register
 766  *
 767  * @info: atom card_info pointer
 768  * @reg: PLL register offset
 769  * @val: value to write to the pll register
 770  *
 771  * Provides a PLL register accessor for the atom interpreter (r4xx+).
 772  */
 773 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
 774 {
 775
 776 }
 777
 778 /**
 779  * cail_mc_read - read MC (Memory Controller) register
 780  *
 781  * @info: atom card_info pointer
 782  * @reg: MC register offset
 783  *
 784  * Provides an MC register accessor for the atom interpreter (r4xx+).
 785  * Returns the value of the MC register.
 786  */
 787 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
 788 {
 789         return 0;
 790 }
 791
 792 /**
 793  * cail_mc_write - write MC (Memory Controller) register
 794  *
 795  * @info: atom card_info pointer
 796  * @reg: MC register offset
 797  * @val: value to write to the pll register
 798  *
 799  * Provides a MC register accessor for the atom interpreter (r4xx+).
 800  */
 801 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
 802 {
 803
 804 }
 805
 806 /**
 807  * cail_reg_write - write MMIO register
 808  *
 809  * @info: atom card_info pointer
 810  * @reg: MMIO register offset
 811  * @val: value to write to the pll register
 812  *
 813  * Provides a MMIO register accessor for the atom interpreter (r4xx+).
 814  */
 815 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
 816 {
 817         struct amdgpu_device *adev = info->dev->dev_private;
 818
 819         WREG32(reg, val);
 820 }
 821
 822 /**
 823  * cail_reg_read - read MMIO register
 824  *
 825  * @info: atom card_info pointer
 826  * @reg: MMIO register offset
 827  *
 828  * Provides an MMIO register accessor for the atom interpreter (r4xx+).
 829  * Returns the value of the MMIO register.
 830  */
 831 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
 832 {
 833         struct amdgpu_device *adev = info->dev->dev_private;
 834         uint32_t r;
 835
 836         r = RREG32(reg);
 837         return r;
 838 }
 839
 840 /**
 841  * cail_ioreg_write - write IO register
 842  *
 843  * @info: atom card_info pointer
 844  * @reg: IO register offset
 845  * @val: value to write to the pll register
 846  *
 847  * Provides a IO register accessor for the atom interpreter (r4xx+).
 848  */
 849 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
 850 {
 851         struct amdgpu_device *adev = info->dev->dev_private;
 852
 853         WREG32_IO(reg, val);
 854 }
 855
 856 /**
 857  * cail_ioreg_read - read IO register
 858  *
 859  * @info: atom card_info pointer
 860  * @reg: IO register offset
 861  *
 862  * Provides an IO register accessor for the atom interpreter (r4xx+).
 863  * Returns the value of the IO register.
 864  */
 865 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
 866 {
 867         struct amdgpu_device *adev = info->dev->dev_private;
 868         uint32_t r;
 869
 870         r = RREG32_IO(reg);
 871         return r;
 872 }
 873
 874 /**
 875  * amdgpu_atombios_fini - free the driver info and callbacks for atombios
 876  *
 877  * @adev: amdgpu_device pointer
 878  *
 879  * Frees the driver info and register access callbacks for the ATOM
 880  * interpreter (r4xx+).
 881  * Called at driver shutdown.
 882  */
 883 static void amdgpu_atombios_fini(struct amdgpu_device *adev)
 884 {
 885         if (adev->mode_info.atom_context) {
 886                 kfree(adev->mode_info.atom_context->scratch);
 887                 kfree(adev->mode_info.atom_context->iio);
 888         }
 889         kfree(adev->mode_info.atom_context);
 890         adev->mode_info.atom_context = NULL;
 891         kfree(adev->mode_info.atom_card_info);
 892         adev->mode_info.atom_card_info = NULL;
 893 }
 894
 895 /**
 896  * amdgpu_atombios_init - init the driver info and callbacks for atombios
 897  *
 898  * @adev: amdgpu_device pointer
 899  *
 900  * Initializes the driver info and register access callbacks for the
 901  * ATOM interpreter (r4xx+).
 902  * Returns 0 on sucess, -ENOMEM on failure.
 903  * Called at driver startup.
 904  */
 905 static int amdgpu_atombios_init(struct amdgpu_device *adev)
 906 {
 907         struct card_info *atom_card_info =
 908             kzalloc(sizeof(struct card_info), GFP_KERNEL);
 909
 910         if (!atom_card_info)
 911                 return -ENOMEM;
 912
 913         adev->mode_info.atom_card_info = atom_card_info;
 914         atom_card_info->dev = adev->ddev;
 915         atom_card_info->reg_read = cail_reg_read;
 916         atom_card_info->reg_write = cail_reg_write;
 917         /* needed for iio ops */
 918         if (adev->rio_mem) {
 919                 atom_card_info->ioreg_read = cail_ioreg_read;
 920                 atom_card_info->ioreg_write = cail_ioreg_write;
 921         } else {
 922                 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
 923                 atom_card_info->ioreg_read = cail_reg_read;
 924                 atom_card_info->ioreg_write = cail_reg_write;
 925         }
 926         atom_card_info->mc_read = cail_mc_read;
 927         atom_card_info->mc_write = cail_mc_write;
 928         atom_card_info->pll_read = cail_pll_read;
 929         atom_card_info->pll_write = cail_pll_write;
 930
 931         adev->mode_info.atom_context = amdgpu_atom_parse(atom_card_info, adev->bios);
 932         if (!adev->mode_info.atom_context) {
 933                 amdgpu_atombios_fini(adev);
 934                 return -ENOMEM;
 935         }
 936
 937         mutex_init(&adev->mode_info.atom_context->mutex);
 938         amdgpu_atombios_scratch_regs_init(adev);
 939         amdgpu_atom_allocate_fb_scratch(adev->mode_info.atom_context);
 940         return 0;
 941 }
 942
 943 /* if we get transitioned to only one device, take VGA back */
 944 /**
 945  * amdgpu_vga_set_decode - enable/disable vga decode
 946  *
 947  * @cookie: amdgpu_device pointer
 948  * @state: enable/disable vga decode
 949  *
 950  * Enable/disable vga decode (all asics).
 951  * Returns VGA resource flags.
 952  */
 953 static unsigned int amdgpu_vga_set_decode(void *cookie, bool state)
 954 {
 955         struct amdgpu_device *adev = cookie;
 956         amdgpu_asic_set_vga_state(adev, state);
 957         if (state)
 958                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 959                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 960         else
 961                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 962 }
 963
 964 /**
 965  * amdgpu_check_pot_argument - check that argument is a power of two
 966  *
 967  * @arg: value to check
 968  *
 969  * Validates that a certain argument is a power of two (all asics).
 970  * Returns true if argument is valid.
 971  */
 972 static bool amdgpu_check_pot_argument(int arg)
 973 {
 974         return (arg & (arg - 1)) == 0;
 975 }
 976
 977 /**
 978  * amdgpu_check_arguments - validate module params
 979  *
 980  * @adev: amdgpu_device pointer
 981  *
 982  * Validates certain module parameters and updates
 983  * the associated values used by the driver (all asics).
 984  */
 985 static void amdgpu_check_arguments(struct amdgpu_device *adev)
 986 {
 987         if (amdgpu_sched_jobs < 4) {
 988                 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
 989                          amdgpu_sched_jobs);
 990                 amdgpu_sched_jobs = 4;
 991         } else if (!amdgpu_check_pot_argument(amdgpu_sched_jobs)){
 992                 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
 993                          amdgpu_sched_jobs);
 994                 amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
 995         }
 996
 997         if (amdgpu_gart_size != -1) {
 998                 /* gtt size must be greater or equal to 32M */
 999                 if (amdgpu_gart_size < 32) {
1000                         dev_warn(adev->dev, "gart size (%d) too small\n",
1001                                  amdgpu_gart_size);
1002                         amdgpu_gart_size = -1;
1003                 }
1004         }
1005
1006         if (!amdgpu_check_pot_argument(amdgpu_vm_size)) {
1007                 dev_warn(adev->dev, "VM size (%d) must be a power of 2\n",
1008                          amdgpu_vm_size);
1009                 amdgpu_vm_size = 8;
1010         }
1011
1012         if (amdgpu_vm_size < 1) {
1013                 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
1014                          amdgpu_vm_size);
1015                 amdgpu_vm_size = 8;
1016         }
1017
1018         /*
1019          * Max GPUVM size for Cayman, SI and CI are 40 bits.
1020          */
1021         if (amdgpu_vm_size > 1024) {
1022                 dev_warn(adev->dev, "VM size (%d) too large, max is 1TB\n",
1023                          amdgpu_vm_size);
1024                 amdgpu_vm_size = 8;
1025         }
1026
1027         /* defines number of bits in page table versus page directory,
1028          * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1029          * page table and the remaining bits are in the page directory */
1030         if (amdgpu_vm_block_size == -1) {
1031
1032                 /* Total bits covered by PD + PTs */
1033                 unsigned bits = ilog2(amdgpu_vm_size) + 18;
1034
1035                 /* Make sure the PD is 4K in size up to 8GB address space.
1036                    Above that split equal between PD and PTs */
1037                 if (amdgpu_vm_size <= 8)
1038                         amdgpu_vm_block_size = bits - 9;
1039                 else
1040                         amdgpu_vm_block_size = (bits + 3) / 2;
1041
1042         } else if (amdgpu_vm_block_size < 9) {
1043                 dev_warn(adev->dev, "VM page table size (%d) too small\n",
1044                          amdgpu_vm_block_size);
1045                 amdgpu_vm_block_size = 9;
1046         }
1047
1048         if (amdgpu_vm_block_size > 24 ||
1049             (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) {
1050                 dev_warn(adev->dev, "VM page table size (%d) too large\n",
1051                          amdgpu_vm_block_size);
1052                 amdgpu_vm_block_size = 9;
1053         }
1054 }
1055
1056 /**
1057  * amdgpu_switcheroo_set_state - set switcheroo state
1058  *
1059  * @pdev: pci dev pointer
1060  * @state: vga_switcheroo state
1061  *
1062  * Callback for the switcheroo driver.  Suspends or resumes the
1063  * the asics before or after it is powered up using ACPI methods.
1064  */
1065 static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1066 {
1067         struct drm_device *dev = pci_get_drvdata(pdev);
1068
1069         if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF)
1070                 return;
1071
1072         if (state == VGA_SWITCHEROO_ON) {
1073                 unsigned d3_delay = dev->pdev->d3_delay;
1074
1075                 printk(KERN_INFO "amdgpu: switched on\n");
1076                 /* don't suspend or resume card normally */
1077                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1078
1079                 amdgpu_device_resume(dev, true, true);
1080
1081                 dev->pdev->d3_delay = d3_delay;
1082
1083                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1084                 drm_kms_helper_poll_enable(dev);
1085         } else {
1086                 printk(KERN_INFO "amdgpu: switched off\n");
1087                 drm_kms_helper_poll_disable(dev);
1088                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1089                 amdgpu_device_suspend(dev, true, true);
1090                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1091         }
1092 }
1093
1094 /**
1095  * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1096  *
1097  * @pdev: pci dev pointer
1098  *
1099  * Callback for the switcheroo driver.  Check of the switcheroo
1100  * state can be changed.
1101  * Returns true if the state can be changed, false if not.
1102  */
1103 static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
1104 {
1105         struct drm_device *dev = pci_get_drvdata(pdev);
1106
1107         /*
1108         * FIXME: open_count is protected by drm_global_mutex but that would lead to
1109         * locking inversion with the driver load path. And the access here is
1110         * completely racy anyway. So don't bother with locking for now.
1111         */
1112         return dev->open_count == 0;
1113 }
1114
1115 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1116         .set_gpu_state = amdgpu_switcheroo_set_state,
1117         .reprobe = NULL,
1118         .can_switch = amdgpu_switcheroo_can_switch,
1119 };
1120
1121 int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
1122                                   enum amd_ip_block_type block_type,
1123                                   enum amd_clockgating_state state)
1124 {
1125         int i, r = 0;
1126
1127         for (i = 0; i < adev->num_ip_blocks; i++) {
1128                 if (!adev->ip_block_status[i].valid)
1129                         continue;
1130                 if (adev->ip_blocks[i].type == block_type) {
1131                         r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1132                                                                             state);
1133                         if (r)
1134                                 return r;
1135                         break;
1136                 }
1137         }
1138         return r;
1139 }
1140
1141 int amdgpu_set_powergating_state(struct amdgpu_device *adev,
1142                                   enum amd_ip_block_type block_type,
1143                                   enum amd_powergating_state state)
1144 {
1145         int i, r = 0;
1146
1147         for (i = 0; i < adev->num_ip_blocks; i++) {
1148                 if (!adev->ip_block_status[i].valid)
1149                         continue;
1150                 if (adev->ip_blocks[i].type == block_type) {
1151                         r = adev->ip_blocks[i].funcs->set_powergating_state((void *)adev,
1152                                                                             state);
1153                         if (r)
1154                                 return r;
1155                         break;
1156                 }
1157         }
1158         return r;
1159 }
1160
1161 int amdgpu_wait_for_idle(struct amdgpu_device *adev,
1162                          enum amd_ip_block_type block_type)
1163 {
1164         int i, r;
1165
1166         for (i = 0; i < adev->num_ip_blocks; i++) {
1167                 if (!adev->ip_block_status[i].valid)
1168                         continue;
1169                 if (adev->ip_blocks[i].type == block_type) {
1170                         r = adev->ip_blocks[i].funcs->wait_for_idle((void *)adev);
1171                         if (r)
1172                                 return r;
1173                         break;
1174                 }
1175         }
1176         return 0;
1177
1178 }
1179
1180 bool amdgpu_is_idle(struct amdgpu_device *adev,
1181                     enum amd_ip_block_type block_type)
1182 {
1183         int i;
1184
1185         for (i = 0; i < adev->num_ip_blocks; i++) {
1186                 if (!adev->ip_block_status[i].valid)
1187                         continue;
1188                 if (adev->ip_blocks[i].type == block_type)
1189                         return adev->ip_blocks[i].funcs->is_idle((void *)adev);
1190         }
1191         return true;
1192
1193 }
1194
1195 const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
1196                                         struct amdgpu_device *adev,
1197                                         enum amd_ip_block_type type)
1198 {
1199         int i;
1200
1201         for (i = 0; i < adev->num_ip_blocks; i++)
1202                 if (adev->ip_blocks[i].type == type)
1203                         return &adev->ip_blocks[i];
1204
1205         return NULL;
1206 }
1207
1208 /**
1209  * amdgpu_ip_block_version_cmp
1210  *
1211  * @adev: amdgpu_device pointer
1212  * @type: enum amd_ip_block_type
1213  * @major: major version
1214  * @minor: minor version
1215  *
1216  * return 0 if equal or greater
1217  * return 1 if smaller or the ip_block doesn't exist
1218  */
1219 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
1220                                 enum amd_ip_block_type type,
1221                                 u32 major, u32 minor)
1222 {
1223         const struct amdgpu_ip_block_version *ip_block;
1224         ip_block = amdgpu_get_ip_block(adev, type);
1225
1226         if (ip_block && ((ip_block->major > major) ||
1227                         ((ip_block->major == major) &&
1228                         (ip_block->minor >= minor))))
1229                 return 0;
1230
1231         return 1;
1232 }
1233
1234 static void amdgpu_whether_enable_virtual_display(struct amdgpu_device *adev)
1235 {
1236         adev->enable_virtual_display = false;
1237
1238         if (amdgpu_virtual_display) {
1239                 struct drm_device *ddev = adev->ddev;
1240                 const char *pci_address_name = pci_name(ddev->pdev);
1241                 char *pciaddstr, *pciaddstr_tmp, *pciaddname;
1242
1243                 pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL);
1244                 pciaddstr_tmp = pciaddstr;
1245                 while ((pciaddname = strsep(&pciaddstr_tmp, ";"))) {
1246                         if (!strcmp(pci_address_name, pciaddname)) {
1247                                 adev->enable_virtual_display = true;
1248                                 break;
1249                         }
1250                 }
1251
1252                 DRM_INFO("virtual display string:%s, %s:virtual_display:%d\n",
1253                                  amdgpu_virtual_display, pci_address_name,
1254                                  adev->enable_virtual_display);
1255
1256                 kfree(pciaddstr);
1257         }
1258 }
1259
1260 static int amdgpu_early_init(struct amdgpu_device *adev)
1261 {
1262         int i, r;
1263
1264         amdgpu_whether_enable_virtual_display(adev);
1265
1266         switch (adev->asic_type) {
1267         case CHIP_TOPAZ:
1268         case CHIP_TONGA:
1269         case CHIP_FIJI:
1270         case CHIP_POLARIS11:
1271         case CHIP_POLARIS10:
1272         case CHIP_CARRIZO:
1273         case CHIP_STONEY:
1274                 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY)
1275                         adev->family = AMDGPU_FAMILY_CZ;
1276                 else
1277                         adev->family = AMDGPU_FAMILY_VI;
1278
1279                 r = vi_set_ip_blocks(adev);
1280                 if (r)
1281                         return r;
1282                 break;
1283 #ifdef CONFIG_DRM_AMDGPU_SI
1284         case CHIP_VERDE:
1285         case CHIP_TAHITI:
1286         case CHIP_PITCAIRN:
1287         case CHIP_OLAND:
1288         case CHIP_HAINAN:
1289                 adev->family = AMDGPU_FAMILY_SI;
1290                 r = si_set_ip_blocks(adev);
1291                 if (r)
1292                         return r;
1293                 break;
1294 #endif
1295 #ifdef CONFIG_DRM_AMDGPU_CIK
1296         case CHIP_BONAIRE:
1297         case CHIP_HAWAII:
1298         case CHIP_KAVERI:
1299         case CHIP_KABINI:
1300         case CHIP_MULLINS:
1301                 if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII))
1302                         adev->family = AMDGPU_FAMILY_CI;
1303                 else
1304                         adev->family = AMDGPU_FAMILY_KV;
1305
1306                 r = cik_set_ip_blocks(adev);
1307                 if (r)
1308                         return r;
1309                 break;
1310 #endif
1311         default:
1312                 /* FIXME: not supported yet */
1313                 return -EINVAL;
1314         }
1315
1316         adev->ip_block_status = kcalloc(adev->num_ip_blocks,
1317                                         sizeof(struct amdgpu_ip_block_status), GFP_KERNEL);
1318         if (adev->ip_block_status == NULL)
1319                 return -ENOMEM;
1320
1321         if (adev->ip_blocks == NULL) {
1322                 DRM_ERROR("No IP blocks found!\n");
1323                 return r;
1324         }
1325
1326         for (i = 0; i < adev->num_ip_blocks; i++) {
1327                 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
1328                         DRM_ERROR("disabled ip block: %d\n", i);
1329                         adev->ip_block_status[i].valid = false;
1330                 } else {
1331                         if (adev->ip_blocks[i].funcs->early_init) {
1332                                 r = adev->ip_blocks[i].funcs->early_init((void *)adev);
1333                                 if (r == -ENOENT) {
1334                                         adev->ip_block_status[i].valid = false;
1335                                 } else if (r) {
1336                                         DRM_ERROR("early_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1337                                         return r;
1338                                 } else {
1339                                         adev->ip_block_status[i].valid = true;
1340                                 }
1341                         } else {
1342                                 adev->ip_block_status[i].valid = true;
1343                         }
1344                 }
1345         }
1346
1347         adev->cg_flags &= amdgpu_cg_mask;
1348         adev->pg_flags &= amdgpu_pg_mask;
1349
1350         return 0;
1351 }
1352
1353 static int amdgpu_init(struct amdgpu_device *adev)
1354 {
1355         int i, r;
1356
1357         for (i = 0; i < adev->num_ip_blocks; i++) {
1358                 if (!adev->ip_block_status[i].valid)
1359                         continue;
1360                 r = adev->ip_blocks[i].funcs->sw_init((void *)adev);
1361                 if (r) {
1362                         DRM_ERROR("sw_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1363                         return r;
1364                 }
1365                 adev->ip_block_status[i].sw = true;
1366                 /* need to do gmc hw init early so we can allocate gpu mem */
1367                 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) {
1368                         r = amdgpu_vram_scratch_init(adev);
1369                         if (r) {
1370                                 DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
1371                                 return r;
1372                         }
1373                         r = adev->ip_blocks[i].funcs->hw_init((void *)adev);
1374                         if (r) {
1375                                 DRM_ERROR("hw_init %d failed %d\n", i, r);
1376                                 return r;
1377                         }
1378                         r = amdgpu_wb_init(adev);
1379                         if (r) {
1380                                 DRM_ERROR("amdgpu_wb_init failed %d\n", r);
1381                                 return r;
1382                         }
1383                         adev->ip_block_status[i].hw = true;
1384                 }
1385         }
1386
1387         for (i = 0; i < adev->num_ip_blocks; i++) {
1388                 if (!adev->ip_block_status[i].sw)
1389                         continue;
1390                 /* gmc hw init is done early */
1391                 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC)
1392                         continue;
1393                 r = adev->ip_blocks[i].funcs->hw_init((void *)adev);
1394                 if (r) {
1395                         DRM_ERROR("hw_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1396                         return r;
1397                 }
1398                 adev->ip_block_status[i].hw = true;
1399         }
1400
1401         return 0;
1402 }
1403
1404 static int amdgpu_late_init(struct amdgpu_device *adev)
1405 {
1406         int i = 0, r;
1407
1408         for (i = 0; i < adev->num_ip_blocks; i++) {
1409                 if (!adev->ip_block_status[i].valid)
1410                         continue;
1411                 if (adev->ip_blocks[i].funcs->late_init) {
1412                         r = adev->ip_blocks[i].funcs->late_init((void *)adev);
1413                         if (r) {
1414                                 DRM_ERROR("late_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1415                                 return r;
1416                         }
1417                         adev->ip_block_status[i].late_initialized = true;
1418                 }
1419                 /* skip CG for VCE/UVD, it's handled specially */
1420                 if (adev->ip_blocks[i].type != AMD_IP_BLOCK_TYPE_UVD &&
1421                     adev->ip_blocks[i].type != AMD_IP_BLOCK_TYPE_VCE) {
1422                         /* enable clockgating to save power */
1423                         r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1424                                                                             AMD_CG_STATE_GATE);
1425                         if (r) {
1426                                 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
1427                                           adev->ip_blocks[i].funcs->name, r);
1428                                 return r;
1429                         }
1430                 }
1431         }
1432
1433         return 0;
1434 }
1435
1436 static int amdgpu_fini(struct amdgpu_device *adev)
1437 {
1438         int i, r;
1439
1440         /* need to disable SMC first */
1441         for (i = 0; i < adev->num_ip_blocks; i++) {
1442                 if (!adev->ip_block_status[i].hw)
1443                         continue;
1444                 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_SMC) {
1445                         /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1446                         r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1447                                                                             AMD_CG_STATE_UNGATE);
1448                         if (r) {
1449                                 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1450                                           adev->ip_blocks[i].funcs->name, r);
1451                                 return r;
1452                         }
1453                         r = adev->ip_blocks[i].funcs->hw_fini((void *)adev);
1454                         /* XXX handle errors */
1455                         if (r) {
1456                                 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
1457                                           adev->ip_blocks[i].funcs->name, r);
1458                         }
1459                         adev->ip_block_status[i].hw = false;
1460                         break;
1461                 }
1462         }
1463
1464         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1465                 if (!adev->ip_block_status[i].hw)
1466                         continue;
1467                 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) {
1468                         amdgpu_wb_fini(adev);
1469                         amdgpu_vram_scratch_fini(adev);
1470                 }
1471                 /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1472                 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1473                                                                     AMD_CG_STATE_UNGATE);
1474                 if (r) {
1475                         DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1476                         return r;
1477                 }
1478                 r = adev->ip_blocks[i].funcs->hw_fini((void *)adev);
1479                 /* XXX handle errors */
1480                 if (r) {
1481                         DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1482                 }
1483                 adev->ip_block_status[i].hw = false;
1484         }
1485
1486         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1487                 if (!adev->ip_block_status[i].sw)
1488                         continue;
1489                 r = adev->ip_blocks[i].funcs->sw_fini((void *)adev);
1490                 /* XXX handle errors */
1491                 if (r) {
1492                         DRM_DEBUG("sw_fini of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1493                 }
1494                 adev->ip_block_status[i].sw = false;
1495                 adev->ip_block_status[i].valid = false;
1496         }
1497
1498         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1499                 if (!adev->ip_block_status[i].late_initialized)
1500                         continue;
1501                 if (adev->ip_blocks[i].funcs->late_fini)
1502                         adev->ip_blocks[i].funcs->late_fini((void *)adev);
1503                 adev->ip_block_status[i].late_initialized = false;
1504         }
1505
1506         return 0;
1507 }
1508
1509 static int amdgpu_suspend(struct amdgpu_device *adev)
1510 {
1511         int i, r;
1512
1513         /* ungate SMC block first */
1514         r = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC,
1515                                          AMD_CG_STATE_UNGATE);
1516         if (r) {
1517                 DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n",r);
1518         }
1519
1520         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1521                 if (!adev->ip_block_status[i].valid)
1522                         continue;
1523                 /* ungate blocks so that suspend can properly shut them down */
1524                 if (i != AMD_IP_BLOCK_TYPE_SMC) {
1525                         r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1526                                                                             AMD_CG_STATE_UNGATE);
1527                         if (r) {
1528                                 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1529                         }
1530                 }
1531                 /* XXX handle errors */
1532                 r = adev->ip_blocks[i].funcs->suspend(adev);
1533                 /* XXX handle errors */
1534                 if (r) {
1535                         DRM_ERROR("suspend of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1536                 }
1537         }
1538
1539         return 0;
1540 }
1541
1542 static int amdgpu_resume(struct amdgpu_device *adev)
1543 {
1544         int i, r;
1545
1546         for (i = 0; i < adev->num_ip_blocks; i++) {
1547                 if (!adev->ip_block_status[i].valid)
1548                         continue;
1549                 r = adev->ip_blocks[i].funcs->resume(adev);
1550                 if (r) {
1551                         DRM_ERROR("resume of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1552                         return r;
1553                 }
1554         }
1555
1556         return 0;
1557 }
1558
1559 static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)
1560 {
1561         if (amdgpu_atombios_has_gpu_virtualization_table(adev))
1562                 adev->virtualization.virtual_caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
1563 }
1564
1565 /**
1566  * amdgpu_device_init - initialize the driver
1567  *
1568  * @adev: amdgpu_device pointer
1569  * @pdev: drm dev pointer
1570  * @pdev: pci dev pointer
1571  * @flags: driver flags
1572  *
1573  * Initializes the driver info and hw (all asics).
1574  * Returns 0 for success or an error on failure.
1575  * Called at driver startup.
1576  */
1577 int amdgpu_device_init(struct amdgpu_device *adev,
1578                        struct drm_device *ddev,
1579                        struct pci_dev *pdev,
1580                        uint32_t flags)
1581 {
1582         int r, i;
1583         bool runtime = false;
1584         u32 max_MBps;
1585
1586         adev->shutdown = false;
1587         adev->dev = &pdev->dev;
1588         adev->ddev = ddev;
1589         adev->pdev = pdev;
1590         adev->flags = flags;
1591         adev->asic_type = flags & AMD_ASIC_MASK;
1592         adev->is_atom_bios = false;
1593         adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
1594         adev->mc.gtt_size = 512 * 1024 * 1024;
1595         adev->accel_working = false;
1596         adev->num_rings = 0;
1597         adev->mman.buffer_funcs = NULL;
1598         adev->mman.buffer_funcs_ring = NULL;
1599         adev->vm_manager.vm_pte_funcs = NULL;
1600         adev->vm_manager.vm_pte_num_rings = 0;
1601         adev->gart.gart_funcs = NULL;
1602         adev->fence_context = fence_context_alloc(AMDGPU_MAX_RINGS);
1603
1604         adev->smc_rreg = &amdgpu_invalid_rreg;
1605         adev->smc_wreg = &amdgpu_invalid_wreg;
1606         adev->pcie_rreg = &amdgpu_invalid_rreg;
1607         adev->pcie_wreg = &amdgpu_invalid_wreg;
1608         adev->pciep_rreg = &amdgpu_invalid_rreg;
1609         adev->pciep_wreg = &amdgpu_invalid_wreg;
1610         adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
1611         adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
1612         adev->didt_rreg = &amdgpu_invalid_rreg;
1613         adev->didt_wreg = &amdgpu_invalid_wreg;
1614         adev->gc_cac_rreg = &amdgpu_invalid_rreg;
1615         adev->gc_cac_wreg = &amdgpu_invalid_wreg;
1616         adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
1617         adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
1618
1619
1620         DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
1621                  amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
1622                  pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
1623
1624         /* mutex initialization are all done here so we
1625          * can recall function without having locking issues */
1626         mutex_init(&adev->vm_manager.lock);
1627         atomic_set(&adev->irq.ih.lock, 0);
1628         mutex_init(&adev->pm.mutex);
1629         mutex_init(&adev->gfx.gpu_clock_mutex);
1630         mutex_init(&adev->srbm_mutex);
1631         mutex_init(&adev->grbm_idx_mutex);
1632         mutex_init(&adev->mn_lock);
1633         hash_init(adev->mn_hash);
1634
1635         amdgpu_check_arguments(adev);
1636
1637         /* Registers mapping */
1638         /* TODO: block userspace mapping of io register */
1639         spin_lock_init(&adev->mmio_idx_lock);
1640         spin_lock_init(&adev->smc_idx_lock);
1641         spin_lock_init(&adev->pcie_idx_lock);
1642         spin_lock_init(&adev->uvd_ctx_idx_lock);
1643         spin_lock_init(&adev->didt_idx_lock);
1644         spin_lock_init(&adev->gc_cac_idx_lock);
1645         spin_lock_init(&adev->audio_endpt_idx_lock);
1646         spin_lock_init(&adev->mm_stats.lock);
1647
1648         INIT_LIST_HEAD(&adev->shadow_list);
1649         mutex_init(&adev->shadow_list_lock);
1650
1651         INIT_LIST_HEAD(&adev->gtt_list);
1652         spin_lock_init(&adev->gtt_list_lock);
1653
1654         if (adev->asic_type >= CHIP_BONAIRE) {
1655                 adev->rmmio_base = pci_resource_start(adev->pdev, 5);
1656                 adev->rmmio_size = pci_resource_len(adev->pdev, 5);
1657         } else {
1658                 adev->rmmio_base = pci_resource_start(adev->pdev, 2);
1659                 adev->rmmio_size = pci_resource_len(adev->pdev, 2);
1660         }
1661
1662         adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
1663         if (adev->rmmio == NULL) {
1664                 return -ENOMEM;
1665         }
1666         DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
1667         DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
1668
1669         if (adev->asic_type >= CHIP_BONAIRE)
1670                 /* doorbell bar mapping */
1671                 amdgpu_doorbell_init(adev);
1672
1673         /* io port mapping */
1674         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1675                 if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) {
1676                         adev->rio_mem_size = pci_resource_len(adev->pdev, i);
1677                         adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size);
1678                         break;
1679                 }
1680         }
1681         if (adev->rio_mem == NULL)
1682                 DRM_ERROR("Unable to find PCI I/O BAR\n");
1683
1684         /* early init functions */
1685         r = amdgpu_early_init(adev);
1686         if (r)
1687                 return r;
1688
1689         /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
1690         /* this will fail for cards that aren't VGA class devices, just
1691          * ignore it */
1692         vga_client_register(adev->pdev, adev, NULL, amdgpu_vga_set_decode);
1693
1694         if (amdgpu_runtime_pm == 1)
1695                 runtime = true;
1696         if (amdgpu_device_is_px(ddev))
1697                 runtime = true;
1698         vga_switcheroo_register_client(adev->pdev, &amdgpu_switcheroo_ops, runtime);
1699         if (runtime)
1700                 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
1701
1702         /* Read BIOS */
1703         if (!amdgpu_get_bios(adev)) {
1704                 r = -EINVAL;
1705                 goto failed;
1706         }
1707         /* Must be an ATOMBIOS */
1708         if (!adev->is_atom_bios) {
1709                 dev_err(adev->dev, "Expecting atombios for GPU\n");
1710                 r = -EINVAL;
1711                 goto failed;
1712         }
1713         r = amdgpu_atombios_init(adev);
1714         if (r) {
1715                 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
1716                 goto failed;
1717         }
1718
1719         /* detect if we are with an SRIOV vbios */
1720         amdgpu_device_detect_sriov_bios(adev);
1721
1722         /* Post card if necessary */
1723         if (amdgpu_vpost_needed(adev)) {
1724                 if (!adev->bios) {
1725                         dev_err(adev->dev, "no vBIOS found\n");
1726                         r = -EINVAL;
1727                         goto failed;
1728                 }
1729                 DRM_INFO("GPU posting now...\n");
1730                 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
1731                 if (r) {
1732                         dev_err(adev->dev, "gpu post error!\n");
1733                         goto failed;
1734                 }
1735         } else {
1736                 DRM_INFO("GPU post is not needed\n");
1737         }
1738
1739         /* Initialize clocks */
1740         r = amdgpu_atombios_get_clock_info(adev);
1741         if (r) {
1742                 dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
1743                 goto failed;
1744         }
1745         /* init i2c buses */
1746         amdgpu_atombios_i2c_init(adev);
1747
1748         /* Fence driver */
1749         r = amdgpu_fence_driver_init(adev);
1750         if (r) {
1751                 dev_err(adev->dev, "amdgpu_fence_driver_init failed\n");
1752                 goto failed;
1753         }
1754
1755         /* init the mode config */
1756         drm_mode_config_init(adev->ddev);
1757
1758         r = amdgpu_init(adev);
1759         if (r) {
1760                 dev_err(adev->dev, "amdgpu_init failed\n");
1761                 amdgpu_fini(adev);
1762                 goto failed;
1763         }
1764
1765         adev->accel_working = true;
1766
1767         /* Initialize the buffer migration limit. */
1768         if (amdgpu_moverate >= 0)
1769                 max_MBps = amdgpu_moverate;
1770         else
1771                 max_MBps = 8; /* Allow 8 MB/s. */
1772         /* Get a log2 for easy divisions. */
1773         adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
1774
1775         amdgpu_fbdev_init(adev);
1776
1777         r = amdgpu_ib_pool_init(adev);
1778         if (r) {
1779                 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
1780                 goto failed;
1781         }
1782
1783         r = amdgpu_ib_ring_tests(adev);
1784         if (r)
1785                 DRM_ERROR("ib ring test failed (%d).\n", r);
1786
1787         r = amdgpu_gem_debugfs_init(adev);
1788         if (r) {
1789                 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
1790         }
1791
1792         r = amdgpu_debugfs_regs_init(adev);
1793         if (r) {
1794                 DRM_ERROR("registering register debugfs failed (%d).\n", r);
1795         }
1796
1797         r = amdgpu_debugfs_firmware_init(adev);
1798         if (r) {
1799                 DRM_ERROR("registering firmware debugfs failed (%d).\n", r);
1800                 return r;
1801         }
1802
1803         if ((amdgpu_testing & 1)) {
1804                 if (adev->accel_working)
1805                         amdgpu_test_moves(adev);
1806                 else
1807                         DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
1808         }
1809         if ((amdgpu_testing & 2)) {
1810                 if (adev->accel_working)
1811                         amdgpu_test_syncing(adev);
1812                 else
1813                         DRM_INFO("amdgpu: acceleration disabled, skipping sync tests\n");
1814         }
1815         if (amdgpu_benchmarking) {
1816                 if (adev->accel_working)
1817                         amdgpu_benchmark(adev, amdgpu_benchmarking);
1818                 else
1819                         DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
1820         }
1821
1822         /* enable clockgating, etc. after ib tests, etc. since some blocks require
1823          * explicit gating rather than handling it automatically.
1824          */
1825         r = amdgpu_late_init(adev);
1826         if (r) {
1827                 dev_err(adev->dev, "amdgpu_late_init failed\n");
1828                 goto failed;
1829         }
1830
1831         return 0;
1832
1833 failed:
1834         if (runtime)
1835                 vga_switcheroo_fini_domain_pm_ops(adev->dev);
1836         return r;
1837 }
1838
1839 static void amdgpu_debugfs_remove_files(struct amdgpu_device *adev);
1840
1841 /**
1842  * amdgpu_device_fini - tear down the driver
1843  *
1844  * @adev: amdgpu_device pointer
1845  *
1846  * Tear down the driver info (all asics).
1847  * Called at driver shutdown.
1848  */
1849 void amdgpu_device_fini(struct amdgpu_device *adev)
1850 {
1851         int r;
1852
1853         DRM_INFO("amdgpu: finishing device.\n");
1854         adev->shutdown = true;
1855         drm_crtc_force_disable_all(adev->ddev);
1856         /* evict vram memory */
1857         amdgpu_bo_evict_vram(adev);
1858         amdgpu_ib_pool_fini(adev);
1859         amdgpu_fence_driver_fini(adev);
1860         amdgpu_fbdev_fini(adev);
1861         r = amdgpu_fini(adev);
1862         kfree(adev->ip_block_status);
1863         adev->ip_block_status = NULL;
1864         adev->accel_working = false;
1865         /* free i2c buses */
1866         amdgpu_i2c_fini(adev);
1867         amdgpu_atombios_fini(adev);
1868         kfree(adev->bios);
1869         adev->bios = NULL;
1870         vga_switcheroo_unregister_client(adev->pdev);
1871         if (adev->flags & AMD_IS_PX)
1872                 vga_switcheroo_fini_domain_pm_ops(adev->dev);
1873         vga_client_register(adev->pdev, NULL, NULL, NULL);
1874         if (adev->rio_mem)
1875                 pci_iounmap(adev->pdev, adev->rio_mem);
1876         adev->rio_mem = NULL;
1877         iounmap(adev->rmmio);
1878         adev->rmmio = NULL;
1879         if (adev->asic_type >= CHIP_BONAIRE)
1880                 amdgpu_doorbell_fini(adev);
1881         amdgpu_debugfs_regs_cleanup(adev);
1882         amdgpu_debugfs_remove_files(adev);
1883 }
1884
1885
1886 /*
1887  * Suspend & resume.
1888  */
1889 /**
1890  * amdgpu_device_suspend - initiate device suspend
1891  *
1892  * @pdev: drm dev pointer
1893  * @state: suspend state
1894  *
1895  * Puts the hw in the suspend state (all asics).
1896  * Returns 0 for success or an error on failure.
1897  * Called at driver suspend.
1898  */
1899 int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon)
1900 {
1901         struct amdgpu_device *adev;
1902         struct drm_crtc *crtc;
1903         struct drm_connector *connector;
1904         int r;
1905
1906         if (dev == NULL || dev->dev_private == NULL) {
1907                 return -ENODEV;
1908         }
1909
1910         adev = dev->dev_private;
1911
1912         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1913                 return 0;
1914
1915         drm_kms_helper_poll_disable(dev);
1916
1917         /* turn off display hw */
1918         drm_modeset_lock_all(dev);
1919         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1920                 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
1921         }
1922         drm_modeset_unlock_all(dev);
1923
1924         /* unpin the front buffers and cursors */
1925         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1926                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1927                 struct amdgpu_framebuffer *rfb = to_amdgpu_framebuffer(crtc->primary->fb);
1928                 struct amdgpu_bo *robj;
1929
1930                 if (amdgpu_crtc->cursor_bo) {
1931                         struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
1932                         r = amdgpu_bo_reserve(aobj, false);
1933                         if (r == 0) {
1934                                 amdgpu_bo_unpin(aobj);
1935                                 amdgpu_bo_unreserve(aobj);
1936                         }
1937                 }
1938
1939                 if (rfb == NULL || rfb->obj == NULL) {
1940                         continue;
1941                 }
1942                 robj = gem_to_amdgpu_bo(rfb->obj);
1943                 /* don't unpin kernel fb objects */
1944                 if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
1945                         r = amdgpu_bo_reserve(robj, false);
1946                         if (r == 0) {
1947                                 amdgpu_bo_unpin(robj);
1948                                 amdgpu_bo_unreserve(robj);
1949                         }
1950                 }
1951         }
1952         /* evict vram memory */
1953         amdgpu_bo_evict_vram(adev);
1954
1955         amdgpu_fence_driver_suspend(adev);
1956
1957         r = amdgpu_suspend(adev);
1958
1959         /* evict remaining vram memory */
1960         amdgpu_bo_evict_vram(adev);
1961
1962         pci_save_state(dev->pdev);
1963         if (suspend) {
1964                 /* Shut down the device */
1965                 pci_disable_device(dev->pdev);
1966                 pci_set_power_state(dev->pdev, PCI_D3hot);
1967         } else {
1968                 r = amdgpu_asic_reset(adev);
1969                 if (r)
1970                         DRM_ERROR("amdgpu asic reset failed\n");
1971         }
1972
1973         if (fbcon) {
1974                 console_lock();
1975                 amdgpu_fbdev_set_suspend(adev, 1);
1976                 console_unlock();
1977         }
1978         return 0;
1979 }
1980
1981 /**
1982  * amdgpu_device_resume - initiate device resume
1983  *
1984  * @pdev: drm dev pointer
1985  *
1986  * Bring the hw back to operating state (all asics).
1987  * Returns 0 for success or an error on failure.
1988  * Called at driver resume.
1989  */
1990 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon)
1991 {
1992         struct drm_connector *connector;
1993         struct amdgpu_device *adev = dev->dev_private;
1994         struct drm_crtc *crtc;
1995         int r;
1996
1997         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1998                 return 0;
1999
2000         if (fbcon)
2001                 console_lock();
2002
2003         if (resume) {
2004                 pci_set_power_state(dev->pdev, PCI_D0);
2005                 pci_restore_state(dev->pdev);
2006                 r = pci_enable_device(dev->pdev);
2007                 if (r) {
2008                         if (fbcon)
2009                                 console_unlock();
2010                         return r;
2011                 }
2012         }
2013
2014         /* post card */
2015         if (!amdgpu_card_posted(adev) || !resume) {
2016                 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
2017                 if (r)
2018                         DRM_ERROR("amdgpu asic init failed\n");
2019         }
2020
2021         r = amdgpu_resume(adev);
2022         if (r)
2023                 DRM_ERROR("amdgpu_resume failed (%d).\n", r);
2024
2025         amdgpu_fence_driver_resume(adev);
2026
2027         if (resume) {
2028                 r = amdgpu_ib_ring_tests(adev);
2029                 if (r)
2030                         DRM_ERROR("ib ring test failed (%d).\n", r);
2031         }
2032
2033         r = amdgpu_late_init(adev);
2034         if (r)
2035                 return r;
2036
2037         /* pin cursors */
2038         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2039                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2040
2041                 if (amdgpu_crtc->cursor_bo) {
2042                         struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2043                         r = amdgpu_bo_reserve(aobj, false);
2044                         if (r == 0) {
2045                                 r = amdgpu_bo_pin(aobj,
2046                                                   AMDGPU_GEM_DOMAIN_VRAM,
2047                                                   &amdgpu_crtc->cursor_addr);
2048                                 if (r != 0)
2049                                         DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
2050                                 amdgpu_bo_unreserve(aobj);
2051                         }
2052                 }
2053         }
2054
2055         /* blat the mode back in */
2056         if (fbcon) {
2057                 drm_helper_resume_force_mode(dev);
2058                 /* turn on display hw */
2059                 drm_modeset_lock_all(dev);
2060                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2061                         drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
2062                 }
2063                 drm_modeset_unlock_all(dev);
2064         }
2065
2066         drm_kms_helper_poll_enable(dev);
2067
2068         /*
2069          * Most of the connector probing functions try to acquire runtime pm
2070          * refs to ensure that the GPU is powered on when connector polling is
2071          * performed. Since we're calling this from a runtime PM callback,
2072          * trying to acquire rpm refs will cause us to deadlock.
2073          *
2074          * Since we're guaranteed to be holding the rpm lock, it's safe to
2075          * temporarily disable the rpm helpers so this doesn't deadlock us.
2076          */
2077 #ifdef CONFIG_PM
2078         dev->dev->power.disable_depth++;
2079 #endif
2080         drm_helper_hpd_irq_event(dev);
2081 #ifdef CONFIG_PM
2082         dev->dev->power.disable_depth--;
2083 #endif
2084
2085         if (fbcon) {
2086                 amdgpu_fbdev_set_suspend(adev, 0);
2087                 console_unlock();
2088         }
2089
2090         return 0;
2091 }
2092
2093 static bool amdgpu_check_soft_reset(struct amdgpu_device *adev)
2094 {
2095         int i;
2096         bool asic_hang = false;
2097
2098         for (i = 0; i < adev->num_ip_blocks; i++) {
2099                 if (!adev->ip_block_status[i].valid)
2100                         continue;
2101                 if (adev->ip_blocks[i].funcs->check_soft_reset)
2102                         adev->ip_block_status[i].hang =
2103                                 adev->ip_blocks[i].funcs->check_soft_reset(adev);
2104                 if (adev->ip_block_status[i].hang) {
2105                         DRM_INFO("IP block:%d is hang!\n", i);
2106                         asic_hang = true;
2107                 }
2108         }
2109         return asic_hang;
2110 }
2111
2112 static int amdgpu_pre_soft_reset(struct amdgpu_device *adev)
2113 {
2114         int i, r = 0;
2115
2116         for (i = 0; i < adev->num_ip_blocks; i++) {
2117                 if (!adev->ip_block_status[i].valid)
2118                         continue;
2119                 if (adev->ip_block_status[i].hang &&
2120                     adev->ip_blocks[i].funcs->pre_soft_reset) {
2121                         r = adev->ip_blocks[i].funcs->pre_soft_reset(adev);
2122                         if (r)
2123                                 return r;
2124                 }
2125         }
2126
2127         return 0;
2128 }
2129
2130 static bool amdgpu_need_full_reset(struct amdgpu_device *adev)
2131 {
2132         int i;
2133
2134         for (i = 0; i < adev->num_ip_blocks; i++) {
2135                 if (!adev->ip_block_status[i].valid)
2136                         continue;
2137                 if ((adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) ||
2138                     (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_SMC) ||
2139                     (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_ACP) ||
2140                     (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_DCE)) {
2141                         if (adev->ip_block_status[i].hang) {
2142                                 DRM_INFO("Some block need full reset!\n");
2143                                 return true;
2144                         }
2145                 }
2146         }
2147         return false;
2148 }
2149
2150 static int amdgpu_soft_reset(struct amdgpu_device *adev)
2151 {
2152         int i, r = 0;
2153
2154         for (i = 0; i < adev->num_ip_blocks; i++) {
2155                 if (!adev->ip_block_status[i].valid)
2156                         continue;
2157                 if (adev->ip_block_status[i].hang &&
2158                     adev->ip_blocks[i].funcs->soft_reset) {
2159                         r = adev->ip_blocks[i].funcs->soft_reset(adev);
2160                         if (r)
2161                                 return r;
2162                 }
2163         }
2164
2165         return 0;
2166 }
2167
2168 static int amdgpu_post_soft_reset(struct amdgpu_device *adev)
2169 {
2170         int i, r = 0;
2171
2172         for (i = 0; i < adev->num_ip_blocks; i++) {
2173                 if (!adev->ip_block_status[i].valid)
2174                         continue;
2175                 if (adev->ip_block_status[i].hang &&
2176                     adev->ip_blocks[i].funcs->post_soft_reset)
2177                         r = adev->ip_blocks[i].funcs->post_soft_reset(adev);
2178                 if (r)
2179                         return r;
2180         }
2181
2182         return 0;
2183 }
2184
2185 bool amdgpu_need_backup(struct amdgpu_device *adev)
2186 {
2187         if (adev->flags & AMD_IS_APU)
2188                 return false;
2189
2190         return amdgpu_lockup_timeout > 0 ? true : false;
2191 }
2192
2193 static int amdgpu_recover_vram_from_shadow(struct amdgpu_device *adev,
2194                                            struct amdgpu_ring *ring,
2195                                            struct amdgpu_bo *bo,
2196                                            struct fence **fence)
2197 {
2198         uint32_t domain;
2199         int r;
2200
2201        if (!bo->shadow)
2202                return 0;
2203
2204        r = amdgpu_bo_reserve(bo, false);
2205        if (r)
2206                return r;
2207        domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
2208        /* if bo has been evicted, then no need to recover */
2209        if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
2210                r = amdgpu_bo_restore_from_shadow(adev, ring, bo,
2211                                                  NULL, fence, true);
2212                if (r) {
2213                        DRM_ERROR("recover page table failed!\n");
2214                        goto err;
2215                }
2216        }
2217 err:
2218        amdgpu_bo_unreserve(bo);
2219        return r;
2220 }
2221
2222 /**
2223  * amdgpu_gpu_reset - reset the asic
2224  *
2225  * @adev: amdgpu device pointer
2226  *
2227  * Attempt the reset the GPU if it has hung (all asics).
2228  * Returns 0 for success or an error on failure.
2229  */
2230 int amdgpu_gpu_reset(struct amdgpu_device *adev)
2231 {
2232         int i, r;
2233         int resched;
2234         bool need_full_reset;
2235
2236         if (!amdgpu_check_soft_reset(adev)) {
2237                 DRM_INFO("No hardware hang detected. Did some blocks stall?\n");
2238                 return 0;
2239         }
2240
2241         atomic_inc(&adev->gpu_reset_counter);
2242
2243         /* block TTM */
2244         resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
2245
2246         /* block scheduler */
2247         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2248                 struct amdgpu_ring *ring = adev->rings[i];
2249
2250                 if (!ring)
2251                         continue;
2252                 kthread_park(ring->sched.thread);
2253                 amd_sched_hw_job_reset(&ring->sched);
2254         }
2255         /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
2256         amdgpu_fence_driver_force_completion(adev);
2257
2258         need_full_reset = amdgpu_need_full_reset(adev);
2259
2260         if (!need_full_reset) {
2261                 amdgpu_pre_soft_reset(adev);
2262                 r = amdgpu_soft_reset(adev);
2263                 amdgpu_post_soft_reset(adev);
2264                 if (r || amdgpu_check_soft_reset(adev)) {
2265                         DRM_INFO("soft reset failed, will fallback to full reset!\n");
2266                         need_full_reset = true;
2267                 }
2268         }
2269
2270         if (need_full_reset) {
2271                 /* save scratch */
2272                 amdgpu_atombios_scratch_regs_save(adev);
2273                 r = amdgpu_suspend(adev);
2274
2275 retry:
2276                 /* Disable fb access */
2277                 if (adev->mode_info.num_crtc) {
2278                         struct amdgpu_mode_mc_save save;
2279                         amdgpu_display_stop_mc_access(adev, &save);
2280                         amdgpu_wait_for_idle(adev, AMD_IP_BLOCK_TYPE_GMC);
2281                 }
2282
2283                 r = amdgpu_asic_reset(adev);
2284                 /* post card */
2285                 amdgpu_atom_asic_init(adev->mode_info.atom_context);
2286
2287                 if (!r) {
2288                         dev_info(adev->dev, "GPU reset succeeded, trying to resume\n");
2289                         r = amdgpu_resume(adev);
2290                 }
2291                 /* restore scratch */
2292                 amdgpu_atombios_scratch_regs_restore(adev);
2293         }
2294         if (!r) {
2295                 amdgpu_irq_gpu_reset_resume_helper(adev);
2296                 if (need_full_reset && amdgpu_need_backup(adev)) {
2297                         r = amdgpu_ttm_recover_gart(adev);
2298                         if (r)
2299                                 DRM_ERROR("gart recovery failed!!!\n");
2300                 }
2301                 r = amdgpu_ib_ring_tests(adev);
2302                 if (r) {
2303                         dev_err(adev->dev, "ib ring test failed (%d).\n", r);
2304                         r = amdgpu_suspend(adev);
2305                         need_full_reset = true;
2306                         goto retry;
2307                 }
2308                 /**
2309                  * recovery vm page tables, since we cannot depend on VRAM is
2310                  * consistent after gpu full reset.
2311                  */
2312                 if (need_full_reset && amdgpu_need_backup(adev)) {
2313                         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2314                         struct amdgpu_bo *bo, *tmp;
2315                         struct fence *fence = NULL, *next = NULL;
2316
2317                         DRM_INFO("recover vram bo from shadow\n");
2318                         mutex_lock(&adev->shadow_list_lock);
2319                         list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) {
2320                                 amdgpu_recover_vram_from_shadow(adev, ring, bo, &next);
2321                                 if (fence) {
2322                                         r = fence_wait(fence, false);
2323                                         if (r) {
2324                                                 WARN(r, "recovery from shadow isn't comleted\n");
2325                                                 break;
2326                                         }
2327                                 }
2328
2329                                 fence_put(fence);
2330                                 fence = next;
2331                         }
2332                         mutex_unlock(&adev->shadow_list_lock);
2333                         if (fence) {
2334                                 r = fence_wait(fence, false);
2335                                 if (r)
2336                                         WARN(r, "recovery from shadow isn't comleted\n");
2337                         }
2338                         fence_put(fence);
2339                 }
2340                 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2341                         struct amdgpu_ring *ring = adev->rings[i];
2342                         if (!ring)
2343                                 continue;
2344
2345                         amd_sched_job_recovery(&ring->sched);
2346                         kthread_unpark(ring->sched.thread);
2347                 }
2348         } else {
2349                 dev_err(adev->dev, "asic resume failed (%d).\n", r);
2350                 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2351                         if (adev->rings[i]) {
2352                                 kthread_unpark(adev->rings[i]->sched.thread);
2353                         }
2354                 }
2355         }
2356
2357         drm_helper_resume_force_mode(adev->ddev);
2358
2359         ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
2360         if (r) {
2361                 /* bad news, how to tell it to userspace ? */
2362                 dev_info(adev->dev, "GPU reset failed\n");
2363         }
2364
2365         return r;
2366 }
2367
2368 void amdgpu_get_pcie_info(struct amdgpu_device *adev)
2369 {
2370         u32 mask;
2371         int ret;
2372
2373         if (amdgpu_pcie_gen_cap)
2374                 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
2375
2376         if (amdgpu_pcie_lane_cap)
2377                 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
2378
2379         /* covers APUs as well */
2380         if (pci_is_root_bus(adev->pdev->bus)) {
2381                 if (adev->pm.pcie_gen_mask == 0)
2382                         adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
2383                 if (adev->pm.pcie_mlw_mask == 0)
2384                         adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
2385                 return;
2386         }
2387
2388         if (adev->pm.pcie_gen_mask == 0) {
2389                 ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
2390                 if (!ret) {
2391                         adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
2392                                                   CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
2393                                                   CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
2394
2395                         if (mask & DRM_PCIE_SPEED_25)
2396                                 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
2397                         if (mask & DRM_PCIE_SPEED_50)
2398                                 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2;
2399                         if (mask & DRM_PCIE_SPEED_80)
2400                                 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3;
2401                 } else {
2402                         adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
2403                 }
2404         }
2405         if (adev->pm.pcie_mlw_mask == 0) {
2406                 ret = drm_pcie_get_max_link_width(adev->ddev, &mask);
2407                 if (!ret) {
2408                         switch (mask) {
2409                         case 32:
2410                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
2411                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
2412                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
2413                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2414                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2415                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2416                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2417                                 break;
2418                         case 16:
2419                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
2420                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
2421                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2422                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2423                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2424                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2425                                 break;
2426                         case 12:
2427                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
2428                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2429                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2430                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2431                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2432                                 break;
2433                         case 8:
2434                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2435                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2436                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2437                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2438                                 break;
2439                         case 4:
2440                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2441                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2442                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2443                                 break;
2444                         case 2:
2445                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2446                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2447                                 break;
2448                         case 1:
2449                                 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
2450                                 break;
2451                         default:
2452                                 break;
2453                         }
2454                 } else {
2455                         adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
2456                 }
2457         }
2458 }
2459
2460 /*
2461  * Debugfs
2462  */
2463 int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
2464                              const struct drm_info_list *files,
2465                              unsigned nfiles)
2466 {
2467         unsigned i;
2468
2469         for (i = 0; i < adev->debugfs_count; i++) {
2470                 if (adev->debugfs[i].files == files) {
2471                         /* Already registered */
2472                         return 0;
2473                 }
2474         }
2475
2476         i = adev->debugfs_count + 1;
2477         if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) {
2478                 DRM_ERROR("Reached maximum number of debugfs components.\n");
2479                 DRM_ERROR("Report so we increase "
2480                           "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n");
2481                 return -EINVAL;
2482         }
2483         adev->debugfs[adev->debugfs_count].files = files;
2484         adev->debugfs[adev->debugfs_count].num_files = nfiles;
2485         adev->debugfs_count = i;
2486 #if defined(CONFIG_DEBUG_FS)
2487         drm_debugfs_create_files(files, nfiles,
2488                                  adev->ddev->control->debugfs_root,
2489                                  adev->ddev->control);
2490         drm_debugfs_create_files(files, nfiles,
2491                                  adev->ddev->primary->debugfs_root,
2492                                  adev->ddev->primary);
2493 #endif
2494         return 0;
2495 }
2496
2497 static void amdgpu_debugfs_remove_files(struct amdgpu_device *adev)
2498 {
2499 #if defined(CONFIG_DEBUG_FS)
2500         unsigned i;
2501
2502         for (i = 0; i < adev->debugfs_count; i++) {
2503                 drm_debugfs_remove_files(adev->debugfs[i].files,
2504                                          adev->debugfs[i].num_files,
2505                                          adev->ddev->control);
2506                 drm_debugfs_remove_files(adev->debugfs[i].files,
2507                                          adev->debugfs[i].num_files,
2508                                          adev->ddev->primary);
2509         }
2510 #endif
2511 }
2512
2513 #if defined(CONFIG_DEBUG_FS)
2514
2515 static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
2516                                         size_t size, loff_t *pos)
2517 {
2518         struct amdgpu_device *adev = f->f_inode->i_private;
2519         ssize_t result = 0;
2520         int r;
2521         bool pm_pg_lock, use_bank;
2522         unsigned instance_bank, sh_bank, se_bank;
2523
2524         if (size & 0x3 || *pos & 0x3)
2525                 return -EINVAL;
2526
2527         /* are we reading registers for which a PG lock is necessary? */
2528         pm_pg_lock = (*pos >> 23) & 1;
2529
2530         if (*pos & (1ULL << 62)) {
2531                 se_bank = (*pos >> 24) & 0x3FF;
2532                 sh_bank = (*pos >> 34) & 0x3FF;
2533                 instance_bank = (*pos >> 44) & 0x3FF;
2534                 use_bank = 1;
2535         } else {
2536                 use_bank = 0;
2537         }
2538
2539         *pos &= 0x3FFFF;
2540
2541         if (use_bank) {
2542                 if (sh_bank >= adev->gfx.config.max_sh_per_se ||
2543                     se_bank >= adev->gfx.config.max_shader_engines)
2544                         return -EINVAL;
2545                 mutex_lock(&adev->grbm_idx_mutex);
2546                 amdgpu_gfx_select_se_sh(adev, se_bank,
2547                                         sh_bank, instance_bank);
2548         }
2549
2550         if (pm_pg_lock)
2551                 mutex_lock(&adev->pm.mutex);
2552
2553         while (size) {
2554                 uint32_t value;
2555
2556                 if (*pos > adev->rmmio_size)
2557                         goto end;
2558
2559                 value = RREG32(*pos >> 2);
2560                 r = put_user(value, (uint32_t *)buf);
2561                 if (r) {
2562                         result = r;
2563                         goto end;
2564                 }
2565
2566                 result += 4;
2567                 buf += 4;
2568                 *pos += 4;
2569                 size -= 4;
2570         }
2571
2572 end:
2573         if (use_bank) {
2574                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
2575                 mutex_unlock(&adev->grbm_idx_mutex);
2576         }
2577
2578         if (pm_pg_lock)
2579                 mutex_unlock(&adev->pm.mutex);
2580
2581         return result;
2582 }
2583
2584 static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,
2585                                          size_t size, loff_t *pos)
2586 {
2587         struct amdgpu_device *adev = f->f_inode->i_private;
2588         ssize_t result = 0;
2589         int r;
2590
2591         if (size & 0x3 || *pos & 0x3)
2592                 return -EINVAL;
2593
2594         while (size) {
2595                 uint32_t value;
2596
2597                 if (*pos > adev->rmmio_size)
2598                         return result;
2599
2600                 r = get_user(value, (uint32_t *)buf);
2601                 if (r)
2602                         return r;
2603
2604                 WREG32(*pos >> 2, value);
2605
2606                 result += 4;
2607                 buf += 4;
2608                 *pos += 4;
2609                 size -= 4;
2610         }
2611
2612         return result;
2613 }
2614
2615 static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf,
2616                                         size_t size, loff_t *pos)
2617 {
2618         struct amdgpu_device *adev = f->f_inode->i_private;
2619         ssize_t result = 0;
2620         int r;
2621
2622         if (size & 0x3 || *pos & 0x3)
2623                 return -EINVAL;
2624
2625         while (size) {
2626                 uint32_t value;
2627
2628                 value = RREG32_PCIE(*pos >> 2);
2629                 r = put_user(value, (uint32_t *)buf);
2630                 if (r)
2631                         return r;
2632
2633                 result += 4;
2634                 buf += 4;
2635                 *pos += 4;
2636                 size -= 4;
2637         }
2638
2639         return result;
2640 }
2641
2642 static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user *buf,
2643                                          size_t size, loff_t *pos)
2644 {
2645         struct amdgpu_device *adev = f->f_inode->i_private;
2646         ssize_t result = 0;
2647         int r;
2648
2649         if (size & 0x3 || *pos & 0x3)
2650                 return -EINVAL;
2651
2652         while (size) {
2653                 uint32_t value;
2654
2655                 r = get_user(value, (uint32_t *)buf);
2656                 if (r)
2657                         return r;
2658
2659                 WREG32_PCIE(*pos >> 2, value);
2660
2661                 result += 4;
2662                 buf += 4;
2663                 *pos += 4;
2664                 size -= 4;
2665         }
2666
2667         return result;
2668 }
2669
2670 static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf,
2671                                         size_t size, loff_t *pos)
2672 {
2673         struct amdgpu_device *adev = f->f_inode->i_private;
2674         ssize_t result = 0;
2675         int r;
2676
2677         if (size & 0x3 || *pos & 0x3)
2678                 return -EINVAL;
2679
2680         while (size) {
2681                 uint32_t value;
2682
2683                 value = RREG32_DIDT(*pos >> 2);
2684                 r = put_user(value, (uint32_t *)buf);
2685                 if (r)
2686                         return r;
2687
2688                 result += 4;
2689                 buf += 4;
2690                 *pos += 4;
2691                 size -= 4;
2692         }
2693
2694         return result;
2695 }
2696
2697 static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user *buf,
2698                                          size_t size, loff_t *pos)
2699 {
2700         struct amdgpu_device *adev = f->f_inode->i_private;
2701         ssize_t result = 0;
2702         int r;
2703
2704         if (size & 0x3 || *pos & 0x3)
2705                 return -EINVAL;
2706
2707         while (size) {
2708                 uint32_t value;
2709
2710                 r = get_user(value, (uint32_t *)buf);
2711                 if (r)
2712                         return r;
2713
2714                 WREG32_DIDT(*pos >> 2, value);
2715
2716                 result += 4;
2717                 buf += 4;
2718                 *pos += 4;
2719                 size -= 4;
2720         }
2721
2722         return result;
2723 }
2724
2725 static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf,
2726                                         size_t size, loff_t *pos)
2727 {
2728         struct amdgpu_device *adev = f->f_inode->i_private;
2729         ssize_t result = 0;
2730         int r;
2731
2732         if (size & 0x3 || *pos & 0x3)
2733                 return -EINVAL;
2734
2735         while (size) {
2736                 uint32_t value;
2737
2738                 value = RREG32_SMC(*pos);
2739                 r = put_user(value, (uint32_t *)buf);
2740                 if (r)
2741                         return r;
2742
2743                 result += 4;
2744                 buf += 4;
2745                 *pos += 4;
2746                 size -= 4;
2747         }
2748
2749         return result;
2750 }
2751
2752 static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *buf,
2753                                          size_t size, loff_t *pos)
2754 {
2755         struct amdgpu_device *adev = f->f_inode->i_private;
2756         ssize_t result = 0;
2757         int r;
2758
2759         if (size & 0x3 || *pos & 0x3)
2760                 return -EINVAL;
2761
2762         while (size) {
2763                 uint32_t value;
2764
2765                 r = get_user(value, (uint32_t *)buf);
2766                 if (r)
2767                         return r;
2768
2769                 WREG32_SMC(*pos, value);
2770
2771                 result += 4;
2772                 buf += 4;
2773                 *pos += 4;
2774                 size -= 4;
2775         }
2776
2777         return result;
2778 }
2779
2780 static ssize_t amdgpu_debugfs_gca_config_read(struct file *f, char __user *buf,
2781                                         size_t size, loff_t *pos)
2782 {
2783         struct amdgpu_device *adev = f->f_inode->i_private;
2784         ssize_t result = 0;
2785         int r;
2786         uint32_t *config, no_regs = 0;
2787
2788         if (size & 0x3 || *pos & 0x3)
2789                 return -EINVAL;
2790
2791         config = kmalloc_array(256, sizeof(*config), GFP_KERNEL);
2792         if (!config)
2793                 return -ENOMEM;
2794
2795         /* version, increment each time something is added */
2796         config[no_regs++] = 2;
2797         config[no_regs++] = adev->gfx.config.max_shader_engines;
2798         config[no_regs++] = adev->gfx.config.max_tile_pipes;
2799         config[no_regs++] = adev->gfx.config.max_cu_per_sh;
2800         config[no_regs++] = adev->gfx.config.max_sh_per_se;
2801         config[no_regs++] = adev->gfx.config.max_backends_per_se;
2802         config[no_regs++] = adev->gfx.config.max_texture_channel_caches;
2803         config[no_regs++] = adev->gfx.config.max_gprs;
2804         config[no_regs++] = adev->gfx.config.max_gs_threads;
2805         config[no_regs++] = adev->gfx.config.max_hw_contexts;
2806         config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_frontend;
2807         config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_backend;
2808         config[no_regs++] = adev->gfx.config.sc_hiz_tile_fifo_size;
2809         config[no_regs++] = adev->gfx.config.sc_earlyz_tile_fifo_size;
2810         config[no_regs++] = adev->gfx.config.num_tile_pipes;
2811         config[no_regs++] = adev->gfx.config.backend_enable_mask;
2812         config[no_regs++] = adev->gfx.config.mem_max_burst_length_bytes;
2813         config[no_regs++] = adev->gfx.config.mem_row_size_in_kb;
2814         config[no_regs++] = adev->gfx.config.shader_engine_tile_size;
2815         config[no_regs++] = adev->gfx.config.num_gpus;
2816         config[no_regs++] = adev->gfx.config.multi_gpu_tile_size;
2817         config[no_regs++] = adev->gfx.config.mc_arb_ramcfg;
2818         config[no_regs++] = adev->gfx.config.gb_addr_config;
2819         config[no_regs++] = adev->gfx.config.num_rbs;
2820
2821         /* rev==1 */
2822         config[no_regs++] = adev->rev_id;
2823         config[no_regs++] = adev->pg_flags;
2824         config[no_regs++] = adev->cg_flags;
2825
2826         /* rev==2 */
2827         config[no_regs++] = adev->family;
2828         config[no_regs++] = adev->external_rev_id;
2829
2830         while (size && (*pos < no_regs * 4)) {
2831                 uint32_t value;
2832
2833                 value = config[*pos >> 2];
2834                 r = put_user(value, (uint32_t *)buf);
2835                 if (r) {
2836                         kfree(config);
2837                         return r;
2838                 }
2839
2840                 result += 4;
2841                 buf += 4;
2842                 *pos += 4;
2843                 size -= 4;
2844         }
2845
2846         kfree(config);
2847         return result;
2848 }
2849
2850 static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf,
2851                                         size_t size, loff_t *pos)
2852 {
2853         struct amdgpu_device *adev = f->f_inode->i_private;
2854         int idx, r;
2855         int32_t value;
2856
2857         if (size != 4 || *pos & 0x3)
2858                 return -EINVAL;
2859
2860         /* convert offset to sensor number */
2861         idx = *pos >> 2;
2862
2863         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor)
2864                 r = adev->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, idx, &value);
2865         else
2866                 return -EINVAL;
2867
2868         if (!r)
2869                 r = put_user(value, (int32_t *)buf);
2870
2871         return !r ? 4 : r;
2872 }
2873
2874 static const struct file_operations amdgpu_debugfs_regs_fops = {
2875         .owner = THIS_MODULE,
2876         .read = amdgpu_debugfs_regs_read,
2877         .write = amdgpu_debugfs_regs_write,
2878         .llseek = default_llseek
2879 };
2880 static const struct file_operations amdgpu_debugfs_regs_didt_fops = {
2881         .owner = THIS_MODULE,
2882         .read = amdgpu_debugfs_regs_didt_read,
2883         .write = amdgpu_debugfs_regs_didt_write,
2884         .llseek = default_llseek
2885 };
2886 static const struct file_operations amdgpu_debugfs_regs_pcie_fops = {
2887         .owner = THIS_MODULE,
2888         .read = amdgpu_debugfs_regs_pcie_read,
2889         .write = amdgpu_debugfs_regs_pcie_write,
2890         .llseek = default_llseek
2891 };
2892 static const struct file_operations amdgpu_debugfs_regs_smc_fops = {
2893         .owner = THIS_MODULE,
2894         .read = amdgpu_debugfs_regs_smc_read,
2895         .write = amdgpu_debugfs_regs_smc_write,
2896         .llseek = default_llseek
2897 };
2898
2899 static const struct file_operations amdgpu_debugfs_gca_config_fops = {
2900         .owner = THIS_MODULE,
2901         .read = amdgpu_debugfs_gca_config_read,
2902         .llseek = default_llseek
2903 };
2904
2905 static const struct file_operations amdgpu_debugfs_sensors_fops = {
2906         .owner = THIS_MODULE,
2907         .read = amdgpu_debugfs_sensor_read,
2908         .llseek = default_llseek
2909 };
2910
2911 static const struct file_operations *debugfs_regs[] = {
2912         &amdgpu_debugfs_regs_fops,
2913         &amdgpu_debugfs_regs_didt_fops,
2914         &amdgpu_debugfs_regs_pcie_fops,
2915         &amdgpu_debugfs_regs_smc_fops,
2916         &amdgpu_debugfs_gca_config_fops,
2917         &amdgpu_debugfs_sensors_fops,
2918 };
2919
2920 static const char *debugfs_regs_names[] = {
2921         "amdgpu_regs",
2922         "amdgpu_regs_didt",
2923         "amdgpu_regs_pcie",
2924         "amdgpu_regs_smc",
2925         "amdgpu_gca_config",
2926         "amdgpu_sensors",
2927 };
2928
2929 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
2930 {
2931         struct drm_minor *minor = adev->ddev->primary;
2932         struct dentry *ent, *root = minor->debugfs_root;
2933         unsigned i, j;
2934
2935         for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
2936                 ent = debugfs_create_file(debugfs_regs_names[i],
2937                                           S_IFREG | S_IRUGO, root,
2938                                           adev, debugfs_regs[i]);
2939                 if (IS_ERR(ent)) {
2940                         for (j = 0; j < i; j++) {
2941                                 debugfs_remove(adev->debugfs_regs[i]);
2942                                 adev->debugfs_regs[i] = NULL;
2943                         }
2944                         return PTR_ERR(ent);
2945                 }
2946
2947                 if (!i)
2948                         i_size_write(ent->d_inode, adev->rmmio_size);
2949                 adev->debugfs_regs[i] = ent;
2950         }
2951
2952         return 0;
2953 }
2954
2955 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev)
2956 {
2957         unsigned i;
2958
2959         for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
2960                 if (adev->debugfs_regs[i]) {
2961                         debugfs_remove(adev->debugfs_regs[i]);
2962                         adev->debugfs_regs[i] = NULL;
2963                 }
2964         }
2965 }
2966
2967 int amdgpu_debugfs_init(struct drm_minor *minor)
2968 {
2969         return 0;
2970 }
2971
2972 void amdgpu_debugfs_cleanup(struct drm_minor *minor)
2973 {
2974 }
2975 #else
2976 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
2977 {
2978         return 0;
2979 }
2980 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { }
2981 #endif