drivers/cpufreq/s3c64xx-cpufreq.c

   1 /*
   2  * Copyright 2009 Wolfson Microelectronics plc
   3  *
   4  * S3C64xx CPUfreq Support
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #define pr_fmt(fmt) "cpufreq: " fmt
  12
  13 #include <linux/kernel.h>
  14 #include <linux/types.h>
  15 #include <linux/init.h>
  16 #include <linux/cpufreq.h>
  17 #include <linux/clk.h>
  18 #include <linux/err.h>
  19 #include <linux/regulator/consumer.h>
  20 #include <linux/module.h>
  21
  22 static struct regulator *vddarm;
  23 static unsigned long regulator_latency;
  24
  25 #ifdef CONFIG_CPU_S3C6410
  26 struct s3c64xx_dvfs {
  27         unsigned int vddarm_min;
  28         unsigned int vddarm_max;
  29 };
  30
  31 static struct s3c64xx_dvfs s3c64xx_dvfs_table[] = {
  32         [0] = { 1000000, 1150000 },
  33         [1] = { 1050000, 1150000 },
  34         [2] = { 1100000, 1150000 },
  35         [3] = { 1200000, 1350000 },
  36         [4] = { 1300000, 1350000 },
  37 };
  38
  39 static struct cpufreq_frequency_table s3c64xx_freq_table[] = {
  40         { 0, 0,  66000 },
  41         { 0, 0, 100000 },
  42         { 0, 0, 133000 },
  43         { 0, 1, 200000 },
  44         { 0, 1, 222000 },
  45         { 0, 1, 266000 },
  46         { 0, 2, 333000 },
  47         { 0, 2, 400000 },
  48         { 0, 2, 532000 },
  49         { 0, 2, 533000 },
  50         { 0, 3, 667000 },
  51         { 0, 4, 800000 },
  52         { 0, 0, CPUFREQ_TABLE_END },
  53 };
  54 #endif
  55
  56 static int s3c64xx_cpufreq_set_target(struct cpufreq_policy *policy,
  57                                       unsigned int index)
  58 {
  59         struct s3c64xx_dvfs *dvfs;
  60         unsigned int old_freq, new_freq;
  61         int ret;
  62
  63         old_freq = clk_get_rate(policy->clk) / 1000;
  64         new_freq = s3c64xx_freq_table[index].frequency;
  65         dvfs = &s3c64xx_dvfs_table[s3c64xx_freq_table[index].driver_data];
  66
  67 #ifdef CONFIG_REGULATOR
  68         if (vddarm && new_freq > old_freq) {
  69                 ret = regulator_set_voltage(vddarm,
  70                                             dvfs->vddarm_min,
  71                                             dvfs->vddarm_max);
  72                 if (ret != 0) {
  73                         pr_err("Failed to set VDDARM for %dkHz: %d\n",
  74                                new_freq, ret);
  75                         return ret;
  76                 }
  77         }
  78 #endif
  79
  80         ret = clk_set_rate(policy->clk, new_freq * 1000);
  81         if (ret < 0) {
  82                 pr_err("Failed to set rate %dkHz: %d\n",
  83                        new_freq, ret);
  84                 return ret;
  85         }
  86
  87 #ifdef CONFIG_REGULATOR
  88         if (vddarm && new_freq < old_freq) {
  89                 ret = regulator_set_voltage(vddarm,
  90                                             dvfs->vddarm_min,
  91                                             dvfs->vddarm_max);
  92                 if (ret != 0) {
  93                         pr_err("Failed to set VDDARM for %dkHz: %d\n",
  94                                new_freq, ret);
  95                         if (clk_set_rate(policy->clk, old_freq * 1000) < 0)
  96                                 pr_err("Failed to restore original clock rate\n");
  97
  98                         return ret;
  99                 }
 100         }
 101 #endif
 102
 103         pr_debug("Set actual frequency %lukHz\n",
 104                  clk_get_rate(policy->clk) / 1000);
 105
 106         return 0;
 107 }
 108
 109 #ifdef CONFIG_REGULATOR
 110 static void s3c64xx_cpufreq_config_regulator(void)
 111 {
 112         int count, v, i, found;
 113         struct cpufreq_frequency_table *freq;
 114         struct s3c64xx_dvfs *dvfs;
 115
 116         count = regulator_count_voltages(vddarm);
 117         if (count < 0) {
 118                 pr_err("Unable to check supported voltages\n");
 119         }
 120
 121         if (!count)
 122                 goto out;
 123
 124         cpufreq_for_each_valid_entry(freq, s3c64xx_freq_table) {
 125                 dvfs = &s3c64xx_dvfs_table[freq->driver_data];
 126                 found = 0;
 127
 128                 for (i = 0; i < count; i++) {
 129                         v = regulator_list_voltage(vddarm, i);
 130                         if (v >= dvfs->vddarm_min && v <= dvfs->vddarm_max)
 131                                 found = 1;
 132                 }
 133
 134                 if (!found) {
 135                         pr_debug("%dkHz unsupported by regulator\n",
 136                                  freq->frequency);
 137                         freq->frequency = CPUFREQ_ENTRY_INVALID;
 138                 }
 139         }
 140
 141 out:
 142         /* Guess based on having to do an I2C/SPI write; in future we
 143          * will be able to query the regulator performance here. */
 144         regulator_latency = 1 * 1000 * 1000;
 145 }
 146 #endif
 147
 148 static int s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy)
 149 {
 150         struct cpufreq_frequency_table *freq;
 151
 152         if (policy->cpu != 0)
 153                 return -EINVAL;
 154
 155         if (s3c64xx_freq_table == NULL) {
 156                 pr_err("No frequency information for this CPU\n");
 157                 return -ENODEV;
 158         }
 159
 160         policy->clk = clk_get(NULL, "armclk");
 161         if (IS_ERR(policy->clk)) {
 162                 pr_err("Unable to obtain ARMCLK: %ld\n",
 163                        PTR_ERR(policy->clk));
 164                 return PTR_ERR(policy->clk);
 165         }
 166
 167 #ifdef CONFIG_REGULATOR
 168         vddarm = regulator_get(NULL, "vddarm");
 169         if (IS_ERR(vddarm)) {
 170                 pr_err("Failed to obtain VDDARM: %ld\n", PTR_ERR(vddarm));
 171                 pr_err("Only frequency scaling available\n");
 172                 vddarm = NULL;
 173         } else {
 174                 s3c64xx_cpufreq_config_regulator();
 175         }
 176 #endif
 177
 178         cpufreq_for_each_entry(freq, s3c64xx_freq_table) {
 179                 unsigned long r;
 180
 181                 /* Check for frequencies we can generate */
 182                 r = clk_round_rate(policy->clk, freq->frequency * 1000);
 183                 r /= 1000;
 184                 if (r != freq->frequency) {
 185                         pr_debug("%dkHz unsupported by clock\n",
 186                                  freq->frequency);
 187                         freq->frequency = CPUFREQ_ENTRY_INVALID;
 188                 }
 189
 190                 /* If we have no regulator then assume startup
 191                  * frequency is the maximum we can support. */
 192                 if (!vddarm && freq->frequency > clk_get_rate(policy->clk) / 1000)
 193                         freq->frequency = CPUFREQ_ENTRY_INVALID;
 194         }
 195
 196         /* Datasheet says PLL stabalisation time (if we were to use
 197          * the PLLs, which we don't currently) is ~300us worst case,
 198          * but add some fudge.
 199          */
 200         cpufreq_generic_init(policy, s3c64xx_freq_table,
 201                         (500 * 1000) + regulator_latency);
 202         return 0;
 203 }
 204
 205 static struct cpufreq_driver s3c64xx_cpufreq_driver = {
 206         .flags          = CPUFREQ_NEED_INITIAL_FREQ_CHECK,
 207         .verify         = cpufreq_generic_frequency_table_verify,
 208         .target_index   = s3c64xx_cpufreq_set_target,
 209         .get            = cpufreq_generic_get,
 210         .init           = s3c64xx_cpufreq_driver_init,
 211         .name           = "s3c",
 212 };
 213
 214 static int __init s3c64xx_cpufreq_init(void)
 215 {
 216         return cpufreq_register_driver(&s3c64xx_cpufreq_driver);
 217 }
 218 module_init(s3c64xx_cpufreq_init);