drivers/clk/qcom/gcc-ipq4019.c

   1 /*
   2  * Copyright (c) 2015 The Linux Foundation. All rights reserved.
   3  *
   4  * This software is licensed under the terms of the GNU General Public
   5  * License version 2, as published by the Free Software Foundation, and
   6  * may be copied, distributed, and modified under those terms.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/err.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/module.h>
  18 #include <linux/of.h>
  19 #include <linux/of_device.h>
  20 #include <linux/clk-provider.h>
  21 #include <linux/regmap.h>
  22 #include <linux/reset-controller.h>
  23
  24 #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
  25
  26 #include "common.h"
  27 #include "clk-regmap.h"
  28 #include "clk-rcg.h"
  29 #include "clk-branch.h"
  30 #include "reset.h"
  31
  32 enum {
  33         P_XO,
  34         P_FEPLL200,
  35         P_FEPLL500,
  36         P_DDRPLL,
  37         P_FEPLLWCSS2G,
  38         P_FEPLLWCSS5G,
  39         P_FEPLL125DLY,
  40         P_DDRPLLAPSS,
  41 };
  42
  43 static struct parent_map gcc_xo_200_500_map[] = {
  44         { P_XO, 0 },
  45         { P_FEPLL200, 1 },
  46         { P_FEPLL500, 2 },
  47 };
  48
  49 static const char * const gcc_xo_200_500[] = {
  50         "xo",
  51         "fepll200",
  52         "fepll500",
  53 };
  54
  55 static struct parent_map gcc_xo_200_map[] = {
  56         {  P_XO, 0 },
  57         {  P_FEPLL200, 1 },
  58 };
  59
  60 static const char * const gcc_xo_200[] = {
  61         "xo",
  62         "fepll200",
  63 };
  64
  65 static struct parent_map gcc_xo_200_spi_map[] = {
  66         {  P_XO, 0 },
  67         {  P_FEPLL200, 2 },
  68 };
  69
  70 static const char * const gcc_xo_200_spi[] = {
  71         "xo",
  72         "fepll200",
  73 };
  74
  75 static struct parent_map gcc_xo_sdcc1_500_map[] = {
  76         {  P_XO, 0 },
  77         {  P_DDRPLL, 1 },
  78         {  P_FEPLL500, 2 },
  79 };
  80
  81 static const char * const gcc_xo_sdcc1_500[] = {
  82         "xo",
  83         "ddrpll",
  84         "fepll500",
  85 };
  86
  87 static struct parent_map gcc_xo_wcss2g_map[] = {
  88         {  P_XO, 0 },
  89         {  P_FEPLLWCSS2G, 1 },
  90 };
  91
  92 static const char * const gcc_xo_wcss2g[] = {
  93         "xo",
  94         "fepllwcss2g",
  95 };
  96
  97 static struct parent_map gcc_xo_wcss5g_map[] = {
  98         {  P_XO, 0 },
  99         {  P_FEPLLWCSS5G, 1 },
 100 };
 101
 102 static const char * const gcc_xo_wcss5g[] = {
 103         "xo",
 104         "fepllwcss5g",
 105 };
 106
 107 static struct parent_map gcc_xo_125_dly_map[] = {
 108         {  P_XO, 0 },
 109         {  P_FEPLL125DLY, 1 },
 110 };
 111
 112 static const char * const gcc_xo_125_dly[] = {
 113         "xo",
 114         "fepll125dly",
 115 };
 116
 117 static struct parent_map gcc_xo_ddr_500_200_map[] = {
 118         {  P_XO, 0 },
 119         {  P_FEPLL200, 3 },
 120         {  P_FEPLL500, 2 },
 121         {  P_DDRPLLAPSS, 1 },
 122 };
 123
 124 static const char * const gcc_xo_ddr_500_200[] = {
 125         "xo",
 126         "fepll200",
 127         "fepll500",
 128         "ddrpllapss",
 129 };
 130
 131 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
 132 #define P_XO 0
 133 #define FE_PLL_200 1
 134 #define FE_PLL_500 2
 135 #define DDRC_PLL_666  3
 136
 137 #define DDRC_PLL_666_SDCC  1
 138 #define FE_PLL_125_DLY 1
 139
 140 #define FE_PLL_WCSS2G 1
 141 #define FE_PLL_WCSS5G 1
 142
 143 static const struct freq_tbl ftbl_gcc_audio_pwm_clk[] = {
 144         F(48000000, P_XO, 1, 0, 0),
 145         F(200000000, FE_PLL_200, 1, 0, 0),
 146         { }
 147 };
 148
 149 static struct clk_rcg2 audio_clk_src = {
 150         .cmd_rcgr = 0x1b000,
 151         .hid_width = 5,
 152         .parent_map = gcc_xo_200_map,
 153         .freq_tbl = ftbl_gcc_audio_pwm_clk,
 154         .clkr.hw.init = &(struct clk_init_data){
 155                 .name = "audio_clk_src",
 156                 .parent_names = gcc_xo_200,
 157                 .num_parents = 2,
 158                 .ops = &clk_rcg2_ops,
 159
 160         },
 161 };
 162
 163 static struct clk_branch gcc_audio_ahb_clk = {
 164         .halt_reg = 0x1b010,
 165         .clkr = {
 166                 .enable_reg = 0x1b010,
 167                 .enable_mask = BIT(0),
 168                 .hw.init = &(struct clk_init_data){
 169                         .name = "gcc_audio_ahb_clk",
 170                         .parent_names = (const char *[]){
 171                                 "pcnoc_clk_src",
 172                         },
 173                         .flags = CLK_SET_RATE_PARENT,
 174                         .num_parents = 1,
 175                         .ops = &clk_branch2_ops,
 176                 },
 177         },
 178 };
 179
 180 static struct clk_branch gcc_audio_pwm_clk = {
 181         .halt_reg = 0x1b00C,
 182         .clkr = {
 183                 .enable_reg = 0x1b00C,
 184                 .enable_mask = BIT(0),
 185                 .hw.init = &(struct clk_init_data){
 186                         .name = "gcc_audio_pwm_clk",
 187                         .parent_names = (const char *[]){
 188                                 "audio_clk_src",
 189                         },
 190                         .flags = CLK_SET_RATE_PARENT,
 191                         .num_parents = 1,
 192                         .ops = &clk_branch2_ops,
 193                 },
 194         },
 195 };
 196
 197 static const struct freq_tbl ftbl_gcc_blsp1_qup1_2_i2c_apps_clk[] = {
 198         F(19200000, P_XO, 1, 2, 5),
 199         F(24000000, P_XO, 1, 1, 2),
 200         { }
 201 };
 202
 203 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
 204         .cmd_rcgr = 0x200c,
 205         .hid_width = 5,
 206         .parent_map = gcc_xo_200_map,
 207         .freq_tbl = ftbl_gcc_blsp1_qup1_2_i2c_apps_clk,
 208         .clkr.hw.init = &(struct clk_init_data){
 209                 .name = "blsp1_qup1_i2c_apps_clk_src",
 210                 .parent_names = gcc_xo_200,
 211                 .num_parents = 2,
 212                 .ops = &clk_rcg2_ops,
 213         },
 214 };
 215
 216 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
 217         .halt_reg = 0x2008,
 218         .clkr = {
 219                 .enable_reg = 0x2008,
 220                 .enable_mask = BIT(0),
 221                 .hw.init = &(struct clk_init_data){
 222                         .name = "gcc_blsp1_qup1_i2c_apps_clk",
 223                         .parent_names = (const char *[]){
 224                                 "blsp1_qup1_i2c_apps_clk_src",
 225                         },
 226                         .num_parents = 1,
 227                         .ops = &clk_branch2_ops,
 228                         .flags = CLK_SET_RATE_PARENT,
 229                 },
 230         },
 231 };
 232
 233 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
 234         .cmd_rcgr = 0x3000,
 235         .hid_width = 5,
 236         .parent_map = gcc_xo_200_map,
 237         .freq_tbl = ftbl_gcc_blsp1_qup1_2_i2c_apps_clk,
 238         .clkr.hw.init = &(struct clk_init_data){
 239                 .name = "blsp1_qup2_i2c_apps_clk_src",
 240                 .parent_names = gcc_xo_200,
 241                 .num_parents = 2,
 242                 .ops = &clk_rcg2_ops,
 243         },
 244 };
 245
 246 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
 247         .halt_reg = 0x3010,
 248         .clkr = {
 249                 .enable_reg = 0x3010,
 250                 .enable_mask = BIT(0),
 251                 .hw.init = &(struct clk_init_data){
 252                         .name = "gcc_blsp1_qup2_i2c_apps_clk",
 253                         .parent_names = (const char *[]){
 254                                 "blsp1_qup2_i2c_apps_clk_src",
 255                         },
 256                         .num_parents = 1,
 257                         .ops = &clk_branch2_ops,
 258                         .flags = CLK_SET_RATE_PARENT,
 259                 },
 260         },
 261 };
 262
 263 static const struct freq_tbl ftbl_gcc_blsp1_qup1_2_spi_apps_clk[] = {
 264         F(960000, P_XO, 12, 1, 4),
 265         F(4800000, P_XO, 1, 1, 10),
 266         F(9600000, P_XO, 1, 1, 5),
 267         F(15000000, P_XO, 1, 1, 3),
 268         F(19200000, P_XO, 1, 2, 5),
 269         F(24000000, P_XO, 1, 1, 2),
 270         F(48000000, P_XO, 1, 0, 0),
 271         { }
 272 };
 273
 274 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
 275         .cmd_rcgr = 0x2024,
 276         .mnd_width = 8,
 277         .hid_width = 5,
 278         .parent_map = gcc_xo_200_spi_map,
 279         .freq_tbl = ftbl_gcc_blsp1_qup1_2_spi_apps_clk,
 280         .clkr.hw.init = &(struct clk_init_data){
 281                 .name = "blsp1_qup1_spi_apps_clk_src",
 282                 .parent_names = gcc_xo_200_spi,
 283                 .num_parents = 2,
 284                 .ops = &clk_rcg2_ops,
 285         },
 286 };
 287
 288 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
 289         .halt_reg = 0x2004,
 290         .clkr = {
 291                 .enable_reg = 0x2004,
 292                 .enable_mask = BIT(0),
 293                 .hw.init = &(struct clk_init_data){
 294                         .name = "gcc_blsp1_qup1_spi_apps_clk",
 295                         .parent_names = (const char *[]){
 296                                 "blsp1_qup1_spi_apps_clk_src",
 297                         },
 298                         .num_parents = 1,
 299                         .ops = &clk_branch2_ops,
 300                         .flags = CLK_SET_RATE_PARENT,
 301                 },
 302         },
 303 };
 304
 305 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
 306         .cmd_rcgr = 0x3014,
 307         .mnd_width = 8,
 308         .hid_width = 5,
 309         .freq_tbl = ftbl_gcc_blsp1_qup1_2_spi_apps_clk,
 310         .parent_map = gcc_xo_200_spi_map,
 311         .clkr.hw.init = &(struct clk_init_data){
 312                 .name = "blsp1_qup2_spi_apps_clk_src",
 313                 .parent_names = gcc_xo_200_spi,
 314                 .num_parents = 2,
 315                 .ops = &clk_rcg2_ops,
 316         },
 317 };
 318
 319 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
 320         .halt_reg = 0x300c,
 321         .clkr = {
 322                 .enable_reg = 0x300c,
 323                 .enable_mask = BIT(0),
 324                 .hw.init = &(struct clk_init_data){
 325                         .name = "gcc_blsp1_qup2_spi_apps_clk",
 326                         .parent_names = (const char *[]){
 327                                 "blsp1_qup2_spi_apps_clk_src",
 328                         },
 329                         .num_parents = 1,
 330                         .ops = &clk_branch2_ops,
 331                         .flags = CLK_SET_RATE_PARENT,
 332                 },
 333         },
 334 };
 335
 336 static const struct freq_tbl ftbl_gcc_blsp1_uart1_2_apps_clk[] = {
 337         F(1843200, FE_PLL_200, 1, 144, 15625),
 338         F(3686400, FE_PLL_200, 1, 288, 15625),
 339         F(7372800, FE_PLL_200, 1, 576, 15625),
 340         F(14745600, FE_PLL_200, 1, 1152, 15625),
 341         F(16000000, FE_PLL_200, 1, 2, 25),
 342         F(24000000, P_XO, 1, 1, 2),
 343         F(32000000, FE_PLL_200, 1, 4, 25),
 344         F(40000000, FE_PLL_200, 1, 1, 5),
 345         F(46400000, FE_PLL_200, 1, 29, 125),
 346         F(48000000, P_XO, 1, 0, 0),
 347         { }
 348 };
 349
 350 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
 351         .cmd_rcgr = 0x2044,
 352         .mnd_width = 16,
 353         .hid_width = 5,
 354         .freq_tbl = ftbl_gcc_blsp1_uart1_2_apps_clk,
 355         .parent_map = gcc_xo_200_spi_map,
 356         .clkr.hw.init = &(struct clk_init_data){
 357                 .name = "blsp1_uart1_apps_clk_src",
 358                 .parent_names = gcc_xo_200_spi,
 359                 .num_parents = 2,
 360                 .ops = &clk_rcg2_ops,
 361         },
 362 };
 363
 364 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
 365         .halt_reg = 0x203c,
 366         .clkr = {
 367                 .enable_reg = 0x203c,
 368                 .enable_mask = BIT(0),
 369                 .hw.init = &(struct clk_init_data){
 370                         .name = "gcc_blsp1_uart1_apps_clk",
 371                         .parent_names = (const char *[]){
 372                                 "blsp1_uart1_apps_clk_src",
 373                         },
 374                         .flags = CLK_SET_RATE_PARENT,
 375                         .num_parents = 1,
 376                         .ops = &clk_branch2_ops,
 377                 },
 378         },
 379 };
 380
 381 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
 382         .cmd_rcgr = 0x3034,
 383         .mnd_width = 16,
 384         .hid_width = 5,
 385         .freq_tbl = ftbl_gcc_blsp1_uart1_2_apps_clk,
 386         .parent_map = gcc_xo_200_spi_map,
 387         .clkr.hw.init = &(struct clk_init_data){
 388                 .name = "blsp1_uart2_apps_clk_src",
 389                 .parent_names = gcc_xo_200_spi,
 390                 .num_parents = 2,
 391                 .ops = &clk_rcg2_ops,
 392         },
 393 };
 394
 395 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
 396         .halt_reg = 0x302c,
 397         .clkr = {
 398                 .enable_reg = 0x302c,
 399                 .enable_mask = BIT(0),
 400                 .hw.init = &(struct clk_init_data){
 401                         .name = "gcc_blsp1_uart2_apps_clk",
 402                         .parent_names = (const char *[]){
 403                                 "blsp1_uart2_apps_clk_src",
 404                         },
 405                         .num_parents = 1,
 406                         .ops = &clk_branch2_ops,
 407                         .flags = CLK_SET_RATE_PARENT,
 408                 },
 409         },
 410 };
 411
 412 static const struct freq_tbl ftbl_gcc_gp_clk[] = {
 413         F(1250000,  FE_PLL_200, 1, 16, 0),
 414         F(2500000,  FE_PLL_200, 1,  8, 0),
 415         F(5000000,  FE_PLL_200, 1,  4, 0),
 416         { }
 417 };
 418
 419 static struct clk_rcg2 gp1_clk_src = {
 420         .cmd_rcgr = 0x8004,
 421         .mnd_width = 8,
 422         .hid_width = 5,
 423         .freq_tbl = ftbl_gcc_gp_clk,
 424         .parent_map = gcc_xo_200_map,
 425         .clkr.hw.init = &(struct clk_init_data){
 426                 .name = "gp1_clk_src",
 427                 .parent_names = gcc_xo_200,
 428                 .num_parents = 2,
 429                 .ops = &clk_rcg2_ops,
 430         },
 431 };
 432
 433 static struct clk_branch gcc_gp1_clk = {
 434         .halt_reg = 0x8000,
 435         .clkr = {
 436                 .enable_reg = 0x8000,
 437                 .enable_mask = BIT(0),
 438                 .hw.init = &(struct clk_init_data){
 439                         .name = "gcc_gp1_clk",
 440                         .parent_names = (const char *[]){
 441                                 "gp1_clk_src",
 442                         },
 443                         .num_parents = 1,
 444                         .ops = &clk_branch2_ops,
 445                         .flags = CLK_SET_RATE_PARENT,
 446                 },
 447         },
 448 };
 449
 450 static struct clk_rcg2 gp2_clk_src = {
 451         .cmd_rcgr = 0x9004,
 452         .mnd_width = 8,
 453         .hid_width = 5,
 454         .freq_tbl = ftbl_gcc_gp_clk,
 455         .parent_map = gcc_xo_200_map,
 456         .clkr.hw.init = &(struct clk_init_data){
 457                 .name = "gp2_clk_src",
 458                 .parent_names = gcc_xo_200,
 459                 .num_parents = 2,
 460                 .ops = &clk_rcg2_ops,
 461         },
 462 };
 463
 464 static struct clk_branch gcc_gp2_clk = {
 465         .halt_reg = 0x9000,
 466         .clkr = {
 467                 .enable_reg = 0x9000,
 468                 .enable_mask = BIT(0),
 469                 .hw.init = &(struct clk_init_data){
 470                         .name = "gcc_gp2_clk",
 471                         .parent_names = (const char *[]){
 472                                 "gp2_clk_src",
 473                         },
 474                         .num_parents = 1,
 475                         .ops = &clk_branch2_ops,
 476                         .flags = CLK_SET_RATE_PARENT,
 477                 },
 478         },
 479 };
 480
 481 static struct clk_rcg2 gp3_clk_src = {
 482         .cmd_rcgr = 0xa004,
 483         .mnd_width = 8,
 484         .hid_width = 5,
 485         .freq_tbl = ftbl_gcc_gp_clk,
 486         .parent_map = gcc_xo_200_map,
 487         .clkr.hw.init = &(struct clk_init_data){
 488                 .name = "gp3_clk_src",
 489                 .parent_names = gcc_xo_200,
 490                 .num_parents = 2,
 491                 .ops = &clk_rcg2_ops,
 492         },
 493 };
 494
 495 static struct clk_branch gcc_gp3_clk = {
 496         .halt_reg = 0xa000,
 497         .clkr = {
 498                 .enable_reg = 0xa000,
 499                 .enable_mask = BIT(0),
 500                 .hw.init = &(struct clk_init_data){
 501                         .name = "gcc_gp3_clk",
 502                         .parent_names = (const char *[]){
 503                                 "gp3_clk_src",
 504                         },
 505                         .num_parents = 1,
 506                         .ops = &clk_branch2_ops,
 507                         .flags = CLK_SET_RATE_PARENT,
 508                 },
 509         },
 510 };
 511
 512 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk[] = {
 513         F(144000,    P_XO,                      1,  3, 240),
 514         F(400000,    P_XO,                      1,  1, 0),
 515         F(20000000,  FE_PLL_500,                1,  1, 25),
 516         F(25000000,  FE_PLL_500,                1,  1, 20),
 517         F(50000000,  FE_PLL_500,                1,  1, 10),
 518         F(100000000, FE_PLL_500,                1,  1, 5),
 519         F(193000000, DDRC_PLL_666_SDCC,         1,  0, 0),
 520         { }
 521 };
 522
 523 static struct clk_rcg2  sdcc1_apps_clk_src = {
 524         .cmd_rcgr = 0x18004,
 525         .hid_width = 5,
 526         .freq_tbl = ftbl_gcc_sdcc1_apps_clk,
 527         .parent_map = gcc_xo_sdcc1_500_map,
 528         .clkr.hw.init = &(struct clk_init_data){
 529                 .name = "sdcc1_apps_clk_src",
 530                 .parent_names = gcc_xo_sdcc1_500,
 531                 .num_parents = 3,
 532                 .ops = &clk_rcg2_ops,
 533                 .flags = CLK_SET_RATE_PARENT,
 534         },
 535 };
 536
 537 static const struct freq_tbl ftbl_gcc_apps_clk[] = {
 538         F(48000000, P_XO,          1, 0, 0),
 539         F(200000000, FE_PLL_200,   1, 0, 0),
 540         F(500000000, FE_PLL_500,   1, 0, 0),
 541         F(626000000, DDRC_PLL_666, 1, 0, 0),
 542         { }
 543 };
 544
 545 static struct clk_rcg2 apps_clk_src = {
 546         .cmd_rcgr = 0x1900c,
 547         .hid_width = 5,
 548         .freq_tbl = ftbl_gcc_apps_clk,
 549         .parent_map = gcc_xo_ddr_500_200_map,
 550         .clkr.hw.init = &(struct clk_init_data){
 551                 .name = "apps_clk_src",
 552                 .parent_names = gcc_xo_ddr_500_200,
 553                 .num_parents = 4,
 554                 .ops = &clk_rcg2_ops,
 555         },
 556 };
 557
 558 static const struct freq_tbl ftbl_gcc_apps_ahb_clk[] = {
 559         F(48000000, P_XO,          1, 0, 0),
 560         F(100000000, FE_PLL_200,   2, 0, 0),
 561         { }
 562 };
 563
 564 static struct clk_rcg2 apps_ahb_clk_src = {
 565         .cmd_rcgr = 0x19014,
 566         .hid_width = 5,
 567         .parent_map = gcc_xo_200_500_map,
 568         .freq_tbl = ftbl_gcc_apps_ahb_clk,
 569         .clkr.hw.init = &(struct clk_init_data){
 570                 .name = "apps_ahb_clk_src",
 571                 .parent_names = gcc_xo_200_500,
 572                 .num_parents = 3,
 573                 .ops = &clk_rcg2_ops,
 574         },
 575 };
 576
 577 static struct clk_branch gcc_apss_ahb_clk = {
 578         .halt_reg = 0x19004,
 579         .halt_check = BRANCH_HALT_VOTED,
 580         .clkr = {
 581                 .enable_reg = 0x6000,
 582                 .enable_mask = BIT(14),
 583                 .hw.init = &(struct clk_init_data){
 584                         .name = "gcc_apss_ahb_clk",
 585                         .parent_names = (const char *[]){
 586                                 "apps_ahb_clk_src",
 587                         },
 588                         .num_parents = 1,
 589                         .ops = &clk_branch2_ops,
 590                         .flags = CLK_SET_RATE_PARENT,
 591                 },
 592         },
 593 };
 594
 595 static struct clk_branch gcc_blsp1_ahb_clk = {
 596         .halt_reg = 0x1008,
 597         .halt_check = BRANCH_HALT_VOTED,
 598         .clkr = {
 599                 .enable_reg = 0x6000,
 600                 .enable_mask = BIT(10),
 601                 .hw.init = &(struct clk_init_data){
 602                         .name = "gcc_blsp1_ahb_clk",
 603                         .parent_names = (const char *[]){
 604                                 "pcnoc_clk_src",
 605                         },
 606                         .num_parents = 1,
 607                         .ops = &clk_branch2_ops,
 608                 },
 609         },
 610 };
 611
 612 static struct clk_branch gcc_dcd_xo_clk = {
 613         .halt_reg = 0x2103c,
 614         .clkr = {
 615                 .enable_reg = 0x2103c,
 616                 .enable_mask = BIT(0),
 617                 .hw.init = &(struct clk_init_data){
 618                         .name = "gcc_dcd_xo_clk",
 619                         .parent_names = (const char *[]){
 620                                 "xo",
 621                         },
 622                         .num_parents = 1,
 623                         .ops = &clk_branch2_ops,
 624                 },
 625         },
 626 };
 627
 628 static struct clk_branch gcc_boot_rom_ahb_clk = {
 629         .halt_reg = 0x1300c,
 630         .clkr = {
 631                 .enable_reg = 0x1300c,
 632                 .enable_mask = BIT(0),
 633                 .hw.init = &(struct clk_init_data){
 634                         .name = "gcc_boot_rom_ahb_clk",
 635                         .parent_names = (const char *[]){
 636                                 "pcnoc_clk_src",
 637                         },
 638                         .num_parents = 1,
 639                         .ops = &clk_branch2_ops,
 640                         .flags = CLK_SET_RATE_PARENT,
 641                 },
 642         },
 643 };
 644
 645 static struct clk_branch gcc_crypto_ahb_clk = {
 646         .halt_reg = 0x16024,
 647         .halt_check = BRANCH_HALT_VOTED,
 648         .clkr = {
 649                 .enable_reg = 0x6000,
 650                 .enable_mask = BIT(0),
 651                 .hw.init = &(struct clk_init_data){
 652                         .name = "gcc_crypto_ahb_clk",
 653                         .parent_names = (const char *[]){
 654                                 "pcnoc_clk_src",
 655                         },
 656                         .num_parents = 1,
 657                         .ops = &clk_branch2_ops,
 658                 },
 659         },
 660 };
 661
 662 static struct clk_branch gcc_crypto_axi_clk = {
 663         .halt_reg = 0x16020,
 664         .halt_check = BRANCH_HALT_VOTED,
 665         .clkr = {
 666                 .enable_reg = 0x6000,
 667                 .enable_mask = BIT(1),
 668                 .hw.init = &(struct clk_init_data){
 669                         .name = "gcc_crypto_axi_clk",
 670                         .parent_names = (const char *[]){
 671                                 "fepll125",
 672                         },
 673                         .num_parents = 1,
 674                         .ops = &clk_branch2_ops,
 675                 },
 676         },
 677 };
 678
 679 static struct clk_branch gcc_crypto_clk = {
 680         .halt_reg = 0x1601c,
 681         .halt_check = BRANCH_HALT_VOTED,
 682         .clkr = {
 683                 .enable_reg = 0x6000,
 684                 .enable_mask = BIT(2),
 685                 .hw.init = &(struct clk_init_data){
 686                         .name = "gcc_crypto_clk",
 687                         .parent_names = (const char *[]){
 688                                 "fepll125",
 689                         },
 690                         .num_parents = 1,
 691                         .ops = &clk_branch2_ops,
 692                 },
 693         },
 694 };
 695
 696 static struct clk_branch gcc_ess_clk = {
 697         .halt_reg = 0x12010,
 698         .clkr = {
 699                 .enable_reg = 0x12010,
 700                 .enable_mask = BIT(0),
 701                 .hw.init = &(struct clk_init_data){
 702                         .name = "gcc_ess_clk",
 703                         .parent_names = (const char *[]){
 704                                 "fephy_125m_dly_clk_src",
 705                         },
 706                         .num_parents = 1,
 707                         .ops = &clk_branch2_ops,
 708                         .flags = CLK_SET_RATE_PARENT,
 709                 },
 710         },
 711 };
 712
 713 static struct clk_branch gcc_imem_axi_clk = {
 714         .halt_reg = 0xe004,
 715         .halt_check = BRANCH_HALT_VOTED,
 716         .clkr = {
 717                 .enable_reg = 0x6000,
 718                 .enable_mask = BIT(17),
 719                 .hw.init = &(struct clk_init_data){
 720                         .name = "gcc_imem_axi_clk",
 721                         .parent_names = (const char *[]){
 722                                 "fepll200",
 723                         },
 724                         .num_parents = 1,
 725                         .ops = &clk_branch2_ops,
 726                 },
 727         },
 728 };
 729
 730 static struct clk_branch gcc_imem_cfg_ahb_clk = {
 731         .halt_reg = 0xe008,
 732         .clkr = {
 733                 .enable_reg = 0xe008,
 734                 .enable_mask = BIT(0),
 735                 .hw.init = &(struct clk_init_data){
 736                         .name = "gcc_imem_cfg_ahb_clk",
 737                         .parent_names = (const char *[]){
 738                                 "pcnoc_clk_src",
 739                         },
 740                         .num_parents = 1,
 741                         .ops = &clk_branch2_ops,
 742                 },
 743         },
 744 };
 745
 746 static struct clk_branch gcc_pcie_ahb_clk = {
 747         .halt_reg = 0x1d00c,
 748         .clkr = {
 749                 .enable_reg = 0x1d00c,
 750                 .enable_mask = BIT(0),
 751                 .hw.init = &(struct clk_init_data){
 752                         .name = "gcc_pcie_ahb_clk",
 753                         .parent_names = (const char *[]){
 754                                 "pcnoc_clk_src",
 755                         },
 756                         .num_parents = 1,
 757                         .ops = &clk_branch2_ops,
 758                 },
 759         },
 760 };
 761
 762 static struct clk_branch gcc_pcie_axi_m_clk = {
 763         .halt_reg = 0x1d004,
 764         .clkr = {
 765                 .enable_reg = 0x1d004,
 766                 .enable_mask = BIT(0),
 767                 .hw.init = &(struct clk_init_data){
 768                         .name = "gcc_pcie_axi_m_clk",
 769                         .parent_names = (const char *[]){
 770                                 "fepll200",
 771                         },
 772                         .num_parents = 1,
 773                         .ops = &clk_branch2_ops,
 774                 },
 775         },
 776 };
 777
 778 static struct clk_branch gcc_pcie_axi_s_clk = {
 779         .halt_reg = 0x1d008,
 780         .clkr = {
 781                 .enable_reg = 0x1d008,
 782                 .enable_mask = BIT(0),
 783                 .hw.init = &(struct clk_init_data){
 784                         .name = "gcc_pcie_axi_s_clk",
 785                         .parent_names = (const char *[]){
 786                                 "fepll200",
 787                         },
 788                         .num_parents = 1,
 789                         .ops = &clk_branch2_ops,
 790                 },
 791         },
 792 };
 793
 794 static struct clk_branch gcc_prng_ahb_clk = {
 795         .halt_reg = 0x13004,
 796         .halt_check = BRANCH_HALT_VOTED,
 797         .clkr = {
 798                 .enable_reg = 0x6000,
 799                 .enable_mask = BIT(8),
 800                 .hw.init = &(struct clk_init_data){
 801                         .name = "gcc_prng_ahb_clk",
 802                         .parent_names = (const char *[]){
 803                                 "pcnoc_clk_src",
 804                         },
 805                         .num_parents = 1,
 806                         .ops = &clk_branch2_ops,
 807                 },
 808         },
 809 };
 810
 811 static struct clk_branch gcc_qpic_ahb_clk = {
 812         .halt_reg = 0x1c008,
 813         .clkr = {
 814                 .enable_reg = 0x1c008,
 815                 .enable_mask = BIT(0),
 816                 .hw.init = &(struct clk_init_data){
 817                         .name = "gcc_qpic_ahb_clk",
 818                         .parent_names = (const char *[]){
 819                                 "pcnoc_clk_src",
 820                         },
 821                         .num_parents = 1,
 822                         .ops = &clk_branch2_ops,
 823                 },
 824         },
 825 };
 826
 827 static struct clk_branch gcc_qpic_clk = {
 828         .halt_reg = 0x1c004,
 829         .clkr = {
 830                 .enable_reg = 0x1c004,
 831                 .enable_mask = BIT(0),
 832                 .hw.init = &(struct clk_init_data){
 833                         .name = "gcc_qpic_clk",
 834                         .parent_names = (const char *[]){
 835                                 "pcnoc_clk_src",
 836                         },
 837                         .num_parents = 1,
 838                         .ops = &clk_branch2_ops,
 839                 },
 840         },
 841 };
 842
 843 static struct clk_branch gcc_sdcc1_ahb_clk = {
 844         .halt_reg = 0x18010,
 845         .clkr = {
 846                 .enable_reg = 0x18010,
 847                 .enable_mask = BIT(0),
 848                 .hw.init = &(struct clk_init_data){
 849                         .name = "gcc_sdcc1_ahb_clk",
 850                         .parent_names = (const char *[]){
 851                                 "pcnoc_clk_src",
 852                         },
 853                         .num_parents = 1,
 854                         .ops = &clk_branch2_ops,
 855                 },
 856         },
 857 };
 858
 859 static struct clk_branch gcc_sdcc1_apps_clk = {
 860         .halt_reg = 0x1800c,
 861         .clkr = {
 862                 .enable_reg = 0x1800c,
 863                 .enable_mask = BIT(0),
 864                 .hw.init = &(struct clk_init_data){
 865                         .name = "gcc_sdcc1_apps_clk",
 866                         .parent_names = (const char *[]){
 867                                 "sdcc1_apps_clk_src",
 868                         },
 869                         .num_parents = 1,
 870                         .ops = &clk_branch2_ops,
 871                         .flags = CLK_SET_RATE_PARENT,
 872                 },
 873         },
 874 };
 875
 876 static struct clk_branch gcc_tlmm_ahb_clk = {
 877         .halt_reg = 0x5004,
 878         .halt_check = BRANCH_HALT_VOTED,
 879         .clkr = {
 880                 .enable_reg = 0x6000,
 881                 .enable_mask = BIT(5),
 882                 .hw.init = &(struct clk_init_data){
 883                         .name = "gcc_tlmm_ahb_clk",
 884                         .parent_names = (const char *[]){
 885                                 "pcnoc_clk_src",
 886                         },
 887                         .num_parents = 1,
 888                         .ops = &clk_branch2_ops,
 889                 },
 890         },
 891 };
 892
 893 static struct clk_branch gcc_usb2_master_clk = {
 894         .halt_reg = 0x1e00c,
 895         .clkr = {
 896                 .enable_reg = 0x1e00c,
 897                 .enable_mask = BIT(0),
 898                 .hw.init = &(struct clk_init_data){
 899                         .name = "gcc_usb2_master_clk",
 900                         .parent_names = (const char *[]){
 901                                 "pcnoc_clk_src",
 902                         },
 903                         .num_parents = 1,
 904                         .ops = &clk_branch2_ops,
 905                 },
 906         },
 907 };
 908
 909 static struct clk_branch gcc_usb2_sleep_clk = {
 910         .halt_reg = 0x1e010,
 911         .clkr = {
 912                 .enable_reg = 0x1e010,
 913                 .enable_mask = BIT(0),
 914                 .hw.init = &(struct clk_init_data){
 915                         .name = "gcc_usb2_sleep_clk",
 916                         .parent_names = (const char *[]){
 917                                 "gcc_sleep_clk_src",
 918                         },
 919                         .num_parents = 1,
 920                         .ops = &clk_branch2_ops,
 921                 },
 922         },
 923 };
 924
 925 static struct clk_branch gcc_usb2_mock_utmi_clk = {
 926         .halt_reg = 0x1e014,
 927         .clkr = {
 928                 .enable_reg = 0x1e014,
 929                 .enable_mask = BIT(0),
 930                 .hw.init = &(struct clk_init_data){
 931                         .name = "gcc_usb2_mock_utmi_clk",
 932                         .parent_names = (const char *[]){
 933                                 "usb30_mock_utmi_clk_src",
 934                         },
 935                         .num_parents = 1,
 936                         .ops = &clk_branch2_ops,
 937                         .flags = CLK_SET_RATE_PARENT,
 938                 },
 939         },
 940 };
 941
 942 static const struct freq_tbl ftbl_gcc_usb30_mock_utmi_clk[] = {
 943         F(2000000, FE_PLL_200, 10, 0, 0),
 944         { }
 945 };
 946
 947 static struct clk_rcg2 usb30_mock_utmi_clk_src = {
 948         .cmd_rcgr = 0x1e000,
 949         .hid_width = 5,
 950         .parent_map = gcc_xo_200_map,
 951         .freq_tbl = ftbl_gcc_usb30_mock_utmi_clk,
 952         .clkr.hw.init = &(struct clk_init_data){
 953                 .name = "usb30_mock_utmi_clk_src",
 954                 .parent_names = gcc_xo_200,
 955                 .num_parents = 2,
 956                 .ops = &clk_rcg2_ops,
 957         },
 958 };
 959
 960 static struct clk_branch gcc_usb3_master_clk = {
 961         .halt_reg = 0x1e028,
 962         .clkr = {
 963                 .enable_reg = 0x1e028,
 964                 .enable_mask = BIT(0),
 965                 .hw.init = &(struct clk_init_data){
 966                         .name = "gcc_usb3_master_clk",
 967                         .parent_names = (const char *[]){
 968                                 "fepll125",
 969                         },
 970                         .num_parents = 1,
 971                         .ops = &clk_branch2_ops,
 972                 },
 973         },
 974 };
 975
 976 static struct clk_branch gcc_usb3_sleep_clk = {
 977         .halt_reg = 0x1e02C,
 978         .clkr = {
 979                 .enable_reg = 0x1e02C,
 980                 .enable_mask = BIT(0),
 981                 .hw.init = &(struct clk_init_data){
 982                         .name = "gcc_usb3_sleep_clk",
 983                         .parent_names = (const char *[]){
 984                                 "gcc_sleep_clk_src",
 985                         },
 986                         .num_parents = 1,
 987                         .ops = &clk_branch2_ops,
 988                 },
 989         },
 990 };
 991
 992 static struct clk_branch gcc_usb3_mock_utmi_clk = {
 993         .halt_reg = 0x1e030,
 994         .clkr = {
 995                 .enable_reg = 0x1e030,
 996                 .enable_mask = BIT(0),
 997                 .hw.init = &(struct clk_init_data){
 998                         .name = "gcc_usb3_mock_utmi_clk",
 999                         .parent_names = (const char *[]){
1000                                 "usb30_mock_utmi_clk_src",
1001                         },
1002                         .num_parents = 1,
1003                         .ops = &clk_branch2_ops,
1004                         .flags = CLK_SET_RATE_PARENT,
1005                 },
1006         },
1007 };
1008
1009 static const struct freq_tbl ftbl_gcc_fephy_dly_clk[] = {
1010         F(125000000, FE_PLL_125_DLY, 1, 0, 0),
1011         { }
1012 };
1013
1014 static struct clk_rcg2 fephy_125m_dly_clk_src = {
1015         .cmd_rcgr = 0x12000,
1016         .hid_width = 5,
1017         .parent_map = gcc_xo_125_dly_map,
1018         .freq_tbl = ftbl_gcc_fephy_dly_clk,
1019         .clkr.hw.init = &(struct clk_init_data){
1020                 .name = "fephy_125m_dly_clk_src",
1021                 .parent_names = gcc_xo_125_dly,
1022                 .num_parents = 2,
1023                 .ops = &clk_rcg2_ops,
1024         },
1025 };
1026
1027
1028 static const struct freq_tbl ftbl_gcc_wcss2g_clk[] = {
1029         F(48000000, P_XO, 1, 0, 0),
1030         F(250000000, FE_PLL_WCSS2G, 1, 0, 0),
1031         { }
1032 };
1033
1034 static struct clk_rcg2 wcss2g_clk_src = {
1035         .cmd_rcgr = 0x1f000,
1036         .hid_width = 5,
1037         .freq_tbl = ftbl_gcc_wcss2g_clk,
1038         .parent_map = gcc_xo_wcss2g_map,
1039         .clkr.hw.init = &(struct clk_init_data){
1040                 .name = "wcss2g_clk_src",
1041                 .parent_names = gcc_xo_wcss2g,
1042                 .num_parents = 2,
1043                 .ops = &clk_rcg2_ops,
1044                 .flags = CLK_SET_RATE_PARENT,
1045         },
1046 };
1047
1048 static struct clk_branch gcc_wcss2g_clk = {
1049         .halt_reg = 0x1f00C,
1050         .clkr = {
1051                 .enable_reg = 0x1f00C,
1052                 .enable_mask = BIT(0),
1053                 .hw.init = &(struct clk_init_data){
1054                         .name = "gcc_wcss2g_clk",
1055                         .parent_names = (const char *[]){
1056                                 "wcss2g_clk_src",
1057                         },
1058                         .num_parents = 1,
1059                         .ops = &clk_branch2_ops,
1060                         .flags = CLK_SET_RATE_PARENT,
1061                 },
1062         },
1063 };
1064
1065 static struct clk_branch gcc_wcss2g_ref_clk = {
1066         .halt_reg = 0x1f00C,
1067         .clkr = {
1068                 .enable_reg = 0x1f00C,
1069                 .enable_mask = BIT(0),
1070                 .hw.init = &(struct clk_init_data){
1071                         .name = "gcc_wcss2g_ref_clk",
1072                         .parent_names = (const char *[]){
1073                                 "xo",
1074                         },
1075                         .num_parents = 1,
1076                         .ops = &clk_branch2_ops,
1077                         .flags = CLK_SET_RATE_PARENT,
1078                 },
1079         },
1080 };
1081
1082 static struct clk_branch gcc_wcss2g_rtc_clk = {
1083         .halt_reg = 0x1f010,
1084         .clkr = {
1085                 .enable_reg = 0x1f010,
1086                 .enable_mask = BIT(0),
1087                 .hw.init = &(struct clk_init_data){
1088                         .name = "gcc_wcss2g_rtc_clk",
1089                         .parent_names = (const char *[]){
1090                                 "gcc_sleep_clk_src",
1091                         },
1092                         .num_parents = 1,
1093                         .ops = &clk_branch2_ops,
1094                 },
1095         },
1096 };
1097
1098 static const struct freq_tbl ftbl_gcc_wcss5g_clk[] = {
1099         F(48000000, P_XO, 1, 0, 0),
1100         F(250000000, FE_PLL_WCSS5G, 1, 0, 0),
1101         { }
1102 };
1103
1104 static struct clk_rcg2 wcss5g_clk_src = {
1105         .cmd_rcgr = 0x20000,
1106         .hid_width = 5,
1107         .parent_map = gcc_xo_wcss5g_map,
1108         .freq_tbl = ftbl_gcc_wcss5g_clk,
1109         .clkr.hw.init = &(struct clk_init_data){
1110                 .name = "wcss5g_clk_src",
1111                 .parent_names = gcc_xo_wcss5g,
1112                 .num_parents = 2,
1113                 .ops = &clk_rcg2_ops,
1114         },
1115 };
1116
1117 static struct clk_branch gcc_wcss5g_clk = {
1118         .halt_reg = 0x2000c,
1119         .clkr = {
1120                 .enable_reg = 0x2000c,
1121                 .enable_mask = BIT(0),
1122                 .hw.init = &(struct clk_init_data){
1123                         .name = "gcc_wcss5g_clk",
1124                         .parent_names = (const char *[]){
1125                                 "wcss5g_clk_src",
1126                         },
1127                         .num_parents = 1,
1128                         .ops = &clk_branch2_ops,
1129                         .flags = CLK_SET_RATE_PARENT,
1130                 },
1131         },
1132 };
1133
1134 static struct clk_branch gcc_wcss5g_ref_clk = {
1135         .halt_reg = 0x2000c,
1136         .clkr = {
1137                 .enable_reg = 0x2000c,
1138                 .enable_mask = BIT(0),
1139                 .hw.init = &(struct clk_init_data){
1140                         .name = "gcc_wcss5g_ref_clk",
1141                         .parent_names = (const char *[]){
1142                                 "xo",
1143                         },
1144                         .num_parents = 1,
1145                         .ops = &clk_branch2_ops,
1146                         .flags = CLK_SET_RATE_PARENT,
1147                 },
1148         },
1149 };
1150
1151 static struct clk_branch gcc_wcss5g_rtc_clk = {
1152         .halt_reg = 0x20010,
1153         .clkr = {
1154                 .enable_reg = 0x20010,
1155                 .enable_mask = BIT(0),
1156                 .hw.init = &(struct clk_init_data){
1157                         .name = "gcc_wcss5g_rtc_clk",
1158                         .parent_names = (const char *[]){
1159                                 "gcc_sleep_clk_src",
1160                         },
1161                         .num_parents = 1,
1162                         .ops = &clk_branch2_ops,
1163                         .flags = CLK_SET_RATE_PARENT,
1164                 },
1165         },
1166 };
1167
1168 static struct clk_regmap *gcc_ipq4019_clocks[] = {
1169         [AUDIO_CLK_SRC] = &audio_clk_src.clkr,
1170         [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
1171         [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
1172         [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
1173         [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
1174         [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
1175         [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
1176         [GCC_USB3_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
1177         [GCC_APPS_CLK_SRC] = &apps_clk_src.clkr,
1178         [GCC_APPS_AHB_CLK_SRC] = &apps_ahb_clk_src.clkr,
1179         [GP1_CLK_SRC] = &gp1_clk_src.clkr,
1180         [GP2_CLK_SRC] = &gp2_clk_src.clkr,
1181         [GP3_CLK_SRC] = &gp3_clk_src.clkr,
1182         [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
1183         [FEPHY_125M_DLY_CLK_SRC] = &fephy_125m_dly_clk_src.clkr,
1184         [WCSS2G_CLK_SRC] = &wcss2g_clk_src.clkr,
1185         [WCSS5G_CLK_SRC] = &wcss5g_clk_src.clkr,
1186         [GCC_APSS_AHB_CLK] = &gcc_apss_ahb_clk.clkr,
1187         [GCC_AUDIO_AHB_CLK] = &gcc_audio_ahb_clk.clkr,
1188         [GCC_AUDIO_PWM_CLK] = &gcc_audio_pwm_clk.clkr,
1189         [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
1190         [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
1191         [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
1192         [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
1193         [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
1194         [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
1195         [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
1196         [GCC_DCD_XO_CLK] = &gcc_dcd_xo_clk.clkr,
1197         [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
1198         [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
1199         [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
1200         [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
1201         [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
1202         [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
1203         [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
1204         [GCC_ESS_CLK] = &gcc_ess_clk.clkr,
1205         [GCC_IMEM_AXI_CLK] = &gcc_imem_axi_clk.clkr,
1206         [GCC_IMEM_CFG_AHB_CLK] = &gcc_imem_cfg_ahb_clk.clkr,
1207         [GCC_PCIE_AHB_CLK] = &gcc_pcie_ahb_clk.clkr,
1208         [GCC_PCIE_AXI_M_CLK] = &gcc_pcie_axi_m_clk.clkr,
1209         [GCC_PCIE_AXI_S_CLK] = &gcc_pcie_axi_s_clk.clkr,
1210         [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
1211         [GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
1212         [GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
1213         [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
1214         [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
1215         [GCC_TLMM_AHB_CLK] = &gcc_tlmm_ahb_clk.clkr,
1216         [GCC_USB2_MASTER_CLK] = &gcc_usb2_master_clk.clkr,
1217         [GCC_USB2_SLEEP_CLK] = &gcc_usb2_sleep_clk.clkr,
1218         [GCC_USB2_MOCK_UTMI_CLK] = &gcc_usb2_mock_utmi_clk.clkr,
1219         [GCC_USB3_MASTER_CLK] = &gcc_usb3_master_clk.clkr,
1220         [GCC_USB3_SLEEP_CLK] = &gcc_usb3_sleep_clk.clkr,
1221         [GCC_USB3_MOCK_UTMI_CLK] = &gcc_usb3_mock_utmi_clk.clkr,
1222         [GCC_WCSS2G_CLK] = &gcc_wcss2g_clk.clkr,
1223         [GCC_WCSS2G_REF_CLK] = &gcc_wcss2g_ref_clk.clkr,
1224         [GCC_WCSS2G_RTC_CLK] = &gcc_wcss2g_rtc_clk.clkr,
1225         [GCC_WCSS5G_CLK] = &gcc_wcss5g_clk.clkr,
1226         [GCC_WCSS5G_REF_CLK] = &gcc_wcss5g_ref_clk.clkr,
1227         [GCC_WCSS5G_RTC_CLK] = &gcc_wcss5g_rtc_clk.clkr,
1228 };
1229
1230 static const struct qcom_reset_map gcc_ipq4019_resets[] = {
1231         [WIFI0_CPU_INIT_RESET] = { 0x1f008, 5 },
1232         [WIFI0_RADIO_SRIF_RESET] = { 0x1f008, 4 },
1233         [WIFI0_RADIO_WARM_RESET] = { 0x1f008, 3 },
1234         [WIFI0_RADIO_COLD_RESET] = { 0x1f008, 2 },
1235         [WIFI0_CORE_WARM_RESET] = { 0x1f008, 1 },
1236         [WIFI0_CORE_COLD_RESET] = { 0x1f008, 0 },
1237         [WIFI1_CPU_INIT_RESET] = { 0x20008, 5 },
1238         [WIFI1_RADIO_SRIF_RESET] = { 0x20008, 4 },
1239         [WIFI1_RADIO_WARM_RESET] = { 0x20008, 3 },
1240         [WIFI1_RADIO_COLD_RESET] = { 0x20008, 2 },
1241         [WIFI1_CORE_WARM_RESET] = { 0x20008, 1 },
1242         [WIFI1_CORE_COLD_RESET] = { 0x20008, 0 },
1243         [USB3_UNIPHY_PHY_ARES] = { 0x1e038, 5 },
1244         [USB3_HSPHY_POR_ARES] = { 0x1e038, 4 },
1245         [USB3_HSPHY_S_ARES] = { 0x1e038, 2 },
1246         [USB2_HSPHY_POR_ARES] = { 0x1e01c, 4 },
1247         [USB2_HSPHY_S_ARES] = { 0x1e01c, 2 },
1248         [PCIE_PHY_AHB_ARES] = { 0x1d010, 11 },
1249         [PCIE_AHB_ARES] = { 0x1d010, 10 },
1250         [PCIE_PWR_ARES] = { 0x1d010, 9 },
1251         [PCIE_PIPE_STICKY_ARES] = { 0x1d010, 8 },
1252         [PCIE_AXI_M_STICKY_ARES] = { 0x1d010, 7 },
1253         [PCIE_PHY_ARES] = { 0x1d010, 6 },
1254         [PCIE_PARF_XPU_ARES] = { 0x1d010, 5 },
1255         [PCIE_AXI_S_XPU_ARES] = { 0x1d010, 4 },
1256         [PCIE_AXI_M_VMIDMT_ARES] = { 0x1d010, 3 },
1257         [PCIE_PIPE_ARES] = { 0x1d010, 2 },
1258         [PCIE_AXI_S_ARES] = { 0x1d010, 1 },
1259         [PCIE_AXI_M_ARES] = { 0x1d010, 0 },
1260         [ESS_RESET] = { 0x12008, 0},
1261         [GCC_BLSP1_BCR] = {0x01000, 0},
1262         [GCC_BLSP1_QUP1_BCR] = {0x02000, 0},
1263         [GCC_BLSP1_UART1_BCR] = {0x02038, 0},
1264         [GCC_BLSP1_QUP2_BCR] = {0x03008, 0},
1265         [GCC_BLSP1_UART2_BCR] = {0x03028, 0},
1266         [GCC_BIMC_BCR] = {0x04000, 0},
1267         [GCC_TLMM_BCR] = {0x05000, 0},
1268         [GCC_IMEM_BCR] = {0x0E000, 0},
1269         [GCC_ESS_BCR] = {0x12008, 0},
1270         [GCC_PRNG_BCR] = {0x13000, 0},
1271         [GCC_BOOT_ROM_BCR] = {0x13008, 0},
1272         [GCC_CRYPTO_BCR] = {0x16000, 0},
1273         [GCC_SDCC1_BCR] = {0x18000, 0},
1274         [GCC_SEC_CTRL_BCR] = {0x1A000, 0},
1275         [GCC_AUDIO_BCR] = {0x1B008, 0},
1276         [GCC_QPIC_BCR] = {0x1C000, 0},
1277         [GCC_PCIE_BCR] = {0x1D000, 0},
1278         [GCC_USB2_BCR] = {0x1E008, 0},
1279         [GCC_USB2_PHY_BCR] = {0x1E018, 0},
1280         [GCC_USB3_BCR] = {0x1E024, 0},
1281         [GCC_USB3_PHY_BCR] = {0x1E034, 0},
1282         [GCC_SYSTEM_NOC_BCR] = {0x21000, 0},
1283         [GCC_PCNOC_BCR] = {0x2102C, 0},
1284         [GCC_DCD_BCR] = {0x21038, 0},
1285         [GCC_SNOC_BUS_TIMEOUT0_BCR] = {0x21064, 0},
1286         [GCC_SNOC_BUS_TIMEOUT1_BCR] = {0x2106C, 0},
1287         [GCC_SNOC_BUS_TIMEOUT2_BCR] = {0x21074, 0},
1288         [GCC_SNOC_BUS_TIMEOUT3_BCR] = {0x2107C, 0},
1289         [GCC_PCNOC_BUS_TIMEOUT0_BCR] = {0x21084, 0},
1290         [GCC_PCNOC_BUS_TIMEOUT1_BCR] = {0x2108C, 0},
1291         [GCC_PCNOC_BUS_TIMEOUT2_BCR] = {0x21094, 0},
1292         [GCC_PCNOC_BUS_TIMEOUT3_BCR] = {0x2109C, 0},
1293         [GCC_PCNOC_BUS_TIMEOUT4_BCR] = {0x210A4, 0},
1294         [GCC_PCNOC_BUS_TIMEOUT5_BCR] = {0x210AC, 0},
1295         [GCC_PCNOC_BUS_TIMEOUT6_BCR] = {0x210B4, 0},
1296         [GCC_PCNOC_BUS_TIMEOUT7_BCR] = {0x210BC, 0},
1297         [GCC_PCNOC_BUS_TIMEOUT8_BCR] = {0x210C4, 0},
1298         [GCC_PCNOC_BUS_TIMEOUT9_BCR] = {0x210CC, 0},
1299         [GCC_TCSR_BCR] = {0x22000, 0},
1300         [GCC_MPM_BCR] = {0x24000, 0},
1301         [GCC_SPDM_BCR] = {0x25000, 0},
1302 };
1303
1304 static const struct regmap_config gcc_ipq4019_regmap_config = {
1305         .reg_bits       = 32,
1306         .reg_stride     = 4,
1307         .val_bits       = 32,
1308         .max_register   = 0x2dfff,
1309         .fast_io        = true,
1310 };
1311
1312 static const struct qcom_cc_desc gcc_ipq4019_desc = {
1313         .config = &gcc_ipq4019_regmap_config,
1314         .clks = gcc_ipq4019_clocks,
1315         .num_clks = ARRAY_SIZE(gcc_ipq4019_clocks),
1316         .resets = gcc_ipq4019_resets,
1317         .num_resets = ARRAY_SIZE(gcc_ipq4019_resets),
1318 };
1319
1320 static const struct of_device_id gcc_ipq4019_match_table[] = {
1321         { .compatible = "qcom,gcc-ipq4019" },
1322         { }
1323 };
1324 MODULE_DEVICE_TABLE(of, gcc_ipq4019_match_table);
1325
1326 static int gcc_ipq4019_probe(struct platform_device *pdev)
1327 {
1328         return qcom_cc_probe(pdev, &gcc_ipq4019_desc);
1329 }
1330
1331 static struct platform_driver gcc_ipq4019_driver = {
1332         .probe          = gcc_ipq4019_probe,
1333         .driver         = {
1334                 .name   = "qcom,gcc-ipq4019",
1335                 .owner  = THIS_MODULE,
1336                 .of_match_table = gcc_ipq4019_match_table,
1337         },
1338 };
1339
1340 static int __init gcc_ipq4019_init(void)
1341 {
1342         return platform_driver_register(&gcc_ipq4019_driver);
1343 }
1344 core_initcall(gcc_ipq4019_init);
1345
1346 static void __exit gcc_ipq4019_exit(void)
1347 {
1348         platform_driver_unregister(&gcc_ipq4019_driver);
1349 }
1350 module_exit(gcc_ipq4019_exit);
1351
1352 MODULE_ALIAS("platform:gcc-ipq4019");
1353 MODULE_LICENSE("GPL v2");
1354 MODULE_DESCRIPTION("QCOM GCC IPQ4019 driver");